1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/iopoll.h> 23 #include <linux/ioport.h> 24 #include <linux/module.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/seq_file.h> 28 #include <linux/slab.h> 29 #include <linux/stat.h> 30 #include <linux/delay.h> 31 #include <linux/irq.h> 32 #include <linux/mmc/card.h> 33 #include <linux/mmc/host.h> 34 #include <linux/mmc/mmc.h> 35 #include <linux/mmc/sd.h> 36 #include <linux/mmc/sdio.h> 37 #include <linux/bitops.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/of.h> 40 #include <linux/of_gpio.h> 41 #include <linux/mmc/slot-gpio.h> 42 43 #include "dw_mmc.h" 44 45 /* Common flag combinations */ 46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 47 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 48 SDMMC_INT_EBE | SDMMC_INT_HLE) 49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 52 DW_MCI_CMD_ERROR_FLAGS) 53 #define DW_MCI_SEND_STATUS 1 54 #define DW_MCI_RECV_STATUS 2 55 #define DW_MCI_DMA_THRESHOLD 16 56 57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 59 60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63 SDMMC_IDMAC_INT_TI) 64 65 #define DESC_RING_BUF_SZ PAGE_SIZE 66 67 struct idmac_desc_64addr { 68 u32 des0; /* Control Descriptor */ 69 #define IDMAC_OWN_CLR64(x) \ 70 !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 71 72 u32 des1; /* Reserved */ 73 74 u32 des2; /*Buffer sizes */ 75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 78 79 u32 des3; /* Reserved */ 80 81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 83 84 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 85 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 86 }; 87 88 struct idmac_desc { 89 __le32 des0; /* Control Descriptor */ 90 #define IDMAC_DES0_DIC BIT(1) 91 #define IDMAC_DES0_LD BIT(2) 92 #define IDMAC_DES0_FD BIT(3) 93 #define IDMAC_DES0_CH BIT(4) 94 #define IDMAC_DES0_ER BIT(5) 95 #define IDMAC_DES0_CES BIT(30) 96 #define IDMAC_DES0_OWN BIT(31) 97 98 __le32 des1; /* Buffer sizes */ 99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 101 102 __le32 des2; /* buffer 1 physical address */ 103 104 __le32 des3; /* buffer 2 physical address */ 105 }; 106 107 /* Each descriptor can transfer up to 4KB of data in chained mode */ 108 #define DW_MCI_DESC_DATA_LENGTH 0x1000 109 110 #if defined(CONFIG_DEBUG_FS) 111 static int dw_mci_req_show(struct seq_file *s, void *v) 112 { 113 struct dw_mci_slot *slot = s->private; 114 struct mmc_request *mrq; 115 struct mmc_command *cmd; 116 struct mmc_command *stop; 117 struct mmc_data *data; 118 119 /* Make sure we get a consistent snapshot */ 120 spin_lock_bh(&slot->host->lock); 121 mrq = slot->mrq; 122 123 if (mrq) { 124 cmd = mrq->cmd; 125 data = mrq->data; 126 stop = mrq->stop; 127 128 if (cmd) 129 seq_printf(s, 130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131 cmd->opcode, cmd->arg, cmd->flags, 132 cmd->resp[0], cmd->resp[1], cmd->resp[2], 133 cmd->resp[2], cmd->error); 134 if (data) 135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136 data->bytes_xfered, data->blocks, 137 data->blksz, data->flags, data->error); 138 if (stop) 139 seq_printf(s, 140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141 stop->opcode, stop->arg, stop->flags, 142 stop->resp[0], stop->resp[1], stop->resp[2], 143 stop->resp[2], stop->error); 144 } 145 146 spin_unlock_bh(&slot->host->lock); 147 148 return 0; 149 } 150 151 static int dw_mci_req_open(struct inode *inode, struct file *file) 152 { 153 return single_open(file, dw_mci_req_show, inode->i_private); 154 } 155 156 static const struct file_operations dw_mci_req_fops = { 157 .owner = THIS_MODULE, 158 .open = dw_mci_req_open, 159 .read = seq_read, 160 .llseek = seq_lseek, 161 .release = single_release, 162 }; 163 164 static int dw_mci_regs_show(struct seq_file *s, void *v) 165 { 166 struct dw_mci *host = s->private; 167 168 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 169 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 170 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 171 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 172 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 173 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 174 175 return 0; 176 } 177 178 static int dw_mci_regs_open(struct inode *inode, struct file *file) 179 { 180 return single_open(file, dw_mci_regs_show, inode->i_private); 181 } 182 183 static const struct file_operations dw_mci_regs_fops = { 184 .owner = THIS_MODULE, 185 .open = dw_mci_regs_open, 186 .read = seq_read, 187 .llseek = seq_lseek, 188 .release = single_release, 189 }; 190 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 192 { 193 struct mmc_host *mmc = slot->mmc; 194 struct dw_mci *host = slot->host; 195 struct dentry *root; 196 struct dentry *node; 197 198 root = mmc->debugfs_root; 199 if (!root) 200 return; 201 202 node = debugfs_create_file("regs", S_IRUSR, root, host, 203 &dw_mci_regs_fops); 204 if (!node) 205 goto err; 206 207 node = debugfs_create_file("req", S_IRUSR, root, slot, 208 &dw_mci_req_fops); 209 if (!node) 210 goto err; 211 212 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 213 if (!node) 214 goto err; 215 216 node = debugfs_create_x32("pending_events", S_IRUSR, root, 217 (u32 *)&host->pending_events); 218 if (!node) 219 goto err; 220 221 node = debugfs_create_x32("completed_events", S_IRUSR, root, 222 (u32 *)&host->completed_events); 223 if (!node) 224 goto err; 225 226 return; 227 228 err: 229 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 230 } 231 #endif /* defined(CONFIG_DEBUG_FS) */ 232 233 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 234 { 235 u32 ctrl; 236 237 ctrl = mci_readl(host, CTRL); 238 ctrl |= reset; 239 mci_writel(host, CTRL, ctrl); 240 241 /* wait till resets clear */ 242 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 243 !(ctrl & reset), 244 1, 500 * USEC_PER_MSEC)) { 245 dev_err(host->dev, 246 "Timeout resetting block (ctrl reset %#x)\n", 247 ctrl & reset); 248 return false; 249 } 250 251 return true; 252 } 253 254 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 255 { 256 u32 status; 257 258 /* 259 * Databook says that before issuing a new data transfer command 260 * we need to check to see if the card is busy. Data transfer commands 261 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 262 * 263 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 264 * expected. 265 */ 266 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 267 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 268 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 269 status, 270 !(status & SDMMC_STATUS_BUSY), 271 10, 500 * USEC_PER_MSEC)) 272 dev_err(host->dev, "Busy; trying anyway\n"); 273 } 274 } 275 276 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 277 { 278 struct dw_mci *host = slot->host; 279 unsigned int cmd_status = 0; 280 281 mci_writel(host, CMDARG, arg); 282 wmb(); /* drain writebuffer */ 283 dw_mci_wait_while_busy(host, cmd); 284 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 285 286 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 287 !(cmd_status & SDMMC_CMD_START), 288 1, 500 * USEC_PER_MSEC)) 289 dev_err(&slot->mmc->class_dev, 290 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 291 cmd, arg, cmd_status); 292 } 293 294 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 295 { 296 struct dw_mci_slot *slot = mmc_priv(mmc); 297 struct dw_mci *host = slot->host; 298 u32 cmdr; 299 300 cmd->error = -EINPROGRESS; 301 cmdr = cmd->opcode; 302 303 if (cmd->opcode == MMC_STOP_TRANSMISSION || 304 cmd->opcode == MMC_GO_IDLE_STATE || 305 cmd->opcode == MMC_GO_INACTIVE_STATE || 306 (cmd->opcode == SD_IO_RW_DIRECT && 307 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 308 cmdr |= SDMMC_CMD_STOP; 309 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 310 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 311 312 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 313 u32 clk_en_a; 314 315 /* Special bit makes CMD11 not die */ 316 cmdr |= SDMMC_CMD_VOLT_SWITCH; 317 318 /* Change state to continue to handle CMD11 weirdness */ 319 WARN_ON(slot->host->state != STATE_SENDING_CMD); 320 slot->host->state = STATE_SENDING_CMD11; 321 322 /* 323 * We need to disable low power mode (automatic clock stop) 324 * while doing voltage switch so we don't confuse the card, 325 * since stopping the clock is a specific part of the UHS 326 * voltage change dance. 327 * 328 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 329 * unconditionally turned back on in dw_mci_setup_bus() if it's 330 * ever called with a non-zero clock. That shouldn't happen 331 * until the voltage change is all done. 332 */ 333 clk_en_a = mci_readl(host, CLKENA); 334 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 335 mci_writel(host, CLKENA, clk_en_a); 336 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 337 SDMMC_CMD_PRV_DAT_WAIT, 0); 338 } 339 340 if (cmd->flags & MMC_RSP_PRESENT) { 341 /* We expect a response, so set this bit */ 342 cmdr |= SDMMC_CMD_RESP_EXP; 343 if (cmd->flags & MMC_RSP_136) 344 cmdr |= SDMMC_CMD_RESP_LONG; 345 } 346 347 if (cmd->flags & MMC_RSP_CRC) 348 cmdr |= SDMMC_CMD_RESP_CRC; 349 350 if (cmd->data) { 351 cmdr |= SDMMC_CMD_DAT_EXP; 352 if (cmd->data->flags & MMC_DATA_WRITE) 353 cmdr |= SDMMC_CMD_DAT_WR; 354 } 355 356 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 357 cmdr |= SDMMC_CMD_USE_HOLD_REG; 358 359 return cmdr; 360 } 361 362 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 363 { 364 struct mmc_command *stop; 365 u32 cmdr; 366 367 if (!cmd->data) 368 return 0; 369 370 stop = &host->stop_abort; 371 cmdr = cmd->opcode; 372 memset(stop, 0, sizeof(struct mmc_command)); 373 374 if (cmdr == MMC_READ_SINGLE_BLOCK || 375 cmdr == MMC_READ_MULTIPLE_BLOCK || 376 cmdr == MMC_WRITE_BLOCK || 377 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 378 cmdr == MMC_SEND_TUNING_BLOCK || 379 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 380 stop->opcode = MMC_STOP_TRANSMISSION; 381 stop->arg = 0; 382 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 383 } else if (cmdr == SD_IO_RW_EXTENDED) { 384 stop->opcode = SD_IO_RW_DIRECT; 385 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 386 ((cmd->arg >> 28) & 0x7); 387 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 388 } else { 389 return 0; 390 } 391 392 cmdr = stop->opcode | SDMMC_CMD_STOP | 393 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 394 395 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 396 cmdr |= SDMMC_CMD_USE_HOLD_REG; 397 398 return cmdr; 399 } 400 401 static inline void dw_mci_set_cto(struct dw_mci *host) 402 { 403 unsigned int cto_clks; 404 unsigned int cto_div; 405 unsigned int cto_ms; 406 unsigned long irqflags; 407 408 cto_clks = mci_readl(host, TMOUT) & 0xff; 409 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 410 if (cto_div == 0) 411 cto_div = 1; 412 cto_ms = DIV_ROUND_UP(MSEC_PER_SEC * cto_clks * cto_div, host->bus_hz); 413 414 /* add a bit spare time */ 415 cto_ms += 10; 416 417 /* 418 * The durations we're working with are fairly short so we have to be 419 * extra careful about synchronization here. Specifically in hardware a 420 * command timeout is _at most_ 5.1 ms, so that means we expect an 421 * interrupt (either command done or timeout) to come rather quickly 422 * after the mci_writel. ...but just in case we have a long interrupt 423 * latency let's add a bit of paranoia. 424 * 425 * In general we'll assume that at least an interrupt will be asserted 426 * in hardware by the time the cto_timer runs. ...and if it hasn't 427 * been asserted in hardware by that time then we'll assume it'll never 428 * come. 429 */ 430 spin_lock_irqsave(&host->irq_lock, irqflags); 431 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 432 mod_timer(&host->cto_timer, 433 jiffies + msecs_to_jiffies(cto_ms) + 1); 434 spin_unlock_irqrestore(&host->irq_lock, irqflags); 435 } 436 437 static void dw_mci_start_command(struct dw_mci *host, 438 struct mmc_command *cmd, u32 cmd_flags) 439 { 440 host->cmd = cmd; 441 dev_vdbg(host->dev, 442 "start command: ARGR=0x%08x CMDR=0x%08x\n", 443 cmd->arg, cmd_flags); 444 445 mci_writel(host, CMDARG, cmd->arg); 446 wmb(); /* drain writebuffer */ 447 dw_mci_wait_while_busy(host, cmd_flags); 448 449 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 450 451 /* response expected command only */ 452 if (cmd_flags & SDMMC_CMD_RESP_EXP) 453 dw_mci_set_cto(host); 454 } 455 456 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 457 { 458 struct mmc_command *stop = &host->stop_abort; 459 460 dw_mci_start_command(host, stop, host->stop_cmdr); 461 } 462 463 /* DMA interface functions */ 464 static void dw_mci_stop_dma(struct dw_mci *host) 465 { 466 if (host->using_dma) { 467 host->dma_ops->stop(host); 468 host->dma_ops->cleanup(host); 469 } 470 471 /* Data transfer was stopped by the interrupt handler */ 472 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 473 } 474 475 static void dw_mci_dma_cleanup(struct dw_mci *host) 476 { 477 struct mmc_data *data = host->data; 478 479 if (data && data->host_cookie == COOKIE_MAPPED) { 480 dma_unmap_sg(host->dev, 481 data->sg, 482 data->sg_len, 483 mmc_get_dma_dir(data)); 484 data->host_cookie = COOKIE_UNMAPPED; 485 } 486 } 487 488 static void dw_mci_idmac_reset(struct dw_mci *host) 489 { 490 u32 bmod = mci_readl(host, BMOD); 491 /* Software reset of DMA */ 492 bmod |= SDMMC_IDMAC_SWRESET; 493 mci_writel(host, BMOD, bmod); 494 } 495 496 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 497 { 498 u32 temp; 499 500 /* Disable and reset the IDMAC interface */ 501 temp = mci_readl(host, CTRL); 502 temp &= ~SDMMC_CTRL_USE_IDMAC; 503 temp |= SDMMC_CTRL_DMA_RESET; 504 mci_writel(host, CTRL, temp); 505 506 /* Stop the IDMAC running */ 507 temp = mci_readl(host, BMOD); 508 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 509 temp |= SDMMC_IDMAC_SWRESET; 510 mci_writel(host, BMOD, temp); 511 } 512 513 static void dw_mci_dmac_complete_dma(void *arg) 514 { 515 struct dw_mci *host = arg; 516 struct mmc_data *data = host->data; 517 518 dev_vdbg(host->dev, "DMA complete\n"); 519 520 if ((host->use_dma == TRANS_MODE_EDMAC) && 521 data && (data->flags & MMC_DATA_READ)) 522 /* Invalidate cache after read */ 523 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 524 data->sg, 525 data->sg_len, 526 DMA_FROM_DEVICE); 527 528 host->dma_ops->cleanup(host); 529 530 /* 531 * If the card was removed, data will be NULL. No point in trying to 532 * send the stop command or waiting for NBUSY in this case. 533 */ 534 if (data) { 535 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 536 tasklet_schedule(&host->tasklet); 537 } 538 } 539 540 static int dw_mci_idmac_init(struct dw_mci *host) 541 { 542 int i; 543 544 if (host->dma_64bit_address == 1) { 545 struct idmac_desc_64addr *p; 546 /* Number of descriptors in the ring buffer */ 547 host->ring_size = 548 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 549 550 /* Forward link the descriptor list */ 551 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 552 i++, p++) { 553 p->des6 = (host->sg_dma + 554 (sizeof(struct idmac_desc_64addr) * 555 (i + 1))) & 0xffffffff; 556 557 p->des7 = (u64)(host->sg_dma + 558 (sizeof(struct idmac_desc_64addr) * 559 (i + 1))) >> 32; 560 /* Initialize reserved and buffer size fields to "0" */ 561 p->des1 = 0; 562 p->des2 = 0; 563 p->des3 = 0; 564 } 565 566 /* Set the last descriptor as the end-of-ring descriptor */ 567 p->des6 = host->sg_dma & 0xffffffff; 568 p->des7 = (u64)host->sg_dma >> 32; 569 p->des0 = IDMAC_DES0_ER; 570 571 } else { 572 struct idmac_desc *p; 573 /* Number of descriptors in the ring buffer */ 574 host->ring_size = 575 DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 576 577 /* Forward link the descriptor list */ 578 for (i = 0, p = host->sg_cpu; 579 i < host->ring_size - 1; 580 i++, p++) { 581 p->des3 = cpu_to_le32(host->sg_dma + 582 (sizeof(struct idmac_desc) * (i + 1))); 583 p->des1 = 0; 584 } 585 586 /* Set the last descriptor as the end-of-ring descriptor */ 587 p->des3 = cpu_to_le32(host->sg_dma); 588 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 589 } 590 591 dw_mci_idmac_reset(host); 592 593 if (host->dma_64bit_address == 1) { 594 /* Mask out interrupts - get Tx & Rx complete only */ 595 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 596 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 597 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 598 599 /* Set the descriptor base address */ 600 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 601 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 602 603 } else { 604 /* Mask out interrupts - get Tx & Rx complete only */ 605 mci_writel(host, IDSTS, IDMAC_INT_CLR); 606 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 607 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 608 609 /* Set the descriptor base address */ 610 mci_writel(host, DBADDR, host->sg_dma); 611 } 612 613 return 0; 614 } 615 616 static inline int dw_mci_prepare_desc64(struct dw_mci *host, 617 struct mmc_data *data, 618 unsigned int sg_len) 619 { 620 unsigned int desc_len; 621 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 622 u32 val; 623 int i; 624 625 desc_first = desc_last = desc = host->sg_cpu; 626 627 for (i = 0; i < sg_len; i++) { 628 unsigned int length = sg_dma_len(&data->sg[i]); 629 630 u64 mem_addr = sg_dma_address(&data->sg[i]); 631 632 for ( ; length ; desc++) { 633 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 634 length : DW_MCI_DESC_DATA_LENGTH; 635 636 length -= desc_len; 637 638 /* 639 * Wait for the former clear OWN bit operation 640 * of IDMAC to make sure that this descriptor 641 * isn't still owned by IDMAC as IDMAC's write 642 * ops and CPU's read ops are asynchronous. 643 */ 644 if (readl_poll_timeout_atomic(&desc->des0, val, 645 !(val & IDMAC_DES0_OWN), 646 10, 100 * USEC_PER_MSEC)) 647 goto err_own_bit; 648 649 /* 650 * Set the OWN bit and disable interrupts 651 * for this descriptor 652 */ 653 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 654 IDMAC_DES0_CH; 655 656 /* Buffer length */ 657 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 658 659 /* Physical address to DMA to/from */ 660 desc->des4 = mem_addr & 0xffffffff; 661 desc->des5 = mem_addr >> 32; 662 663 /* Update physical address for the next desc */ 664 mem_addr += desc_len; 665 666 /* Save pointer to the last descriptor */ 667 desc_last = desc; 668 } 669 } 670 671 /* Set first descriptor */ 672 desc_first->des0 |= IDMAC_DES0_FD; 673 674 /* Set last descriptor */ 675 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 676 desc_last->des0 |= IDMAC_DES0_LD; 677 678 return 0; 679 err_own_bit: 680 /* restore the descriptor chain as it's polluted */ 681 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 682 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 683 dw_mci_idmac_init(host); 684 return -EINVAL; 685 } 686 687 688 static inline int dw_mci_prepare_desc32(struct dw_mci *host, 689 struct mmc_data *data, 690 unsigned int sg_len) 691 { 692 unsigned int desc_len; 693 struct idmac_desc *desc_first, *desc_last, *desc; 694 u32 val; 695 int i; 696 697 desc_first = desc_last = desc = host->sg_cpu; 698 699 for (i = 0; i < sg_len; i++) { 700 unsigned int length = sg_dma_len(&data->sg[i]); 701 702 u32 mem_addr = sg_dma_address(&data->sg[i]); 703 704 for ( ; length ; desc++) { 705 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 706 length : DW_MCI_DESC_DATA_LENGTH; 707 708 length -= desc_len; 709 710 /* 711 * Wait for the former clear OWN bit operation 712 * of IDMAC to make sure that this descriptor 713 * isn't still owned by IDMAC as IDMAC's write 714 * ops and CPU's read ops are asynchronous. 715 */ 716 if (readl_poll_timeout_atomic(&desc->des0, val, 717 IDMAC_OWN_CLR64(val), 718 10, 719 100 * USEC_PER_MSEC)) 720 goto err_own_bit; 721 722 /* 723 * Set the OWN bit and disable interrupts 724 * for this descriptor 725 */ 726 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 727 IDMAC_DES0_DIC | 728 IDMAC_DES0_CH); 729 730 /* Buffer length */ 731 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 732 733 /* Physical address to DMA to/from */ 734 desc->des2 = cpu_to_le32(mem_addr); 735 736 /* Update physical address for the next desc */ 737 mem_addr += desc_len; 738 739 /* Save pointer to the last descriptor */ 740 desc_last = desc; 741 } 742 } 743 744 /* Set first descriptor */ 745 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 746 747 /* Set last descriptor */ 748 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 749 IDMAC_DES0_DIC)); 750 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 751 752 return 0; 753 err_own_bit: 754 /* restore the descriptor chain as it's polluted */ 755 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 756 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 757 dw_mci_idmac_init(host); 758 return -EINVAL; 759 } 760 761 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 762 { 763 u32 temp; 764 int ret; 765 766 if (host->dma_64bit_address == 1) 767 ret = dw_mci_prepare_desc64(host, host->data, sg_len); 768 else 769 ret = dw_mci_prepare_desc32(host, host->data, sg_len); 770 771 if (ret) 772 goto out; 773 774 /* drain writebuffer */ 775 wmb(); 776 777 /* Make sure to reset DMA in case we did PIO before this */ 778 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 779 dw_mci_idmac_reset(host); 780 781 /* Select IDMAC interface */ 782 temp = mci_readl(host, CTRL); 783 temp |= SDMMC_CTRL_USE_IDMAC; 784 mci_writel(host, CTRL, temp); 785 786 /* drain writebuffer */ 787 wmb(); 788 789 /* Enable the IDMAC */ 790 temp = mci_readl(host, BMOD); 791 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 792 mci_writel(host, BMOD, temp); 793 794 /* Start it running */ 795 mci_writel(host, PLDMND, 1); 796 797 out: 798 return ret; 799 } 800 801 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 802 .init = dw_mci_idmac_init, 803 .start = dw_mci_idmac_start_dma, 804 .stop = dw_mci_idmac_stop_dma, 805 .complete = dw_mci_dmac_complete_dma, 806 .cleanup = dw_mci_dma_cleanup, 807 }; 808 809 static void dw_mci_edmac_stop_dma(struct dw_mci *host) 810 { 811 dmaengine_terminate_async(host->dms->ch); 812 } 813 814 static int dw_mci_edmac_start_dma(struct dw_mci *host, 815 unsigned int sg_len) 816 { 817 struct dma_slave_config cfg; 818 struct dma_async_tx_descriptor *desc = NULL; 819 struct scatterlist *sgl = host->data->sg; 820 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 821 u32 sg_elems = host->data->sg_len; 822 u32 fifoth_val; 823 u32 fifo_offset = host->fifo_reg - host->regs; 824 int ret = 0; 825 826 /* Set external dma config: burst size, burst width */ 827 cfg.dst_addr = host->phy_regs + fifo_offset; 828 cfg.src_addr = cfg.dst_addr; 829 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 830 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 831 832 /* Match burst msize with external dma config */ 833 fifoth_val = mci_readl(host, FIFOTH); 834 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 835 cfg.src_maxburst = cfg.dst_maxburst; 836 837 if (host->data->flags & MMC_DATA_WRITE) 838 cfg.direction = DMA_MEM_TO_DEV; 839 else 840 cfg.direction = DMA_DEV_TO_MEM; 841 842 ret = dmaengine_slave_config(host->dms->ch, &cfg); 843 if (ret) { 844 dev_err(host->dev, "Failed to config edmac.\n"); 845 return -EBUSY; 846 } 847 848 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 849 sg_len, cfg.direction, 850 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 851 if (!desc) { 852 dev_err(host->dev, "Can't prepare slave sg.\n"); 853 return -EBUSY; 854 } 855 856 /* Set dw_mci_dmac_complete_dma as callback */ 857 desc->callback = dw_mci_dmac_complete_dma; 858 desc->callback_param = (void *)host; 859 dmaengine_submit(desc); 860 861 /* Flush cache before write */ 862 if (host->data->flags & MMC_DATA_WRITE) 863 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 864 sg_elems, DMA_TO_DEVICE); 865 866 dma_async_issue_pending(host->dms->ch); 867 868 return 0; 869 } 870 871 static int dw_mci_edmac_init(struct dw_mci *host) 872 { 873 /* Request external dma channel */ 874 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 875 if (!host->dms) 876 return -ENOMEM; 877 878 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 879 if (!host->dms->ch) { 880 dev_err(host->dev, "Failed to get external DMA channel.\n"); 881 kfree(host->dms); 882 host->dms = NULL; 883 return -ENXIO; 884 } 885 886 return 0; 887 } 888 889 static void dw_mci_edmac_exit(struct dw_mci *host) 890 { 891 if (host->dms) { 892 if (host->dms->ch) { 893 dma_release_channel(host->dms->ch); 894 host->dms->ch = NULL; 895 } 896 kfree(host->dms); 897 host->dms = NULL; 898 } 899 } 900 901 static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 902 .init = dw_mci_edmac_init, 903 .exit = dw_mci_edmac_exit, 904 .start = dw_mci_edmac_start_dma, 905 .stop = dw_mci_edmac_stop_dma, 906 .complete = dw_mci_dmac_complete_dma, 907 .cleanup = dw_mci_dma_cleanup, 908 }; 909 910 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 911 struct mmc_data *data, 912 int cookie) 913 { 914 struct scatterlist *sg; 915 unsigned int i, sg_len; 916 917 if (data->host_cookie == COOKIE_PRE_MAPPED) 918 return data->sg_len; 919 920 /* 921 * We don't do DMA on "complex" transfers, i.e. with 922 * non-word-aligned buffers or lengths. Also, we don't bother 923 * with all the DMA setup overhead for short transfers. 924 */ 925 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 926 return -EINVAL; 927 928 if (data->blksz & 3) 929 return -EINVAL; 930 931 for_each_sg(data->sg, sg, data->sg_len, i) { 932 if (sg->offset & 3 || sg->length & 3) 933 return -EINVAL; 934 } 935 936 sg_len = dma_map_sg(host->dev, 937 data->sg, 938 data->sg_len, 939 mmc_get_dma_dir(data)); 940 if (sg_len == 0) 941 return -EINVAL; 942 943 data->host_cookie = cookie; 944 945 return sg_len; 946 } 947 948 static void dw_mci_pre_req(struct mmc_host *mmc, 949 struct mmc_request *mrq) 950 { 951 struct dw_mci_slot *slot = mmc_priv(mmc); 952 struct mmc_data *data = mrq->data; 953 954 if (!slot->host->use_dma || !data) 955 return; 956 957 /* This data might be unmapped at this time */ 958 data->host_cookie = COOKIE_UNMAPPED; 959 960 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 961 COOKIE_PRE_MAPPED) < 0) 962 data->host_cookie = COOKIE_UNMAPPED; 963 } 964 965 static void dw_mci_post_req(struct mmc_host *mmc, 966 struct mmc_request *mrq, 967 int err) 968 { 969 struct dw_mci_slot *slot = mmc_priv(mmc); 970 struct mmc_data *data = mrq->data; 971 972 if (!slot->host->use_dma || !data) 973 return; 974 975 if (data->host_cookie != COOKIE_UNMAPPED) 976 dma_unmap_sg(slot->host->dev, 977 data->sg, 978 data->sg_len, 979 mmc_get_dma_dir(data)); 980 data->host_cookie = COOKIE_UNMAPPED; 981 } 982 983 static int dw_mci_get_cd(struct mmc_host *mmc) 984 { 985 int present; 986 struct dw_mci_slot *slot = mmc_priv(mmc); 987 struct dw_mci *host = slot->host; 988 int gpio_cd = mmc_gpio_get_cd(mmc); 989 990 /* Use platform get_cd function, else try onboard card detect */ 991 if (((mmc->caps & MMC_CAP_NEEDS_POLL) 992 || !mmc_card_is_removable(mmc))) { 993 present = 1; 994 995 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 996 if (mmc->caps & MMC_CAP_NEEDS_POLL) { 997 dev_info(&mmc->class_dev, 998 "card is polling.\n"); 999 } else { 1000 dev_info(&mmc->class_dev, 1001 "card is non-removable.\n"); 1002 } 1003 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1004 } 1005 1006 return present; 1007 } else if (gpio_cd >= 0) 1008 present = gpio_cd; 1009 else 1010 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1011 == 0 ? 1 : 0; 1012 1013 spin_lock_bh(&host->lock); 1014 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 1015 dev_dbg(&mmc->class_dev, "card is present\n"); 1016 else if (!present && 1017 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 1018 dev_dbg(&mmc->class_dev, "card is not present\n"); 1019 spin_unlock_bh(&host->lock); 1020 1021 return present; 1022 } 1023 1024 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 1025 { 1026 unsigned int blksz = data->blksz; 1027 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 1028 u32 fifo_width = 1 << host->data_shift; 1029 u32 blksz_depth = blksz / fifo_width, fifoth_val; 1030 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 1031 int idx = ARRAY_SIZE(mszs) - 1; 1032 1033 /* pio should ship this scenario */ 1034 if (!host->use_dma) 1035 return; 1036 1037 tx_wmark = (host->fifo_depth) / 2; 1038 tx_wmark_invers = host->fifo_depth - tx_wmark; 1039 1040 /* 1041 * MSIZE is '1', 1042 * if blksz is not a multiple of the FIFO width 1043 */ 1044 if (blksz % fifo_width) 1045 goto done; 1046 1047 do { 1048 if (!((blksz_depth % mszs[idx]) || 1049 (tx_wmark_invers % mszs[idx]))) { 1050 msize = idx; 1051 rx_wmark = mszs[idx] - 1; 1052 break; 1053 } 1054 } while (--idx > 0); 1055 /* 1056 * If idx is '0', it won't be tried 1057 * Thus, initial values are uesed 1058 */ 1059 done: 1060 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 1061 mci_writel(host, FIFOTH, fifoth_val); 1062 } 1063 1064 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1065 { 1066 unsigned int blksz = data->blksz; 1067 u32 blksz_depth, fifo_depth; 1068 u16 thld_size; 1069 u8 enable; 1070 1071 /* 1072 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 1073 * in the FIFO region, so we really shouldn't access it). 1074 */ 1075 if (host->verid < DW_MMC_240A || 1076 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 1077 return; 1078 1079 /* 1080 * Card write Threshold is introduced since 2.80a 1081 * It's used when HS400 mode is enabled. 1082 */ 1083 if (data->flags & MMC_DATA_WRITE && 1084 !(host->timing != MMC_TIMING_MMC_HS400)) 1085 return; 1086 1087 if (data->flags & MMC_DATA_WRITE) 1088 enable = SDMMC_CARD_WR_THR_EN; 1089 else 1090 enable = SDMMC_CARD_RD_THR_EN; 1091 1092 if (host->timing != MMC_TIMING_MMC_HS200 && 1093 host->timing != MMC_TIMING_UHS_SDR104) 1094 goto disable; 1095 1096 blksz_depth = blksz / (1 << host->data_shift); 1097 fifo_depth = host->fifo_depth; 1098 1099 if (blksz_depth > fifo_depth) 1100 goto disable; 1101 1102 /* 1103 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1104 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1105 * Currently just choose blksz. 1106 */ 1107 thld_size = blksz; 1108 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1109 return; 1110 1111 disable: 1112 mci_writel(host, CDTHRCTL, 0); 1113 } 1114 1115 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 1116 { 1117 unsigned long irqflags; 1118 int sg_len; 1119 u32 temp; 1120 1121 host->using_dma = 0; 1122 1123 /* If we don't have a channel, we can't do DMA */ 1124 if (!host->use_dma) 1125 return -ENODEV; 1126 1127 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1128 if (sg_len < 0) { 1129 host->dma_ops->stop(host); 1130 return sg_len; 1131 } 1132 1133 host->using_dma = 1; 1134 1135 if (host->use_dma == TRANS_MODE_IDMAC) 1136 dev_vdbg(host->dev, 1137 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 1138 (unsigned long)host->sg_cpu, 1139 (unsigned long)host->sg_dma, 1140 sg_len); 1141 1142 /* 1143 * Decide the MSIZE and RX/TX Watermark. 1144 * If current block size is same with previous size, 1145 * no need to update fifoth. 1146 */ 1147 if (host->prev_blksz != data->blksz) 1148 dw_mci_adjust_fifoth(host, data); 1149 1150 /* Enable the DMA interface */ 1151 temp = mci_readl(host, CTRL); 1152 temp |= SDMMC_CTRL_DMA_ENABLE; 1153 mci_writel(host, CTRL, temp); 1154 1155 /* Disable RX/TX IRQs, let DMA handle it */ 1156 spin_lock_irqsave(&host->irq_lock, irqflags); 1157 temp = mci_readl(host, INTMASK); 1158 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1159 mci_writel(host, INTMASK, temp); 1160 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1161 1162 if (host->dma_ops->start(host, sg_len)) { 1163 host->dma_ops->stop(host); 1164 /* We can't do DMA, try PIO for this one */ 1165 dev_dbg(host->dev, 1166 "%s: fall back to PIO mode for current transfer\n", 1167 __func__); 1168 return -ENODEV; 1169 } 1170 1171 return 0; 1172 } 1173 1174 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1175 { 1176 unsigned long irqflags; 1177 int flags = SG_MITER_ATOMIC; 1178 u32 temp; 1179 1180 data->error = -EINPROGRESS; 1181 1182 WARN_ON(host->data); 1183 host->sg = NULL; 1184 host->data = data; 1185 1186 if (data->flags & MMC_DATA_READ) 1187 host->dir_status = DW_MCI_RECV_STATUS; 1188 else 1189 host->dir_status = DW_MCI_SEND_STATUS; 1190 1191 dw_mci_ctrl_thld(host, data); 1192 1193 if (dw_mci_submit_data_dma(host, data)) { 1194 if (host->data->flags & MMC_DATA_READ) 1195 flags |= SG_MITER_TO_SG; 1196 else 1197 flags |= SG_MITER_FROM_SG; 1198 1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1200 host->sg = data->sg; 1201 host->part_buf_start = 0; 1202 host->part_buf_count = 0; 1203 1204 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1205 1206 spin_lock_irqsave(&host->irq_lock, irqflags); 1207 temp = mci_readl(host, INTMASK); 1208 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1209 mci_writel(host, INTMASK, temp); 1210 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1211 1212 temp = mci_readl(host, CTRL); 1213 temp &= ~SDMMC_CTRL_DMA_ENABLE; 1214 mci_writel(host, CTRL, temp); 1215 1216 /* 1217 * Use the initial fifoth_val for PIO mode. If wm_algined 1218 * is set, we set watermark same as data size. 1219 * If next issued data may be transfered by DMA mode, 1220 * prev_blksz should be invalidated. 1221 */ 1222 if (host->wm_aligned) 1223 dw_mci_adjust_fifoth(host, data); 1224 else 1225 mci_writel(host, FIFOTH, host->fifoth_val); 1226 host->prev_blksz = 0; 1227 } else { 1228 /* 1229 * Keep the current block size. 1230 * It will be used to decide whether to update 1231 * fifoth register next time. 1232 */ 1233 host->prev_blksz = data->blksz; 1234 } 1235 } 1236 1237 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1238 { 1239 struct dw_mci *host = slot->host; 1240 unsigned int clock = slot->clock; 1241 u32 div; 1242 u32 clk_en_a; 1243 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 1244 1245 /* We must continue to set bit 28 in CMD until the change is complete */ 1246 if (host->state == STATE_WAITING_CMD11_DONE) 1247 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1248 1249 if (!clock) { 1250 mci_writel(host, CLKENA, 0); 1251 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1252 } else if (clock != host->current_speed || force_clkinit) { 1253 div = host->bus_hz / clock; 1254 if (host->bus_hz % clock && host->bus_hz > clock) 1255 /* 1256 * move the + 1 after the divide to prevent 1257 * over-clocking the card. 1258 */ 1259 div += 1; 1260 1261 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1262 1263 if ((clock != slot->__clk_old && 1264 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1265 force_clkinit) { 1266 /* Silent the verbose log if calling from PM context */ 1267 if (!force_clkinit) 1268 dev_info(&slot->mmc->class_dev, 1269 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1270 slot->id, host->bus_hz, clock, 1271 div ? ((host->bus_hz / div) >> 1) : 1272 host->bus_hz, div); 1273 1274 /* 1275 * If card is polling, display the message only 1276 * one time at boot time. 1277 */ 1278 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1279 slot->mmc->f_min == clock) 1280 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1281 } 1282 1283 /* disable clock */ 1284 mci_writel(host, CLKENA, 0); 1285 mci_writel(host, CLKSRC, 0); 1286 1287 /* inform CIU */ 1288 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1289 1290 /* set clock to desired speed */ 1291 mci_writel(host, CLKDIV, div); 1292 1293 /* inform CIU */ 1294 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1295 1296 /* enable clock; only low power if no SDIO */ 1297 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1298 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1299 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1300 mci_writel(host, CLKENA, clk_en_a); 1301 1302 /* inform CIU */ 1303 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1304 1305 /* keep the last clock value that was requested from core */ 1306 slot->__clk_old = clock; 1307 } 1308 1309 host->current_speed = clock; 1310 1311 /* Set the current slot bus width */ 1312 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1313 } 1314 1315 static void __dw_mci_start_request(struct dw_mci *host, 1316 struct dw_mci_slot *slot, 1317 struct mmc_command *cmd) 1318 { 1319 struct mmc_request *mrq; 1320 struct mmc_data *data; 1321 u32 cmdflags; 1322 1323 mrq = slot->mrq; 1324 1325 host->mrq = mrq; 1326 1327 host->pending_events = 0; 1328 host->completed_events = 0; 1329 host->cmd_status = 0; 1330 host->data_status = 0; 1331 host->dir_status = 0; 1332 1333 data = cmd->data; 1334 if (data) { 1335 mci_writel(host, TMOUT, 0xFFFFFFFF); 1336 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1337 mci_writel(host, BLKSIZ, data->blksz); 1338 } 1339 1340 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1341 1342 /* this is the first command, send the initialization clock */ 1343 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1344 cmdflags |= SDMMC_CMD_INIT; 1345 1346 if (data) { 1347 dw_mci_submit_data(host, data); 1348 wmb(); /* drain writebuffer */ 1349 } 1350 1351 dw_mci_start_command(host, cmd, cmdflags); 1352 1353 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1354 unsigned long irqflags; 1355 1356 /* 1357 * Databook says to fail after 2ms w/ no response, but evidence 1358 * shows that sometimes the cmd11 interrupt takes over 130ms. 1359 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1360 * is just about to roll over. 1361 * 1362 * We do this whole thing under spinlock and only if the 1363 * command hasn't already completed (indicating the the irq 1364 * already ran so we don't want the timeout). 1365 */ 1366 spin_lock_irqsave(&host->irq_lock, irqflags); 1367 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1368 mod_timer(&host->cmd11_timer, 1369 jiffies + msecs_to_jiffies(500) + 1); 1370 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1371 } 1372 1373 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1374 } 1375 1376 static void dw_mci_start_request(struct dw_mci *host, 1377 struct dw_mci_slot *slot) 1378 { 1379 struct mmc_request *mrq = slot->mrq; 1380 struct mmc_command *cmd; 1381 1382 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1383 __dw_mci_start_request(host, slot, cmd); 1384 } 1385 1386 /* must be called with host->lock held */ 1387 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1388 struct mmc_request *mrq) 1389 { 1390 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1391 host->state); 1392 1393 slot->mrq = mrq; 1394 1395 if (host->state == STATE_WAITING_CMD11_DONE) { 1396 dev_warn(&slot->mmc->class_dev, 1397 "Voltage change didn't complete\n"); 1398 /* 1399 * this case isn't expected to happen, so we can 1400 * either crash here or just try to continue on 1401 * in the closest possible state 1402 */ 1403 host->state = STATE_IDLE; 1404 } 1405 1406 if (host->state == STATE_IDLE) { 1407 host->state = STATE_SENDING_CMD; 1408 dw_mci_start_request(host, slot); 1409 } else { 1410 list_add_tail(&slot->queue_node, &host->queue); 1411 } 1412 } 1413 1414 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1415 { 1416 struct dw_mci_slot *slot = mmc_priv(mmc); 1417 struct dw_mci *host = slot->host; 1418 1419 WARN_ON(slot->mrq); 1420 1421 /* 1422 * The check for card presence and queueing of the request must be 1423 * atomic, otherwise the card could be removed in between and the 1424 * request wouldn't fail until another card was inserted. 1425 */ 1426 1427 if (!dw_mci_get_cd(mmc)) { 1428 mrq->cmd->error = -ENOMEDIUM; 1429 mmc_request_done(mmc, mrq); 1430 return; 1431 } 1432 1433 spin_lock_bh(&host->lock); 1434 1435 dw_mci_queue_request(host, slot, mrq); 1436 1437 spin_unlock_bh(&host->lock); 1438 } 1439 1440 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1441 { 1442 struct dw_mci_slot *slot = mmc_priv(mmc); 1443 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1444 u32 regs; 1445 int ret; 1446 1447 switch (ios->bus_width) { 1448 case MMC_BUS_WIDTH_4: 1449 slot->ctype = SDMMC_CTYPE_4BIT; 1450 break; 1451 case MMC_BUS_WIDTH_8: 1452 slot->ctype = SDMMC_CTYPE_8BIT; 1453 break; 1454 default: 1455 /* set default 1 bit mode */ 1456 slot->ctype = SDMMC_CTYPE_1BIT; 1457 } 1458 1459 regs = mci_readl(slot->host, UHS_REG); 1460 1461 /* DDR mode set */ 1462 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1463 ios->timing == MMC_TIMING_UHS_DDR50 || 1464 ios->timing == MMC_TIMING_MMC_HS400) 1465 regs |= ((0x1 << slot->id) << 16); 1466 else 1467 regs &= ~((0x1 << slot->id) << 16); 1468 1469 mci_writel(slot->host, UHS_REG, regs); 1470 slot->host->timing = ios->timing; 1471 1472 /* 1473 * Use mirror of ios->clock to prevent race with mmc 1474 * core ios update when finding the minimum. 1475 */ 1476 slot->clock = ios->clock; 1477 1478 if (drv_data && drv_data->set_ios) 1479 drv_data->set_ios(slot->host, ios); 1480 1481 switch (ios->power_mode) { 1482 case MMC_POWER_UP: 1483 if (!IS_ERR(mmc->supply.vmmc)) { 1484 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1485 ios->vdd); 1486 if (ret) { 1487 dev_err(slot->host->dev, 1488 "failed to enable vmmc regulator\n"); 1489 /*return, if failed turn on vmmc*/ 1490 return; 1491 } 1492 } 1493 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1494 regs = mci_readl(slot->host, PWREN); 1495 regs |= (1 << slot->id); 1496 mci_writel(slot->host, PWREN, regs); 1497 break; 1498 case MMC_POWER_ON: 1499 if (!slot->host->vqmmc_enabled) { 1500 if (!IS_ERR(mmc->supply.vqmmc)) { 1501 ret = regulator_enable(mmc->supply.vqmmc); 1502 if (ret < 0) 1503 dev_err(slot->host->dev, 1504 "failed to enable vqmmc\n"); 1505 else 1506 slot->host->vqmmc_enabled = true; 1507 1508 } else { 1509 /* Keep track so we don't reset again */ 1510 slot->host->vqmmc_enabled = true; 1511 } 1512 1513 /* Reset our state machine after powering on */ 1514 dw_mci_ctrl_reset(slot->host, 1515 SDMMC_CTRL_ALL_RESET_FLAGS); 1516 } 1517 1518 /* Adjust clock / bus width after power is up */ 1519 dw_mci_setup_bus(slot, false); 1520 1521 break; 1522 case MMC_POWER_OFF: 1523 /* Turn clock off before power goes down */ 1524 dw_mci_setup_bus(slot, false); 1525 1526 if (!IS_ERR(mmc->supply.vmmc)) 1527 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1528 1529 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1530 regulator_disable(mmc->supply.vqmmc); 1531 slot->host->vqmmc_enabled = false; 1532 1533 regs = mci_readl(slot->host, PWREN); 1534 regs &= ~(1 << slot->id); 1535 mci_writel(slot->host, PWREN, regs); 1536 break; 1537 default: 1538 break; 1539 } 1540 1541 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1542 slot->host->state = STATE_IDLE; 1543 } 1544 1545 static int dw_mci_card_busy(struct mmc_host *mmc) 1546 { 1547 struct dw_mci_slot *slot = mmc_priv(mmc); 1548 u32 status; 1549 1550 /* 1551 * Check the busy bit which is low when DAT[3:0] 1552 * (the data lines) are 0000 1553 */ 1554 status = mci_readl(slot->host, STATUS); 1555 1556 return !!(status & SDMMC_STATUS_BUSY); 1557 } 1558 1559 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1560 { 1561 struct dw_mci_slot *slot = mmc_priv(mmc); 1562 struct dw_mci *host = slot->host; 1563 const struct dw_mci_drv_data *drv_data = host->drv_data; 1564 u32 uhs; 1565 u32 v18 = SDMMC_UHS_18V << slot->id; 1566 int ret; 1567 1568 if (drv_data && drv_data->switch_voltage) 1569 return drv_data->switch_voltage(mmc, ios); 1570 1571 /* 1572 * Program the voltage. Note that some instances of dw_mmc may use 1573 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1574 * does no harm but you need to set the regulator directly. Try both. 1575 */ 1576 uhs = mci_readl(host, UHS_REG); 1577 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1578 uhs &= ~v18; 1579 else 1580 uhs |= v18; 1581 1582 if (!IS_ERR(mmc->supply.vqmmc)) { 1583 ret = mmc_regulator_set_vqmmc(mmc, ios); 1584 1585 if (ret) { 1586 dev_dbg(&mmc->class_dev, 1587 "Regulator set error %d - %s V\n", 1588 ret, uhs & v18 ? "1.8" : "3.3"); 1589 return ret; 1590 } 1591 } 1592 mci_writel(host, UHS_REG, uhs); 1593 1594 return 0; 1595 } 1596 1597 static int dw_mci_get_ro(struct mmc_host *mmc) 1598 { 1599 int read_only; 1600 struct dw_mci_slot *slot = mmc_priv(mmc); 1601 int gpio_ro = mmc_gpio_get_ro(mmc); 1602 1603 /* Use platform get_ro function, else try on board write protect */ 1604 if (gpio_ro >= 0) 1605 read_only = gpio_ro; 1606 else 1607 read_only = 1608 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1609 1610 dev_dbg(&mmc->class_dev, "card is %s\n", 1611 read_only ? "read-only" : "read-write"); 1612 1613 return read_only; 1614 } 1615 1616 static void dw_mci_hw_reset(struct mmc_host *mmc) 1617 { 1618 struct dw_mci_slot *slot = mmc_priv(mmc); 1619 struct dw_mci *host = slot->host; 1620 int reset; 1621 1622 if (host->use_dma == TRANS_MODE_IDMAC) 1623 dw_mci_idmac_reset(host); 1624 1625 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1626 SDMMC_CTRL_FIFO_RESET)) 1627 return; 1628 1629 /* 1630 * According to eMMC spec, card reset procedure: 1631 * tRstW >= 1us: RST_n pulse width 1632 * tRSCA >= 200us: RST_n to Command time 1633 * tRSTH >= 1us: RST_n high period 1634 */ 1635 reset = mci_readl(host, RST_N); 1636 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1637 mci_writel(host, RST_N, reset); 1638 usleep_range(1, 2); 1639 reset |= SDMMC_RST_HWACTIVE << slot->id; 1640 mci_writel(host, RST_N, reset); 1641 usleep_range(200, 300); 1642 } 1643 1644 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1645 { 1646 struct dw_mci_slot *slot = mmc_priv(mmc); 1647 struct dw_mci *host = slot->host; 1648 1649 /* 1650 * Low power mode will stop the card clock when idle. According to the 1651 * description of the CLKENA register we should disable low power mode 1652 * for SDIO cards if we need SDIO interrupts to work. 1653 */ 1654 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1655 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1656 u32 clk_en_a_old; 1657 u32 clk_en_a; 1658 1659 clk_en_a_old = mci_readl(host, CLKENA); 1660 1661 if (card->type == MMC_TYPE_SDIO || 1662 card->type == MMC_TYPE_SD_COMBO) { 1663 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1664 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1665 } else { 1666 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1667 clk_en_a = clk_en_a_old | clken_low_pwr; 1668 } 1669 1670 if (clk_en_a != clk_en_a_old) { 1671 mci_writel(host, CLKENA, clk_en_a); 1672 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1673 SDMMC_CMD_PRV_DAT_WAIT, 0); 1674 } 1675 } 1676 } 1677 1678 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 1679 { 1680 struct dw_mci *host = slot->host; 1681 unsigned long irqflags; 1682 u32 int_mask; 1683 1684 spin_lock_irqsave(&host->irq_lock, irqflags); 1685 1686 /* Enable/disable Slot Specific SDIO interrupt */ 1687 int_mask = mci_readl(host, INTMASK); 1688 if (enb) 1689 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1690 else 1691 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1692 mci_writel(host, INTMASK, int_mask); 1693 1694 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1695 } 1696 1697 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1698 { 1699 struct dw_mci_slot *slot = mmc_priv(mmc); 1700 struct dw_mci *host = slot->host; 1701 1702 __dw_mci_enable_sdio_irq(slot, enb); 1703 1704 /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1705 if (enb) 1706 pm_runtime_get_noresume(host->dev); 1707 else 1708 pm_runtime_put_noidle(host->dev); 1709 } 1710 1711 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 1712 { 1713 struct dw_mci_slot *slot = mmc_priv(mmc); 1714 1715 __dw_mci_enable_sdio_irq(slot, 1); 1716 } 1717 1718 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1719 { 1720 struct dw_mci_slot *slot = mmc_priv(mmc); 1721 struct dw_mci *host = slot->host; 1722 const struct dw_mci_drv_data *drv_data = host->drv_data; 1723 int err = -EINVAL; 1724 1725 if (drv_data && drv_data->execute_tuning) 1726 err = drv_data->execute_tuning(slot, opcode); 1727 return err; 1728 } 1729 1730 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1731 struct mmc_ios *ios) 1732 { 1733 struct dw_mci_slot *slot = mmc_priv(mmc); 1734 struct dw_mci *host = slot->host; 1735 const struct dw_mci_drv_data *drv_data = host->drv_data; 1736 1737 if (drv_data && drv_data->prepare_hs400_tuning) 1738 return drv_data->prepare_hs400_tuning(host, ios); 1739 1740 return 0; 1741 } 1742 1743 static bool dw_mci_reset(struct dw_mci *host) 1744 { 1745 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 1746 bool ret = false; 1747 u32 status = 0; 1748 1749 /* 1750 * Resetting generates a block interrupt, hence setting 1751 * the scatter-gather pointer to NULL. 1752 */ 1753 if (host->sg) { 1754 sg_miter_stop(&host->sg_miter); 1755 host->sg = NULL; 1756 } 1757 1758 if (host->use_dma) 1759 flags |= SDMMC_CTRL_DMA_RESET; 1760 1761 if (dw_mci_ctrl_reset(host, flags)) { 1762 /* 1763 * In all cases we clear the RAWINTS 1764 * register to clear any interrupts. 1765 */ 1766 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1767 1768 if (!host->use_dma) { 1769 ret = true; 1770 goto ciu_out; 1771 } 1772 1773 /* Wait for dma_req to be cleared */ 1774 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 1775 status, 1776 !(status & SDMMC_STATUS_DMA_REQ), 1777 1, 500 * USEC_PER_MSEC)) { 1778 dev_err(host->dev, 1779 "%s: Timeout waiting for dma_req to be cleared\n", 1780 __func__); 1781 goto ciu_out; 1782 } 1783 1784 /* when using DMA next we reset the fifo again */ 1785 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 1786 goto ciu_out; 1787 } else { 1788 /* if the controller reset bit did clear, then set clock regs */ 1789 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 1790 dev_err(host->dev, 1791 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 1792 __func__); 1793 goto ciu_out; 1794 } 1795 } 1796 1797 if (host->use_dma == TRANS_MODE_IDMAC) 1798 /* It is also recommended that we reset and reprogram idmac */ 1799 dw_mci_idmac_reset(host); 1800 1801 ret = true; 1802 1803 ciu_out: 1804 /* After a CTRL reset we need to have CIU set clock registers */ 1805 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 1806 1807 return ret; 1808 } 1809 1810 static const struct mmc_host_ops dw_mci_ops = { 1811 .request = dw_mci_request, 1812 .pre_req = dw_mci_pre_req, 1813 .post_req = dw_mci_post_req, 1814 .set_ios = dw_mci_set_ios, 1815 .get_ro = dw_mci_get_ro, 1816 .get_cd = dw_mci_get_cd, 1817 .hw_reset = dw_mci_hw_reset, 1818 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1819 .ack_sdio_irq = dw_mci_ack_sdio_irq, 1820 .execute_tuning = dw_mci_execute_tuning, 1821 .card_busy = dw_mci_card_busy, 1822 .start_signal_voltage_switch = dw_mci_switch_voltage, 1823 .init_card = dw_mci_init_card, 1824 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1825 }; 1826 1827 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1828 __releases(&host->lock) 1829 __acquires(&host->lock) 1830 { 1831 struct dw_mci_slot *slot; 1832 struct mmc_host *prev_mmc = host->slot->mmc; 1833 1834 WARN_ON(host->cmd || host->data); 1835 1836 host->slot->mrq = NULL; 1837 host->mrq = NULL; 1838 if (!list_empty(&host->queue)) { 1839 slot = list_entry(host->queue.next, 1840 struct dw_mci_slot, queue_node); 1841 list_del(&slot->queue_node); 1842 dev_vdbg(host->dev, "list not empty: %s is next\n", 1843 mmc_hostname(slot->mmc)); 1844 host->state = STATE_SENDING_CMD; 1845 dw_mci_start_request(host, slot); 1846 } else { 1847 dev_vdbg(host->dev, "list empty\n"); 1848 1849 if (host->state == STATE_SENDING_CMD11) 1850 host->state = STATE_WAITING_CMD11_DONE; 1851 else 1852 host->state = STATE_IDLE; 1853 } 1854 1855 spin_unlock(&host->lock); 1856 mmc_request_done(prev_mmc, mrq); 1857 spin_lock(&host->lock); 1858 } 1859 1860 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1861 { 1862 u32 status = host->cmd_status; 1863 1864 host->cmd_status = 0; 1865 1866 /* Read the response from the card (up to 16 bytes) */ 1867 if (cmd->flags & MMC_RSP_PRESENT) { 1868 if (cmd->flags & MMC_RSP_136) { 1869 cmd->resp[3] = mci_readl(host, RESP0); 1870 cmd->resp[2] = mci_readl(host, RESP1); 1871 cmd->resp[1] = mci_readl(host, RESP2); 1872 cmd->resp[0] = mci_readl(host, RESP3); 1873 } else { 1874 cmd->resp[0] = mci_readl(host, RESP0); 1875 cmd->resp[1] = 0; 1876 cmd->resp[2] = 0; 1877 cmd->resp[3] = 0; 1878 } 1879 } 1880 1881 if (status & SDMMC_INT_RTO) 1882 cmd->error = -ETIMEDOUT; 1883 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1884 cmd->error = -EILSEQ; 1885 else if (status & SDMMC_INT_RESP_ERR) 1886 cmd->error = -EIO; 1887 else 1888 cmd->error = 0; 1889 1890 return cmd->error; 1891 } 1892 1893 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1894 { 1895 u32 status = host->data_status; 1896 1897 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1898 if (status & SDMMC_INT_DRTO) { 1899 data->error = -ETIMEDOUT; 1900 } else if (status & SDMMC_INT_DCRC) { 1901 data->error = -EILSEQ; 1902 } else if (status & SDMMC_INT_EBE) { 1903 if (host->dir_status == 1904 DW_MCI_SEND_STATUS) { 1905 /* 1906 * No data CRC status was returned. 1907 * The number of bytes transferred 1908 * will be exaggerated in PIO mode. 1909 */ 1910 data->bytes_xfered = 0; 1911 data->error = -ETIMEDOUT; 1912 } else if (host->dir_status == 1913 DW_MCI_RECV_STATUS) { 1914 data->error = -EILSEQ; 1915 } 1916 } else { 1917 /* SDMMC_INT_SBE is included */ 1918 data->error = -EILSEQ; 1919 } 1920 1921 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1922 1923 /* 1924 * After an error, there may be data lingering 1925 * in the FIFO 1926 */ 1927 dw_mci_reset(host); 1928 } else { 1929 data->bytes_xfered = data->blocks * data->blksz; 1930 data->error = 0; 1931 } 1932 1933 return data->error; 1934 } 1935 1936 static void dw_mci_set_drto(struct dw_mci *host) 1937 { 1938 unsigned int drto_clks; 1939 unsigned int drto_div; 1940 unsigned int drto_ms; 1941 unsigned long irqflags; 1942 1943 drto_clks = mci_readl(host, TMOUT) >> 8; 1944 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 1945 if (drto_div == 0) 1946 drto_div = 1; 1947 drto_ms = DIV_ROUND_UP(MSEC_PER_SEC * drto_clks * drto_div, 1948 host->bus_hz); 1949 1950 /* add a bit spare time */ 1951 drto_ms += 10; 1952 1953 spin_lock_irqsave(&host->irq_lock, irqflags); 1954 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1955 mod_timer(&host->dto_timer, 1956 jiffies + msecs_to_jiffies(drto_ms)); 1957 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1958 } 1959 1960 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host) 1961 { 1962 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1963 return false; 1964 1965 /* 1966 * Really be certain that the timer has stopped. This is a bit of 1967 * paranoia and could only really happen if we had really bad 1968 * interrupt latency and the interrupt routine and timeout were 1969 * running concurrently so that the del_timer() in the interrupt 1970 * handler couldn't run. 1971 */ 1972 WARN_ON(del_timer_sync(&host->cto_timer)); 1973 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1974 1975 return true; 1976 } 1977 1978 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host) 1979 { 1980 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1981 return false; 1982 1983 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */ 1984 WARN_ON(del_timer_sync(&host->dto_timer)); 1985 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1986 1987 return true; 1988 } 1989 1990 static void dw_mci_tasklet_func(unsigned long priv) 1991 { 1992 struct dw_mci *host = (struct dw_mci *)priv; 1993 struct mmc_data *data; 1994 struct mmc_command *cmd; 1995 struct mmc_request *mrq; 1996 enum dw_mci_state state; 1997 enum dw_mci_state prev_state; 1998 unsigned int err; 1999 2000 spin_lock(&host->lock); 2001 2002 state = host->state; 2003 data = host->data; 2004 mrq = host->mrq; 2005 2006 do { 2007 prev_state = state; 2008 2009 switch (state) { 2010 case STATE_IDLE: 2011 case STATE_WAITING_CMD11_DONE: 2012 break; 2013 2014 case STATE_SENDING_CMD11: 2015 case STATE_SENDING_CMD: 2016 if (!dw_mci_clear_pending_cmd_complete(host)) 2017 break; 2018 2019 cmd = host->cmd; 2020 host->cmd = NULL; 2021 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 2022 err = dw_mci_command_complete(host, cmd); 2023 if (cmd == mrq->sbc && !err) { 2024 prev_state = state = STATE_SENDING_CMD; 2025 __dw_mci_start_request(host, host->slot, 2026 mrq->cmd); 2027 goto unlock; 2028 } 2029 2030 if (cmd->data && err) { 2031 /* 2032 * During UHS tuning sequence, sending the stop 2033 * command after the response CRC error would 2034 * throw the system into a confused state 2035 * causing all future tuning phases to report 2036 * failure. 2037 * 2038 * In such case controller will move into a data 2039 * transfer state after a response error or 2040 * response CRC error. Let's let that finish 2041 * before trying to send a stop, so we'll go to 2042 * STATE_SENDING_DATA. 2043 * 2044 * Although letting the data transfer take place 2045 * will waste a bit of time (we already know 2046 * the command was bad), it can't cause any 2047 * errors since it's possible it would have 2048 * taken place anyway if this tasklet got 2049 * delayed. Allowing the transfer to take place 2050 * avoids races and keeps things simple. 2051 */ 2052 if ((err != -ETIMEDOUT) && 2053 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 2054 state = STATE_SENDING_DATA; 2055 continue; 2056 } 2057 2058 dw_mci_stop_dma(host); 2059 send_stop_abort(host, data); 2060 state = STATE_SENDING_STOP; 2061 break; 2062 } 2063 2064 if (!cmd->data || err) { 2065 dw_mci_request_end(host, mrq); 2066 goto unlock; 2067 } 2068 2069 prev_state = state = STATE_SENDING_DATA; 2070 /* fall through */ 2071 2072 case STATE_SENDING_DATA: 2073 /* 2074 * We could get a data error and never a transfer 2075 * complete so we'd better check for it here. 2076 * 2077 * Note that we don't really care if we also got a 2078 * transfer complete; stopping the DMA and sending an 2079 * abort won't hurt. 2080 */ 2081 if (test_and_clear_bit(EVENT_DATA_ERROR, 2082 &host->pending_events)) { 2083 dw_mci_stop_dma(host); 2084 if (!(host->data_status & (SDMMC_INT_DRTO | 2085 SDMMC_INT_EBE))) 2086 send_stop_abort(host, data); 2087 state = STATE_DATA_ERROR; 2088 break; 2089 } 2090 2091 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2092 &host->pending_events)) { 2093 /* 2094 * If all data-related interrupts don't come 2095 * within the given time in reading data state. 2096 */ 2097 if (host->dir_status == DW_MCI_RECV_STATUS) 2098 dw_mci_set_drto(host); 2099 break; 2100 } 2101 2102 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 2103 2104 /* 2105 * Handle an EVENT_DATA_ERROR that might have shown up 2106 * before the transfer completed. This might not have 2107 * been caught by the check above because the interrupt 2108 * could have gone off between the previous check and 2109 * the check for transfer complete. 2110 * 2111 * Technically this ought not be needed assuming we 2112 * get a DATA_COMPLETE eventually (we'll notice the 2113 * error and end the request), but it shouldn't hurt. 2114 * 2115 * This has the advantage of sending the stop command. 2116 */ 2117 if (test_and_clear_bit(EVENT_DATA_ERROR, 2118 &host->pending_events)) { 2119 dw_mci_stop_dma(host); 2120 if (!(host->data_status & (SDMMC_INT_DRTO | 2121 SDMMC_INT_EBE))) 2122 send_stop_abort(host, data); 2123 state = STATE_DATA_ERROR; 2124 break; 2125 } 2126 prev_state = state = STATE_DATA_BUSY; 2127 2128 /* fall through */ 2129 2130 case STATE_DATA_BUSY: 2131 if (!dw_mci_clear_pending_data_complete(host)) { 2132 /* 2133 * If data error interrupt comes but data over 2134 * interrupt doesn't come within the given time. 2135 * in reading data state. 2136 */ 2137 if (host->dir_status == DW_MCI_RECV_STATUS) 2138 dw_mci_set_drto(host); 2139 break; 2140 } 2141 2142 host->data = NULL; 2143 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2144 err = dw_mci_data_complete(host, data); 2145 2146 if (!err) { 2147 if (!data->stop || mrq->sbc) { 2148 if (mrq->sbc && data->stop) 2149 data->stop->error = 0; 2150 dw_mci_request_end(host, mrq); 2151 goto unlock; 2152 } 2153 2154 /* stop command for open-ended transfer*/ 2155 if (data->stop) 2156 send_stop_abort(host, data); 2157 } else { 2158 /* 2159 * If we don't have a command complete now we'll 2160 * never get one since we just reset everything; 2161 * better end the request. 2162 * 2163 * If we do have a command complete we'll fall 2164 * through to the SENDING_STOP command and 2165 * everything will be peachy keen. 2166 */ 2167 if (!test_bit(EVENT_CMD_COMPLETE, 2168 &host->pending_events)) { 2169 host->cmd = NULL; 2170 dw_mci_request_end(host, mrq); 2171 goto unlock; 2172 } 2173 } 2174 2175 /* 2176 * If err has non-zero, 2177 * stop-abort command has been already issued. 2178 */ 2179 prev_state = state = STATE_SENDING_STOP; 2180 2181 /* fall through */ 2182 2183 case STATE_SENDING_STOP: 2184 if (!dw_mci_clear_pending_cmd_complete(host)) 2185 break; 2186 2187 /* CMD error in data command */ 2188 if (mrq->cmd->error && mrq->data) 2189 dw_mci_reset(host); 2190 2191 host->cmd = NULL; 2192 host->data = NULL; 2193 2194 if (!mrq->sbc && mrq->stop) 2195 dw_mci_command_complete(host, mrq->stop); 2196 else 2197 host->cmd_status = 0; 2198 2199 dw_mci_request_end(host, mrq); 2200 goto unlock; 2201 2202 case STATE_DATA_ERROR: 2203 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2204 &host->pending_events)) 2205 break; 2206 2207 state = STATE_DATA_BUSY; 2208 break; 2209 } 2210 } while (state != prev_state); 2211 2212 host->state = state; 2213 unlock: 2214 spin_unlock(&host->lock); 2215 2216 } 2217 2218 /* push final bytes to part_buf, only use during push */ 2219 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 2220 { 2221 memcpy((void *)&host->part_buf, buf, cnt); 2222 host->part_buf_count = cnt; 2223 } 2224 2225 /* append bytes to part_buf, only use during push */ 2226 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 2227 { 2228 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 2229 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 2230 host->part_buf_count += cnt; 2231 return cnt; 2232 } 2233 2234 /* pull first bytes from part_buf, only use during pull */ 2235 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 2236 { 2237 cnt = min_t(int, cnt, host->part_buf_count); 2238 if (cnt) { 2239 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 2240 cnt); 2241 host->part_buf_count -= cnt; 2242 host->part_buf_start += cnt; 2243 } 2244 return cnt; 2245 } 2246 2247 /* pull final bytes from the part_buf, assuming it's just been filled */ 2248 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 2249 { 2250 memcpy(buf, &host->part_buf, cnt); 2251 host->part_buf_start = cnt; 2252 host->part_buf_count = (1 << host->data_shift) - cnt; 2253 } 2254 2255 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2256 { 2257 struct mmc_data *data = host->data; 2258 int init_cnt = cnt; 2259 2260 /* try and push anything in the part_buf */ 2261 if (unlikely(host->part_buf_count)) { 2262 int len = dw_mci_push_part_bytes(host, buf, cnt); 2263 2264 buf += len; 2265 cnt -= len; 2266 if (host->part_buf_count == 2) { 2267 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2268 host->part_buf_count = 0; 2269 } 2270 } 2271 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2272 if (unlikely((unsigned long)buf & 0x1)) { 2273 while (cnt >= 2) { 2274 u16 aligned_buf[64]; 2275 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2276 int items = len >> 1; 2277 int i; 2278 /* memcpy from input buffer into aligned buffer */ 2279 memcpy(aligned_buf, buf, len); 2280 buf += len; 2281 cnt -= len; 2282 /* push data from aligned buffer into fifo */ 2283 for (i = 0; i < items; ++i) 2284 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 2285 } 2286 } else 2287 #endif 2288 { 2289 u16 *pdata = buf; 2290 2291 for (; cnt >= 2; cnt -= 2) 2292 mci_fifo_writew(host->fifo_reg, *pdata++); 2293 buf = pdata; 2294 } 2295 /* put anything remaining in the part_buf */ 2296 if (cnt) { 2297 dw_mci_set_part_bytes(host, buf, cnt); 2298 /* Push data if we have reached the expected data length */ 2299 if ((data->bytes_xfered + init_cnt) == 2300 (data->blksz * data->blocks)) 2301 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2302 } 2303 } 2304 2305 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2306 { 2307 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2308 if (unlikely((unsigned long)buf & 0x1)) { 2309 while (cnt >= 2) { 2310 /* pull data from fifo into aligned buffer */ 2311 u16 aligned_buf[64]; 2312 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2313 int items = len >> 1; 2314 int i; 2315 2316 for (i = 0; i < items; ++i) 2317 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 2318 /* memcpy from aligned buffer into output buffer */ 2319 memcpy(buf, aligned_buf, len); 2320 buf += len; 2321 cnt -= len; 2322 } 2323 } else 2324 #endif 2325 { 2326 u16 *pdata = buf; 2327 2328 for (; cnt >= 2; cnt -= 2) 2329 *pdata++ = mci_fifo_readw(host->fifo_reg); 2330 buf = pdata; 2331 } 2332 if (cnt) { 2333 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 2334 dw_mci_pull_final_bytes(host, buf, cnt); 2335 } 2336 } 2337 2338 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2339 { 2340 struct mmc_data *data = host->data; 2341 int init_cnt = cnt; 2342 2343 /* try and push anything in the part_buf */ 2344 if (unlikely(host->part_buf_count)) { 2345 int len = dw_mci_push_part_bytes(host, buf, cnt); 2346 2347 buf += len; 2348 cnt -= len; 2349 if (host->part_buf_count == 4) { 2350 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2351 host->part_buf_count = 0; 2352 } 2353 } 2354 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2355 if (unlikely((unsigned long)buf & 0x3)) { 2356 while (cnt >= 4) { 2357 u32 aligned_buf[32]; 2358 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2359 int items = len >> 2; 2360 int i; 2361 /* memcpy from input buffer into aligned buffer */ 2362 memcpy(aligned_buf, buf, len); 2363 buf += len; 2364 cnt -= len; 2365 /* push data from aligned buffer into fifo */ 2366 for (i = 0; i < items; ++i) 2367 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 2368 } 2369 } else 2370 #endif 2371 { 2372 u32 *pdata = buf; 2373 2374 for (; cnt >= 4; cnt -= 4) 2375 mci_fifo_writel(host->fifo_reg, *pdata++); 2376 buf = pdata; 2377 } 2378 /* put anything remaining in the part_buf */ 2379 if (cnt) { 2380 dw_mci_set_part_bytes(host, buf, cnt); 2381 /* Push data if we have reached the expected data length */ 2382 if ((data->bytes_xfered + init_cnt) == 2383 (data->blksz * data->blocks)) 2384 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2385 } 2386 } 2387 2388 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2389 { 2390 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2391 if (unlikely((unsigned long)buf & 0x3)) { 2392 while (cnt >= 4) { 2393 /* pull data from fifo into aligned buffer */ 2394 u32 aligned_buf[32]; 2395 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2396 int items = len >> 2; 2397 int i; 2398 2399 for (i = 0; i < items; ++i) 2400 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 2401 /* memcpy from aligned buffer into output buffer */ 2402 memcpy(buf, aligned_buf, len); 2403 buf += len; 2404 cnt -= len; 2405 } 2406 } else 2407 #endif 2408 { 2409 u32 *pdata = buf; 2410 2411 for (; cnt >= 4; cnt -= 4) 2412 *pdata++ = mci_fifo_readl(host->fifo_reg); 2413 buf = pdata; 2414 } 2415 if (cnt) { 2416 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 2417 dw_mci_pull_final_bytes(host, buf, cnt); 2418 } 2419 } 2420 2421 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2422 { 2423 struct mmc_data *data = host->data; 2424 int init_cnt = cnt; 2425 2426 /* try and push anything in the part_buf */ 2427 if (unlikely(host->part_buf_count)) { 2428 int len = dw_mci_push_part_bytes(host, buf, cnt); 2429 2430 buf += len; 2431 cnt -= len; 2432 2433 if (host->part_buf_count == 8) { 2434 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2435 host->part_buf_count = 0; 2436 } 2437 } 2438 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2439 if (unlikely((unsigned long)buf & 0x7)) { 2440 while (cnt >= 8) { 2441 u64 aligned_buf[16]; 2442 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2443 int items = len >> 3; 2444 int i; 2445 /* memcpy from input buffer into aligned buffer */ 2446 memcpy(aligned_buf, buf, len); 2447 buf += len; 2448 cnt -= len; 2449 /* push data from aligned buffer into fifo */ 2450 for (i = 0; i < items; ++i) 2451 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2452 } 2453 } else 2454 #endif 2455 { 2456 u64 *pdata = buf; 2457 2458 for (; cnt >= 8; cnt -= 8) 2459 mci_fifo_writeq(host->fifo_reg, *pdata++); 2460 buf = pdata; 2461 } 2462 /* put anything remaining in the part_buf */ 2463 if (cnt) { 2464 dw_mci_set_part_bytes(host, buf, cnt); 2465 /* Push data if we have reached the expected data length */ 2466 if ((data->bytes_xfered + init_cnt) == 2467 (data->blksz * data->blocks)) 2468 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2469 } 2470 } 2471 2472 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2473 { 2474 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2475 if (unlikely((unsigned long)buf & 0x7)) { 2476 while (cnt >= 8) { 2477 /* pull data from fifo into aligned buffer */ 2478 u64 aligned_buf[16]; 2479 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2480 int items = len >> 3; 2481 int i; 2482 2483 for (i = 0; i < items; ++i) 2484 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2485 2486 /* memcpy from aligned buffer into output buffer */ 2487 memcpy(buf, aligned_buf, len); 2488 buf += len; 2489 cnt -= len; 2490 } 2491 } else 2492 #endif 2493 { 2494 u64 *pdata = buf; 2495 2496 for (; cnt >= 8; cnt -= 8) 2497 *pdata++ = mci_fifo_readq(host->fifo_reg); 2498 buf = pdata; 2499 } 2500 if (cnt) { 2501 host->part_buf = mci_fifo_readq(host->fifo_reg); 2502 dw_mci_pull_final_bytes(host, buf, cnt); 2503 } 2504 } 2505 2506 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2507 { 2508 int len; 2509 2510 /* get remaining partial bytes */ 2511 len = dw_mci_pull_part_bytes(host, buf, cnt); 2512 if (unlikely(len == cnt)) 2513 return; 2514 buf += len; 2515 cnt -= len; 2516 2517 /* get the rest of the data */ 2518 host->pull_data(host, buf, cnt); 2519 } 2520 2521 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2522 { 2523 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2524 void *buf; 2525 unsigned int offset; 2526 struct mmc_data *data = host->data; 2527 int shift = host->data_shift; 2528 u32 status; 2529 unsigned int len; 2530 unsigned int remain, fcnt; 2531 2532 do { 2533 if (!sg_miter_next(sg_miter)) 2534 goto done; 2535 2536 host->sg = sg_miter->piter.sg; 2537 buf = sg_miter->addr; 2538 remain = sg_miter->length; 2539 offset = 0; 2540 2541 do { 2542 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2543 << shift) + host->part_buf_count; 2544 len = min(remain, fcnt); 2545 if (!len) 2546 break; 2547 dw_mci_pull_data(host, (void *)(buf + offset), len); 2548 data->bytes_xfered += len; 2549 offset += len; 2550 remain -= len; 2551 } while (remain); 2552 2553 sg_miter->consumed = offset; 2554 status = mci_readl(host, MINTSTS); 2555 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2556 /* if the RXDR is ready read again */ 2557 } while ((status & SDMMC_INT_RXDR) || 2558 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2559 2560 if (!remain) { 2561 if (!sg_miter_next(sg_miter)) 2562 goto done; 2563 sg_miter->consumed = 0; 2564 } 2565 sg_miter_stop(sg_miter); 2566 return; 2567 2568 done: 2569 sg_miter_stop(sg_miter); 2570 host->sg = NULL; 2571 smp_wmb(); /* drain writebuffer */ 2572 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2573 } 2574 2575 static void dw_mci_write_data_pio(struct dw_mci *host) 2576 { 2577 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2578 void *buf; 2579 unsigned int offset; 2580 struct mmc_data *data = host->data; 2581 int shift = host->data_shift; 2582 u32 status; 2583 unsigned int len; 2584 unsigned int fifo_depth = host->fifo_depth; 2585 unsigned int remain, fcnt; 2586 2587 do { 2588 if (!sg_miter_next(sg_miter)) 2589 goto done; 2590 2591 host->sg = sg_miter->piter.sg; 2592 buf = sg_miter->addr; 2593 remain = sg_miter->length; 2594 offset = 0; 2595 2596 do { 2597 fcnt = ((fifo_depth - 2598 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2599 << shift) - host->part_buf_count; 2600 len = min(remain, fcnt); 2601 if (!len) 2602 break; 2603 host->push_data(host, (void *)(buf + offset), len); 2604 data->bytes_xfered += len; 2605 offset += len; 2606 remain -= len; 2607 } while (remain); 2608 2609 sg_miter->consumed = offset; 2610 status = mci_readl(host, MINTSTS); 2611 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2612 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2613 2614 if (!remain) { 2615 if (!sg_miter_next(sg_miter)) 2616 goto done; 2617 sg_miter->consumed = 0; 2618 } 2619 sg_miter_stop(sg_miter); 2620 return; 2621 2622 done: 2623 sg_miter_stop(sg_miter); 2624 host->sg = NULL; 2625 smp_wmb(); /* drain writebuffer */ 2626 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2627 } 2628 2629 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2630 { 2631 del_timer(&host->cto_timer); 2632 2633 if (!host->cmd_status) 2634 host->cmd_status = status; 2635 2636 smp_wmb(); /* drain writebuffer */ 2637 2638 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2639 tasklet_schedule(&host->tasklet); 2640 } 2641 2642 static void dw_mci_handle_cd(struct dw_mci *host) 2643 { 2644 struct dw_mci_slot *slot = host->slot; 2645 2646 if (slot->mmc->ops->card_event) 2647 slot->mmc->ops->card_event(slot->mmc); 2648 mmc_detect_change(slot->mmc, 2649 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2650 } 2651 2652 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2653 { 2654 struct dw_mci *host = dev_id; 2655 u32 pending; 2656 struct dw_mci_slot *slot = host->slot; 2657 unsigned long irqflags; 2658 2659 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2660 2661 if (pending) { 2662 /* Check volt switch first, since it can look like an error */ 2663 if ((host->state == STATE_SENDING_CMD11) && 2664 (pending & SDMMC_INT_VOLT_SWITCH)) { 2665 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2666 pending &= ~SDMMC_INT_VOLT_SWITCH; 2667 2668 /* 2669 * Hold the lock; we know cmd11_timer can't be kicked 2670 * off after the lock is released, so safe to delete. 2671 */ 2672 spin_lock_irqsave(&host->irq_lock, irqflags); 2673 dw_mci_cmd_interrupt(host, pending); 2674 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2675 2676 del_timer(&host->cmd11_timer); 2677 } 2678 2679 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2680 spin_lock_irqsave(&host->irq_lock, irqflags); 2681 2682 del_timer(&host->cto_timer); 2683 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2684 host->cmd_status = pending; 2685 smp_wmb(); /* drain writebuffer */ 2686 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2687 2688 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2689 } 2690 2691 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2692 /* if there is an error report DATA_ERROR */ 2693 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2694 host->data_status = pending; 2695 smp_wmb(); /* drain writebuffer */ 2696 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2697 tasklet_schedule(&host->tasklet); 2698 } 2699 2700 if (pending & SDMMC_INT_DATA_OVER) { 2701 spin_lock_irqsave(&host->irq_lock, irqflags); 2702 2703 del_timer(&host->dto_timer); 2704 2705 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2706 if (!host->data_status) 2707 host->data_status = pending; 2708 smp_wmb(); /* drain writebuffer */ 2709 if (host->dir_status == DW_MCI_RECV_STATUS) { 2710 if (host->sg != NULL) 2711 dw_mci_read_data_pio(host, true); 2712 } 2713 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2714 tasklet_schedule(&host->tasklet); 2715 2716 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2717 } 2718 2719 if (pending & SDMMC_INT_RXDR) { 2720 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2721 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2722 dw_mci_read_data_pio(host, false); 2723 } 2724 2725 if (pending & SDMMC_INT_TXDR) { 2726 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2727 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2728 dw_mci_write_data_pio(host); 2729 } 2730 2731 if (pending & SDMMC_INT_CMD_DONE) { 2732 spin_lock_irqsave(&host->irq_lock, irqflags); 2733 2734 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2735 dw_mci_cmd_interrupt(host, pending); 2736 2737 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2738 } 2739 2740 if (pending & SDMMC_INT_CD) { 2741 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2742 dw_mci_handle_cd(host); 2743 } 2744 2745 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2746 mci_writel(host, RINTSTS, 2747 SDMMC_INT_SDIO(slot->sdio_id)); 2748 __dw_mci_enable_sdio_irq(slot, 0); 2749 sdio_signal_irq(slot->mmc); 2750 } 2751 2752 } 2753 2754 if (host->use_dma != TRANS_MODE_IDMAC) 2755 return IRQ_HANDLED; 2756 2757 /* Handle IDMA interrupts */ 2758 if (host->dma_64bit_address == 1) { 2759 pending = mci_readl(host, IDSTS64); 2760 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2761 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2762 SDMMC_IDMAC_INT_RI); 2763 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2764 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2765 host->dma_ops->complete((void *)host); 2766 } 2767 } else { 2768 pending = mci_readl(host, IDSTS); 2769 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2770 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2771 SDMMC_IDMAC_INT_RI); 2772 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2773 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2774 host->dma_ops->complete((void *)host); 2775 } 2776 } 2777 2778 return IRQ_HANDLED; 2779 } 2780 2781 static int dw_mci_init_slot(struct dw_mci *host) 2782 { 2783 struct mmc_host *mmc; 2784 struct dw_mci_slot *slot; 2785 const struct dw_mci_drv_data *drv_data = host->drv_data; 2786 int ctrl_id, ret; 2787 u32 freq[2]; 2788 2789 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2790 if (!mmc) 2791 return -ENOMEM; 2792 2793 slot = mmc_priv(mmc); 2794 slot->id = 0; 2795 slot->sdio_id = host->sdio_id0 + slot->id; 2796 slot->mmc = mmc; 2797 slot->host = host; 2798 host->slot = slot; 2799 2800 mmc->ops = &dw_mci_ops; 2801 if (device_property_read_u32_array(host->dev, "clock-freq-min-max", 2802 freq, 2)) { 2803 mmc->f_min = DW_MCI_FREQ_MIN; 2804 mmc->f_max = DW_MCI_FREQ_MAX; 2805 } else { 2806 dev_info(host->dev, 2807 "'clock-freq-min-max' property was deprecated.\n"); 2808 mmc->f_min = freq[0]; 2809 mmc->f_max = freq[1]; 2810 } 2811 2812 /*if there are external regulators, get them*/ 2813 ret = mmc_regulator_get_supply(mmc); 2814 if (ret) 2815 goto err_host_allocated; 2816 2817 if (!mmc->ocr_avail) 2818 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2819 2820 if (host->pdata->caps) 2821 mmc->caps = host->pdata->caps; 2822 2823 /* 2824 * Support MMC_CAP_ERASE by default. 2825 * It needs to use trim/discard/erase commands. 2826 */ 2827 mmc->caps |= MMC_CAP_ERASE; 2828 2829 if (host->pdata->pm_caps) 2830 mmc->pm_caps = host->pdata->pm_caps; 2831 2832 if (host->dev->of_node) { 2833 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2834 if (ctrl_id < 0) 2835 ctrl_id = 0; 2836 } else { 2837 ctrl_id = to_platform_device(host->dev)->id; 2838 } 2839 if (drv_data && drv_data->caps) 2840 mmc->caps |= drv_data->caps[ctrl_id]; 2841 2842 if (host->pdata->caps2) 2843 mmc->caps2 = host->pdata->caps2; 2844 2845 ret = mmc_of_parse(mmc); 2846 if (ret) 2847 goto err_host_allocated; 2848 2849 /* Process SDIO IRQs through the sdio_irq_work. */ 2850 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2851 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2852 2853 /* Useful defaults if platform data is unset. */ 2854 if (host->use_dma == TRANS_MODE_IDMAC) { 2855 mmc->max_segs = host->ring_size; 2856 mmc->max_blk_size = 65535; 2857 mmc->max_seg_size = 0x1000; 2858 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2859 mmc->max_blk_count = mmc->max_req_size / 512; 2860 } else if (host->use_dma == TRANS_MODE_EDMAC) { 2861 mmc->max_segs = 64; 2862 mmc->max_blk_size = 65535; 2863 mmc->max_blk_count = 65535; 2864 mmc->max_req_size = 2865 mmc->max_blk_size * mmc->max_blk_count; 2866 mmc->max_seg_size = mmc->max_req_size; 2867 } else { 2868 /* TRANS_MODE_PIO */ 2869 mmc->max_segs = 64; 2870 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2871 mmc->max_blk_count = 512; 2872 mmc->max_req_size = mmc->max_blk_size * 2873 mmc->max_blk_count; 2874 mmc->max_seg_size = mmc->max_req_size; 2875 } 2876 2877 dw_mci_get_cd(mmc); 2878 2879 ret = mmc_add_host(mmc); 2880 if (ret) 2881 goto err_host_allocated; 2882 2883 #if defined(CONFIG_DEBUG_FS) 2884 dw_mci_init_debugfs(slot); 2885 #endif 2886 2887 return 0; 2888 2889 err_host_allocated: 2890 mmc_free_host(mmc); 2891 return ret; 2892 } 2893 2894 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2895 { 2896 /* Debugfs stuff is cleaned up by mmc core */ 2897 mmc_remove_host(slot->mmc); 2898 slot->host->slot = NULL; 2899 mmc_free_host(slot->mmc); 2900 } 2901 2902 static void dw_mci_init_dma(struct dw_mci *host) 2903 { 2904 int addr_config; 2905 struct device *dev = host->dev; 2906 2907 /* 2908 * Check tansfer mode from HCON[17:16] 2909 * Clear the ambiguous description of dw_mmc databook: 2910 * 2b'00: No DMA Interface -> Actually means using Internal DMA block 2911 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 2912 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 2913 * 2b'11: Non DW DMA Interface -> pio only 2914 * Compared to DesignWare DMA Interface, Generic DMA Interface has a 2915 * simpler request/acknowledge handshake mechanism and both of them 2916 * are regarded as external dma master for dw_mmc. 2917 */ 2918 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 2919 if (host->use_dma == DMA_INTERFACE_IDMA) { 2920 host->use_dma = TRANS_MODE_IDMAC; 2921 } else if (host->use_dma == DMA_INTERFACE_DWDMA || 2922 host->use_dma == DMA_INTERFACE_GDMA) { 2923 host->use_dma = TRANS_MODE_EDMAC; 2924 } else { 2925 goto no_dma; 2926 } 2927 2928 /* Determine which DMA interface to use */ 2929 if (host->use_dma == TRANS_MODE_IDMAC) { 2930 /* 2931 * Check ADDR_CONFIG bit in HCON to find 2932 * IDMAC address bus width 2933 */ 2934 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 2935 2936 if (addr_config == 1) { 2937 /* host supports IDMAC in 64-bit address mode */ 2938 host->dma_64bit_address = 1; 2939 dev_info(host->dev, 2940 "IDMAC supports 64-bit address mode.\n"); 2941 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2942 dma_set_coherent_mask(host->dev, 2943 DMA_BIT_MASK(64)); 2944 } else { 2945 /* host supports IDMAC in 32-bit address mode */ 2946 host->dma_64bit_address = 0; 2947 dev_info(host->dev, 2948 "IDMAC supports 32-bit address mode.\n"); 2949 } 2950 2951 /* Alloc memory for sg translation */ 2952 host->sg_cpu = dmam_alloc_coherent(host->dev, 2953 DESC_RING_BUF_SZ, 2954 &host->sg_dma, GFP_KERNEL); 2955 if (!host->sg_cpu) { 2956 dev_err(host->dev, 2957 "%s: could not alloc DMA memory\n", 2958 __func__); 2959 goto no_dma; 2960 } 2961 2962 host->dma_ops = &dw_mci_idmac_ops; 2963 dev_info(host->dev, "Using internal DMA controller.\n"); 2964 } else { 2965 /* TRANS_MODE_EDMAC: check dma bindings again */ 2966 if ((device_property_read_string_array(dev, "dma-names", 2967 NULL, 0) < 0) || 2968 !device_property_present(dev, "dmas")) { 2969 goto no_dma; 2970 } 2971 host->dma_ops = &dw_mci_edmac_ops; 2972 dev_info(host->dev, "Using external DMA controller.\n"); 2973 } 2974 2975 if (host->dma_ops->init && host->dma_ops->start && 2976 host->dma_ops->stop && host->dma_ops->cleanup) { 2977 if (host->dma_ops->init(host)) { 2978 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 2979 __func__); 2980 goto no_dma; 2981 } 2982 } else { 2983 dev_err(host->dev, "DMA initialization not found.\n"); 2984 goto no_dma; 2985 } 2986 2987 return; 2988 2989 no_dma: 2990 dev_info(host->dev, "Using PIO mode.\n"); 2991 host->use_dma = TRANS_MODE_PIO; 2992 } 2993 2994 static void dw_mci_cmd11_timer(struct timer_list *t) 2995 { 2996 struct dw_mci *host = from_timer(host, t, cmd11_timer); 2997 2998 if (host->state != STATE_SENDING_CMD11) { 2999 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 3000 return; 3001 } 3002 3003 host->cmd_status = SDMMC_INT_RTO; 3004 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3005 tasklet_schedule(&host->tasklet); 3006 } 3007 3008 static void dw_mci_cto_timer(struct timer_list *t) 3009 { 3010 struct dw_mci *host = from_timer(host, t, cto_timer); 3011 unsigned long irqflags; 3012 u32 pending; 3013 3014 spin_lock_irqsave(&host->irq_lock, irqflags); 3015 3016 /* 3017 * If somehow we have very bad interrupt latency it's remotely possible 3018 * that the timer could fire while the interrupt is still pending or 3019 * while the interrupt is midway through running. Let's be paranoid 3020 * and detect those two cases. Note that this is paranoia is somewhat 3021 * justified because in this function we don't actually cancel the 3022 * pending command in the controller--we just assume it will never come. 3023 */ 3024 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3025 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) { 3026 /* The interrupt should fire; no need to act but we can warn */ 3027 dev_warn(host->dev, "Unexpected interrupt latency\n"); 3028 goto exit; 3029 } 3030 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { 3031 /* Presumably interrupt handler couldn't delete the timer */ 3032 dev_warn(host->dev, "CTO timeout when already completed\n"); 3033 goto exit; 3034 } 3035 3036 /* 3037 * Continued paranoia to make sure we're in the state we expect. 3038 * This paranoia isn't really justified but it seems good to be safe. 3039 */ 3040 switch (host->state) { 3041 case STATE_SENDING_CMD11: 3042 case STATE_SENDING_CMD: 3043 case STATE_SENDING_STOP: 3044 /* 3045 * If CMD_DONE interrupt does NOT come in sending command 3046 * state, we should notify the driver to terminate current 3047 * transfer and report a command timeout to the core. 3048 */ 3049 host->cmd_status = SDMMC_INT_RTO; 3050 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3051 tasklet_schedule(&host->tasklet); 3052 break; 3053 default: 3054 dev_warn(host->dev, "Unexpected command timeout, state %d\n", 3055 host->state); 3056 break; 3057 } 3058 3059 exit: 3060 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3061 } 3062 3063 static void dw_mci_dto_timer(struct timer_list *t) 3064 { 3065 struct dw_mci *host = from_timer(host, t, dto_timer); 3066 unsigned long irqflags; 3067 u32 pending; 3068 3069 spin_lock_irqsave(&host->irq_lock, irqflags); 3070 3071 /* 3072 * The DTO timer is much longer than the CTO timer, so it's even less 3073 * likely that we'll these cases, but it pays to be paranoid. 3074 */ 3075 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3076 if (pending & SDMMC_INT_DATA_OVER) { 3077 /* The interrupt should fire; no need to act but we can warn */ 3078 dev_warn(host->dev, "Unexpected data interrupt latency\n"); 3079 goto exit; 3080 } 3081 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { 3082 /* Presumably interrupt handler couldn't delete the timer */ 3083 dev_warn(host->dev, "DTO timeout when already completed\n"); 3084 goto exit; 3085 } 3086 3087 /* 3088 * Continued paranoia to make sure we're in the state we expect. 3089 * This paranoia isn't really justified but it seems good to be safe. 3090 */ 3091 switch (host->state) { 3092 case STATE_SENDING_DATA: 3093 case STATE_DATA_BUSY: 3094 /* 3095 * If DTO interrupt does NOT come in sending data state, 3096 * we should notify the driver to terminate current transfer 3097 * and report a data timeout to the core. 3098 */ 3099 host->data_status = SDMMC_INT_DRTO; 3100 set_bit(EVENT_DATA_ERROR, &host->pending_events); 3101 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 3102 tasklet_schedule(&host->tasklet); 3103 break; 3104 default: 3105 dev_warn(host->dev, "Unexpected data timeout, state %d\n", 3106 host->state); 3107 break; 3108 } 3109 3110 exit: 3111 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3112 } 3113 3114 #ifdef CONFIG_OF 3115 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3116 { 3117 struct dw_mci_board *pdata; 3118 struct device *dev = host->dev; 3119 const struct dw_mci_drv_data *drv_data = host->drv_data; 3120 int ret; 3121 u32 clock_frequency; 3122 3123 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3124 if (!pdata) 3125 return ERR_PTR(-ENOMEM); 3126 3127 /* find reset controller when exist */ 3128 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 3129 if (IS_ERR(pdata->rstc)) { 3130 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 3131 return ERR_PTR(-EPROBE_DEFER); 3132 } 3133 3134 /* find out number of slots supported */ 3135 if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots)) 3136 dev_info(dev, "'num-slots' was deprecated.\n"); 3137 3138 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 3139 dev_info(dev, 3140 "fifo-depth property not found, using value of FIFOTH register as default\n"); 3141 3142 device_property_read_u32(dev, "card-detect-delay", 3143 &pdata->detect_delay_ms); 3144 3145 device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3146 3147 if (device_property_present(dev, "fifo-watermark-aligned")) 3148 host->wm_aligned = true; 3149 3150 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 3151 pdata->bus_hz = clock_frequency; 3152 3153 if (drv_data && drv_data->parse_dt) { 3154 ret = drv_data->parse_dt(host); 3155 if (ret) 3156 return ERR_PTR(ret); 3157 } 3158 3159 return pdata; 3160 } 3161 3162 #else /* CONFIG_OF */ 3163 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3164 { 3165 return ERR_PTR(-EINVAL); 3166 } 3167 #endif /* CONFIG_OF */ 3168 3169 static void dw_mci_enable_cd(struct dw_mci *host) 3170 { 3171 unsigned long irqflags; 3172 u32 temp; 3173 3174 /* 3175 * No need for CD if all slots have a non-error GPIO 3176 * as well as broken card detection is found. 3177 */ 3178 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3179 return; 3180 3181 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3182 spin_lock_irqsave(&host->irq_lock, irqflags); 3183 temp = mci_readl(host, INTMASK); 3184 temp |= SDMMC_INT_CD; 3185 mci_writel(host, INTMASK, temp); 3186 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3187 } 3188 } 3189 3190 int dw_mci_probe(struct dw_mci *host) 3191 { 3192 const struct dw_mci_drv_data *drv_data = host->drv_data; 3193 int width, i, ret = 0; 3194 u32 fifo_size; 3195 3196 if (!host->pdata) { 3197 host->pdata = dw_mci_parse_dt(host); 3198 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3199 return -EPROBE_DEFER; 3200 } else if (IS_ERR(host->pdata)) { 3201 dev_err(host->dev, "platform data not available\n"); 3202 return -EINVAL; 3203 } 3204 } 3205 3206 host->biu_clk = devm_clk_get(host->dev, "biu"); 3207 if (IS_ERR(host->biu_clk)) { 3208 dev_dbg(host->dev, "biu clock not available\n"); 3209 } else { 3210 ret = clk_prepare_enable(host->biu_clk); 3211 if (ret) { 3212 dev_err(host->dev, "failed to enable biu clock\n"); 3213 return ret; 3214 } 3215 } 3216 3217 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3218 if (IS_ERR(host->ciu_clk)) { 3219 dev_dbg(host->dev, "ciu clock not available\n"); 3220 host->bus_hz = host->pdata->bus_hz; 3221 } else { 3222 ret = clk_prepare_enable(host->ciu_clk); 3223 if (ret) { 3224 dev_err(host->dev, "failed to enable ciu clock\n"); 3225 goto err_clk_biu; 3226 } 3227 3228 if (host->pdata->bus_hz) { 3229 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 3230 if (ret) 3231 dev_warn(host->dev, 3232 "Unable to set bus rate to %uHz\n", 3233 host->pdata->bus_hz); 3234 } 3235 host->bus_hz = clk_get_rate(host->ciu_clk); 3236 } 3237 3238 if (!host->bus_hz) { 3239 dev_err(host->dev, 3240 "Platform data must supply bus speed\n"); 3241 ret = -ENODEV; 3242 goto err_clk_ciu; 3243 } 3244 3245 if (!IS_ERR(host->pdata->rstc)) { 3246 reset_control_assert(host->pdata->rstc); 3247 usleep_range(10, 50); 3248 reset_control_deassert(host->pdata->rstc); 3249 } 3250 3251 if (drv_data && drv_data->init) { 3252 ret = drv_data->init(host); 3253 if (ret) { 3254 dev_err(host->dev, 3255 "implementation specific init failed\n"); 3256 goto err_clk_ciu; 3257 } 3258 } 3259 3260 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); 3261 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); 3262 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); 3263 3264 spin_lock_init(&host->lock); 3265 spin_lock_init(&host->irq_lock); 3266 INIT_LIST_HEAD(&host->queue); 3267 3268 /* 3269 * Get the host data width - this assumes that HCON has been set with 3270 * the correct values. 3271 */ 3272 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3273 if (!i) { 3274 host->push_data = dw_mci_push_data16; 3275 host->pull_data = dw_mci_pull_data16; 3276 width = 16; 3277 host->data_shift = 1; 3278 } else if (i == 2) { 3279 host->push_data = dw_mci_push_data64; 3280 host->pull_data = dw_mci_pull_data64; 3281 width = 64; 3282 host->data_shift = 3; 3283 } else { 3284 /* Check for a reserved value, and warn if it is */ 3285 WARN((i != 1), 3286 "HCON reports a reserved host data width!\n" 3287 "Defaulting to 32-bit access.\n"); 3288 host->push_data = dw_mci_push_data32; 3289 host->pull_data = dw_mci_pull_data32; 3290 width = 32; 3291 host->data_shift = 2; 3292 } 3293 3294 /* Reset all blocks */ 3295 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3296 ret = -ENODEV; 3297 goto err_clk_ciu; 3298 } 3299 3300 host->dma_ops = host->pdata->dma_ops; 3301 dw_mci_init_dma(host); 3302 3303 /* Clear the interrupts for the host controller */ 3304 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3305 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3306 3307 /* Put in max timeout */ 3308 mci_writel(host, TMOUT, 0xFFFFFFFF); 3309 3310 /* 3311 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3312 * Tx Mark = fifo_size / 2 DMA Size = 8 3313 */ 3314 if (!host->pdata->fifo_depth) { 3315 /* 3316 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3317 * have been overwritten by the bootloader, just like we're 3318 * about to do, so if you know the value for your hardware, you 3319 * should put it in the platform data. 3320 */ 3321 fifo_size = mci_readl(host, FIFOTH); 3322 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3323 } else { 3324 fifo_size = host->pdata->fifo_depth; 3325 } 3326 host->fifo_depth = fifo_size; 3327 host->fifoth_val = 3328 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3329 mci_writel(host, FIFOTH, host->fifoth_val); 3330 3331 /* disable clock to CIU */ 3332 mci_writel(host, CLKENA, 0); 3333 mci_writel(host, CLKSRC, 0); 3334 3335 /* 3336 * In 2.40a spec, Data offset is changed. 3337 * Need to check the version-id and set data-offset for DATA register. 3338 */ 3339 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 3340 dev_info(host->dev, "Version ID is %04x\n", host->verid); 3341 3342 if (host->data_addr_override) 3343 host->fifo_reg = host->regs + host->data_addr_override; 3344 else if (host->verid < DW_MMC_240A) 3345 host->fifo_reg = host->regs + DATA_OFFSET; 3346 else 3347 host->fifo_reg = host->regs + DATA_240A_OFFSET; 3348 3349 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3350 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3351 host->irq_flags, "dw-mci", host); 3352 if (ret) 3353 goto err_dmaunmap; 3354 3355 /* 3356 * Enable interrupts for command done, data over, data empty, 3357 * receive ready and error such as transmit, receive timeout, crc error 3358 */ 3359 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3360 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3361 DW_MCI_ERROR_FLAGS); 3362 /* Enable mci interrupt */ 3363 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3364 3365 dev_info(host->dev, 3366 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 3367 host->irq, width, fifo_size); 3368 3369 /* We need at least one slot to succeed */ 3370 ret = dw_mci_init_slot(host); 3371 if (ret) { 3372 dev_dbg(host->dev, "slot %d init failed\n", i); 3373 goto err_dmaunmap; 3374 } 3375 3376 /* Now that slots are all setup, we can enable card detect */ 3377 dw_mci_enable_cd(host); 3378 3379 return 0; 3380 3381 err_dmaunmap: 3382 if (host->use_dma && host->dma_ops->exit) 3383 host->dma_ops->exit(host); 3384 3385 if (!IS_ERR(host->pdata->rstc)) 3386 reset_control_assert(host->pdata->rstc); 3387 3388 err_clk_ciu: 3389 clk_disable_unprepare(host->ciu_clk); 3390 3391 err_clk_biu: 3392 clk_disable_unprepare(host->biu_clk); 3393 3394 return ret; 3395 } 3396 EXPORT_SYMBOL(dw_mci_probe); 3397 3398 void dw_mci_remove(struct dw_mci *host) 3399 { 3400 dev_dbg(host->dev, "remove slot\n"); 3401 if (host->slot) 3402 dw_mci_cleanup_slot(host->slot); 3403 3404 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3405 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3406 3407 /* disable clock to CIU */ 3408 mci_writel(host, CLKENA, 0); 3409 mci_writel(host, CLKSRC, 0); 3410 3411 if (host->use_dma && host->dma_ops->exit) 3412 host->dma_ops->exit(host); 3413 3414 if (!IS_ERR(host->pdata->rstc)) 3415 reset_control_assert(host->pdata->rstc); 3416 3417 clk_disable_unprepare(host->ciu_clk); 3418 clk_disable_unprepare(host->biu_clk); 3419 } 3420 EXPORT_SYMBOL(dw_mci_remove); 3421 3422 3423 3424 #ifdef CONFIG_PM 3425 int dw_mci_runtime_suspend(struct device *dev) 3426 { 3427 struct dw_mci *host = dev_get_drvdata(dev); 3428 3429 if (host->use_dma && host->dma_ops->exit) 3430 host->dma_ops->exit(host); 3431 3432 clk_disable_unprepare(host->ciu_clk); 3433 3434 if (host->slot && 3435 (mmc_can_gpio_cd(host->slot->mmc) || 3436 !mmc_card_is_removable(host->slot->mmc))) 3437 clk_disable_unprepare(host->biu_clk); 3438 3439 return 0; 3440 } 3441 EXPORT_SYMBOL(dw_mci_runtime_suspend); 3442 3443 int dw_mci_runtime_resume(struct device *dev) 3444 { 3445 int ret = 0; 3446 struct dw_mci *host = dev_get_drvdata(dev); 3447 3448 if (host->slot && 3449 (mmc_can_gpio_cd(host->slot->mmc) || 3450 !mmc_card_is_removable(host->slot->mmc))) { 3451 ret = clk_prepare_enable(host->biu_clk); 3452 if (ret) 3453 return ret; 3454 } 3455 3456 ret = clk_prepare_enable(host->ciu_clk); 3457 if (ret) 3458 goto err; 3459 3460 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3461 clk_disable_unprepare(host->ciu_clk); 3462 ret = -ENODEV; 3463 goto err; 3464 } 3465 3466 if (host->use_dma && host->dma_ops->init) 3467 host->dma_ops->init(host); 3468 3469 /* 3470 * Restore the initial value at FIFOTH register 3471 * And Invalidate the prev_blksz with zero 3472 */ 3473 mci_writel(host, FIFOTH, host->fifoth_val); 3474 host->prev_blksz = 0; 3475 3476 /* Put in max timeout */ 3477 mci_writel(host, TMOUT, 0xFFFFFFFF); 3478 3479 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3480 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3481 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3482 DW_MCI_ERROR_FLAGS); 3483 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3484 3485 3486 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3487 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3488 3489 /* Force setup bus to guarantee available clock output */ 3490 dw_mci_setup_bus(host->slot, true); 3491 3492 /* Now that slots are all setup, we can enable card detect */ 3493 dw_mci_enable_cd(host); 3494 3495 return 0; 3496 3497 err: 3498 if (host->slot && 3499 (mmc_can_gpio_cd(host->slot->mmc) || 3500 !mmc_card_is_removable(host->slot->mmc))) 3501 clk_disable_unprepare(host->biu_clk); 3502 3503 return ret; 3504 } 3505 EXPORT_SYMBOL(dw_mci_runtime_resume); 3506 #endif /* CONFIG_PM */ 3507 3508 static int __init dw_mci_init(void) 3509 { 3510 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3511 return 0; 3512 } 3513 3514 static void __exit dw_mci_exit(void) 3515 { 3516 } 3517 3518 module_init(dw_mci_init); 3519 module_exit(dw_mci_exit); 3520 3521 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3522 MODULE_AUTHOR("NXP Semiconductor VietNam"); 3523 MODULE_AUTHOR("Imagination Technologies Ltd"); 3524 MODULE_LICENSE("GPL v2"); 3525