1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/ioport.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 #include <linux/stat.h> 28 #include <linux/delay.h> 29 #include <linux/irq.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/host.h> 32 #include <linux/mmc/mmc.h> 33 #include <linux/mmc/sd.h> 34 #include <linux/mmc/sdio.h> 35 #include <linux/mmc/dw_mmc.h> 36 #include <linux/bitops.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/of.h> 39 #include <linux/of_gpio.h> 40 #include <linux/mmc/slot-gpio.h> 41 42 #include "dw_mmc.h" 43 44 /* Common flag combinations */ 45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47 SDMMC_INT_EBE | SDMMC_INT_HLE) 48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51 DW_MCI_CMD_ERROR_FLAGS) 52 #define DW_MCI_SEND_STATUS 1 53 #define DW_MCI_RECV_STATUS 2 54 #define DW_MCI_DMA_THRESHOLD 16 55 56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 58 59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 62 SDMMC_IDMAC_INT_TI) 63 64 #define DESC_RING_BUF_SZ PAGE_SIZE 65 66 struct idmac_desc_64addr { 67 u32 des0; /* Control Descriptor */ 68 69 u32 des1; /* Reserved */ 70 71 u32 des2; /*Buffer sizes */ 72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 73 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 74 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 75 76 u32 des3; /* Reserved */ 77 78 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 79 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 80 81 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 82 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 83 }; 84 85 struct idmac_desc { 86 __le32 des0; /* Control Descriptor */ 87 #define IDMAC_DES0_DIC BIT(1) 88 #define IDMAC_DES0_LD BIT(2) 89 #define IDMAC_DES0_FD BIT(3) 90 #define IDMAC_DES0_CH BIT(4) 91 #define IDMAC_DES0_ER BIT(5) 92 #define IDMAC_DES0_CES BIT(30) 93 #define IDMAC_DES0_OWN BIT(31) 94 95 __le32 des1; /* Buffer sizes */ 96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 97 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 98 99 __le32 des2; /* buffer 1 physical address */ 100 101 __le32 des3; /* buffer 2 physical address */ 102 }; 103 104 /* Each descriptor can transfer up to 4KB of data in chained mode */ 105 #define DW_MCI_DESC_DATA_LENGTH 0x1000 106 107 static bool dw_mci_reset(struct dw_mci *host); 108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 109 static int dw_mci_card_busy(struct mmc_host *mmc); 110 static int dw_mci_get_cd(struct mmc_host *mmc); 111 112 #if defined(CONFIG_DEBUG_FS) 113 static int dw_mci_req_show(struct seq_file *s, void *v) 114 { 115 struct dw_mci_slot *slot = s->private; 116 struct mmc_request *mrq; 117 struct mmc_command *cmd; 118 struct mmc_command *stop; 119 struct mmc_data *data; 120 121 /* Make sure we get a consistent snapshot */ 122 spin_lock_bh(&slot->host->lock); 123 mrq = slot->mrq; 124 125 if (mrq) { 126 cmd = mrq->cmd; 127 data = mrq->data; 128 stop = mrq->stop; 129 130 if (cmd) 131 seq_printf(s, 132 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 133 cmd->opcode, cmd->arg, cmd->flags, 134 cmd->resp[0], cmd->resp[1], cmd->resp[2], 135 cmd->resp[2], cmd->error); 136 if (data) 137 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 138 data->bytes_xfered, data->blocks, 139 data->blksz, data->flags, data->error); 140 if (stop) 141 seq_printf(s, 142 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 143 stop->opcode, stop->arg, stop->flags, 144 stop->resp[0], stop->resp[1], stop->resp[2], 145 stop->resp[2], stop->error); 146 } 147 148 spin_unlock_bh(&slot->host->lock); 149 150 return 0; 151 } 152 153 static int dw_mci_req_open(struct inode *inode, struct file *file) 154 { 155 return single_open(file, dw_mci_req_show, inode->i_private); 156 } 157 158 static const struct file_operations dw_mci_req_fops = { 159 .owner = THIS_MODULE, 160 .open = dw_mci_req_open, 161 .read = seq_read, 162 .llseek = seq_lseek, 163 .release = single_release, 164 }; 165 166 static int dw_mci_regs_show(struct seq_file *s, void *v) 167 { 168 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 169 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 170 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 171 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 172 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 173 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 174 175 return 0; 176 } 177 178 static int dw_mci_regs_open(struct inode *inode, struct file *file) 179 { 180 return single_open(file, dw_mci_regs_show, inode->i_private); 181 } 182 183 static const struct file_operations dw_mci_regs_fops = { 184 .owner = THIS_MODULE, 185 .open = dw_mci_regs_open, 186 .read = seq_read, 187 .llseek = seq_lseek, 188 .release = single_release, 189 }; 190 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 192 { 193 struct mmc_host *mmc = slot->mmc; 194 struct dw_mci *host = slot->host; 195 struct dentry *root; 196 struct dentry *node; 197 198 root = mmc->debugfs_root; 199 if (!root) 200 return; 201 202 node = debugfs_create_file("regs", S_IRUSR, root, host, 203 &dw_mci_regs_fops); 204 if (!node) 205 goto err; 206 207 node = debugfs_create_file("req", S_IRUSR, root, slot, 208 &dw_mci_req_fops); 209 if (!node) 210 goto err; 211 212 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 213 if (!node) 214 goto err; 215 216 node = debugfs_create_x32("pending_events", S_IRUSR, root, 217 (u32 *)&host->pending_events); 218 if (!node) 219 goto err; 220 221 node = debugfs_create_x32("completed_events", S_IRUSR, root, 222 (u32 *)&host->completed_events); 223 if (!node) 224 goto err; 225 226 return; 227 228 err: 229 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 230 } 231 #endif /* defined(CONFIG_DEBUG_FS) */ 232 233 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 234 235 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 236 { 237 struct mmc_data *data; 238 struct dw_mci_slot *slot = mmc_priv(mmc); 239 struct dw_mci *host = slot->host; 240 u32 cmdr; 241 242 cmd->error = -EINPROGRESS; 243 cmdr = cmd->opcode; 244 245 if (cmd->opcode == MMC_STOP_TRANSMISSION || 246 cmd->opcode == MMC_GO_IDLE_STATE || 247 cmd->opcode == MMC_GO_INACTIVE_STATE || 248 (cmd->opcode == SD_IO_RW_DIRECT && 249 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 250 cmdr |= SDMMC_CMD_STOP; 251 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 252 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 253 254 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 255 u32 clk_en_a; 256 257 /* Special bit makes CMD11 not die */ 258 cmdr |= SDMMC_CMD_VOLT_SWITCH; 259 260 /* Change state to continue to handle CMD11 weirdness */ 261 WARN_ON(slot->host->state != STATE_SENDING_CMD); 262 slot->host->state = STATE_SENDING_CMD11; 263 264 /* 265 * We need to disable low power mode (automatic clock stop) 266 * while doing voltage switch so we don't confuse the card, 267 * since stopping the clock is a specific part of the UHS 268 * voltage change dance. 269 * 270 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 271 * unconditionally turned back on in dw_mci_setup_bus() if it's 272 * ever called with a non-zero clock. That shouldn't happen 273 * until the voltage change is all done. 274 */ 275 clk_en_a = mci_readl(host, CLKENA); 276 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 277 mci_writel(host, CLKENA, clk_en_a); 278 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 279 SDMMC_CMD_PRV_DAT_WAIT, 0); 280 } 281 282 if (cmd->flags & MMC_RSP_PRESENT) { 283 /* We expect a response, so set this bit */ 284 cmdr |= SDMMC_CMD_RESP_EXP; 285 if (cmd->flags & MMC_RSP_136) 286 cmdr |= SDMMC_CMD_RESP_LONG; 287 } 288 289 if (cmd->flags & MMC_RSP_CRC) 290 cmdr |= SDMMC_CMD_RESP_CRC; 291 292 data = cmd->data; 293 if (data) { 294 cmdr |= SDMMC_CMD_DAT_EXP; 295 if (data->flags & MMC_DATA_WRITE) 296 cmdr |= SDMMC_CMD_DAT_WR; 297 } 298 299 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 300 cmdr |= SDMMC_CMD_USE_HOLD_REG; 301 302 return cmdr; 303 } 304 305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 306 { 307 struct mmc_command *stop; 308 u32 cmdr; 309 310 if (!cmd->data) 311 return 0; 312 313 stop = &host->stop_abort; 314 cmdr = cmd->opcode; 315 memset(stop, 0, sizeof(struct mmc_command)); 316 317 if (cmdr == MMC_READ_SINGLE_BLOCK || 318 cmdr == MMC_READ_MULTIPLE_BLOCK || 319 cmdr == MMC_WRITE_BLOCK || 320 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 321 cmdr == MMC_SEND_TUNING_BLOCK || 322 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 323 stop->opcode = MMC_STOP_TRANSMISSION; 324 stop->arg = 0; 325 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 326 } else if (cmdr == SD_IO_RW_EXTENDED) { 327 stop->opcode = SD_IO_RW_DIRECT; 328 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 329 ((cmd->arg >> 28) & 0x7); 330 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 331 } else { 332 return 0; 333 } 334 335 cmdr = stop->opcode | SDMMC_CMD_STOP | 336 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 337 338 return cmdr; 339 } 340 341 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 342 { 343 unsigned long timeout = jiffies + msecs_to_jiffies(500); 344 345 /* 346 * Databook says that before issuing a new data transfer command 347 * we need to check to see if the card is busy. Data transfer commands 348 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 349 * 350 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 351 * expected. 352 */ 353 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 354 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 355 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 356 if (time_after(jiffies, timeout)) { 357 /* Command will fail; we'll pass error then */ 358 dev_err(host->dev, "Busy; trying anyway\n"); 359 break; 360 } 361 udelay(10); 362 } 363 } 364 } 365 366 static void dw_mci_start_command(struct dw_mci *host, 367 struct mmc_command *cmd, u32 cmd_flags) 368 { 369 host->cmd = cmd; 370 dev_vdbg(host->dev, 371 "start command: ARGR=0x%08x CMDR=0x%08x\n", 372 cmd->arg, cmd_flags); 373 374 mci_writel(host, CMDARG, cmd->arg); 375 wmb(); /* drain writebuffer */ 376 dw_mci_wait_while_busy(host, cmd_flags); 377 378 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 379 } 380 381 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 382 { 383 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 384 385 dw_mci_start_command(host, stop, host->stop_cmdr); 386 } 387 388 /* DMA interface functions */ 389 static void dw_mci_stop_dma(struct dw_mci *host) 390 { 391 if (host->using_dma) { 392 host->dma_ops->stop(host); 393 host->dma_ops->cleanup(host); 394 } 395 396 /* Data transfer was stopped by the interrupt handler */ 397 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 398 } 399 400 static int dw_mci_get_dma_dir(struct mmc_data *data) 401 { 402 if (data->flags & MMC_DATA_WRITE) 403 return DMA_TO_DEVICE; 404 else 405 return DMA_FROM_DEVICE; 406 } 407 408 static void dw_mci_dma_cleanup(struct dw_mci *host) 409 { 410 struct mmc_data *data = host->data; 411 412 if (data) 413 if (!data->host_cookie) 414 dma_unmap_sg(host->dev, 415 data->sg, 416 data->sg_len, 417 dw_mci_get_dma_dir(data)); 418 } 419 420 static void dw_mci_idmac_reset(struct dw_mci *host) 421 { 422 u32 bmod = mci_readl(host, BMOD); 423 /* Software reset of DMA */ 424 bmod |= SDMMC_IDMAC_SWRESET; 425 mci_writel(host, BMOD, bmod); 426 } 427 428 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 429 { 430 u32 temp; 431 432 /* Disable and reset the IDMAC interface */ 433 temp = mci_readl(host, CTRL); 434 temp &= ~SDMMC_CTRL_USE_IDMAC; 435 temp |= SDMMC_CTRL_DMA_RESET; 436 mci_writel(host, CTRL, temp); 437 438 /* Stop the IDMAC running */ 439 temp = mci_readl(host, BMOD); 440 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 441 temp |= SDMMC_IDMAC_SWRESET; 442 mci_writel(host, BMOD, temp); 443 } 444 445 static void dw_mci_dmac_complete_dma(void *arg) 446 { 447 struct dw_mci *host = arg; 448 struct mmc_data *data = host->data; 449 450 dev_vdbg(host->dev, "DMA complete\n"); 451 452 if ((host->use_dma == TRANS_MODE_EDMAC) && 453 data && (data->flags & MMC_DATA_READ)) 454 /* Invalidate cache after read */ 455 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), 456 data->sg, 457 data->sg_len, 458 DMA_FROM_DEVICE); 459 460 host->dma_ops->cleanup(host); 461 462 /* 463 * If the card was removed, data will be NULL. No point in trying to 464 * send the stop command or waiting for NBUSY in this case. 465 */ 466 if (data) { 467 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 468 tasklet_schedule(&host->tasklet); 469 } 470 } 471 472 static int dw_mci_idmac_init(struct dw_mci *host) 473 { 474 int i; 475 476 if (host->dma_64bit_address == 1) { 477 struct idmac_desc_64addr *p; 478 /* Number of descriptors in the ring buffer */ 479 host->ring_size = 480 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 481 482 /* Forward link the descriptor list */ 483 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 484 i++, p++) { 485 p->des6 = (host->sg_dma + 486 (sizeof(struct idmac_desc_64addr) * 487 (i + 1))) & 0xffffffff; 488 489 p->des7 = (u64)(host->sg_dma + 490 (sizeof(struct idmac_desc_64addr) * 491 (i + 1))) >> 32; 492 /* Initialize reserved and buffer size fields to "0" */ 493 p->des1 = 0; 494 p->des2 = 0; 495 p->des3 = 0; 496 } 497 498 /* Set the last descriptor as the end-of-ring descriptor */ 499 p->des6 = host->sg_dma & 0xffffffff; 500 p->des7 = (u64)host->sg_dma >> 32; 501 p->des0 = IDMAC_DES0_ER; 502 503 } else { 504 struct idmac_desc *p; 505 /* Number of descriptors in the ring buffer */ 506 host->ring_size = 507 DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 508 509 /* Forward link the descriptor list */ 510 for (i = 0, p = host->sg_cpu; 511 i < host->ring_size - 1; 512 i++, p++) { 513 p->des3 = cpu_to_le32(host->sg_dma + 514 (sizeof(struct idmac_desc) * (i + 1))); 515 p->des1 = 0; 516 } 517 518 /* Set the last descriptor as the end-of-ring descriptor */ 519 p->des3 = cpu_to_le32(host->sg_dma); 520 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 521 } 522 523 dw_mci_idmac_reset(host); 524 525 if (host->dma_64bit_address == 1) { 526 /* Mask out interrupts - get Tx & Rx complete only */ 527 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 528 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 529 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 530 531 /* Set the descriptor base address */ 532 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 533 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 534 535 } else { 536 /* Mask out interrupts - get Tx & Rx complete only */ 537 mci_writel(host, IDSTS, IDMAC_INT_CLR); 538 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 539 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 540 541 /* Set the descriptor base address */ 542 mci_writel(host, DBADDR, host->sg_dma); 543 } 544 545 return 0; 546 } 547 548 static inline int dw_mci_prepare_desc64(struct dw_mci *host, 549 struct mmc_data *data, 550 unsigned int sg_len) 551 { 552 unsigned int desc_len; 553 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 554 unsigned long timeout; 555 int i; 556 557 desc_first = desc_last = desc = host->sg_cpu; 558 559 for (i = 0; i < sg_len; i++) { 560 unsigned int length = sg_dma_len(&data->sg[i]); 561 562 u64 mem_addr = sg_dma_address(&data->sg[i]); 563 564 for ( ; length ; desc++) { 565 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 566 length : DW_MCI_DESC_DATA_LENGTH; 567 568 length -= desc_len; 569 570 /* 571 * Wait for the former clear OWN bit operation 572 * of IDMAC to make sure that this descriptor 573 * isn't still owned by IDMAC as IDMAC's write 574 * ops and CPU's read ops are asynchronous. 575 */ 576 timeout = jiffies + msecs_to_jiffies(100); 577 while (readl(&desc->des0) & IDMAC_DES0_OWN) { 578 if (time_after(jiffies, timeout)) 579 goto err_own_bit; 580 udelay(10); 581 } 582 583 /* 584 * Set the OWN bit and disable interrupts 585 * for this descriptor 586 */ 587 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 588 IDMAC_DES0_CH; 589 590 /* Buffer length */ 591 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 592 593 /* Physical address to DMA to/from */ 594 desc->des4 = mem_addr & 0xffffffff; 595 desc->des5 = mem_addr >> 32; 596 597 /* Update physical address for the next desc */ 598 mem_addr += desc_len; 599 600 /* Save pointer to the last descriptor */ 601 desc_last = desc; 602 } 603 } 604 605 /* Set first descriptor */ 606 desc_first->des0 |= IDMAC_DES0_FD; 607 608 /* Set last descriptor */ 609 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 610 desc_last->des0 |= IDMAC_DES0_LD; 611 612 return 0; 613 err_own_bit: 614 /* restore the descriptor chain as it's polluted */ 615 dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n"); 616 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 617 dw_mci_idmac_init(host); 618 return -EINVAL; 619 } 620 621 622 static inline int dw_mci_prepare_desc32(struct dw_mci *host, 623 struct mmc_data *data, 624 unsigned int sg_len) 625 { 626 unsigned int desc_len; 627 struct idmac_desc *desc_first, *desc_last, *desc; 628 unsigned long timeout; 629 int i; 630 631 desc_first = desc_last = desc = host->sg_cpu; 632 633 for (i = 0; i < sg_len; i++) { 634 unsigned int length = sg_dma_len(&data->sg[i]); 635 636 u32 mem_addr = sg_dma_address(&data->sg[i]); 637 638 for ( ; length ; desc++) { 639 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 640 length : DW_MCI_DESC_DATA_LENGTH; 641 642 length -= desc_len; 643 644 /* 645 * Wait for the former clear OWN bit operation 646 * of IDMAC to make sure that this descriptor 647 * isn't still owned by IDMAC as IDMAC's write 648 * ops and CPU's read ops are asynchronous. 649 */ 650 timeout = jiffies + msecs_to_jiffies(100); 651 while (readl(&desc->des0) & 652 cpu_to_le32(IDMAC_DES0_OWN)) { 653 if (time_after(jiffies, timeout)) 654 goto err_own_bit; 655 udelay(10); 656 } 657 658 /* 659 * Set the OWN bit and disable interrupts 660 * for this descriptor 661 */ 662 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 663 IDMAC_DES0_DIC | 664 IDMAC_DES0_CH); 665 666 /* Buffer length */ 667 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 668 669 /* Physical address to DMA to/from */ 670 desc->des2 = cpu_to_le32(mem_addr); 671 672 /* Update physical address for the next desc */ 673 mem_addr += desc_len; 674 675 /* Save pointer to the last descriptor */ 676 desc_last = desc; 677 } 678 } 679 680 /* Set first descriptor */ 681 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 682 683 /* Set last descriptor */ 684 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 685 IDMAC_DES0_DIC)); 686 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 687 688 return 0; 689 err_own_bit: 690 /* restore the descriptor chain as it's polluted */ 691 dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n"); 692 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 693 dw_mci_idmac_init(host); 694 return -EINVAL; 695 } 696 697 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 698 { 699 u32 temp; 700 int ret; 701 702 if (host->dma_64bit_address == 1) 703 ret = dw_mci_prepare_desc64(host, host->data, sg_len); 704 else 705 ret = dw_mci_prepare_desc32(host, host->data, sg_len); 706 707 if (ret) 708 goto out; 709 710 /* drain writebuffer */ 711 wmb(); 712 713 /* Make sure to reset DMA in case we did PIO before this */ 714 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 715 dw_mci_idmac_reset(host); 716 717 /* Select IDMAC interface */ 718 temp = mci_readl(host, CTRL); 719 temp |= SDMMC_CTRL_USE_IDMAC; 720 mci_writel(host, CTRL, temp); 721 722 /* drain writebuffer */ 723 wmb(); 724 725 /* Enable the IDMAC */ 726 temp = mci_readl(host, BMOD); 727 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 728 mci_writel(host, BMOD, temp); 729 730 /* Start it running */ 731 mci_writel(host, PLDMND, 1); 732 733 out: 734 return ret; 735 } 736 737 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 738 .init = dw_mci_idmac_init, 739 .start = dw_mci_idmac_start_dma, 740 .stop = dw_mci_idmac_stop_dma, 741 .complete = dw_mci_dmac_complete_dma, 742 .cleanup = dw_mci_dma_cleanup, 743 }; 744 745 static void dw_mci_edmac_stop_dma(struct dw_mci *host) 746 { 747 dmaengine_terminate_async(host->dms->ch); 748 } 749 750 static int dw_mci_edmac_start_dma(struct dw_mci *host, 751 unsigned int sg_len) 752 { 753 struct dma_slave_config cfg; 754 struct dma_async_tx_descriptor *desc = NULL; 755 struct scatterlist *sgl = host->data->sg; 756 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 757 u32 sg_elems = host->data->sg_len; 758 u32 fifoth_val; 759 u32 fifo_offset = host->fifo_reg - host->regs; 760 int ret = 0; 761 762 /* Set external dma config: burst size, burst width */ 763 cfg.dst_addr = host->phy_regs + fifo_offset; 764 cfg.src_addr = cfg.dst_addr; 765 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 766 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 767 768 /* Match burst msize with external dma config */ 769 fifoth_val = mci_readl(host, FIFOTH); 770 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 771 cfg.src_maxburst = cfg.dst_maxburst; 772 773 if (host->data->flags & MMC_DATA_WRITE) 774 cfg.direction = DMA_MEM_TO_DEV; 775 else 776 cfg.direction = DMA_DEV_TO_MEM; 777 778 ret = dmaengine_slave_config(host->dms->ch, &cfg); 779 if (ret) { 780 dev_err(host->dev, "Failed to config edmac.\n"); 781 return -EBUSY; 782 } 783 784 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 785 sg_len, cfg.direction, 786 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 787 if (!desc) { 788 dev_err(host->dev, "Can't prepare slave sg.\n"); 789 return -EBUSY; 790 } 791 792 /* Set dw_mci_dmac_complete_dma as callback */ 793 desc->callback = dw_mci_dmac_complete_dma; 794 desc->callback_param = (void *)host; 795 dmaengine_submit(desc); 796 797 /* Flush cache before write */ 798 if (host->data->flags & MMC_DATA_WRITE) 799 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl, 800 sg_elems, DMA_TO_DEVICE); 801 802 dma_async_issue_pending(host->dms->ch); 803 804 return 0; 805 } 806 807 static int dw_mci_edmac_init(struct dw_mci *host) 808 { 809 /* Request external dma channel */ 810 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 811 if (!host->dms) 812 return -ENOMEM; 813 814 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 815 if (!host->dms->ch) { 816 dev_err(host->dev, "Failed to get external DMA channel.\n"); 817 kfree(host->dms); 818 host->dms = NULL; 819 return -ENXIO; 820 } 821 822 return 0; 823 } 824 825 static void dw_mci_edmac_exit(struct dw_mci *host) 826 { 827 if (host->dms) { 828 if (host->dms->ch) { 829 dma_release_channel(host->dms->ch); 830 host->dms->ch = NULL; 831 } 832 kfree(host->dms); 833 host->dms = NULL; 834 } 835 } 836 837 static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 838 .init = dw_mci_edmac_init, 839 .exit = dw_mci_edmac_exit, 840 .start = dw_mci_edmac_start_dma, 841 .stop = dw_mci_edmac_stop_dma, 842 .complete = dw_mci_dmac_complete_dma, 843 .cleanup = dw_mci_dma_cleanup, 844 }; 845 846 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 847 struct mmc_data *data, 848 bool next) 849 { 850 struct scatterlist *sg; 851 unsigned int i, sg_len; 852 853 if (!next && data->host_cookie) 854 return data->host_cookie; 855 856 /* 857 * We don't do DMA on "complex" transfers, i.e. with 858 * non-word-aligned buffers or lengths. Also, we don't bother 859 * with all the DMA setup overhead for short transfers. 860 */ 861 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 862 return -EINVAL; 863 864 if (data->blksz & 3) 865 return -EINVAL; 866 867 for_each_sg(data->sg, sg, data->sg_len, i) { 868 if (sg->offset & 3 || sg->length & 3) 869 return -EINVAL; 870 } 871 872 sg_len = dma_map_sg(host->dev, 873 data->sg, 874 data->sg_len, 875 dw_mci_get_dma_dir(data)); 876 if (sg_len == 0) 877 return -EINVAL; 878 879 if (next) 880 data->host_cookie = sg_len; 881 882 return sg_len; 883 } 884 885 static void dw_mci_pre_req(struct mmc_host *mmc, 886 struct mmc_request *mrq, 887 bool is_first_req) 888 { 889 struct dw_mci_slot *slot = mmc_priv(mmc); 890 struct mmc_data *data = mrq->data; 891 892 if (!slot->host->use_dma || !data) 893 return; 894 895 if (data->host_cookie) { 896 data->host_cookie = 0; 897 return; 898 } 899 900 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 901 data->host_cookie = 0; 902 } 903 904 static void dw_mci_post_req(struct mmc_host *mmc, 905 struct mmc_request *mrq, 906 int err) 907 { 908 struct dw_mci_slot *slot = mmc_priv(mmc); 909 struct mmc_data *data = mrq->data; 910 911 if (!slot->host->use_dma || !data) 912 return; 913 914 if (data->host_cookie) 915 dma_unmap_sg(slot->host->dev, 916 data->sg, 917 data->sg_len, 918 dw_mci_get_dma_dir(data)); 919 data->host_cookie = 0; 920 } 921 922 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 923 { 924 unsigned int blksz = data->blksz; 925 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 926 u32 fifo_width = 1 << host->data_shift; 927 u32 blksz_depth = blksz / fifo_width, fifoth_val; 928 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 929 int idx = ARRAY_SIZE(mszs) - 1; 930 931 /* pio should ship this scenario */ 932 if (!host->use_dma) 933 return; 934 935 tx_wmark = (host->fifo_depth) / 2; 936 tx_wmark_invers = host->fifo_depth - tx_wmark; 937 938 /* 939 * MSIZE is '1', 940 * if blksz is not a multiple of the FIFO width 941 */ 942 if (blksz % fifo_width) 943 goto done; 944 945 do { 946 if (!((blksz_depth % mszs[idx]) || 947 (tx_wmark_invers % mszs[idx]))) { 948 msize = idx; 949 rx_wmark = mszs[idx] - 1; 950 break; 951 } 952 } while (--idx > 0); 953 /* 954 * If idx is '0', it won't be tried 955 * Thus, initial values are uesed 956 */ 957 done: 958 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 959 mci_writel(host, FIFOTH, fifoth_val); 960 } 961 962 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 963 { 964 unsigned int blksz = data->blksz; 965 u32 blksz_depth, fifo_depth; 966 u16 thld_size; 967 u8 enable; 968 969 /* 970 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 971 * in the FIFO region, so we really shouldn't access it). 972 */ 973 if (host->verid < DW_MMC_240A || 974 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 975 return; 976 977 /* 978 * Card write Threshold is introduced since 2.80a 979 * It's used when HS400 mode is enabled. 980 */ 981 if (data->flags & MMC_DATA_WRITE && 982 !(host->timing != MMC_TIMING_MMC_HS400)) 983 return; 984 985 if (data->flags & MMC_DATA_WRITE) 986 enable = SDMMC_CARD_WR_THR_EN; 987 else 988 enable = SDMMC_CARD_RD_THR_EN; 989 990 if (host->timing != MMC_TIMING_MMC_HS200 && 991 host->timing != MMC_TIMING_UHS_SDR104) 992 goto disable; 993 994 blksz_depth = blksz / (1 << host->data_shift); 995 fifo_depth = host->fifo_depth; 996 997 if (blksz_depth > fifo_depth) 998 goto disable; 999 1000 /* 1001 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1002 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1003 * Currently just choose blksz. 1004 */ 1005 thld_size = blksz; 1006 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1007 return; 1008 1009 disable: 1010 mci_writel(host, CDTHRCTL, 0); 1011 } 1012 1013 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 1014 { 1015 unsigned long irqflags; 1016 int sg_len; 1017 u32 temp; 1018 1019 host->using_dma = 0; 1020 1021 /* If we don't have a channel, we can't do DMA */ 1022 if (!host->use_dma) 1023 return -ENODEV; 1024 1025 sg_len = dw_mci_pre_dma_transfer(host, data, 0); 1026 if (sg_len < 0) { 1027 host->dma_ops->stop(host); 1028 return sg_len; 1029 } 1030 1031 host->using_dma = 1; 1032 1033 if (host->use_dma == TRANS_MODE_IDMAC) 1034 dev_vdbg(host->dev, 1035 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 1036 (unsigned long)host->sg_cpu, 1037 (unsigned long)host->sg_dma, 1038 sg_len); 1039 1040 /* 1041 * Decide the MSIZE and RX/TX Watermark. 1042 * If current block size is same with previous size, 1043 * no need to update fifoth. 1044 */ 1045 if (host->prev_blksz != data->blksz) 1046 dw_mci_adjust_fifoth(host, data); 1047 1048 /* Enable the DMA interface */ 1049 temp = mci_readl(host, CTRL); 1050 temp |= SDMMC_CTRL_DMA_ENABLE; 1051 mci_writel(host, CTRL, temp); 1052 1053 /* Disable RX/TX IRQs, let DMA handle it */ 1054 spin_lock_irqsave(&host->irq_lock, irqflags); 1055 temp = mci_readl(host, INTMASK); 1056 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1057 mci_writel(host, INTMASK, temp); 1058 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1059 1060 if (host->dma_ops->start(host, sg_len)) { 1061 host->dma_ops->stop(host); 1062 /* We can't do DMA, try PIO for this one */ 1063 dev_dbg(host->dev, 1064 "%s: fall back to PIO mode for current transfer\n", 1065 __func__); 1066 return -ENODEV; 1067 } 1068 1069 return 0; 1070 } 1071 1072 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1073 { 1074 unsigned long irqflags; 1075 int flags = SG_MITER_ATOMIC; 1076 u32 temp; 1077 1078 data->error = -EINPROGRESS; 1079 1080 WARN_ON(host->data); 1081 host->sg = NULL; 1082 host->data = data; 1083 1084 if (data->flags & MMC_DATA_READ) 1085 host->dir_status = DW_MCI_RECV_STATUS; 1086 else 1087 host->dir_status = DW_MCI_SEND_STATUS; 1088 1089 dw_mci_ctrl_thld(host, data); 1090 1091 if (dw_mci_submit_data_dma(host, data)) { 1092 if (host->data->flags & MMC_DATA_READ) 1093 flags |= SG_MITER_TO_SG; 1094 else 1095 flags |= SG_MITER_FROM_SG; 1096 1097 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1098 host->sg = data->sg; 1099 host->part_buf_start = 0; 1100 host->part_buf_count = 0; 1101 1102 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1103 1104 spin_lock_irqsave(&host->irq_lock, irqflags); 1105 temp = mci_readl(host, INTMASK); 1106 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1107 mci_writel(host, INTMASK, temp); 1108 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1109 1110 temp = mci_readl(host, CTRL); 1111 temp &= ~SDMMC_CTRL_DMA_ENABLE; 1112 mci_writel(host, CTRL, temp); 1113 1114 /* 1115 * Use the initial fifoth_val for PIO mode. 1116 * If next issued data may be transfered by DMA mode, 1117 * prev_blksz should be invalidated. 1118 */ 1119 mci_writel(host, FIFOTH, host->fifoth_val); 1120 host->prev_blksz = 0; 1121 } else { 1122 /* 1123 * Keep the current block size. 1124 * It will be used to decide whether to update 1125 * fifoth register next time. 1126 */ 1127 host->prev_blksz = data->blksz; 1128 } 1129 } 1130 1131 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 1132 { 1133 struct dw_mci *host = slot->host; 1134 unsigned long timeout = jiffies + msecs_to_jiffies(500); 1135 unsigned int cmd_status = 0; 1136 1137 mci_writel(host, CMDARG, arg); 1138 wmb(); /* drain writebuffer */ 1139 dw_mci_wait_while_busy(host, cmd); 1140 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 1141 1142 while (time_before(jiffies, timeout)) { 1143 cmd_status = mci_readl(host, CMD); 1144 if (!(cmd_status & SDMMC_CMD_START)) 1145 return; 1146 } 1147 dev_err(&slot->mmc->class_dev, 1148 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 1149 cmd, arg, cmd_status); 1150 } 1151 1152 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1153 { 1154 struct dw_mci *host = slot->host; 1155 unsigned int clock = slot->clock; 1156 u32 div; 1157 u32 clk_en_a; 1158 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 1159 1160 /* We must continue to set bit 28 in CMD until the change is complete */ 1161 if (host->state == STATE_WAITING_CMD11_DONE) 1162 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1163 1164 if (!clock) { 1165 mci_writel(host, CLKENA, 0); 1166 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1167 } else if (clock != host->current_speed || force_clkinit) { 1168 div = host->bus_hz / clock; 1169 if (host->bus_hz % clock && host->bus_hz > clock) 1170 /* 1171 * move the + 1 after the divide to prevent 1172 * over-clocking the card. 1173 */ 1174 div += 1; 1175 1176 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1177 1178 if (clock != slot->__clk_old || force_clkinit) 1179 dev_info(&slot->mmc->class_dev, 1180 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1181 slot->id, host->bus_hz, clock, 1182 div ? ((host->bus_hz / div) >> 1) : 1183 host->bus_hz, div); 1184 1185 /* disable clock */ 1186 mci_writel(host, CLKENA, 0); 1187 mci_writel(host, CLKSRC, 0); 1188 1189 /* inform CIU */ 1190 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1191 1192 /* set clock to desired speed */ 1193 mci_writel(host, CLKDIV, div); 1194 1195 /* inform CIU */ 1196 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1197 1198 /* enable clock; only low power if no SDIO */ 1199 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1200 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1201 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1202 mci_writel(host, CLKENA, clk_en_a); 1203 1204 /* inform CIU */ 1205 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1206 1207 /* keep the last clock value that was requested from core */ 1208 slot->__clk_old = clock; 1209 } 1210 1211 host->current_speed = clock; 1212 1213 /* Set the current slot bus width */ 1214 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1215 } 1216 1217 static void __dw_mci_start_request(struct dw_mci *host, 1218 struct dw_mci_slot *slot, 1219 struct mmc_command *cmd) 1220 { 1221 struct mmc_request *mrq; 1222 struct mmc_data *data; 1223 u32 cmdflags; 1224 1225 mrq = slot->mrq; 1226 1227 host->cur_slot = slot; 1228 host->mrq = mrq; 1229 1230 host->pending_events = 0; 1231 host->completed_events = 0; 1232 host->cmd_status = 0; 1233 host->data_status = 0; 1234 host->dir_status = 0; 1235 1236 data = cmd->data; 1237 if (data) { 1238 mci_writel(host, TMOUT, 0xFFFFFFFF); 1239 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1240 mci_writel(host, BLKSIZ, data->blksz); 1241 } 1242 1243 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1244 1245 /* this is the first command, send the initialization clock */ 1246 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1247 cmdflags |= SDMMC_CMD_INIT; 1248 1249 if (data) { 1250 dw_mci_submit_data(host, data); 1251 wmb(); /* drain writebuffer */ 1252 } 1253 1254 dw_mci_start_command(host, cmd, cmdflags); 1255 1256 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1257 unsigned long irqflags; 1258 1259 /* 1260 * Databook says to fail after 2ms w/ no response, but evidence 1261 * shows that sometimes the cmd11 interrupt takes over 130ms. 1262 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1263 * is just about to roll over. 1264 * 1265 * We do this whole thing under spinlock and only if the 1266 * command hasn't already completed (indicating the the irq 1267 * already ran so we don't want the timeout). 1268 */ 1269 spin_lock_irqsave(&host->irq_lock, irqflags); 1270 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1271 mod_timer(&host->cmd11_timer, 1272 jiffies + msecs_to_jiffies(500) + 1); 1273 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1274 } 1275 1276 if (mrq->stop) 1277 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 1278 else 1279 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1280 } 1281 1282 static void dw_mci_start_request(struct dw_mci *host, 1283 struct dw_mci_slot *slot) 1284 { 1285 struct mmc_request *mrq = slot->mrq; 1286 struct mmc_command *cmd; 1287 1288 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1289 __dw_mci_start_request(host, slot, cmd); 1290 } 1291 1292 /* must be called with host->lock held */ 1293 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1294 struct mmc_request *mrq) 1295 { 1296 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1297 host->state); 1298 1299 slot->mrq = mrq; 1300 1301 if (host->state == STATE_WAITING_CMD11_DONE) { 1302 dev_warn(&slot->mmc->class_dev, 1303 "Voltage change didn't complete\n"); 1304 /* 1305 * this case isn't expected to happen, so we can 1306 * either crash here or just try to continue on 1307 * in the closest possible state 1308 */ 1309 host->state = STATE_IDLE; 1310 } 1311 1312 if (host->state == STATE_IDLE) { 1313 host->state = STATE_SENDING_CMD; 1314 dw_mci_start_request(host, slot); 1315 } else { 1316 list_add_tail(&slot->queue_node, &host->queue); 1317 } 1318 } 1319 1320 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1321 { 1322 struct dw_mci_slot *slot = mmc_priv(mmc); 1323 struct dw_mci *host = slot->host; 1324 1325 WARN_ON(slot->mrq); 1326 1327 /* 1328 * The check for card presence and queueing of the request must be 1329 * atomic, otherwise the card could be removed in between and the 1330 * request wouldn't fail until another card was inserted. 1331 */ 1332 1333 if (!dw_mci_get_cd(mmc)) { 1334 mrq->cmd->error = -ENOMEDIUM; 1335 mmc_request_done(mmc, mrq); 1336 return; 1337 } 1338 1339 spin_lock_bh(&host->lock); 1340 1341 dw_mci_queue_request(host, slot, mrq); 1342 1343 spin_unlock_bh(&host->lock); 1344 } 1345 1346 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1347 { 1348 struct dw_mci_slot *slot = mmc_priv(mmc); 1349 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1350 u32 regs; 1351 int ret; 1352 1353 switch (ios->bus_width) { 1354 case MMC_BUS_WIDTH_4: 1355 slot->ctype = SDMMC_CTYPE_4BIT; 1356 break; 1357 case MMC_BUS_WIDTH_8: 1358 slot->ctype = SDMMC_CTYPE_8BIT; 1359 break; 1360 default: 1361 /* set default 1 bit mode */ 1362 slot->ctype = SDMMC_CTYPE_1BIT; 1363 } 1364 1365 regs = mci_readl(slot->host, UHS_REG); 1366 1367 /* DDR mode set */ 1368 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1369 ios->timing == MMC_TIMING_UHS_DDR50 || 1370 ios->timing == MMC_TIMING_MMC_HS400) 1371 regs |= ((0x1 << slot->id) << 16); 1372 else 1373 regs &= ~((0x1 << slot->id) << 16); 1374 1375 mci_writel(slot->host, UHS_REG, regs); 1376 slot->host->timing = ios->timing; 1377 1378 /* 1379 * Use mirror of ios->clock to prevent race with mmc 1380 * core ios update when finding the minimum. 1381 */ 1382 slot->clock = ios->clock; 1383 1384 if (drv_data && drv_data->set_ios) 1385 drv_data->set_ios(slot->host, ios); 1386 1387 switch (ios->power_mode) { 1388 case MMC_POWER_UP: 1389 if (!IS_ERR(mmc->supply.vmmc)) { 1390 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1391 ios->vdd); 1392 if (ret) { 1393 dev_err(slot->host->dev, 1394 "failed to enable vmmc regulator\n"); 1395 /*return, if failed turn on vmmc*/ 1396 return; 1397 } 1398 } 1399 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1400 regs = mci_readl(slot->host, PWREN); 1401 regs |= (1 << slot->id); 1402 mci_writel(slot->host, PWREN, regs); 1403 break; 1404 case MMC_POWER_ON: 1405 if (!slot->host->vqmmc_enabled) { 1406 if (!IS_ERR(mmc->supply.vqmmc)) { 1407 ret = regulator_enable(mmc->supply.vqmmc); 1408 if (ret < 0) 1409 dev_err(slot->host->dev, 1410 "failed to enable vqmmc\n"); 1411 else 1412 slot->host->vqmmc_enabled = true; 1413 1414 } else { 1415 /* Keep track so we don't reset again */ 1416 slot->host->vqmmc_enabled = true; 1417 } 1418 1419 /* Reset our state machine after powering on */ 1420 dw_mci_ctrl_reset(slot->host, 1421 SDMMC_CTRL_ALL_RESET_FLAGS); 1422 } 1423 1424 /* Adjust clock / bus width after power is up */ 1425 dw_mci_setup_bus(slot, false); 1426 1427 break; 1428 case MMC_POWER_OFF: 1429 /* Turn clock off before power goes down */ 1430 dw_mci_setup_bus(slot, false); 1431 1432 if (!IS_ERR(mmc->supply.vmmc)) 1433 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1434 1435 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1436 regulator_disable(mmc->supply.vqmmc); 1437 slot->host->vqmmc_enabled = false; 1438 1439 regs = mci_readl(slot->host, PWREN); 1440 regs &= ~(1 << slot->id); 1441 mci_writel(slot->host, PWREN, regs); 1442 break; 1443 default: 1444 break; 1445 } 1446 1447 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1448 slot->host->state = STATE_IDLE; 1449 } 1450 1451 static int dw_mci_card_busy(struct mmc_host *mmc) 1452 { 1453 struct dw_mci_slot *slot = mmc_priv(mmc); 1454 u32 status; 1455 1456 /* 1457 * Check the busy bit which is low when DAT[3:0] 1458 * (the data lines) are 0000 1459 */ 1460 status = mci_readl(slot->host, STATUS); 1461 1462 return !!(status & SDMMC_STATUS_BUSY); 1463 } 1464 1465 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1466 { 1467 struct dw_mci_slot *slot = mmc_priv(mmc); 1468 struct dw_mci *host = slot->host; 1469 const struct dw_mci_drv_data *drv_data = host->drv_data; 1470 u32 uhs; 1471 u32 v18 = SDMMC_UHS_18V << slot->id; 1472 int ret; 1473 1474 if (drv_data && drv_data->switch_voltage) 1475 return drv_data->switch_voltage(mmc, ios); 1476 1477 /* 1478 * Program the voltage. Note that some instances of dw_mmc may use 1479 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1480 * does no harm but you need to set the regulator directly. Try both. 1481 */ 1482 uhs = mci_readl(host, UHS_REG); 1483 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1484 uhs &= ~v18; 1485 else 1486 uhs |= v18; 1487 1488 if (!IS_ERR(mmc->supply.vqmmc)) { 1489 ret = mmc_regulator_set_vqmmc(mmc, ios); 1490 1491 if (ret) { 1492 dev_dbg(&mmc->class_dev, 1493 "Regulator set error %d - %s V\n", 1494 ret, uhs & v18 ? "1.8" : "3.3"); 1495 return ret; 1496 } 1497 } 1498 mci_writel(host, UHS_REG, uhs); 1499 1500 return 0; 1501 } 1502 1503 static int dw_mci_get_ro(struct mmc_host *mmc) 1504 { 1505 int read_only; 1506 struct dw_mci_slot *slot = mmc_priv(mmc); 1507 int gpio_ro = mmc_gpio_get_ro(mmc); 1508 1509 /* Use platform get_ro function, else try on board write protect */ 1510 if (gpio_ro >= 0) 1511 read_only = gpio_ro; 1512 else 1513 read_only = 1514 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1515 1516 dev_dbg(&mmc->class_dev, "card is %s\n", 1517 read_only ? "read-only" : "read-write"); 1518 1519 return read_only; 1520 } 1521 1522 static int dw_mci_get_cd(struct mmc_host *mmc) 1523 { 1524 int present; 1525 struct dw_mci_slot *slot = mmc_priv(mmc); 1526 struct dw_mci *host = slot->host; 1527 int gpio_cd = mmc_gpio_get_cd(mmc); 1528 1529 /* Use platform get_cd function, else try onboard card detect */ 1530 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc)) 1531 present = 1; 1532 else if (gpio_cd >= 0) 1533 present = gpio_cd; 1534 else 1535 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1536 == 0 ? 1 : 0; 1537 1538 spin_lock_bh(&host->lock); 1539 if (present) { 1540 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1541 dev_dbg(&mmc->class_dev, "card is present\n"); 1542 } else { 1543 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1544 dev_dbg(&mmc->class_dev, "card is not present\n"); 1545 } 1546 spin_unlock_bh(&host->lock); 1547 1548 return present; 1549 } 1550 1551 static void dw_mci_hw_reset(struct mmc_host *mmc) 1552 { 1553 struct dw_mci_slot *slot = mmc_priv(mmc); 1554 struct dw_mci *host = slot->host; 1555 int reset; 1556 1557 if (host->use_dma == TRANS_MODE_IDMAC) 1558 dw_mci_idmac_reset(host); 1559 1560 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1561 SDMMC_CTRL_FIFO_RESET)) 1562 return; 1563 1564 /* 1565 * According to eMMC spec, card reset procedure: 1566 * tRstW >= 1us: RST_n pulse width 1567 * tRSCA >= 200us: RST_n to Command time 1568 * tRSTH >= 1us: RST_n high period 1569 */ 1570 reset = mci_readl(host, RST_N); 1571 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1572 mci_writel(host, RST_N, reset); 1573 usleep_range(1, 2); 1574 reset |= SDMMC_RST_HWACTIVE << slot->id; 1575 mci_writel(host, RST_N, reset); 1576 usleep_range(200, 300); 1577 } 1578 1579 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1580 { 1581 struct dw_mci_slot *slot = mmc_priv(mmc); 1582 struct dw_mci *host = slot->host; 1583 1584 /* 1585 * Low power mode will stop the card clock when idle. According to the 1586 * description of the CLKENA register we should disable low power mode 1587 * for SDIO cards if we need SDIO interrupts to work. 1588 */ 1589 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1590 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1591 u32 clk_en_a_old; 1592 u32 clk_en_a; 1593 1594 clk_en_a_old = mci_readl(host, CLKENA); 1595 1596 if (card->type == MMC_TYPE_SDIO || 1597 card->type == MMC_TYPE_SD_COMBO) { 1598 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1599 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1600 } else { 1601 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1602 clk_en_a = clk_en_a_old | clken_low_pwr; 1603 } 1604 1605 if (clk_en_a != clk_en_a_old) { 1606 mci_writel(host, CLKENA, clk_en_a); 1607 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1608 SDMMC_CMD_PRV_DAT_WAIT, 0); 1609 } 1610 } 1611 } 1612 1613 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1614 { 1615 struct dw_mci_slot *slot = mmc_priv(mmc); 1616 struct dw_mci *host = slot->host; 1617 unsigned long irqflags; 1618 u32 int_mask; 1619 1620 spin_lock_irqsave(&host->irq_lock, irqflags); 1621 1622 /* Enable/disable Slot Specific SDIO interrupt */ 1623 int_mask = mci_readl(host, INTMASK); 1624 if (enb) 1625 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1626 else 1627 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1628 mci_writel(host, INTMASK, int_mask); 1629 1630 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1631 } 1632 1633 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1634 { 1635 struct dw_mci_slot *slot = mmc_priv(mmc); 1636 struct dw_mci *host = slot->host; 1637 const struct dw_mci_drv_data *drv_data = host->drv_data; 1638 int err = -EINVAL; 1639 1640 if (drv_data && drv_data->execute_tuning) 1641 err = drv_data->execute_tuning(slot, opcode); 1642 return err; 1643 } 1644 1645 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1646 struct mmc_ios *ios) 1647 { 1648 struct dw_mci_slot *slot = mmc_priv(mmc); 1649 struct dw_mci *host = slot->host; 1650 const struct dw_mci_drv_data *drv_data = host->drv_data; 1651 1652 if (drv_data && drv_data->prepare_hs400_tuning) 1653 return drv_data->prepare_hs400_tuning(host, ios); 1654 1655 return 0; 1656 } 1657 1658 static const struct mmc_host_ops dw_mci_ops = { 1659 .request = dw_mci_request, 1660 .pre_req = dw_mci_pre_req, 1661 .post_req = dw_mci_post_req, 1662 .set_ios = dw_mci_set_ios, 1663 .get_ro = dw_mci_get_ro, 1664 .get_cd = dw_mci_get_cd, 1665 .hw_reset = dw_mci_hw_reset, 1666 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1667 .execute_tuning = dw_mci_execute_tuning, 1668 .card_busy = dw_mci_card_busy, 1669 .start_signal_voltage_switch = dw_mci_switch_voltage, 1670 .init_card = dw_mci_init_card, 1671 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1672 }; 1673 1674 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1675 __releases(&host->lock) 1676 __acquires(&host->lock) 1677 { 1678 struct dw_mci_slot *slot; 1679 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1680 1681 WARN_ON(host->cmd || host->data); 1682 1683 host->cur_slot->mrq = NULL; 1684 host->mrq = NULL; 1685 if (!list_empty(&host->queue)) { 1686 slot = list_entry(host->queue.next, 1687 struct dw_mci_slot, queue_node); 1688 list_del(&slot->queue_node); 1689 dev_vdbg(host->dev, "list not empty: %s is next\n", 1690 mmc_hostname(slot->mmc)); 1691 host->state = STATE_SENDING_CMD; 1692 dw_mci_start_request(host, slot); 1693 } else { 1694 dev_vdbg(host->dev, "list empty\n"); 1695 1696 if (host->state == STATE_SENDING_CMD11) 1697 host->state = STATE_WAITING_CMD11_DONE; 1698 else 1699 host->state = STATE_IDLE; 1700 } 1701 1702 spin_unlock(&host->lock); 1703 mmc_request_done(prev_mmc, mrq); 1704 spin_lock(&host->lock); 1705 } 1706 1707 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1708 { 1709 u32 status = host->cmd_status; 1710 1711 host->cmd_status = 0; 1712 1713 /* Read the response from the card (up to 16 bytes) */ 1714 if (cmd->flags & MMC_RSP_PRESENT) { 1715 if (cmd->flags & MMC_RSP_136) { 1716 cmd->resp[3] = mci_readl(host, RESP0); 1717 cmd->resp[2] = mci_readl(host, RESP1); 1718 cmd->resp[1] = mci_readl(host, RESP2); 1719 cmd->resp[0] = mci_readl(host, RESP3); 1720 } else { 1721 cmd->resp[0] = mci_readl(host, RESP0); 1722 cmd->resp[1] = 0; 1723 cmd->resp[2] = 0; 1724 cmd->resp[3] = 0; 1725 } 1726 } 1727 1728 if (status & SDMMC_INT_RTO) 1729 cmd->error = -ETIMEDOUT; 1730 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1731 cmd->error = -EILSEQ; 1732 else if (status & SDMMC_INT_RESP_ERR) 1733 cmd->error = -EIO; 1734 else 1735 cmd->error = 0; 1736 1737 return cmd->error; 1738 } 1739 1740 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1741 { 1742 u32 status = host->data_status; 1743 1744 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1745 if (status & SDMMC_INT_DRTO) { 1746 data->error = -ETIMEDOUT; 1747 } else if (status & SDMMC_INT_DCRC) { 1748 data->error = -EILSEQ; 1749 } else if (status & SDMMC_INT_EBE) { 1750 if (host->dir_status == 1751 DW_MCI_SEND_STATUS) { 1752 /* 1753 * No data CRC status was returned. 1754 * The number of bytes transferred 1755 * will be exaggerated in PIO mode. 1756 */ 1757 data->bytes_xfered = 0; 1758 data->error = -ETIMEDOUT; 1759 } else if (host->dir_status == 1760 DW_MCI_RECV_STATUS) { 1761 data->error = -EILSEQ; 1762 } 1763 } else { 1764 /* SDMMC_INT_SBE is included */ 1765 data->error = -EILSEQ; 1766 } 1767 1768 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1769 1770 /* 1771 * After an error, there may be data lingering 1772 * in the FIFO 1773 */ 1774 dw_mci_reset(host); 1775 } else { 1776 data->bytes_xfered = data->blocks * data->blksz; 1777 data->error = 0; 1778 } 1779 1780 return data->error; 1781 } 1782 1783 static void dw_mci_set_drto(struct dw_mci *host) 1784 { 1785 unsigned int drto_clks; 1786 unsigned int drto_ms; 1787 1788 drto_clks = mci_readl(host, TMOUT) >> 8; 1789 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 1790 1791 /* add a bit spare time */ 1792 drto_ms += 10; 1793 1794 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 1795 } 1796 1797 static void dw_mci_tasklet_func(unsigned long priv) 1798 { 1799 struct dw_mci *host = (struct dw_mci *)priv; 1800 struct mmc_data *data; 1801 struct mmc_command *cmd; 1802 struct mmc_request *mrq; 1803 enum dw_mci_state state; 1804 enum dw_mci_state prev_state; 1805 unsigned int err; 1806 1807 spin_lock(&host->lock); 1808 1809 state = host->state; 1810 data = host->data; 1811 mrq = host->mrq; 1812 1813 do { 1814 prev_state = state; 1815 1816 switch (state) { 1817 case STATE_IDLE: 1818 case STATE_WAITING_CMD11_DONE: 1819 break; 1820 1821 case STATE_SENDING_CMD11: 1822 case STATE_SENDING_CMD: 1823 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1824 &host->pending_events)) 1825 break; 1826 1827 cmd = host->cmd; 1828 host->cmd = NULL; 1829 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1830 err = dw_mci_command_complete(host, cmd); 1831 if (cmd == mrq->sbc && !err) { 1832 prev_state = state = STATE_SENDING_CMD; 1833 __dw_mci_start_request(host, host->cur_slot, 1834 mrq->cmd); 1835 goto unlock; 1836 } 1837 1838 if (cmd->data && err) { 1839 /* 1840 * During UHS tuning sequence, sending the stop 1841 * command after the response CRC error would 1842 * throw the system into a confused state 1843 * causing all future tuning phases to report 1844 * failure. 1845 * 1846 * In such case controller will move into a data 1847 * transfer state after a response error or 1848 * response CRC error. Let's let that finish 1849 * before trying to send a stop, so we'll go to 1850 * STATE_SENDING_DATA. 1851 * 1852 * Although letting the data transfer take place 1853 * will waste a bit of time (we already know 1854 * the command was bad), it can't cause any 1855 * errors since it's possible it would have 1856 * taken place anyway if this tasklet got 1857 * delayed. Allowing the transfer to take place 1858 * avoids races and keeps things simple. 1859 */ 1860 if ((err != -ETIMEDOUT) && 1861 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 1862 state = STATE_SENDING_DATA; 1863 continue; 1864 } 1865 1866 dw_mci_stop_dma(host); 1867 send_stop_abort(host, data); 1868 state = STATE_SENDING_STOP; 1869 break; 1870 } 1871 1872 if (!cmd->data || err) { 1873 dw_mci_request_end(host, mrq); 1874 goto unlock; 1875 } 1876 1877 prev_state = state = STATE_SENDING_DATA; 1878 /* fall through */ 1879 1880 case STATE_SENDING_DATA: 1881 /* 1882 * We could get a data error and never a transfer 1883 * complete so we'd better check for it here. 1884 * 1885 * Note that we don't really care if we also got a 1886 * transfer complete; stopping the DMA and sending an 1887 * abort won't hurt. 1888 */ 1889 if (test_and_clear_bit(EVENT_DATA_ERROR, 1890 &host->pending_events)) { 1891 dw_mci_stop_dma(host); 1892 if (data->stop || 1893 !(host->data_status & (SDMMC_INT_DRTO | 1894 SDMMC_INT_EBE))) 1895 send_stop_abort(host, data); 1896 state = STATE_DATA_ERROR; 1897 break; 1898 } 1899 1900 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1901 &host->pending_events)) { 1902 /* 1903 * If all data-related interrupts don't come 1904 * within the given time in reading data state. 1905 */ 1906 if (host->dir_status == DW_MCI_RECV_STATUS) 1907 dw_mci_set_drto(host); 1908 break; 1909 } 1910 1911 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 1912 1913 /* 1914 * Handle an EVENT_DATA_ERROR that might have shown up 1915 * before the transfer completed. This might not have 1916 * been caught by the check above because the interrupt 1917 * could have gone off between the previous check and 1918 * the check for transfer complete. 1919 * 1920 * Technically this ought not be needed assuming we 1921 * get a DATA_COMPLETE eventually (we'll notice the 1922 * error and end the request), but it shouldn't hurt. 1923 * 1924 * This has the advantage of sending the stop command. 1925 */ 1926 if (test_and_clear_bit(EVENT_DATA_ERROR, 1927 &host->pending_events)) { 1928 dw_mci_stop_dma(host); 1929 if (data->stop || 1930 !(host->data_status & (SDMMC_INT_DRTO | 1931 SDMMC_INT_EBE))) 1932 send_stop_abort(host, data); 1933 state = STATE_DATA_ERROR; 1934 break; 1935 } 1936 prev_state = state = STATE_DATA_BUSY; 1937 1938 /* fall through */ 1939 1940 case STATE_DATA_BUSY: 1941 if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1942 &host->pending_events)) { 1943 /* 1944 * If data error interrupt comes but data over 1945 * interrupt doesn't come within the given time. 1946 * in reading data state. 1947 */ 1948 if (host->dir_status == DW_MCI_RECV_STATUS) 1949 dw_mci_set_drto(host); 1950 break; 1951 } 1952 1953 host->data = NULL; 1954 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1955 err = dw_mci_data_complete(host, data); 1956 1957 if (!err) { 1958 if (!data->stop || mrq->sbc) { 1959 if (mrq->sbc && data->stop) 1960 data->stop->error = 0; 1961 dw_mci_request_end(host, mrq); 1962 goto unlock; 1963 } 1964 1965 /* stop command for open-ended transfer*/ 1966 if (data->stop) 1967 send_stop_abort(host, data); 1968 } else { 1969 /* 1970 * If we don't have a command complete now we'll 1971 * never get one since we just reset everything; 1972 * better end the request. 1973 * 1974 * If we do have a command complete we'll fall 1975 * through to the SENDING_STOP command and 1976 * everything will be peachy keen. 1977 */ 1978 if (!test_bit(EVENT_CMD_COMPLETE, 1979 &host->pending_events)) { 1980 host->cmd = NULL; 1981 dw_mci_request_end(host, mrq); 1982 goto unlock; 1983 } 1984 } 1985 1986 /* 1987 * If err has non-zero, 1988 * stop-abort command has been already issued. 1989 */ 1990 prev_state = state = STATE_SENDING_STOP; 1991 1992 /* fall through */ 1993 1994 case STATE_SENDING_STOP: 1995 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1996 &host->pending_events)) 1997 break; 1998 1999 /* CMD error in data command */ 2000 if (mrq->cmd->error && mrq->data) 2001 dw_mci_reset(host); 2002 2003 host->cmd = NULL; 2004 host->data = NULL; 2005 2006 if (mrq->stop) 2007 dw_mci_command_complete(host, mrq->stop); 2008 else 2009 host->cmd_status = 0; 2010 2011 dw_mci_request_end(host, mrq); 2012 goto unlock; 2013 2014 case STATE_DATA_ERROR: 2015 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2016 &host->pending_events)) 2017 break; 2018 2019 state = STATE_DATA_BUSY; 2020 break; 2021 } 2022 } while (state != prev_state); 2023 2024 host->state = state; 2025 unlock: 2026 spin_unlock(&host->lock); 2027 2028 } 2029 2030 /* push final bytes to part_buf, only use during push */ 2031 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 2032 { 2033 memcpy((void *)&host->part_buf, buf, cnt); 2034 host->part_buf_count = cnt; 2035 } 2036 2037 /* append bytes to part_buf, only use during push */ 2038 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 2039 { 2040 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 2041 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 2042 host->part_buf_count += cnt; 2043 return cnt; 2044 } 2045 2046 /* pull first bytes from part_buf, only use during pull */ 2047 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 2048 { 2049 cnt = min_t(int, cnt, host->part_buf_count); 2050 if (cnt) { 2051 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 2052 cnt); 2053 host->part_buf_count -= cnt; 2054 host->part_buf_start += cnt; 2055 } 2056 return cnt; 2057 } 2058 2059 /* pull final bytes from the part_buf, assuming it's just been filled */ 2060 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 2061 { 2062 memcpy(buf, &host->part_buf, cnt); 2063 host->part_buf_start = cnt; 2064 host->part_buf_count = (1 << host->data_shift) - cnt; 2065 } 2066 2067 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2068 { 2069 struct mmc_data *data = host->data; 2070 int init_cnt = cnt; 2071 2072 /* try and push anything in the part_buf */ 2073 if (unlikely(host->part_buf_count)) { 2074 int len = dw_mci_push_part_bytes(host, buf, cnt); 2075 2076 buf += len; 2077 cnt -= len; 2078 if (host->part_buf_count == 2) { 2079 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2080 host->part_buf_count = 0; 2081 } 2082 } 2083 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2084 if (unlikely((unsigned long)buf & 0x1)) { 2085 while (cnt >= 2) { 2086 u16 aligned_buf[64]; 2087 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2088 int items = len >> 1; 2089 int i; 2090 /* memcpy from input buffer into aligned buffer */ 2091 memcpy(aligned_buf, buf, len); 2092 buf += len; 2093 cnt -= len; 2094 /* push data from aligned buffer into fifo */ 2095 for (i = 0; i < items; ++i) 2096 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 2097 } 2098 } else 2099 #endif 2100 { 2101 u16 *pdata = buf; 2102 2103 for (; cnt >= 2; cnt -= 2) 2104 mci_fifo_writew(host->fifo_reg, *pdata++); 2105 buf = pdata; 2106 } 2107 /* put anything remaining in the part_buf */ 2108 if (cnt) { 2109 dw_mci_set_part_bytes(host, buf, cnt); 2110 /* Push data if we have reached the expected data length */ 2111 if ((data->bytes_xfered + init_cnt) == 2112 (data->blksz * data->blocks)) 2113 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2114 } 2115 } 2116 2117 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2118 { 2119 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2120 if (unlikely((unsigned long)buf & 0x1)) { 2121 while (cnt >= 2) { 2122 /* pull data from fifo into aligned buffer */ 2123 u16 aligned_buf[64]; 2124 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2125 int items = len >> 1; 2126 int i; 2127 2128 for (i = 0; i < items; ++i) 2129 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 2130 /* memcpy from aligned buffer into output buffer */ 2131 memcpy(buf, aligned_buf, len); 2132 buf += len; 2133 cnt -= len; 2134 } 2135 } else 2136 #endif 2137 { 2138 u16 *pdata = buf; 2139 2140 for (; cnt >= 2; cnt -= 2) 2141 *pdata++ = mci_fifo_readw(host->fifo_reg); 2142 buf = pdata; 2143 } 2144 if (cnt) { 2145 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 2146 dw_mci_pull_final_bytes(host, buf, cnt); 2147 } 2148 } 2149 2150 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2151 { 2152 struct mmc_data *data = host->data; 2153 int init_cnt = cnt; 2154 2155 /* try and push anything in the part_buf */ 2156 if (unlikely(host->part_buf_count)) { 2157 int len = dw_mci_push_part_bytes(host, buf, cnt); 2158 2159 buf += len; 2160 cnt -= len; 2161 if (host->part_buf_count == 4) { 2162 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2163 host->part_buf_count = 0; 2164 } 2165 } 2166 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2167 if (unlikely((unsigned long)buf & 0x3)) { 2168 while (cnt >= 4) { 2169 u32 aligned_buf[32]; 2170 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2171 int items = len >> 2; 2172 int i; 2173 /* memcpy from input buffer into aligned buffer */ 2174 memcpy(aligned_buf, buf, len); 2175 buf += len; 2176 cnt -= len; 2177 /* push data from aligned buffer into fifo */ 2178 for (i = 0; i < items; ++i) 2179 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 2180 } 2181 } else 2182 #endif 2183 { 2184 u32 *pdata = buf; 2185 2186 for (; cnt >= 4; cnt -= 4) 2187 mci_fifo_writel(host->fifo_reg, *pdata++); 2188 buf = pdata; 2189 } 2190 /* put anything remaining in the part_buf */ 2191 if (cnt) { 2192 dw_mci_set_part_bytes(host, buf, cnt); 2193 /* Push data if we have reached the expected data length */ 2194 if ((data->bytes_xfered + init_cnt) == 2195 (data->blksz * data->blocks)) 2196 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2197 } 2198 } 2199 2200 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2201 { 2202 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2203 if (unlikely((unsigned long)buf & 0x3)) { 2204 while (cnt >= 4) { 2205 /* pull data from fifo into aligned buffer */ 2206 u32 aligned_buf[32]; 2207 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2208 int items = len >> 2; 2209 int i; 2210 2211 for (i = 0; i < items; ++i) 2212 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 2213 /* memcpy from aligned buffer into output buffer */ 2214 memcpy(buf, aligned_buf, len); 2215 buf += len; 2216 cnt -= len; 2217 } 2218 } else 2219 #endif 2220 { 2221 u32 *pdata = buf; 2222 2223 for (; cnt >= 4; cnt -= 4) 2224 *pdata++ = mci_fifo_readl(host->fifo_reg); 2225 buf = pdata; 2226 } 2227 if (cnt) { 2228 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 2229 dw_mci_pull_final_bytes(host, buf, cnt); 2230 } 2231 } 2232 2233 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2234 { 2235 struct mmc_data *data = host->data; 2236 int init_cnt = cnt; 2237 2238 /* try and push anything in the part_buf */ 2239 if (unlikely(host->part_buf_count)) { 2240 int len = dw_mci_push_part_bytes(host, buf, cnt); 2241 2242 buf += len; 2243 cnt -= len; 2244 2245 if (host->part_buf_count == 8) { 2246 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2247 host->part_buf_count = 0; 2248 } 2249 } 2250 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2251 if (unlikely((unsigned long)buf & 0x7)) { 2252 while (cnt >= 8) { 2253 u64 aligned_buf[16]; 2254 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2255 int items = len >> 3; 2256 int i; 2257 /* memcpy from input buffer into aligned buffer */ 2258 memcpy(aligned_buf, buf, len); 2259 buf += len; 2260 cnt -= len; 2261 /* push data from aligned buffer into fifo */ 2262 for (i = 0; i < items; ++i) 2263 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2264 } 2265 } else 2266 #endif 2267 { 2268 u64 *pdata = buf; 2269 2270 for (; cnt >= 8; cnt -= 8) 2271 mci_fifo_writeq(host->fifo_reg, *pdata++); 2272 buf = pdata; 2273 } 2274 /* put anything remaining in the part_buf */ 2275 if (cnt) { 2276 dw_mci_set_part_bytes(host, buf, cnt); 2277 /* Push data if we have reached the expected data length */ 2278 if ((data->bytes_xfered + init_cnt) == 2279 (data->blksz * data->blocks)) 2280 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2281 } 2282 } 2283 2284 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2285 { 2286 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2287 if (unlikely((unsigned long)buf & 0x7)) { 2288 while (cnt >= 8) { 2289 /* pull data from fifo into aligned buffer */ 2290 u64 aligned_buf[16]; 2291 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2292 int items = len >> 3; 2293 int i; 2294 2295 for (i = 0; i < items; ++i) 2296 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2297 2298 /* memcpy from aligned buffer into output buffer */ 2299 memcpy(buf, aligned_buf, len); 2300 buf += len; 2301 cnt -= len; 2302 } 2303 } else 2304 #endif 2305 { 2306 u64 *pdata = buf; 2307 2308 for (; cnt >= 8; cnt -= 8) 2309 *pdata++ = mci_fifo_readq(host->fifo_reg); 2310 buf = pdata; 2311 } 2312 if (cnt) { 2313 host->part_buf = mci_fifo_readq(host->fifo_reg); 2314 dw_mci_pull_final_bytes(host, buf, cnt); 2315 } 2316 } 2317 2318 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2319 { 2320 int len; 2321 2322 /* get remaining partial bytes */ 2323 len = dw_mci_pull_part_bytes(host, buf, cnt); 2324 if (unlikely(len == cnt)) 2325 return; 2326 buf += len; 2327 cnt -= len; 2328 2329 /* get the rest of the data */ 2330 host->pull_data(host, buf, cnt); 2331 } 2332 2333 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2334 { 2335 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2336 void *buf; 2337 unsigned int offset; 2338 struct mmc_data *data = host->data; 2339 int shift = host->data_shift; 2340 u32 status; 2341 unsigned int len; 2342 unsigned int remain, fcnt; 2343 2344 do { 2345 if (!sg_miter_next(sg_miter)) 2346 goto done; 2347 2348 host->sg = sg_miter->piter.sg; 2349 buf = sg_miter->addr; 2350 remain = sg_miter->length; 2351 offset = 0; 2352 2353 do { 2354 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2355 << shift) + host->part_buf_count; 2356 len = min(remain, fcnt); 2357 if (!len) 2358 break; 2359 dw_mci_pull_data(host, (void *)(buf + offset), len); 2360 data->bytes_xfered += len; 2361 offset += len; 2362 remain -= len; 2363 } while (remain); 2364 2365 sg_miter->consumed = offset; 2366 status = mci_readl(host, MINTSTS); 2367 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2368 /* if the RXDR is ready read again */ 2369 } while ((status & SDMMC_INT_RXDR) || 2370 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2371 2372 if (!remain) { 2373 if (!sg_miter_next(sg_miter)) 2374 goto done; 2375 sg_miter->consumed = 0; 2376 } 2377 sg_miter_stop(sg_miter); 2378 return; 2379 2380 done: 2381 sg_miter_stop(sg_miter); 2382 host->sg = NULL; 2383 smp_wmb(); /* drain writebuffer */ 2384 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2385 } 2386 2387 static void dw_mci_write_data_pio(struct dw_mci *host) 2388 { 2389 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2390 void *buf; 2391 unsigned int offset; 2392 struct mmc_data *data = host->data; 2393 int shift = host->data_shift; 2394 u32 status; 2395 unsigned int len; 2396 unsigned int fifo_depth = host->fifo_depth; 2397 unsigned int remain, fcnt; 2398 2399 do { 2400 if (!sg_miter_next(sg_miter)) 2401 goto done; 2402 2403 host->sg = sg_miter->piter.sg; 2404 buf = sg_miter->addr; 2405 remain = sg_miter->length; 2406 offset = 0; 2407 2408 do { 2409 fcnt = ((fifo_depth - 2410 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2411 << shift) - host->part_buf_count; 2412 len = min(remain, fcnt); 2413 if (!len) 2414 break; 2415 host->push_data(host, (void *)(buf + offset), len); 2416 data->bytes_xfered += len; 2417 offset += len; 2418 remain -= len; 2419 } while (remain); 2420 2421 sg_miter->consumed = offset; 2422 status = mci_readl(host, MINTSTS); 2423 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2424 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2425 2426 if (!remain) { 2427 if (!sg_miter_next(sg_miter)) 2428 goto done; 2429 sg_miter->consumed = 0; 2430 } 2431 sg_miter_stop(sg_miter); 2432 return; 2433 2434 done: 2435 sg_miter_stop(sg_miter); 2436 host->sg = NULL; 2437 smp_wmb(); /* drain writebuffer */ 2438 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2439 } 2440 2441 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2442 { 2443 if (!host->cmd_status) 2444 host->cmd_status = status; 2445 2446 smp_wmb(); /* drain writebuffer */ 2447 2448 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2449 tasklet_schedule(&host->tasklet); 2450 } 2451 2452 static void dw_mci_handle_cd(struct dw_mci *host) 2453 { 2454 int i; 2455 2456 for (i = 0; i < host->num_slots; i++) { 2457 struct dw_mci_slot *slot = host->slot[i]; 2458 2459 if (!slot) 2460 continue; 2461 2462 if (slot->mmc->ops->card_event) 2463 slot->mmc->ops->card_event(slot->mmc); 2464 mmc_detect_change(slot->mmc, 2465 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2466 } 2467 } 2468 2469 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2470 { 2471 struct dw_mci *host = dev_id; 2472 u32 pending; 2473 int i; 2474 2475 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2476 2477 if (pending) { 2478 /* Check volt switch first, since it can look like an error */ 2479 if ((host->state == STATE_SENDING_CMD11) && 2480 (pending & SDMMC_INT_VOLT_SWITCH)) { 2481 unsigned long irqflags; 2482 2483 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2484 pending &= ~SDMMC_INT_VOLT_SWITCH; 2485 2486 /* 2487 * Hold the lock; we know cmd11_timer can't be kicked 2488 * off after the lock is released, so safe to delete. 2489 */ 2490 spin_lock_irqsave(&host->irq_lock, irqflags); 2491 dw_mci_cmd_interrupt(host, pending); 2492 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2493 2494 del_timer(&host->cmd11_timer); 2495 } 2496 2497 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2498 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2499 host->cmd_status = pending; 2500 smp_wmb(); /* drain writebuffer */ 2501 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2502 } 2503 2504 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2505 /* if there is an error report DATA_ERROR */ 2506 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2507 host->data_status = pending; 2508 smp_wmb(); /* drain writebuffer */ 2509 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2510 tasklet_schedule(&host->tasklet); 2511 } 2512 2513 if (pending & SDMMC_INT_DATA_OVER) { 2514 del_timer(&host->dto_timer); 2515 2516 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2517 if (!host->data_status) 2518 host->data_status = pending; 2519 smp_wmb(); /* drain writebuffer */ 2520 if (host->dir_status == DW_MCI_RECV_STATUS) { 2521 if (host->sg != NULL) 2522 dw_mci_read_data_pio(host, true); 2523 } 2524 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2525 tasklet_schedule(&host->tasklet); 2526 } 2527 2528 if (pending & SDMMC_INT_RXDR) { 2529 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2530 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2531 dw_mci_read_data_pio(host, false); 2532 } 2533 2534 if (pending & SDMMC_INT_TXDR) { 2535 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2536 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2537 dw_mci_write_data_pio(host); 2538 } 2539 2540 if (pending & SDMMC_INT_CMD_DONE) { 2541 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2542 dw_mci_cmd_interrupt(host, pending); 2543 } 2544 2545 if (pending & SDMMC_INT_CD) { 2546 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2547 dw_mci_handle_cd(host); 2548 } 2549 2550 /* Handle SDIO Interrupts */ 2551 for (i = 0; i < host->num_slots; i++) { 2552 struct dw_mci_slot *slot = host->slot[i]; 2553 2554 if (!slot) 2555 continue; 2556 2557 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2558 mci_writel(host, RINTSTS, 2559 SDMMC_INT_SDIO(slot->sdio_id)); 2560 mmc_signal_sdio_irq(slot->mmc); 2561 } 2562 } 2563 2564 } 2565 2566 if (host->use_dma != TRANS_MODE_IDMAC) 2567 return IRQ_HANDLED; 2568 2569 /* Handle IDMA interrupts */ 2570 if (host->dma_64bit_address == 1) { 2571 pending = mci_readl(host, IDSTS64); 2572 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2573 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2574 SDMMC_IDMAC_INT_RI); 2575 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2576 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2577 host->dma_ops->complete((void *)host); 2578 } 2579 } else { 2580 pending = mci_readl(host, IDSTS); 2581 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2582 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2583 SDMMC_IDMAC_INT_RI); 2584 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2585 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2586 host->dma_ops->complete((void *)host); 2587 } 2588 } 2589 2590 return IRQ_HANDLED; 2591 } 2592 2593 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2594 { 2595 struct mmc_host *mmc; 2596 struct dw_mci_slot *slot; 2597 const struct dw_mci_drv_data *drv_data = host->drv_data; 2598 int ctrl_id, ret; 2599 u32 freq[2]; 2600 2601 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2602 if (!mmc) 2603 return -ENOMEM; 2604 2605 slot = mmc_priv(mmc); 2606 slot->id = id; 2607 slot->sdio_id = host->sdio_id0 + id; 2608 slot->mmc = mmc; 2609 slot->host = host; 2610 host->slot[id] = slot; 2611 2612 mmc->ops = &dw_mci_ops; 2613 if (of_property_read_u32_array(host->dev->of_node, 2614 "clock-freq-min-max", freq, 2)) { 2615 mmc->f_min = DW_MCI_FREQ_MIN; 2616 mmc->f_max = DW_MCI_FREQ_MAX; 2617 } else { 2618 mmc->f_min = freq[0]; 2619 mmc->f_max = freq[1]; 2620 } 2621 2622 /*if there are external regulators, get them*/ 2623 ret = mmc_regulator_get_supply(mmc); 2624 if (ret == -EPROBE_DEFER) 2625 goto err_host_allocated; 2626 2627 if (!mmc->ocr_avail) 2628 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2629 2630 if (host->pdata->caps) 2631 mmc->caps = host->pdata->caps; 2632 2633 /* 2634 * Support MMC_CAP_ERASE by default. 2635 * It needs to use trim/discard/erase commands. 2636 */ 2637 mmc->caps |= MMC_CAP_ERASE; 2638 2639 if (host->pdata->pm_caps) 2640 mmc->pm_caps = host->pdata->pm_caps; 2641 2642 if (host->dev->of_node) { 2643 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2644 if (ctrl_id < 0) 2645 ctrl_id = 0; 2646 } else { 2647 ctrl_id = to_platform_device(host->dev)->id; 2648 } 2649 if (drv_data && drv_data->caps) 2650 mmc->caps |= drv_data->caps[ctrl_id]; 2651 2652 if (host->pdata->caps2) 2653 mmc->caps2 = host->pdata->caps2; 2654 2655 ret = mmc_of_parse(mmc); 2656 if (ret) 2657 goto err_host_allocated; 2658 2659 /* Useful defaults if platform data is unset. */ 2660 if (host->use_dma == TRANS_MODE_IDMAC) { 2661 mmc->max_segs = host->ring_size; 2662 mmc->max_blk_size = 65535; 2663 mmc->max_seg_size = 0x1000; 2664 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2665 mmc->max_blk_count = mmc->max_req_size / 512; 2666 } else if (host->use_dma == TRANS_MODE_EDMAC) { 2667 mmc->max_segs = 64; 2668 mmc->max_blk_size = 65535; 2669 mmc->max_blk_count = 65535; 2670 mmc->max_req_size = 2671 mmc->max_blk_size * mmc->max_blk_count; 2672 mmc->max_seg_size = mmc->max_req_size; 2673 } else { 2674 /* TRANS_MODE_PIO */ 2675 mmc->max_segs = 64; 2676 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2677 mmc->max_blk_count = 512; 2678 mmc->max_req_size = mmc->max_blk_size * 2679 mmc->max_blk_count; 2680 mmc->max_seg_size = mmc->max_req_size; 2681 } 2682 2683 dw_mci_get_cd(mmc); 2684 2685 ret = mmc_add_host(mmc); 2686 if (ret) 2687 goto err_host_allocated; 2688 2689 #if defined(CONFIG_DEBUG_FS) 2690 dw_mci_init_debugfs(slot); 2691 #endif 2692 2693 return 0; 2694 2695 err_host_allocated: 2696 mmc_free_host(mmc); 2697 return ret; 2698 } 2699 2700 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2701 { 2702 /* Debugfs stuff is cleaned up by mmc core */ 2703 mmc_remove_host(slot->mmc); 2704 slot->host->slot[id] = NULL; 2705 mmc_free_host(slot->mmc); 2706 } 2707 2708 static void dw_mci_init_dma(struct dw_mci *host) 2709 { 2710 int addr_config; 2711 struct device *dev = host->dev; 2712 struct device_node *np = dev->of_node; 2713 2714 /* 2715 * Check tansfer mode from HCON[17:16] 2716 * Clear the ambiguous description of dw_mmc databook: 2717 * 2b'00: No DMA Interface -> Actually means using Internal DMA block 2718 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 2719 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 2720 * 2b'11: Non DW DMA Interface -> pio only 2721 * Compared to DesignWare DMA Interface, Generic DMA Interface has a 2722 * simpler request/acknowledge handshake mechanism and both of them 2723 * are regarded as external dma master for dw_mmc. 2724 */ 2725 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 2726 if (host->use_dma == DMA_INTERFACE_IDMA) { 2727 host->use_dma = TRANS_MODE_IDMAC; 2728 } else if (host->use_dma == DMA_INTERFACE_DWDMA || 2729 host->use_dma == DMA_INTERFACE_GDMA) { 2730 host->use_dma = TRANS_MODE_EDMAC; 2731 } else { 2732 goto no_dma; 2733 } 2734 2735 /* Determine which DMA interface to use */ 2736 if (host->use_dma == TRANS_MODE_IDMAC) { 2737 /* 2738 * Check ADDR_CONFIG bit in HCON to find 2739 * IDMAC address bus width 2740 */ 2741 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 2742 2743 if (addr_config == 1) { 2744 /* host supports IDMAC in 64-bit address mode */ 2745 host->dma_64bit_address = 1; 2746 dev_info(host->dev, 2747 "IDMAC supports 64-bit address mode.\n"); 2748 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2749 dma_set_coherent_mask(host->dev, 2750 DMA_BIT_MASK(64)); 2751 } else { 2752 /* host supports IDMAC in 32-bit address mode */ 2753 host->dma_64bit_address = 0; 2754 dev_info(host->dev, 2755 "IDMAC supports 32-bit address mode.\n"); 2756 } 2757 2758 /* Alloc memory for sg translation */ 2759 host->sg_cpu = dmam_alloc_coherent(host->dev, 2760 DESC_RING_BUF_SZ, 2761 &host->sg_dma, GFP_KERNEL); 2762 if (!host->sg_cpu) { 2763 dev_err(host->dev, 2764 "%s: could not alloc DMA memory\n", 2765 __func__); 2766 goto no_dma; 2767 } 2768 2769 host->dma_ops = &dw_mci_idmac_ops; 2770 dev_info(host->dev, "Using internal DMA controller.\n"); 2771 } else { 2772 /* TRANS_MODE_EDMAC: check dma bindings again */ 2773 if ((of_property_count_strings(np, "dma-names") < 0) || 2774 (!of_find_property(np, "dmas", NULL))) { 2775 goto no_dma; 2776 } 2777 host->dma_ops = &dw_mci_edmac_ops; 2778 dev_info(host->dev, "Using external DMA controller.\n"); 2779 } 2780 2781 if (host->dma_ops->init && host->dma_ops->start && 2782 host->dma_ops->stop && host->dma_ops->cleanup) { 2783 if (host->dma_ops->init(host)) { 2784 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 2785 __func__); 2786 goto no_dma; 2787 } 2788 } else { 2789 dev_err(host->dev, "DMA initialization not found.\n"); 2790 goto no_dma; 2791 } 2792 2793 return; 2794 2795 no_dma: 2796 dev_info(host->dev, "Using PIO mode.\n"); 2797 host->use_dma = TRANS_MODE_PIO; 2798 } 2799 2800 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2801 { 2802 unsigned long timeout = jiffies + msecs_to_jiffies(500); 2803 u32 ctrl; 2804 2805 ctrl = mci_readl(host, CTRL); 2806 ctrl |= reset; 2807 mci_writel(host, CTRL, ctrl); 2808 2809 /* wait till resets clear */ 2810 do { 2811 ctrl = mci_readl(host, CTRL); 2812 if (!(ctrl & reset)) 2813 return true; 2814 } while (time_before(jiffies, timeout)); 2815 2816 dev_err(host->dev, 2817 "Timeout resetting block (ctrl reset %#x)\n", 2818 ctrl & reset); 2819 2820 return false; 2821 } 2822 2823 static bool dw_mci_reset(struct dw_mci *host) 2824 { 2825 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 2826 bool ret = false; 2827 2828 /* 2829 * Reseting generates a block interrupt, hence setting 2830 * the scatter-gather pointer to NULL. 2831 */ 2832 if (host->sg) { 2833 sg_miter_stop(&host->sg_miter); 2834 host->sg = NULL; 2835 } 2836 2837 if (host->use_dma) 2838 flags |= SDMMC_CTRL_DMA_RESET; 2839 2840 if (dw_mci_ctrl_reset(host, flags)) { 2841 /* 2842 * In all cases we clear the RAWINTS register to clear any 2843 * interrupts. 2844 */ 2845 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2846 2847 /* if using dma we wait for dma_req to clear */ 2848 if (host->use_dma) { 2849 unsigned long timeout = jiffies + msecs_to_jiffies(500); 2850 u32 status; 2851 2852 do { 2853 status = mci_readl(host, STATUS); 2854 if (!(status & SDMMC_STATUS_DMA_REQ)) 2855 break; 2856 cpu_relax(); 2857 } while (time_before(jiffies, timeout)); 2858 2859 if (status & SDMMC_STATUS_DMA_REQ) { 2860 dev_err(host->dev, 2861 "%s: Timeout waiting for dma_req to clear during reset\n", 2862 __func__); 2863 goto ciu_out; 2864 } 2865 2866 /* when using DMA next we reset the fifo again */ 2867 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 2868 goto ciu_out; 2869 } 2870 } else { 2871 /* if the controller reset bit did clear, then set clock regs */ 2872 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 2873 dev_err(host->dev, 2874 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 2875 __func__); 2876 goto ciu_out; 2877 } 2878 } 2879 2880 if (host->use_dma == TRANS_MODE_IDMAC) 2881 /* It is also recommended that we reset and reprogram idmac */ 2882 dw_mci_idmac_reset(host); 2883 2884 ret = true; 2885 2886 ciu_out: 2887 /* After a CTRL reset we need to have CIU set clock registers */ 2888 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 2889 2890 return ret; 2891 } 2892 2893 static void dw_mci_cmd11_timer(unsigned long arg) 2894 { 2895 struct dw_mci *host = (struct dw_mci *)arg; 2896 2897 if (host->state != STATE_SENDING_CMD11) { 2898 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2899 return; 2900 } 2901 2902 host->cmd_status = SDMMC_INT_RTO; 2903 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2904 tasklet_schedule(&host->tasklet); 2905 } 2906 2907 static void dw_mci_dto_timer(unsigned long arg) 2908 { 2909 struct dw_mci *host = (struct dw_mci *)arg; 2910 2911 switch (host->state) { 2912 case STATE_SENDING_DATA: 2913 case STATE_DATA_BUSY: 2914 /* 2915 * If DTO interrupt does NOT come in sending data state, 2916 * we should notify the driver to terminate current transfer 2917 * and report a data timeout to the core. 2918 */ 2919 host->data_status = SDMMC_INT_DRTO; 2920 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2921 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2922 tasklet_schedule(&host->tasklet); 2923 break; 2924 default: 2925 break; 2926 } 2927 } 2928 2929 #ifdef CONFIG_OF 2930 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2931 { 2932 struct dw_mci_board *pdata; 2933 struct device *dev = host->dev; 2934 struct device_node *np = dev->of_node; 2935 const struct dw_mci_drv_data *drv_data = host->drv_data; 2936 int ret; 2937 u32 clock_frequency; 2938 2939 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2940 if (!pdata) 2941 return ERR_PTR(-ENOMEM); 2942 2943 /* find reset controller when exist */ 2944 pdata->rstc = devm_reset_control_get_optional(dev, "reset"); 2945 if (IS_ERR(pdata->rstc)) { 2946 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 2947 return ERR_PTR(-EPROBE_DEFER); 2948 } 2949 2950 /* find out number of slots supported */ 2951 of_property_read_u32(np, "num-slots", &pdata->num_slots); 2952 2953 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2954 dev_info(dev, 2955 "fifo-depth property not found, using value of FIFOTH register as default\n"); 2956 2957 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2958 2959 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 2960 pdata->bus_hz = clock_frequency; 2961 2962 if (drv_data && drv_data->parse_dt) { 2963 ret = drv_data->parse_dt(host); 2964 if (ret) 2965 return ERR_PTR(ret); 2966 } 2967 2968 return pdata; 2969 } 2970 2971 #else /* CONFIG_OF */ 2972 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2973 { 2974 return ERR_PTR(-EINVAL); 2975 } 2976 #endif /* CONFIG_OF */ 2977 2978 static void dw_mci_enable_cd(struct dw_mci *host) 2979 { 2980 unsigned long irqflags; 2981 u32 temp; 2982 int i; 2983 struct dw_mci_slot *slot; 2984 2985 /* 2986 * No need for CD if all slots have a non-error GPIO 2987 * as well as broken card detection is found. 2988 */ 2989 for (i = 0; i < host->num_slots; i++) { 2990 slot = host->slot[i]; 2991 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL) 2992 return; 2993 2994 if (mmc_gpio_get_cd(slot->mmc) < 0) 2995 break; 2996 } 2997 if (i == host->num_slots) 2998 return; 2999 3000 spin_lock_irqsave(&host->irq_lock, irqflags); 3001 temp = mci_readl(host, INTMASK); 3002 temp |= SDMMC_INT_CD; 3003 mci_writel(host, INTMASK, temp); 3004 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3005 } 3006 3007 int dw_mci_probe(struct dw_mci *host) 3008 { 3009 const struct dw_mci_drv_data *drv_data = host->drv_data; 3010 int width, i, ret = 0; 3011 u32 fifo_size; 3012 int init_slots = 0; 3013 3014 if (!host->pdata) { 3015 host->pdata = dw_mci_parse_dt(host); 3016 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3017 return -EPROBE_DEFER; 3018 } else if (IS_ERR(host->pdata)) { 3019 dev_err(host->dev, "platform data not available\n"); 3020 return -EINVAL; 3021 } 3022 } 3023 3024 host->biu_clk = devm_clk_get(host->dev, "biu"); 3025 if (IS_ERR(host->biu_clk)) { 3026 dev_dbg(host->dev, "biu clock not available\n"); 3027 } else { 3028 ret = clk_prepare_enable(host->biu_clk); 3029 if (ret) { 3030 dev_err(host->dev, "failed to enable biu clock\n"); 3031 return ret; 3032 } 3033 } 3034 3035 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3036 if (IS_ERR(host->ciu_clk)) { 3037 dev_dbg(host->dev, "ciu clock not available\n"); 3038 host->bus_hz = host->pdata->bus_hz; 3039 } else { 3040 ret = clk_prepare_enable(host->ciu_clk); 3041 if (ret) { 3042 dev_err(host->dev, "failed to enable ciu clock\n"); 3043 goto err_clk_biu; 3044 } 3045 3046 if (host->pdata->bus_hz) { 3047 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 3048 if (ret) 3049 dev_warn(host->dev, 3050 "Unable to set bus rate to %uHz\n", 3051 host->pdata->bus_hz); 3052 } 3053 host->bus_hz = clk_get_rate(host->ciu_clk); 3054 } 3055 3056 if (!host->bus_hz) { 3057 dev_err(host->dev, 3058 "Platform data must supply bus speed\n"); 3059 ret = -ENODEV; 3060 goto err_clk_ciu; 3061 } 3062 3063 if (drv_data && drv_data->init) { 3064 ret = drv_data->init(host); 3065 if (ret) { 3066 dev_err(host->dev, 3067 "implementation specific init failed\n"); 3068 goto err_clk_ciu; 3069 } 3070 } 3071 3072 if (!IS_ERR(host->pdata->rstc)) { 3073 reset_control_assert(host->pdata->rstc); 3074 usleep_range(10, 50); 3075 reset_control_deassert(host->pdata->rstc); 3076 } 3077 3078 setup_timer(&host->cmd11_timer, 3079 dw_mci_cmd11_timer, (unsigned long)host); 3080 3081 setup_timer(&host->dto_timer, 3082 dw_mci_dto_timer, (unsigned long)host); 3083 3084 spin_lock_init(&host->lock); 3085 spin_lock_init(&host->irq_lock); 3086 INIT_LIST_HEAD(&host->queue); 3087 3088 /* 3089 * Get the host data width - this assumes that HCON has been set with 3090 * the correct values. 3091 */ 3092 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3093 if (!i) { 3094 host->push_data = dw_mci_push_data16; 3095 host->pull_data = dw_mci_pull_data16; 3096 width = 16; 3097 host->data_shift = 1; 3098 } else if (i == 2) { 3099 host->push_data = dw_mci_push_data64; 3100 host->pull_data = dw_mci_pull_data64; 3101 width = 64; 3102 host->data_shift = 3; 3103 } else { 3104 /* Check for a reserved value, and warn if it is */ 3105 WARN((i != 1), 3106 "HCON reports a reserved host data width!\n" 3107 "Defaulting to 32-bit access.\n"); 3108 host->push_data = dw_mci_push_data32; 3109 host->pull_data = dw_mci_pull_data32; 3110 width = 32; 3111 host->data_shift = 2; 3112 } 3113 3114 /* Reset all blocks */ 3115 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3116 ret = -ENODEV; 3117 goto err_clk_ciu; 3118 } 3119 3120 host->dma_ops = host->pdata->dma_ops; 3121 dw_mci_init_dma(host); 3122 3123 /* Clear the interrupts for the host controller */ 3124 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3125 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3126 3127 /* Put in max timeout */ 3128 mci_writel(host, TMOUT, 0xFFFFFFFF); 3129 3130 /* 3131 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3132 * Tx Mark = fifo_size / 2 DMA Size = 8 3133 */ 3134 if (!host->pdata->fifo_depth) { 3135 /* 3136 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3137 * have been overwritten by the bootloader, just like we're 3138 * about to do, so if you know the value for your hardware, you 3139 * should put it in the platform data. 3140 */ 3141 fifo_size = mci_readl(host, FIFOTH); 3142 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3143 } else { 3144 fifo_size = host->pdata->fifo_depth; 3145 } 3146 host->fifo_depth = fifo_size; 3147 host->fifoth_val = 3148 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3149 mci_writel(host, FIFOTH, host->fifoth_val); 3150 3151 /* disable clock to CIU */ 3152 mci_writel(host, CLKENA, 0); 3153 mci_writel(host, CLKSRC, 0); 3154 3155 /* 3156 * In 2.40a spec, Data offset is changed. 3157 * Need to check the version-id and set data-offset for DATA register. 3158 */ 3159 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 3160 dev_info(host->dev, "Version ID is %04x\n", host->verid); 3161 3162 if (host->verid < DW_MMC_240A) 3163 host->fifo_reg = host->regs + DATA_OFFSET; 3164 else 3165 host->fifo_reg = host->regs + DATA_240A_OFFSET; 3166 3167 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3168 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3169 host->irq_flags, "dw-mci", host); 3170 if (ret) 3171 goto err_dmaunmap; 3172 3173 if (host->pdata->num_slots) 3174 host->num_slots = host->pdata->num_slots; 3175 else 3176 host->num_slots = 1; 3177 3178 if (host->num_slots < 1 || 3179 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) { 3180 dev_err(host->dev, 3181 "Platform data must supply correct num_slots.\n"); 3182 ret = -ENODEV; 3183 goto err_clk_ciu; 3184 } 3185 3186 /* 3187 * Enable interrupts for command done, data over, data empty, 3188 * receive ready and error such as transmit, receive timeout, crc error 3189 */ 3190 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3191 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3192 DW_MCI_ERROR_FLAGS); 3193 /* Enable mci interrupt */ 3194 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3195 3196 dev_info(host->dev, 3197 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 3198 host->irq, width, fifo_size); 3199 3200 /* We need at least one slot to succeed */ 3201 for (i = 0; i < host->num_slots; i++) { 3202 ret = dw_mci_init_slot(host, i); 3203 if (ret) 3204 dev_dbg(host->dev, "slot %d init failed\n", i); 3205 else 3206 init_slots++; 3207 } 3208 3209 if (init_slots) { 3210 dev_info(host->dev, "%d slots initialized\n", init_slots); 3211 } else { 3212 dev_dbg(host->dev, 3213 "attempted to initialize %d slots, but failed on all\n", 3214 host->num_slots); 3215 goto err_dmaunmap; 3216 } 3217 3218 /* Now that slots are all setup, we can enable card detect */ 3219 dw_mci_enable_cd(host); 3220 3221 return 0; 3222 3223 err_dmaunmap: 3224 if (host->use_dma && host->dma_ops->exit) 3225 host->dma_ops->exit(host); 3226 3227 if (!IS_ERR(host->pdata->rstc)) 3228 reset_control_assert(host->pdata->rstc); 3229 3230 err_clk_ciu: 3231 clk_disable_unprepare(host->ciu_clk); 3232 3233 err_clk_biu: 3234 clk_disable_unprepare(host->biu_clk); 3235 3236 return ret; 3237 } 3238 EXPORT_SYMBOL(dw_mci_probe); 3239 3240 void dw_mci_remove(struct dw_mci *host) 3241 { 3242 int i; 3243 3244 for (i = 0; i < host->num_slots; i++) { 3245 dev_dbg(host->dev, "remove slot %d\n", i); 3246 if (host->slot[i]) 3247 dw_mci_cleanup_slot(host->slot[i], i); 3248 } 3249 3250 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3251 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3252 3253 /* disable clock to CIU */ 3254 mci_writel(host, CLKENA, 0); 3255 mci_writel(host, CLKSRC, 0); 3256 3257 if (host->use_dma && host->dma_ops->exit) 3258 host->dma_ops->exit(host); 3259 3260 if (!IS_ERR(host->pdata->rstc)) 3261 reset_control_assert(host->pdata->rstc); 3262 3263 clk_disable_unprepare(host->ciu_clk); 3264 clk_disable_unprepare(host->biu_clk); 3265 } 3266 EXPORT_SYMBOL(dw_mci_remove); 3267 3268 3269 3270 #ifdef CONFIG_PM 3271 /* 3272 * TODO: we should probably disable the clock to the card in the suspend path. 3273 */ 3274 int dw_mci_suspend(struct dw_mci *host) 3275 { 3276 if (host->use_dma && host->dma_ops->exit) 3277 host->dma_ops->exit(host); 3278 3279 return 0; 3280 } 3281 EXPORT_SYMBOL(dw_mci_suspend); 3282 3283 int dw_mci_resume(struct dw_mci *host) 3284 { 3285 int i, ret; 3286 3287 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3288 ret = -ENODEV; 3289 return ret; 3290 } 3291 3292 if (host->use_dma && host->dma_ops->init) 3293 host->dma_ops->init(host); 3294 3295 /* 3296 * Restore the initial value at FIFOTH register 3297 * And Invalidate the prev_blksz with zero 3298 */ 3299 mci_writel(host, FIFOTH, host->fifoth_val); 3300 host->prev_blksz = 0; 3301 3302 /* Put in max timeout */ 3303 mci_writel(host, TMOUT, 0xFFFFFFFF); 3304 3305 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3306 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3307 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3308 DW_MCI_ERROR_FLAGS); 3309 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3310 3311 for (i = 0; i < host->num_slots; i++) { 3312 struct dw_mci_slot *slot = host->slot[i]; 3313 3314 if (!slot) 3315 continue; 3316 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 3317 dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3318 dw_mci_setup_bus(slot, true); 3319 } 3320 } 3321 3322 /* Now that slots are all setup, we can enable card detect */ 3323 dw_mci_enable_cd(host); 3324 3325 return 0; 3326 } 3327 EXPORT_SYMBOL(dw_mci_resume); 3328 3329 int dw_mci_runtime_suspend(struct device *dev) 3330 { 3331 int err = 0; 3332 struct dw_mci *host = dev_get_drvdata(dev); 3333 3334 err = dw_mci_suspend(host); 3335 if (err) 3336 return err; 3337 3338 clk_disable_unprepare(host->ciu_clk); 3339 3340 if (host->cur_slot && 3341 (mmc_can_gpio_cd(host->cur_slot->mmc) || 3342 !mmc_card_is_removable(host->cur_slot->mmc))) 3343 clk_disable_unprepare(host->biu_clk); 3344 3345 return err; 3346 } 3347 EXPORT_SYMBOL(dw_mci_runtime_suspend); 3348 3349 int dw_mci_runtime_resume(struct device *dev) 3350 { 3351 int ret = 0; 3352 struct dw_mci *host = dev_get_drvdata(dev); 3353 3354 if (host->cur_slot && 3355 (mmc_can_gpio_cd(host->cur_slot->mmc) || 3356 !mmc_card_is_removable(host->cur_slot->mmc))) { 3357 ret = clk_prepare_enable(host->biu_clk); 3358 if (ret) 3359 return ret; 3360 } 3361 3362 ret = clk_prepare_enable(host->ciu_clk); 3363 if (ret) 3364 return ret; 3365 3366 return dw_mci_resume(host); 3367 } 3368 EXPORT_SYMBOL(dw_mci_runtime_resume); 3369 #endif /* CONFIG_PM */ 3370 3371 static int __init dw_mci_init(void) 3372 { 3373 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3374 return 0; 3375 } 3376 3377 static void __exit dw_mci_exit(void) 3378 { 3379 } 3380 3381 module_init(dw_mci_init); 3382 module_exit(dw_mci_exit); 3383 3384 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3385 MODULE_AUTHOR("NXP Semiconductor VietNam"); 3386 MODULE_AUTHOR("Imagination Technologies Ltd"); 3387 MODULE_LICENSE("GPL v2"); 3388