1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 477a3c5677SDoug Anderson SDMMC_INT_EBE | SDMMC_INT_HLE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 497a3c5677SDoug Anderson SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 517a3c5677SDoug Anderson DW_MCI_CMD_ERROR_FLAGS) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 60fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 63fc79a4d6SJoonyoung Shim 6469d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6569d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6669d99fdcSPrabu Thangamuthu 6769d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 6869d99fdcSPrabu Thangamuthu 6969d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7069d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 716687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 726687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7569d99fdcSPrabu Thangamuthu 7669d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7769d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8069d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8169d99fdcSPrabu Thangamuthu }; 8269d99fdcSPrabu Thangamuthu 83f95f3850SWill Newton struct idmac_desc { 846687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 85f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 86f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 87f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 88f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 89f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 90f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 91f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 92f95f3850SWill Newton 936687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 94f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 95e5306c3aSBen Dooks ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 96f95f3850SWill Newton 976687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 98f95f3850SWill Newton 996687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 100f95f3850SWill Newton }; 1015959b32eSAlexey Brodkin 1025959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1035959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 104f95f3850SWill Newton 1053a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 106536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 1070bdbd0e8SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc); 10856f6911cSShawn Lin static int dw_mci_get_cd(struct mmc_host *mmc); 10931bff450SSeungwon Jeon 110f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 111f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 112f95f3850SWill Newton { 113f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 114f95f3850SWill Newton struct mmc_request *mrq; 115f95f3850SWill Newton struct mmc_command *cmd; 116f95f3850SWill Newton struct mmc_command *stop; 117f95f3850SWill Newton struct mmc_data *data; 118f95f3850SWill Newton 119f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 120f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 121f95f3850SWill Newton mrq = slot->mrq; 122f95f3850SWill Newton 123f95f3850SWill Newton if (mrq) { 124f95f3850SWill Newton cmd = mrq->cmd; 125f95f3850SWill Newton data = mrq->data; 126f95f3850SWill Newton stop = mrq->stop; 127f95f3850SWill Newton 128f95f3850SWill Newton if (cmd) 129f95f3850SWill Newton seq_printf(s, 130f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 132f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 133f95f3850SWill Newton cmd->resp[2], cmd->error); 134f95f3850SWill Newton if (data) 135f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136f95f3850SWill Newton data->bytes_xfered, data->blocks, 137f95f3850SWill Newton data->blksz, data->flags, data->error); 138f95f3850SWill Newton if (stop) 139f95f3850SWill Newton seq_printf(s, 140f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 142f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 143f95f3850SWill Newton stop->resp[2], stop->error); 144f95f3850SWill Newton } 145f95f3850SWill Newton 146f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 147f95f3850SWill Newton 148f95f3850SWill Newton return 0; 149f95f3850SWill Newton } 150f95f3850SWill Newton 151f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 152f95f3850SWill Newton { 153f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 154f95f3850SWill Newton } 155f95f3850SWill Newton 156f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 157f95f3850SWill Newton .owner = THIS_MODULE, 158f95f3850SWill Newton .open = dw_mci_req_open, 159f95f3850SWill Newton .read = seq_read, 160f95f3850SWill Newton .llseek = seq_lseek, 161f95f3850SWill Newton .release = single_release, 162f95f3850SWill Newton }; 163f95f3850SWill Newton 164f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 165f95f3850SWill Newton { 166f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 167f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 168f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 169f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 170f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 171f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 172f95f3850SWill Newton 173f95f3850SWill Newton return 0; 174f95f3850SWill Newton } 175f95f3850SWill Newton 176f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 177f95f3850SWill Newton { 178f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 179f95f3850SWill Newton } 180f95f3850SWill Newton 181f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 182f95f3850SWill Newton .owner = THIS_MODULE, 183f95f3850SWill Newton .open = dw_mci_regs_open, 184f95f3850SWill Newton .read = seq_read, 185f95f3850SWill Newton .llseek = seq_lseek, 186f95f3850SWill Newton .release = single_release, 187f95f3850SWill Newton }; 188f95f3850SWill Newton 189f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 190f95f3850SWill Newton { 191f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 192f95f3850SWill Newton struct dw_mci *host = slot->host; 193f95f3850SWill Newton struct dentry *root; 194f95f3850SWill Newton struct dentry *node; 195f95f3850SWill Newton 196f95f3850SWill Newton root = mmc->debugfs_root; 197f95f3850SWill Newton if (!root) 198f95f3850SWill Newton return; 199f95f3850SWill Newton 200f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 201f95f3850SWill Newton &dw_mci_regs_fops); 202f95f3850SWill Newton if (!node) 203f95f3850SWill Newton goto err; 204f95f3850SWill Newton 205f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 206f95f3850SWill Newton &dw_mci_req_fops); 207f95f3850SWill Newton if (!node) 208f95f3850SWill Newton goto err; 209f95f3850SWill Newton 210f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 211f95f3850SWill Newton if (!node) 212f95f3850SWill Newton goto err; 213f95f3850SWill Newton 214f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 215f95f3850SWill Newton (u32 *)&host->pending_events); 216f95f3850SWill Newton if (!node) 217f95f3850SWill Newton goto err; 218f95f3850SWill Newton 219f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 220f95f3850SWill Newton (u32 *)&host->completed_events); 221f95f3850SWill Newton if (!node) 222f95f3850SWill Newton goto err; 223f95f3850SWill Newton 224f95f3850SWill Newton return; 225f95f3850SWill Newton 226f95f3850SWill Newton err: 227f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 228f95f3850SWill Newton } 229f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 230f95f3850SWill Newton 23101730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 23201730558SDoug Anderson 233f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 234f95f3850SWill Newton { 235f95f3850SWill Newton struct mmc_data *data; 236800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23701730558SDoug Anderson struct dw_mci *host = slot->host; 238f95f3850SWill Newton u32 cmdr; 239f95f3850SWill Newton 2400e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 241f95f3850SWill Newton cmdr = cmd->opcode; 242f95f3850SWill Newton 24390c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24590c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24690c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24790c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 248f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2494a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 250f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 251f95f3850SWill Newton 25201730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25301730558SDoug Anderson u32 clk_en_a; 25401730558SDoug Anderson 25501730558SDoug Anderson /* Special bit makes CMD11 not die */ 25601730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25701730558SDoug Anderson 25801730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 25901730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 26001730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 26101730558SDoug Anderson 26201730558SDoug Anderson /* 26301730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26401730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26501730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26601730558SDoug Anderson * voltage change dance. 26701730558SDoug Anderson * 26801730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 26901730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 27001730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 27101730558SDoug Anderson * until the voltage change is all done. 27201730558SDoug Anderson */ 27301730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27401730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27501730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27601730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27701730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 27801730558SDoug Anderson } 27901730558SDoug Anderson 280f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 281f95f3850SWill Newton /* We expect a response, so set this bit */ 282f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 283f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 284f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 285f95f3850SWill Newton } 286f95f3850SWill Newton 287f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 288f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 289f95f3850SWill Newton 290f95f3850SWill Newton data = cmd->data; 291f95f3850SWill Newton if (data) { 292f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 293f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 294f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 295f95f3850SWill Newton } 296f95f3850SWill Newton 297aaaaeb7aSJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 298aaaaeb7aSJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 299800d78bfSThomas Abraham 300f95f3850SWill Newton return cmdr; 301f95f3850SWill Newton } 302f95f3850SWill Newton 30390c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30490c2143aSSeungwon Jeon { 30590c2143aSSeungwon Jeon struct mmc_command *stop; 30690c2143aSSeungwon Jeon u32 cmdr; 30790c2143aSSeungwon Jeon 30890c2143aSSeungwon Jeon if (!cmd->data) 30990c2143aSSeungwon Jeon return 0; 31090c2143aSSeungwon Jeon 31190c2143aSSeungwon Jeon stop = &host->stop_abort; 31290c2143aSSeungwon Jeon cmdr = cmd->opcode; 31390c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31490c2143aSSeungwon Jeon 31590c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31690c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31790c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3186c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3196c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3206c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 32190c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 32290c2143aSSeungwon Jeon stop->arg = 0; 32390c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32490c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32590c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32690c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32790c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 32890c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 32990c2143aSSeungwon Jeon } else { 33090c2143aSSeungwon Jeon return 0; 33190c2143aSSeungwon Jeon } 33290c2143aSSeungwon Jeon 33390c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33490c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33590c2143aSSeungwon Jeon 33690c2143aSSeungwon Jeon return cmdr; 33790c2143aSSeungwon Jeon } 33890c2143aSSeungwon Jeon 3390bdbd0e8SDoug Anderson static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 3400bdbd0e8SDoug Anderson { 3410bdbd0e8SDoug Anderson unsigned long timeout = jiffies + msecs_to_jiffies(500); 3420bdbd0e8SDoug Anderson 3430bdbd0e8SDoug Anderson /* 3440bdbd0e8SDoug Anderson * Databook says that before issuing a new data transfer command 3450bdbd0e8SDoug Anderson * we need to check to see if the card is busy. Data transfer commands 3460bdbd0e8SDoug Anderson * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 3470bdbd0e8SDoug Anderson * 3480bdbd0e8SDoug Anderson * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 3490bdbd0e8SDoug Anderson * expected. 3500bdbd0e8SDoug Anderson */ 3510bdbd0e8SDoug Anderson if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 3520bdbd0e8SDoug Anderson !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 3530bdbd0e8SDoug Anderson while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 3540bdbd0e8SDoug Anderson if (time_after(jiffies, timeout)) { 3550bdbd0e8SDoug Anderson /* Command will fail; we'll pass error then */ 3560bdbd0e8SDoug Anderson dev_err(host->dev, "Busy; trying anyway\n"); 3570bdbd0e8SDoug Anderson break; 3580bdbd0e8SDoug Anderson } 3590bdbd0e8SDoug Anderson udelay(10); 3600bdbd0e8SDoug Anderson } 3610bdbd0e8SDoug Anderson } 3620bdbd0e8SDoug Anderson } 3630bdbd0e8SDoug Anderson 364f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 365f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 366f95f3850SWill Newton { 367f95f3850SWill Newton host->cmd = cmd; 3684a90920cSThomas Abraham dev_vdbg(host->dev, 369f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 370f95f3850SWill Newton cmd->arg, cmd_flags); 371f95f3850SWill Newton 372f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 3730e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 3740bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 375f95f3850SWill Newton 376f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 377f95f3850SWill Newton } 378f95f3850SWill Newton 37990c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 380f95f3850SWill Newton { 38190c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 3820e3a22c0SShawn Lin 38390c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 384f95f3850SWill Newton } 385f95f3850SWill Newton 386f95f3850SWill Newton /* DMA interface functions */ 387f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 388f95f3850SWill Newton { 38903e8cb53SJames Hogan if (host->using_dma) { 390f95f3850SWill Newton host->dma_ops->stop(host); 391f95f3850SWill Newton host->dma_ops->cleanup(host); 392aa50f259SSeungwon Jeon } 393aa50f259SSeungwon Jeon 394f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 395f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 396f95f3850SWill Newton } 397f95f3850SWill Newton 3989aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 3999aa51408SSeungwon Jeon { 4009aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 4019aa51408SSeungwon Jeon return DMA_TO_DEVICE; 4029aa51408SSeungwon Jeon else 4039aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 4049aa51408SSeungwon Jeon } 4059aa51408SSeungwon Jeon 406f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 407f95f3850SWill Newton { 408f95f3850SWill Newton struct mmc_data *data = host->data; 409f95f3850SWill Newton 410f95f3850SWill Newton if (data) 4119aa51408SSeungwon Jeon if (!data->host_cookie) 4124a90920cSThomas Abraham dma_unmap_sg(host->dev, 4139aa51408SSeungwon Jeon data->sg, 4149aa51408SSeungwon Jeon data->sg_len, 4159aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 416f95f3850SWill Newton } 417f95f3850SWill Newton 4185ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4195ce9d961SSeungwon Jeon { 4205ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4215ce9d961SSeungwon Jeon /* Software reset of DMA */ 4225ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4235ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4245ce9d961SSeungwon Jeon } 4255ce9d961SSeungwon Jeon 426f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 427f95f3850SWill Newton { 428f95f3850SWill Newton u32 temp; 429f95f3850SWill Newton 430f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 431f95f3850SWill Newton temp = mci_readl(host, CTRL); 432f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 433f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 434f95f3850SWill Newton mci_writel(host, CTRL, temp); 435f95f3850SWill Newton 436f95f3850SWill Newton /* Stop the IDMAC running */ 437f95f3850SWill Newton temp = mci_readl(host, BMOD); 438a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4395ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 440f95f3850SWill Newton mci_writel(host, BMOD, temp); 441f95f3850SWill Newton } 442f95f3850SWill Newton 4433fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 444f95f3850SWill Newton { 4453fc7eaefSShawn Lin struct dw_mci *host = arg; 446f95f3850SWill Newton struct mmc_data *data = host->data; 447f95f3850SWill Newton 4484a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 449f95f3850SWill Newton 4503fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 4513fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 4523fc7eaefSShawn Lin /* Invalidate cache after read */ 4533fc7eaefSShawn Lin dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), 4543fc7eaefSShawn Lin data->sg, 4553fc7eaefSShawn Lin data->sg_len, 4563fc7eaefSShawn Lin DMA_FROM_DEVICE); 4573fc7eaefSShawn Lin 458f95f3850SWill Newton host->dma_ops->cleanup(host); 459f95f3850SWill Newton 460f95f3850SWill Newton /* 461f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 462f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 463f95f3850SWill Newton */ 464f95f3850SWill Newton if (data) { 465f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 466f95f3850SWill Newton tasklet_schedule(&host->tasklet); 467f95f3850SWill Newton } 468f95f3850SWill Newton } 469f95f3850SWill Newton 470f95f3850SWill Newton static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 471f95f3850SWill Newton unsigned int sg_len) 472f95f3850SWill Newton { 4735959b32eSAlexey Brodkin unsigned int desc_len; 474f95f3850SWill Newton int i; 4750e3a22c0SShawn Lin 47669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 4775959b32eSAlexey Brodkin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 47869d99fdcSPrabu Thangamuthu 4795959b32eSAlexey Brodkin desc_first = desc_last = desc = host->sg_cpu; 4805959b32eSAlexey Brodkin 4815959b32eSAlexey Brodkin for (i = 0; i < sg_len; i++) { 48269d99fdcSPrabu Thangamuthu unsigned int length = sg_dma_len(&data->sg[i]); 4830e3a22c0SShawn Lin 48469d99fdcSPrabu Thangamuthu u64 mem_addr = sg_dma_address(&data->sg[i]); 48569d99fdcSPrabu Thangamuthu 4865959b32eSAlexey Brodkin for ( ; length ; desc++) { 4875959b32eSAlexey Brodkin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 4885959b32eSAlexey Brodkin length : DW_MCI_DESC_DATA_LENGTH; 4895959b32eSAlexey Brodkin 4905959b32eSAlexey Brodkin length -= desc_len; 4915959b32eSAlexey Brodkin 49269d99fdcSPrabu Thangamuthu /* 4935959b32eSAlexey Brodkin * Set the OWN bit and disable interrupts 4945959b32eSAlexey Brodkin * for this descriptor 49569d99fdcSPrabu Thangamuthu */ 49669d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 49769d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 4985959b32eSAlexey Brodkin 49969d99fdcSPrabu Thangamuthu /* Buffer length */ 5005959b32eSAlexey Brodkin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 50169d99fdcSPrabu Thangamuthu 50269d99fdcSPrabu Thangamuthu /* Physical address to DMA to/from */ 50369d99fdcSPrabu Thangamuthu desc->des4 = mem_addr & 0xffffffff; 50469d99fdcSPrabu Thangamuthu desc->des5 = mem_addr >> 32; 5055959b32eSAlexey Brodkin 5065959b32eSAlexey Brodkin /* Update physical address for the next desc */ 5075959b32eSAlexey Brodkin mem_addr += desc_len; 5085959b32eSAlexey Brodkin 5095959b32eSAlexey Brodkin /* Save pointer to the last descriptor */ 5105959b32eSAlexey Brodkin desc_last = desc; 5115959b32eSAlexey Brodkin } 51269d99fdcSPrabu Thangamuthu } 51369d99fdcSPrabu Thangamuthu 51469d99fdcSPrabu Thangamuthu /* Set first descriptor */ 5155959b32eSAlexey Brodkin desc_first->des0 |= IDMAC_DES0_FD; 51669d99fdcSPrabu Thangamuthu 51769d99fdcSPrabu Thangamuthu /* Set last descriptor */ 5185959b32eSAlexey Brodkin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 5195959b32eSAlexey Brodkin desc_last->des0 |= IDMAC_DES0_LD; 52069d99fdcSPrabu Thangamuthu 52169d99fdcSPrabu Thangamuthu } else { 5225959b32eSAlexey Brodkin struct idmac_desc *desc_first, *desc_last, *desc; 523f95f3850SWill Newton 5245959b32eSAlexey Brodkin desc_first = desc_last = desc = host->sg_cpu; 5255959b32eSAlexey Brodkin 5265959b32eSAlexey Brodkin for (i = 0; i < sg_len; i++) { 527f95f3850SWill Newton unsigned int length = sg_dma_len(&data->sg[i]); 5280e3a22c0SShawn Lin 529f95f3850SWill Newton u32 mem_addr = sg_dma_address(&data->sg[i]); 530f95f3850SWill Newton 5315959b32eSAlexey Brodkin for ( ; length ; desc++) { 5325959b32eSAlexey Brodkin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 5335959b32eSAlexey Brodkin length : DW_MCI_DESC_DATA_LENGTH; 5345959b32eSAlexey Brodkin 5355959b32eSAlexey Brodkin length -= desc_len; 5365959b32eSAlexey Brodkin 53769d99fdcSPrabu Thangamuthu /* 5385959b32eSAlexey Brodkin * Set the OWN bit and disable interrupts 5395959b32eSAlexey Brodkin * for this descriptor 54069d99fdcSPrabu Thangamuthu */ 5416687c42fSBen Dooks desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 5425959b32eSAlexey Brodkin IDMAC_DES0_DIC | 5435959b32eSAlexey Brodkin IDMAC_DES0_CH); 5445959b32eSAlexey Brodkin 545f95f3850SWill Newton /* Buffer length */ 5465959b32eSAlexey Brodkin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 547f95f3850SWill Newton 548f95f3850SWill Newton /* Physical address to DMA to/from */ 5496687c42fSBen Dooks desc->des2 = cpu_to_le32(mem_addr); 5505959b32eSAlexey Brodkin 5515959b32eSAlexey Brodkin /* Update physical address for the next desc */ 5525959b32eSAlexey Brodkin mem_addr += desc_len; 5535959b32eSAlexey Brodkin 5545959b32eSAlexey Brodkin /* Save pointer to the last descriptor */ 5555959b32eSAlexey Brodkin desc_last = desc; 5565959b32eSAlexey Brodkin } 557f95f3850SWill Newton } 558f95f3850SWill Newton 559f95f3850SWill Newton /* Set first descriptor */ 5605959b32eSAlexey Brodkin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 561f95f3850SWill Newton 562f95f3850SWill Newton /* Set last descriptor */ 5635959b32eSAlexey Brodkin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 5645959b32eSAlexey Brodkin IDMAC_DES0_DIC)); 5655959b32eSAlexey Brodkin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 56669d99fdcSPrabu Thangamuthu } 567f95f3850SWill Newton 5680e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 569f95f3850SWill Newton } 570f95f3850SWill Newton 5713fc7eaefSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 572f95f3850SWill Newton { 573f95f3850SWill Newton u32 temp; 574f95f3850SWill Newton 575f95f3850SWill Newton dw_mci_translate_sglist(host, host->data, sg_len); 576f95f3850SWill Newton 577536f6b91SSonny Rao /* Make sure to reset DMA in case we did PIO before this */ 578536f6b91SSonny Rao dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 579536f6b91SSonny Rao dw_mci_idmac_reset(host); 580536f6b91SSonny Rao 581f95f3850SWill Newton /* Select IDMAC interface */ 582f95f3850SWill Newton temp = mci_readl(host, CTRL); 583f95f3850SWill Newton temp |= SDMMC_CTRL_USE_IDMAC; 584f95f3850SWill Newton mci_writel(host, CTRL, temp); 585f95f3850SWill Newton 5860e3a22c0SShawn Lin /* drain writebuffer */ 587f95f3850SWill Newton wmb(); 588f95f3850SWill Newton 589f95f3850SWill Newton /* Enable the IDMAC */ 590f95f3850SWill Newton temp = mci_readl(host, BMOD); 591a5289a43SJaehoon Chung temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 592f95f3850SWill Newton mci_writel(host, BMOD, temp); 593f95f3850SWill Newton 594f95f3850SWill Newton /* Start it running */ 595f95f3850SWill Newton mci_writel(host, PLDMND, 1); 5963fc7eaefSShawn Lin 5973fc7eaefSShawn Lin return 0; 598f95f3850SWill Newton } 599f95f3850SWill Newton 600f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 601f95f3850SWill Newton { 602897b69e7SSeungwon Jeon int i; 603f95f3850SWill Newton 60469d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 60569d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 60669d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 60769d99fdcSPrabu Thangamuthu host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 60869d99fdcSPrabu Thangamuthu 60969d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 61069d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 61169d99fdcSPrabu Thangamuthu i++, p++) { 61269d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 61369d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 61469d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 61569d99fdcSPrabu Thangamuthu 61669d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 61769d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 61869d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 61969d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 62069d99fdcSPrabu Thangamuthu p->des1 = 0; 62169d99fdcSPrabu Thangamuthu p->des2 = 0; 62269d99fdcSPrabu Thangamuthu p->des3 = 0; 62369d99fdcSPrabu Thangamuthu } 62469d99fdcSPrabu Thangamuthu 62569d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 62669d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 62769d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 62869d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 62969d99fdcSPrabu Thangamuthu 63069d99fdcSPrabu Thangamuthu } else { 63169d99fdcSPrabu Thangamuthu struct idmac_desc *p; 632f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 633f95f3850SWill Newton host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 634f95f3850SWill Newton 635f95f3850SWill Newton /* Forward link the descriptor list */ 6360e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 6370e3a22c0SShawn Lin i < host->ring_size - 1; 6380e3a22c0SShawn Lin i++, p++) { 6396687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 6406687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 6414b244724SZhangfei Gao p->des1 = 0; 6424b244724SZhangfei Gao } 643f95f3850SWill Newton 644f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 6456687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 6466687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 64769d99fdcSPrabu Thangamuthu } 648f95f3850SWill Newton 6495ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 650141a712aSSeungwon Jeon 65169d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 65269d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 65369d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 65469d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 65569d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 65669d99fdcSPrabu Thangamuthu 65769d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 65869d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 65969d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 66069d99fdcSPrabu Thangamuthu 66169d99fdcSPrabu Thangamuthu } else { 662f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 663fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 66469d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 66569d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 666f95f3850SWill Newton 667f95f3850SWill Newton /* Set the descriptor base address */ 668f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 66969d99fdcSPrabu Thangamuthu } 67069d99fdcSPrabu Thangamuthu 671f95f3850SWill Newton return 0; 672f95f3850SWill Newton } 673f95f3850SWill Newton 6748e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 675885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 676885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 677885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 6783fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 679885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 680885c3e80SSeungwon Jeon }; 6813fc7eaefSShawn Lin 6823fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 6833fc7eaefSShawn Lin { 684ab925a31SShawn Lin dmaengine_terminate_async(host->dms->ch); 6853fc7eaefSShawn Lin } 6863fc7eaefSShawn Lin 6873fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 6883fc7eaefSShawn Lin unsigned int sg_len) 6893fc7eaefSShawn Lin { 6903fc7eaefSShawn Lin struct dma_slave_config cfg; 6913fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 6923fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 6933fc7eaefSShawn Lin const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 6943fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 6953fc7eaefSShawn Lin u32 fifoth_val; 6963fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 6973fc7eaefSShawn Lin int ret = 0; 6983fc7eaefSShawn Lin 6993fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 700260b3164SArnd Bergmann cfg.dst_addr = host->phy_regs + fifo_offset; 7013fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 7023fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7033fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7043fc7eaefSShawn Lin 7053fc7eaefSShawn Lin /* Match burst msize with external dma config */ 7063fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 7073fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 7083fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 7093fc7eaefSShawn Lin 7103fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7113fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 7123fc7eaefSShawn Lin else 7133fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 7143fc7eaefSShawn Lin 7153fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 7163fc7eaefSShawn Lin if (ret) { 7173fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 7183fc7eaefSShawn Lin return -EBUSY; 7193fc7eaefSShawn Lin } 7203fc7eaefSShawn Lin 7213fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 7223fc7eaefSShawn Lin sg_len, cfg.direction, 7233fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 7243fc7eaefSShawn Lin if (!desc) { 7253fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 7263fc7eaefSShawn Lin return -EBUSY; 7273fc7eaefSShawn Lin } 7283fc7eaefSShawn Lin 7293fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 7303fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 7313fc7eaefSShawn Lin desc->callback_param = (void *)host; 7323fc7eaefSShawn Lin dmaengine_submit(desc); 7333fc7eaefSShawn Lin 7343fc7eaefSShawn Lin /* Flush cache before write */ 7353fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7363fc7eaefSShawn Lin dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl, 7373fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 7383fc7eaefSShawn Lin 7393fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 7403fc7eaefSShawn Lin 7413fc7eaefSShawn Lin return 0; 7423fc7eaefSShawn Lin } 7433fc7eaefSShawn Lin 7443fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 7453fc7eaefSShawn Lin { 7463fc7eaefSShawn Lin /* Request external dma channel */ 7473fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 7483fc7eaefSShawn Lin if (!host->dms) 7493fc7eaefSShawn Lin return -ENOMEM; 7503fc7eaefSShawn Lin 7513fc7eaefSShawn Lin host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 7523fc7eaefSShawn Lin if (!host->dms->ch) { 7534539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 7543fc7eaefSShawn Lin kfree(host->dms); 7553fc7eaefSShawn Lin host->dms = NULL; 7563fc7eaefSShawn Lin return -ENXIO; 7573fc7eaefSShawn Lin } 7583fc7eaefSShawn Lin 7593fc7eaefSShawn Lin return 0; 7603fc7eaefSShawn Lin } 7613fc7eaefSShawn Lin 7623fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 7633fc7eaefSShawn Lin { 7643fc7eaefSShawn Lin if (host->dms) { 7653fc7eaefSShawn Lin if (host->dms->ch) { 7663fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 7673fc7eaefSShawn Lin host->dms->ch = NULL; 7683fc7eaefSShawn Lin } 7693fc7eaefSShawn Lin kfree(host->dms); 7703fc7eaefSShawn Lin host->dms = NULL; 7713fc7eaefSShawn Lin } 7723fc7eaefSShawn Lin } 7733fc7eaefSShawn Lin 7743fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 7753fc7eaefSShawn Lin .init = dw_mci_edmac_init, 7763fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 7773fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 7783fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 7793fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 7803fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 7813fc7eaefSShawn Lin }; 782885c3e80SSeungwon Jeon 7839aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 7849aa51408SSeungwon Jeon struct mmc_data *data, 7859aa51408SSeungwon Jeon bool next) 786f95f3850SWill Newton { 787f95f3850SWill Newton struct scatterlist *sg; 7889aa51408SSeungwon Jeon unsigned int i, sg_len; 789f95f3850SWill Newton 7909aa51408SSeungwon Jeon if (!next && data->host_cookie) 7919aa51408SSeungwon Jeon return data->host_cookie; 792f95f3850SWill Newton 793f95f3850SWill Newton /* 794f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 795f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 796f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 797f95f3850SWill Newton */ 798f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 799f95f3850SWill Newton return -EINVAL; 8009aa51408SSeungwon Jeon 801f95f3850SWill Newton if (data->blksz & 3) 802f95f3850SWill Newton return -EINVAL; 803f95f3850SWill Newton 804f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 805f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 806f95f3850SWill Newton return -EINVAL; 807f95f3850SWill Newton } 808f95f3850SWill Newton 8094a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 8109aa51408SSeungwon Jeon data->sg, 8119aa51408SSeungwon Jeon data->sg_len, 8129aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 8139aa51408SSeungwon Jeon if (sg_len == 0) 8149aa51408SSeungwon Jeon return -EINVAL; 8159aa51408SSeungwon Jeon 8169aa51408SSeungwon Jeon if (next) 8179aa51408SSeungwon Jeon data->host_cookie = sg_len; 8189aa51408SSeungwon Jeon 8199aa51408SSeungwon Jeon return sg_len; 8209aa51408SSeungwon Jeon } 8219aa51408SSeungwon Jeon 8229aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 8239aa51408SSeungwon Jeon struct mmc_request *mrq, 8249aa51408SSeungwon Jeon bool is_first_req) 8259aa51408SSeungwon Jeon { 8269aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 8279aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 8289aa51408SSeungwon Jeon 8299aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 8309aa51408SSeungwon Jeon return; 8319aa51408SSeungwon Jeon 8329aa51408SSeungwon Jeon if (data->host_cookie) { 8339aa51408SSeungwon Jeon data->host_cookie = 0; 8349aa51408SSeungwon Jeon return; 8359aa51408SSeungwon Jeon } 8369aa51408SSeungwon Jeon 8379aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 8389aa51408SSeungwon Jeon data->host_cookie = 0; 8399aa51408SSeungwon Jeon } 8409aa51408SSeungwon Jeon 8419aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 8429aa51408SSeungwon Jeon struct mmc_request *mrq, 8439aa51408SSeungwon Jeon int err) 8449aa51408SSeungwon Jeon { 8459aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 8469aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 8479aa51408SSeungwon Jeon 8489aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 8499aa51408SSeungwon Jeon return; 8509aa51408SSeungwon Jeon 8519aa51408SSeungwon Jeon if (data->host_cookie) 8524a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 8539aa51408SSeungwon Jeon data->sg, 8549aa51408SSeungwon Jeon data->sg_len, 8559aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 8569aa51408SSeungwon Jeon data->host_cookie = 0; 8579aa51408SSeungwon Jeon } 8589aa51408SSeungwon Jeon 85952426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 86052426899SSeungwon Jeon { 86152426899SSeungwon Jeon unsigned int blksz = data->blksz; 86252426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 86352426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 86452426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 86552426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 8660e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 86752426899SSeungwon Jeon 8683fc7eaefSShawn Lin /* pio should ship this scenario */ 8693fc7eaefSShawn Lin if (!host->use_dma) 8703fc7eaefSShawn Lin return; 8713fc7eaefSShawn Lin 87252426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 87352426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 87452426899SSeungwon Jeon 87552426899SSeungwon Jeon /* 87652426899SSeungwon Jeon * MSIZE is '1', 87752426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 87852426899SSeungwon Jeon */ 87952426899SSeungwon Jeon if (blksz % fifo_width) { 88052426899SSeungwon Jeon msize = 0; 88152426899SSeungwon Jeon rx_wmark = 1; 88252426899SSeungwon Jeon goto done; 88352426899SSeungwon Jeon } 88452426899SSeungwon Jeon 88552426899SSeungwon Jeon do { 88652426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 88752426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 88852426899SSeungwon Jeon msize = idx; 88952426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 89052426899SSeungwon Jeon break; 89152426899SSeungwon Jeon } 89252426899SSeungwon Jeon } while (--idx > 0); 89352426899SSeungwon Jeon /* 89452426899SSeungwon Jeon * If idx is '0', it won't be tried 89552426899SSeungwon Jeon * Thus, initial values are uesed 89652426899SSeungwon Jeon */ 89752426899SSeungwon Jeon done: 89852426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 89952426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 90052426899SSeungwon Jeon } 90152426899SSeungwon Jeon 9027e4bf1bcSJaehoon Chung static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 903f1d2736cSSeungwon Jeon { 904f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 905f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 906f1d2736cSSeungwon Jeon u16 thld_size; 9077e4bf1bcSJaehoon Chung u8 enable; 908f1d2736cSSeungwon Jeon 90966dfd101SJames Hogan /* 91066dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 91166dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 91266dfd101SJames Hogan */ 9137e4bf1bcSJaehoon Chung if (host->verid < DW_MMC_240A || 9147e4bf1bcSJaehoon Chung (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 91566dfd101SJames Hogan return; 91666dfd101SJames Hogan 9177e4bf1bcSJaehoon Chung /* 9187e4bf1bcSJaehoon Chung * Card write Threshold is introduced since 2.80a 9197e4bf1bcSJaehoon Chung * It's used when HS400 mode is enabled. 9207e4bf1bcSJaehoon Chung */ 9217e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE && 9227e4bf1bcSJaehoon Chung !(host->timing != MMC_TIMING_MMC_HS400)) 9237e4bf1bcSJaehoon Chung return; 9247e4bf1bcSJaehoon Chung 9257e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE) 9267e4bf1bcSJaehoon Chung enable = SDMMC_CARD_WR_THR_EN; 9277e4bf1bcSJaehoon Chung else 9287e4bf1bcSJaehoon Chung enable = SDMMC_CARD_RD_THR_EN; 9297e4bf1bcSJaehoon Chung 930f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 931f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 932f1d2736cSSeungwon Jeon goto disable; 933f1d2736cSSeungwon Jeon 934f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 935f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 936f1d2736cSSeungwon Jeon 937f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 938f1d2736cSSeungwon Jeon goto disable; 939f1d2736cSSeungwon Jeon 940f1d2736cSSeungwon Jeon /* 941f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 942f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 943f1d2736cSSeungwon Jeon * Currently just choose blksz. 944f1d2736cSSeungwon Jeon */ 945f1d2736cSSeungwon Jeon thld_size = blksz; 9467e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 947f1d2736cSSeungwon Jeon return; 948f1d2736cSSeungwon Jeon 949f1d2736cSSeungwon Jeon disable: 9507e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, 0); 951f1d2736cSSeungwon Jeon } 952f1d2736cSSeungwon Jeon 9539aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 9549aa51408SSeungwon Jeon { 955f8c58c11SDoug Anderson unsigned long irqflags; 9569aa51408SSeungwon Jeon int sg_len; 9579aa51408SSeungwon Jeon u32 temp; 9589aa51408SSeungwon Jeon 9599aa51408SSeungwon Jeon host->using_dma = 0; 9609aa51408SSeungwon Jeon 9619aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 9629aa51408SSeungwon Jeon if (!host->use_dma) 9639aa51408SSeungwon Jeon return -ENODEV; 9649aa51408SSeungwon Jeon 9659aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 966a99aa9b9SSeungwon Jeon if (sg_len < 0) { 967a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 9689aa51408SSeungwon Jeon return sg_len; 969a99aa9b9SSeungwon Jeon } 9709aa51408SSeungwon Jeon 97103e8cb53SJames Hogan host->using_dma = 1; 97203e8cb53SJames Hogan 9733fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 9744a90920cSThomas Abraham dev_vdbg(host->dev, 975f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 9763fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 9773fc7eaefSShawn Lin (unsigned long)host->sg_dma, 978f95f3850SWill Newton sg_len); 979f95f3850SWill Newton 98052426899SSeungwon Jeon /* 98152426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 98252426899SSeungwon Jeon * If current block size is same with previous size, 98352426899SSeungwon Jeon * no need to update fifoth. 98452426899SSeungwon Jeon */ 98552426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 98652426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 98752426899SSeungwon Jeon 988f95f3850SWill Newton /* Enable the DMA interface */ 989f95f3850SWill Newton temp = mci_readl(host, CTRL); 990f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 991f95f3850SWill Newton mci_writel(host, CTRL, temp); 992f95f3850SWill Newton 993f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 994f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 995f95f3850SWill Newton temp = mci_readl(host, INTMASK); 996f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 997f95f3850SWill Newton mci_writel(host, INTMASK, temp); 998f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 999f95f3850SWill Newton 10003fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 10013fc7eaefSShawn Lin /* We can't do DMA */ 10023fc7eaefSShawn Lin dev_err(host->dev, "%s: failed to start DMA.\n", __func__); 10033fc7eaefSShawn Lin return -ENODEV; 10043fc7eaefSShawn Lin } 1005f95f3850SWill Newton 1006f95f3850SWill Newton return 0; 1007f95f3850SWill Newton } 1008f95f3850SWill Newton 1009f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1010f95f3850SWill Newton { 1011f8c58c11SDoug Anderson unsigned long irqflags; 10120e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1013f95f3850SWill Newton u32 temp; 1014f95f3850SWill Newton 1015f95f3850SWill Newton data->error = -EINPROGRESS; 1016f95f3850SWill Newton 1017f95f3850SWill Newton WARN_ON(host->data); 1018f95f3850SWill Newton host->sg = NULL; 1019f95f3850SWill Newton host->data = data; 1020f95f3850SWill Newton 10217e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_READ) 102255c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 10237e4bf1bcSJaehoon Chung else 102455c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 10257e4bf1bcSJaehoon Chung 10267e4bf1bcSJaehoon Chung dw_mci_ctrl_thld(host, data); 102755c5efbcSJames Hogan 1028f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1029f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1030f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1031f9c2a0dcSSeungwon Jeon else 1032f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1033f9c2a0dcSSeungwon Jeon 1034f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1035f95f3850SWill Newton host->sg = data->sg; 103634b664a2SJames Hogan host->part_buf_start = 0; 103734b664a2SJames Hogan host->part_buf_count = 0; 1038f95f3850SWill Newton 1039b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1040f8c58c11SDoug Anderson 1041f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1042f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1043f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1044f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1045f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1046f95f3850SWill Newton 1047f95f3850SWill Newton temp = mci_readl(host, CTRL); 1048f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1049f95f3850SWill Newton mci_writel(host, CTRL, temp); 105052426899SSeungwon Jeon 105152426899SSeungwon Jeon /* 105252426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 105352426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 105452426899SSeungwon Jeon * prev_blksz should be invalidated. 105552426899SSeungwon Jeon */ 105652426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 105752426899SSeungwon Jeon host->prev_blksz = 0; 105852426899SSeungwon Jeon } else { 105952426899SSeungwon Jeon /* 106052426899SSeungwon Jeon * Keep the current block size. 106152426899SSeungwon Jeon * It will be used to decide whether to update 106252426899SSeungwon Jeon * fifoth register next time. 106352426899SSeungwon Jeon */ 106452426899SSeungwon Jeon host->prev_blksz = data->blksz; 1065f95f3850SWill Newton } 1066f95f3850SWill Newton } 1067f95f3850SWill Newton 1068f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 1069f95f3850SWill Newton { 1070f95f3850SWill Newton struct dw_mci *host = slot->host; 1071f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 1072f95f3850SWill Newton unsigned int cmd_status = 0; 1073f95f3850SWill Newton 1074f95f3850SWill Newton mci_writel(host, CMDARG, arg); 10750e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 10760bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd); 1077f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 1078f95f3850SWill Newton 1079f95f3850SWill Newton while (time_before(jiffies, timeout)) { 1080f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 1081f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 1082f95f3850SWill Newton return; 1083f95f3850SWill Newton } 1084f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 1085f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 1086f95f3850SWill Newton cmd, arg, cmd_status); 1087f95f3850SWill Newton } 1088f95f3850SWill Newton 1089ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1090f95f3850SWill Newton { 1091f95f3850SWill Newton struct dw_mci *host = slot->host; 1092fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1093f95f3850SWill Newton u32 div; 10949623b5b9SDoug Anderson u32 clk_en_a; 109501730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 109601730558SDoug Anderson 109701730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 109801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 109901730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1100f95f3850SWill Newton 1101fdf492a1SDoug Anderson if (!clock) { 1102fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 110301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1104fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1105fdf492a1SDoug Anderson div = host->bus_hz / clock; 1106fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1107f95f3850SWill Newton /* 1108f95f3850SWill Newton * move the + 1 after the divide to prevent 1109f95f3850SWill Newton * over-clocking the card. 1110f95f3850SWill Newton */ 1111e419990bSSeungwon Jeon div += 1; 1112e419990bSSeungwon Jeon 1113fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1114f95f3850SWill Newton 1115005d675aSJaehoon Chung if (clock != slot->__clk_old || force_clkinit) 1116f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1117fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1118fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1119fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1120fdf492a1SDoug Anderson host->bus_hz, div); 1121f95f3850SWill Newton 1122f95f3850SWill Newton /* disable clock */ 1123f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1124f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1125f95f3850SWill Newton 1126f95f3850SWill Newton /* inform CIU */ 112701730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1128f95f3850SWill Newton 1129f95f3850SWill Newton /* set clock to desired speed */ 1130f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1131f95f3850SWill Newton 1132f95f3850SWill Newton /* inform CIU */ 113301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1134f95f3850SWill Newton 11359623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 11369623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1137b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 11389623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 11399623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1140f95f3850SWill Newton 1141f95f3850SWill Newton /* inform CIU */ 114201730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1143005d675aSJaehoon Chung 1144005d675aSJaehoon Chung /* keep the last clock value that was requested from core */ 1145005d675aSJaehoon Chung slot->__clk_old = clock; 1146f95f3850SWill Newton } 1147f95f3850SWill Newton 1148fdf492a1SDoug Anderson host->current_speed = clock; 1149fdf492a1SDoug Anderson 1150f95f3850SWill Newton /* Set the current slot bus width */ 11511d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1152f95f3850SWill Newton } 1153f95f3850SWill Newton 1154053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1155053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1156053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1157f95f3850SWill Newton { 1158f95f3850SWill Newton struct mmc_request *mrq; 1159f95f3850SWill Newton struct mmc_data *data; 1160f95f3850SWill Newton u32 cmdflags; 1161f95f3850SWill Newton 1162f95f3850SWill Newton mrq = slot->mrq; 1163f95f3850SWill Newton 1164f95f3850SWill Newton host->cur_slot = slot; 1165f95f3850SWill Newton host->mrq = mrq; 1166f95f3850SWill Newton 1167f95f3850SWill Newton host->pending_events = 0; 1168f95f3850SWill Newton host->completed_events = 0; 1169e352c813SSeungwon Jeon host->cmd_status = 0; 1170f95f3850SWill Newton host->data_status = 0; 1171e352c813SSeungwon Jeon host->dir_status = 0; 1172f95f3850SWill Newton 1173053b3ce6SSeungwon Jeon data = cmd->data; 1174f95f3850SWill Newton if (data) { 1175f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1176f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1177f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1178f95f3850SWill Newton } 1179f95f3850SWill Newton 1180f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1181f95f3850SWill Newton 1182f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1183f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1184f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1185f95f3850SWill Newton 1186f95f3850SWill Newton if (data) { 1187f95f3850SWill Newton dw_mci_submit_data(host, data); 11880e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1189f95f3850SWill Newton } 1190f95f3850SWill Newton 1191f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1192f95f3850SWill Newton 11935c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 119449ba0302SDoug Anderson unsigned long irqflags; 119549ba0302SDoug Anderson 11965c935165SDoug Anderson /* 11978886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 11988886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 11998886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 12008886a6fdSDoug Anderson * is just about to roll over. 120149ba0302SDoug Anderson * 120249ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 120349ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 120449ba0302SDoug Anderson * already ran so we don't want the timeout). 12055c935165SDoug Anderson */ 120649ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 120749ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 12085c935165SDoug Anderson mod_timer(&host->cmd11_timer, 12098886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 121049ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 12115c935165SDoug Anderson } 12125c935165SDoug Anderson 1213f95f3850SWill Newton if (mrq->stop) 1214f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 121590c2143aSSeungwon Jeon else 121690c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1217f95f3850SWill Newton } 1218f95f3850SWill Newton 1219053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1220053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1221053b3ce6SSeungwon Jeon { 1222053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1223053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1224053b3ce6SSeungwon Jeon 1225053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1226053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1227053b3ce6SSeungwon Jeon } 1228053b3ce6SSeungwon Jeon 12297456caaeSJames Hogan /* must be called with host->lock held */ 1230f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1231f95f3850SWill Newton struct mmc_request *mrq) 1232f95f3850SWill Newton { 1233f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1234f95f3850SWill Newton host->state); 1235f95f3850SWill Newton 1236f95f3850SWill Newton slot->mrq = mrq; 1237f95f3850SWill Newton 123801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 123901730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 124001730558SDoug Anderson "Voltage change didn't complete\n"); 124101730558SDoug Anderson /* 124201730558SDoug Anderson * this case isn't expected to happen, so we can 124301730558SDoug Anderson * either crash here or just try to continue on 124401730558SDoug Anderson * in the closest possible state 124501730558SDoug Anderson */ 124601730558SDoug Anderson host->state = STATE_IDLE; 124701730558SDoug Anderson } 124801730558SDoug Anderson 1249f95f3850SWill Newton if (host->state == STATE_IDLE) { 1250f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1251f95f3850SWill Newton dw_mci_start_request(host, slot); 1252f95f3850SWill Newton } else { 1253f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1254f95f3850SWill Newton } 1255f95f3850SWill Newton } 1256f95f3850SWill Newton 1257f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1258f95f3850SWill Newton { 1259f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1260f95f3850SWill Newton struct dw_mci *host = slot->host; 1261f95f3850SWill Newton 1262f95f3850SWill Newton WARN_ON(slot->mrq); 1263f95f3850SWill Newton 12647456caaeSJames Hogan /* 12657456caaeSJames Hogan * The check for card presence and queueing of the request must be 12667456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 12677456caaeSJames Hogan * request wouldn't fail until another card was inserted. 12687456caaeSJames Hogan */ 12697456caaeSJames Hogan 127056f6911cSShawn Lin if (!dw_mci_get_cd(mmc)) { 1271f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1272f95f3850SWill Newton mmc_request_done(mmc, mrq); 1273f95f3850SWill Newton return; 1274f95f3850SWill Newton } 1275f95f3850SWill Newton 127656f6911cSShawn Lin spin_lock_bh(&host->lock); 127756f6911cSShawn Lin 1278f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 12797456caaeSJames Hogan 12807456caaeSJames Hogan spin_unlock_bh(&host->lock); 1281f95f3850SWill Newton } 1282f95f3850SWill Newton 1283f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1284f95f3850SWill Newton { 1285f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1286e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 128741babf75SJaehoon Chung u32 regs; 128851da2240SYuvaraj CD int ret; 1289f95f3850SWill Newton 1290f95f3850SWill Newton switch (ios->bus_width) { 1291f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1292f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1293f95f3850SWill Newton break; 1294c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1295c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1296c9b2a06fSJaehoon Chung break; 1297b2f7cb45SJaehoon Chung default: 1298b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1299b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1300f95f3850SWill Newton } 1301f95f3850SWill Newton 130241babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 13033f514291SSeungwon Jeon 13043f514291SSeungwon Jeon /* DDR mode set */ 130580113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 13067cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 130780113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1308c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 13093f514291SSeungwon Jeon else 1310c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 13113f514291SSeungwon Jeon 131241babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1313f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 131441babf75SJaehoon Chung 1315f95f3850SWill Newton /* 1316f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1317f95f3850SWill Newton * core ios update when finding the minimum. 1318f95f3850SWill Newton */ 1319f95f3850SWill Newton slot->clock = ios->clock; 1320f95f3850SWill Newton 1321cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1322cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1323800d78bfSThomas Abraham 1324f95f3850SWill Newton switch (ios->power_mode) { 1325f95f3850SWill Newton case MMC_POWER_UP: 132651da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 132751da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 132851da2240SYuvaraj CD ios->vdd); 132951da2240SYuvaraj CD if (ret) { 133051da2240SYuvaraj CD dev_err(slot->host->dev, 133151da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 133251da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 133351da2240SYuvaraj CD return; 133451da2240SYuvaraj CD } 133551da2240SYuvaraj CD } 133629d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 133729d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 133829d0d161SDoug Anderson regs |= (1 << slot->id); 133929d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 134029d0d161SDoug Anderson break; 134129d0d161SDoug Anderson case MMC_POWER_ON: 1342d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1343d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 134451da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 134551da2240SYuvaraj CD if (ret < 0) 134651da2240SYuvaraj CD dev_err(slot->host->dev, 1347d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 134851da2240SYuvaraj CD else 134951da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1350d1f1dd86SDoug Anderson 1351d1f1dd86SDoug Anderson } else { 1352d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1353d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1354d1f1dd86SDoug Anderson } 1355d1f1dd86SDoug Anderson 1356d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1357d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1358d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 135951da2240SYuvaraj CD } 1360655babbdSDoug Anderson 1361655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1362655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1363655babbdSDoug Anderson 1364e6f34e2fSJames Hogan break; 1365e6f34e2fSJames Hogan case MMC_POWER_OFF: 1366655babbdSDoug Anderson /* Turn clock off before power goes down */ 1367655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1368655babbdSDoug Anderson 136951da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 137051da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 137151da2240SYuvaraj CD 1372d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 137351da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 137451da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 137551da2240SYuvaraj CD 13764366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 13774366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 13784366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1379f95f3850SWill Newton break; 1380f95f3850SWill Newton default: 1381f95f3850SWill Newton break; 1382f95f3850SWill Newton } 1383655babbdSDoug Anderson 1384655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1385655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1386f95f3850SWill Newton } 1387f95f3850SWill Newton 138801730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 138901730558SDoug Anderson { 139001730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 139101730558SDoug Anderson u32 status; 139201730558SDoug Anderson 139301730558SDoug Anderson /* 139401730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 139501730558SDoug Anderson * (the data lines) are 0000 139601730558SDoug Anderson */ 139701730558SDoug Anderson status = mci_readl(slot->host, STATUS); 139801730558SDoug Anderson 139901730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 140001730558SDoug Anderson } 140101730558SDoug Anderson 140201730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 140301730558SDoug Anderson { 140401730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 140501730558SDoug Anderson struct dw_mci *host = slot->host; 14068f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 140701730558SDoug Anderson u32 uhs; 140801730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 140901730558SDoug Anderson int ret; 141001730558SDoug Anderson 14118f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 14128f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 14138f7849c4SZhangfei Gao 141401730558SDoug Anderson /* 141501730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 141601730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 141701730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 141801730558SDoug Anderson */ 141901730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1420e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 142101730558SDoug Anderson uhs &= ~v18; 1422e0848f5dSDouglas Anderson else 142301730558SDoug Anderson uhs |= v18; 1424e0848f5dSDouglas Anderson 142501730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1426e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 142701730558SDoug Anderson 142801730558SDoug Anderson if (ret) { 1429b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1430e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1431e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 143201730558SDoug Anderson return ret; 143301730558SDoug Anderson } 143401730558SDoug Anderson } 143501730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 143601730558SDoug Anderson 143701730558SDoug Anderson return 0; 143801730558SDoug Anderson } 143901730558SDoug Anderson 1440f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1441f95f3850SWill Newton { 1442f95f3850SWill Newton int read_only; 1443f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 14449795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1445f95f3850SWill Newton 1446f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1447287980e4SArnd Bergmann if (gpio_ro >= 0) 14489795a846SJaehoon Chung read_only = gpio_ro; 1449f95f3850SWill Newton else 1450f95f3850SWill Newton read_only = 1451f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1452f95f3850SWill Newton 1453f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1454f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1455f95f3850SWill Newton 1456f95f3850SWill Newton return read_only; 1457f95f3850SWill Newton } 1458f95f3850SWill Newton 1459f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1460f95f3850SWill Newton { 1461f95f3850SWill Newton int present; 1462f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 14637cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 14647cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1465f95f3850SWill Newton 1466f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 1467860951c5SJaehoon Chung if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc)) 1468fc3d7720SJaehoon Chung present = 1; 1469287980e4SArnd Bergmann else if (gpio_cd >= 0) 14707cf347bdSZhangfei Gao present = gpio_cd; 1471f95f3850SWill Newton else 1472f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1473f95f3850SWill Newton == 0 ? 1 : 0; 1474f95f3850SWill Newton 14757cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1476bf626e55SZhangfei Gao if (present) { 1477bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1478f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1479bf626e55SZhangfei Gao } else { 1480bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1481f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1482bf626e55SZhangfei Gao } 14837cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1484f95f3850SWill Newton 1485f95f3850SWill Newton return present; 1486f95f3850SWill Newton } 1487f95f3850SWill Newton 1488935a665eSShawn Lin static void dw_mci_hw_reset(struct mmc_host *mmc) 1489935a665eSShawn Lin { 1490935a665eSShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 1491935a665eSShawn Lin struct dw_mci *host = slot->host; 1492935a665eSShawn Lin int reset; 1493935a665eSShawn Lin 1494935a665eSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 1495935a665eSShawn Lin dw_mci_idmac_reset(host); 1496935a665eSShawn Lin 1497935a665eSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1498935a665eSShawn Lin SDMMC_CTRL_FIFO_RESET)) 1499935a665eSShawn Lin return; 1500935a665eSShawn Lin 1501935a665eSShawn Lin /* 1502935a665eSShawn Lin * According to eMMC spec, card reset procedure: 1503935a665eSShawn Lin * tRstW >= 1us: RST_n pulse width 1504935a665eSShawn Lin * tRSCA >= 200us: RST_n to Command time 1505935a665eSShawn Lin * tRSTH >= 1us: RST_n high period 1506935a665eSShawn Lin */ 1507935a665eSShawn Lin reset = mci_readl(host, RST_N); 1508935a665eSShawn Lin reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1509935a665eSShawn Lin mci_writel(host, RST_N, reset); 1510935a665eSShawn Lin usleep_range(1, 2); 1511935a665eSShawn Lin reset |= SDMMC_RST_HWACTIVE << slot->id; 1512935a665eSShawn Lin mci_writel(host, RST_N, reset); 1513935a665eSShawn Lin usleep_range(200, 300); 1514935a665eSShawn Lin } 1515935a665eSShawn Lin 1516b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1517b24c8b26SDoug Anderson { 1518b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1519b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1520b24c8b26SDoug Anderson 15219623b5b9SDoug Anderson /* 15229623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 15239623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 15249623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 15259623b5b9SDoug Anderson */ 1526b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 15279623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1528b24c8b26SDoug Anderson u32 clk_en_a_old; 1529b24c8b26SDoug Anderson u32 clk_en_a; 15309623b5b9SDoug Anderson 1531b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 15329623b5b9SDoug Anderson 1533b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1534b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1535b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1536b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1537b24c8b26SDoug Anderson } else { 1538b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1539b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1540b24c8b26SDoug Anderson } 1541b24c8b26SDoug Anderson 1542b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1543b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 15449623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 15459623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 15469623b5b9SDoug Anderson } 15479623b5b9SDoug Anderson } 1548b24c8b26SDoug Anderson } 15499623b5b9SDoug Anderson 15501a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 15511a5c8e1fSShashidhar Hiremath { 15521a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 15531a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1554f8c58c11SDoug Anderson unsigned long irqflags; 15551a5c8e1fSShashidhar Hiremath u32 int_mask; 15561a5c8e1fSShashidhar Hiremath 1557f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1558f8c58c11SDoug Anderson 15591a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 15601a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1561b24c8b26SDoug Anderson if (enb) 1562b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1563b24c8b26SDoug Anderson else 1564b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1565b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1566f8c58c11SDoug Anderson 1567f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 15681a5c8e1fSShashidhar Hiremath } 15691a5c8e1fSShashidhar Hiremath 15700976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 15710976f16dSSeungwon Jeon { 15720976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 15730976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 15740976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 15750e3a22c0SShawn Lin int err = -EINVAL; 15760976f16dSSeungwon Jeon 15770976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 15789979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 15790976f16dSSeungwon Jeon return err; 15800976f16dSSeungwon Jeon } 15810976f16dSSeungwon Jeon 15820e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 15830e3a22c0SShawn Lin struct mmc_ios *ios) 158480113132SSeungwon Jeon { 158580113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 158680113132SSeungwon Jeon struct dw_mci *host = slot->host; 158780113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 158880113132SSeungwon Jeon 158980113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 159080113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 159180113132SSeungwon Jeon 159280113132SSeungwon Jeon return 0; 159380113132SSeungwon Jeon } 159480113132SSeungwon Jeon 1595f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1596f95f3850SWill Newton .request = dw_mci_request, 15979aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 15989aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1599f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1600f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1601f95f3850SWill Newton .get_cd = dw_mci_get_cd, 1602935a665eSShawn Lin .hw_reset = dw_mci_hw_reset, 16031a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 16040976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 160501730558SDoug Anderson .card_busy = dw_mci_card_busy, 160601730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1607b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 160880113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1609f95f3850SWill Newton }; 1610f95f3850SWill Newton 1611f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1612f95f3850SWill Newton __releases(&host->lock) 1613f95f3850SWill Newton __acquires(&host->lock) 1614f95f3850SWill Newton { 1615f95f3850SWill Newton struct dw_mci_slot *slot; 1616f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1617f95f3850SWill Newton 1618f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1619f95f3850SWill Newton 1620f95f3850SWill Newton host->cur_slot->mrq = NULL; 1621f95f3850SWill Newton host->mrq = NULL; 1622f95f3850SWill Newton if (!list_empty(&host->queue)) { 1623f95f3850SWill Newton slot = list_entry(host->queue.next, 1624f95f3850SWill Newton struct dw_mci_slot, queue_node); 1625f95f3850SWill Newton list_del(&slot->queue_node); 16264a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1627f95f3850SWill Newton mmc_hostname(slot->mmc)); 1628f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1629f95f3850SWill Newton dw_mci_start_request(host, slot); 1630f95f3850SWill Newton } else { 16314a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 163201730558SDoug Anderson 163301730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 163401730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 163501730558SDoug Anderson else 1636f95f3850SWill Newton host->state = STATE_IDLE; 1637f95f3850SWill Newton } 1638f95f3850SWill Newton 1639f95f3850SWill Newton spin_unlock(&host->lock); 1640f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1641f95f3850SWill Newton spin_lock(&host->lock); 1642f95f3850SWill Newton } 1643f95f3850SWill Newton 1644e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1645f95f3850SWill Newton { 1646f95f3850SWill Newton u32 status = host->cmd_status; 1647f95f3850SWill Newton 1648f95f3850SWill Newton host->cmd_status = 0; 1649f95f3850SWill Newton 1650f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1651f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1652f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1653f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1654f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1655f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1656f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1657f95f3850SWill Newton } else { 1658f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1659f95f3850SWill Newton cmd->resp[1] = 0; 1660f95f3850SWill Newton cmd->resp[2] = 0; 1661f95f3850SWill Newton cmd->resp[3] = 0; 1662f95f3850SWill Newton } 1663f95f3850SWill Newton } 1664f95f3850SWill Newton 1665f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1666f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1667f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1668f95f3850SWill Newton cmd->error = -EILSEQ; 1669f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1670f95f3850SWill Newton cmd->error = -EIO; 1671f95f3850SWill Newton else 1672f95f3850SWill Newton cmd->error = 0; 1673f95f3850SWill Newton 1674e352c813SSeungwon Jeon return cmd->error; 1675e352c813SSeungwon Jeon } 1676e352c813SSeungwon Jeon 1677e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1678e352c813SSeungwon Jeon { 167931bff450SSeungwon Jeon u32 status = host->data_status; 1680e352c813SSeungwon Jeon 1681e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1682e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1683e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1684e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1685e352c813SSeungwon Jeon data->error = -EILSEQ; 1686e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1687e352c813SSeungwon Jeon if (host->dir_status == 1688e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1689e352c813SSeungwon Jeon /* 1690e352c813SSeungwon Jeon * No data CRC status was returned. 1691e352c813SSeungwon Jeon * The number of bytes transferred 1692e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1693e352c813SSeungwon Jeon */ 1694e352c813SSeungwon Jeon data->bytes_xfered = 0; 1695e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1696e352c813SSeungwon Jeon } else if (host->dir_status == 1697e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1698e7a1dec1SShawn Lin data->error = -EILSEQ; 1699e352c813SSeungwon Jeon } 1700e352c813SSeungwon Jeon } else { 1701e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1702e7a1dec1SShawn Lin data->error = -EILSEQ; 1703e352c813SSeungwon Jeon } 1704e352c813SSeungwon Jeon 1705e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1706e352c813SSeungwon Jeon 1707e352c813SSeungwon Jeon /* 1708e352c813SSeungwon Jeon * After an error, there may be data lingering 170931bff450SSeungwon Jeon * in the FIFO 1710e352c813SSeungwon Jeon */ 17113a33a94cSSonny Rao dw_mci_reset(host); 1712e352c813SSeungwon Jeon } else { 1713e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1714e352c813SSeungwon Jeon data->error = 0; 1715e352c813SSeungwon Jeon } 1716e352c813SSeungwon Jeon 1717e352c813SSeungwon Jeon return data->error; 1718f95f3850SWill Newton } 1719f95f3850SWill Newton 172057e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 172157e10486SAddy Ke { 172257e10486SAddy Ke unsigned int drto_clks; 172357e10486SAddy Ke unsigned int drto_ms; 172457e10486SAddy Ke 172557e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 172657e10486SAddy Ke drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 172757e10486SAddy Ke 172857e10486SAddy Ke /* add a bit spare time */ 172957e10486SAddy Ke drto_ms += 10; 173057e10486SAddy Ke 173157e10486SAddy Ke mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 173257e10486SAddy Ke } 173357e10486SAddy Ke 1734f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1735f95f3850SWill Newton { 1736f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1737f95f3850SWill Newton struct mmc_data *data; 1738f95f3850SWill Newton struct mmc_command *cmd; 1739e352c813SSeungwon Jeon struct mmc_request *mrq; 1740f95f3850SWill Newton enum dw_mci_state state; 1741f95f3850SWill Newton enum dw_mci_state prev_state; 1742e352c813SSeungwon Jeon unsigned int err; 1743f95f3850SWill Newton 1744f95f3850SWill Newton spin_lock(&host->lock); 1745f95f3850SWill Newton 1746f95f3850SWill Newton state = host->state; 1747f95f3850SWill Newton data = host->data; 1748e352c813SSeungwon Jeon mrq = host->mrq; 1749f95f3850SWill Newton 1750f95f3850SWill Newton do { 1751f95f3850SWill Newton prev_state = state; 1752f95f3850SWill Newton 1753f95f3850SWill Newton switch (state) { 1754f95f3850SWill Newton case STATE_IDLE: 175501730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1756f95f3850SWill Newton break; 1757f95f3850SWill Newton 175801730558SDoug Anderson case STATE_SENDING_CMD11: 1759f95f3850SWill Newton case STATE_SENDING_CMD: 1760f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1761f95f3850SWill Newton &host->pending_events)) 1762f95f3850SWill Newton break; 1763f95f3850SWill Newton 1764f95f3850SWill Newton cmd = host->cmd; 1765f95f3850SWill Newton host->cmd = NULL; 1766f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1767e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1768e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1769053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1770053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1771e352c813SSeungwon Jeon mrq->cmd); 1772053b3ce6SSeungwon Jeon goto unlock; 1773053b3ce6SSeungwon Jeon } 1774053b3ce6SSeungwon Jeon 1775e352c813SSeungwon Jeon if (cmd->data && err) { 177646d17952SDoug Anderson /* 177746d17952SDoug Anderson * During UHS tuning sequence, sending the stop 177846d17952SDoug Anderson * command after the response CRC error would 177946d17952SDoug Anderson * throw the system into a confused state 178046d17952SDoug Anderson * causing all future tuning phases to report 178146d17952SDoug Anderson * failure. 178246d17952SDoug Anderson * 178346d17952SDoug Anderson * In such case controller will move into a data 178446d17952SDoug Anderson * transfer state after a response error or 178546d17952SDoug Anderson * response CRC error. Let's let that finish 178646d17952SDoug Anderson * before trying to send a stop, so we'll go to 178746d17952SDoug Anderson * STATE_SENDING_DATA. 178846d17952SDoug Anderson * 178946d17952SDoug Anderson * Although letting the data transfer take place 179046d17952SDoug Anderson * will waste a bit of time (we already know 179146d17952SDoug Anderson * the command was bad), it can't cause any 179246d17952SDoug Anderson * errors since it's possible it would have 179346d17952SDoug Anderson * taken place anyway if this tasklet got 179446d17952SDoug Anderson * delayed. Allowing the transfer to take place 179546d17952SDoug Anderson * avoids races and keeps things simple. 179646d17952SDoug Anderson */ 179746d17952SDoug Anderson if ((err != -ETIMEDOUT) && 179846d17952SDoug Anderson (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 179946d17952SDoug Anderson state = STATE_SENDING_DATA; 180046d17952SDoug Anderson continue; 180146d17952SDoug Anderson } 180246d17952SDoug Anderson 180371abb133SSeungwon Jeon dw_mci_stop_dma(host); 180490c2143aSSeungwon Jeon send_stop_abort(host, data); 180571abb133SSeungwon Jeon state = STATE_SENDING_STOP; 180671abb133SSeungwon Jeon break; 180771abb133SSeungwon Jeon } 180871abb133SSeungwon Jeon 1809e352c813SSeungwon Jeon if (!cmd->data || err) { 1810e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1811f95f3850SWill Newton goto unlock; 1812f95f3850SWill Newton } 1813f95f3850SWill Newton 1814f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1815f95f3850SWill Newton /* fall through */ 1816f95f3850SWill Newton 1817f95f3850SWill Newton case STATE_SENDING_DATA: 18182aa35465SDoug Anderson /* 18192aa35465SDoug Anderson * We could get a data error and never a transfer 18202aa35465SDoug Anderson * complete so we'd better check for it here. 18212aa35465SDoug Anderson * 18222aa35465SDoug Anderson * Note that we don't really care if we also got a 18232aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 18242aa35465SDoug Anderson * abort won't hurt. 18252aa35465SDoug Anderson */ 1826f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1827f95f3850SWill Newton &host->pending_events)) { 1828f95f3850SWill Newton dw_mci_stop_dma(host); 1829bdb9a90bSaddy ke if (data->stop || 1830bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1831bdb9a90bSaddy ke SDMMC_INT_EBE))) 183290c2143aSSeungwon Jeon send_stop_abort(host, data); 1833f95f3850SWill Newton state = STATE_DATA_ERROR; 1834f95f3850SWill Newton break; 1835f95f3850SWill Newton } 1836f95f3850SWill Newton 1837f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 183857e10486SAddy Ke &host->pending_events)) { 183957e10486SAddy Ke /* 184057e10486SAddy Ke * If all data-related interrupts don't come 184157e10486SAddy Ke * within the given time in reading data state. 184257e10486SAddy Ke */ 184316a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 184457e10486SAddy Ke dw_mci_set_drto(host); 1845f95f3850SWill Newton break; 184657e10486SAddy Ke } 1847f95f3850SWill Newton 1848f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 18492aa35465SDoug Anderson 18502aa35465SDoug Anderson /* 18512aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 18522aa35465SDoug Anderson * before the transfer completed. This might not have 18532aa35465SDoug Anderson * been caught by the check above because the interrupt 18542aa35465SDoug Anderson * could have gone off between the previous check and 18552aa35465SDoug Anderson * the check for transfer complete. 18562aa35465SDoug Anderson * 18572aa35465SDoug Anderson * Technically this ought not be needed assuming we 18582aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 18592aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 18602aa35465SDoug Anderson * 18612aa35465SDoug Anderson * This has the advantage of sending the stop command. 18622aa35465SDoug Anderson */ 18632aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 18642aa35465SDoug Anderson &host->pending_events)) { 18652aa35465SDoug Anderson dw_mci_stop_dma(host); 1866bdb9a90bSaddy ke if (data->stop || 1867bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1868bdb9a90bSaddy ke SDMMC_INT_EBE))) 18692aa35465SDoug Anderson send_stop_abort(host, data); 18702aa35465SDoug Anderson state = STATE_DATA_ERROR; 18712aa35465SDoug Anderson break; 18722aa35465SDoug Anderson } 1873f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 18742aa35465SDoug Anderson 1875f95f3850SWill Newton /* fall through */ 1876f95f3850SWill Newton 1877f95f3850SWill Newton case STATE_DATA_BUSY: 1878f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 187957e10486SAddy Ke &host->pending_events)) { 188057e10486SAddy Ke /* 188157e10486SAddy Ke * If data error interrupt comes but data over 188257e10486SAddy Ke * interrupt doesn't come within the given time. 188357e10486SAddy Ke * in reading data state. 188457e10486SAddy Ke */ 188516a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 188657e10486SAddy Ke dw_mci_set_drto(host); 1887f95f3850SWill Newton break; 188857e10486SAddy Ke } 1889f95f3850SWill Newton 1890f95f3850SWill Newton host->data = NULL; 1891f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1892e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1893f95f3850SWill Newton 1894e352c813SSeungwon Jeon if (!err) { 1895e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 189617c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1897053b3ce6SSeungwon Jeon data->stop->error = 0; 1898e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1899053b3ce6SSeungwon Jeon goto unlock; 1900053b3ce6SSeungwon Jeon } 1901053b3ce6SSeungwon Jeon 190290c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1903e352c813SSeungwon Jeon if (data->stop) 190490c2143aSSeungwon Jeon send_stop_abort(host, data); 19052aa35465SDoug Anderson } else { 19062aa35465SDoug Anderson /* 19072aa35465SDoug Anderson * If we don't have a command complete now we'll 19082aa35465SDoug Anderson * never get one since we just reset everything; 19092aa35465SDoug Anderson * better end the request. 19102aa35465SDoug Anderson * 19112aa35465SDoug Anderson * If we do have a command complete we'll fall 19122aa35465SDoug Anderson * through to the SENDING_STOP command and 19132aa35465SDoug Anderson * everything will be peachy keen. 19142aa35465SDoug Anderson */ 19152aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 19162aa35465SDoug Anderson &host->pending_events)) { 19172aa35465SDoug Anderson host->cmd = NULL; 19182aa35465SDoug Anderson dw_mci_request_end(host, mrq); 19192aa35465SDoug Anderson goto unlock; 19202aa35465SDoug Anderson } 192190c2143aSSeungwon Jeon } 1922e352c813SSeungwon Jeon 1923e352c813SSeungwon Jeon /* 1924e352c813SSeungwon Jeon * If err has non-zero, 1925e352c813SSeungwon Jeon * stop-abort command has been already issued. 1926e352c813SSeungwon Jeon */ 1927e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1928e352c813SSeungwon Jeon 1929f95f3850SWill Newton /* fall through */ 1930f95f3850SWill Newton 1931f95f3850SWill Newton case STATE_SENDING_STOP: 1932f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1933f95f3850SWill Newton &host->pending_events)) 1934f95f3850SWill Newton break; 1935f95f3850SWill Newton 193671abb133SSeungwon Jeon /* CMD error in data command */ 193731bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 19383a33a94cSSonny Rao dw_mci_reset(host); 193971abb133SSeungwon Jeon 1940f95f3850SWill Newton host->cmd = NULL; 194171abb133SSeungwon Jeon host->data = NULL; 194290c2143aSSeungwon Jeon 1943e352c813SSeungwon Jeon if (mrq->stop) 1944e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 194590c2143aSSeungwon Jeon else 194690c2143aSSeungwon Jeon host->cmd_status = 0; 194790c2143aSSeungwon Jeon 1948e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1949f95f3850SWill Newton goto unlock; 1950f95f3850SWill Newton 1951f95f3850SWill Newton case STATE_DATA_ERROR: 1952f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1953f95f3850SWill Newton &host->pending_events)) 1954f95f3850SWill Newton break; 1955f95f3850SWill Newton 1956f95f3850SWill Newton state = STATE_DATA_BUSY; 1957f95f3850SWill Newton break; 1958f95f3850SWill Newton } 1959f95f3850SWill Newton } while (state != prev_state); 1960f95f3850SWill Newton 1961f95f3850SWill Newton host->state = state; 1962f95f3850SWill Newton unlock: 1963f95f3850SWill Newton spin_unlock(&host->lock); 1964f95f3850SWill Newton 1965f95f3850SWill Newton } 1966f95f3850SWill Newton 196734b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 196834b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 196934b664a2SJames Hogan { 197034b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 197134b664a2SJames Hogan host->part_buf_count = cnt; 197234b664a2SJames Hogan } 197334b664a2SJames Hogan 197434b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 197534b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 197634b664a2SJames Hogan { 197734b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 197834b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 197934b664a2SJames Hogan host->part_buf_count += cnt; 198034b664a2SJames Hogan return cnt; 198134b664a2SJames Hogan } 198234b664a2SJames Hogan 198334b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 198434b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 198534b664a2SJames Hogan { 19860e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 198734b664a2SJames Hogan if (cnt) { 198834b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 198934b664a2SJames Hogan cnt); 199034b664a2SJames Hogan host->part_buf_count -= cnt; 199134b664a2SJames Hogan host->part_buf_start += cnt; 199234b664a2SJames Hogan } 199334b664a2SJames Hogan return cnt; 199434b664a2SJames Hogan } 199534b664a2SJames Hogan 199634b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 199734b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 199834b664a2SJames Hogan { 199934b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 200034b664a2SJames Hogan host->part_buf_start = cnt; 200134b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 200234b664a2SJames Hogan } 200334b664a2SJames Hogan 2004f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2005f95f3850SWill Newton { 2006cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2007cfbeb59cSMarkos Chandras int init_cnt = cnt; 2008cfbeb59cSMarkos Chandras 200934b664a2SJames Hogan /* try and push anything in the part_buf */ 201034b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 201134b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 20120e3a22c0SShawn Lin 201334b664a2SJames Hogan buf += len; 201434b664a2SJames Hogan cnt -= len; 2015cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 201676184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 201734b664a2SJames Hogan host->part_buf_count = 0; 201834b664a2SJames Hogan } 201934b664a2SJames Hogan } 202034b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 202134b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 202234b664a2SJames Hogan while (cnt >= 2) { 202334b664a2SJames Hogan u16 aligned_buf[64]; 202434b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 202534b664a2SJames Hogan int items = len >> 1; 202634b664a2SJames Hogan int i; 202734b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 202834b664a2SJames Hogan memcpy(aligned_buf, buf, len); 202934b664a2SJames Hogan buf += len; 203034b664a2SJames Hogan cnt -= len; 203134b664a2SJames Hogan /* push data from aligned buffer into fifo */ 203234b664a2SJames Hogan for (i = 0; i < items; ++i) 203376184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 203434b664a2SJames Hogan } 203534b664a2SJames Hogan } else 203634b664a2SJames Hogan #endif 203734b664a2SJames Hogan { 203834b664a2SJames Hogan u16 *pdata = buf; 20390e3a22c0SShawn Lin 204034b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 204176184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 204234b664a2SJames Hogan buf = pdata; 204334b664a2SJames Hogan } 204434b664a2SJames Hogan /* put anything remaining in the part_buf */ 204534b664a2SJames Hogan if (cnt) { 204634b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2047cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2048cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2049cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 205076184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 2051f95f3850SWill Newton } 2052f95f3850SWill Newton } 2053f95f3850SWill Newton 2054f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2055f95f3850SWill Newton { 205634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 205734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 205834b664a2SJames Hogan while (cnt >= 2) { 205934b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 206034b664a2SJames Hogan u16 aligned_buf[64]; 206134b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 206234b664a2SJames Hogan int items = len >> 1; 206334b664a2SJames Hogan int i; 20640e3a22c0SShawn Lin 206534b664a2SJames Hogan for (i = 0; i < items; ++i) 206676184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 206734b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 206834b664a2SJames Hogan memcpy(buf, aligned_buf, len); 206934b664a2SJames Hogan buf += len; 207034b664a2SJames Hogan cnt -= len; 207134b664a2SJames Hogan } 207234b664a2SJames Hogan } else 207334b664a2SJames Hogan #endif 207434b664a2SJames Hogan { 207534b664a2SJames Hogan u16 *pdata = buf; 20760e3a22c0SShawn Lin 207734b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 207876184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 207934b664a2SJames Hogan buf = pdata; 208034b664a2SJames Hogan } 208134b664a2SJames Hogan if (cnt) { 208276184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 208334b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2084f95f3850SWill Newton } 2085f95f3850SWill Newton } 2086f95f3850SWill Newton 2087f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2088f95f3850SWill Newton { 2089cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2090cfbeb59cSMarkos Chandras int init_cnt = cnt; 2091cfbeb59cSMarkos Chandras 209234b664a2SJames Hogan /* try and push anything in the part_buf */ 209334b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 209434b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 20950e3a22c0SShawn Lin 209634b664a2SJames Hogan buf += len; 209734b664a2SJames Hogan cnt -= len; 2098cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 209976184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 210034b664a2SJames Hogan host->part_buf_count = 0; 210134b664a2SJames Hogan } 210234b664a2SJames Hogan } 210334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 210434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 210534b664a2SJames Hogan while (cnt >= 4) { 210634b664a2SJames Hogan u32 aligned_buf[32]; 210734b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 210834b664a2SJames Hogan int items = len >> 2; 210934b664a2SJames Hogan int i; 211034b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 211134b664a2SJames Hogan memcpy(aligned_buf, buf, len); 211234b664a2SJames Hogan buf += len; 211334b664a2SJames Hogan cnt -= len; 211434b664a2SJames Hogan /* push data from aligned buffer into fifo */ 211534b664a2SJames Hogan for (i = 0; i < items; ++i) 211676184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 211734b664a2SJames Hogan } 211834b664a2SJames Hogan } else 211934b664a2SJames Hogan #endif 212034b664a2SJames Hogan { 212134b664a2SJames Hogan u32 *pdata = buf; 21220e3a22c0SShawn Lin 212334b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 212476184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 212534b664a2SJames Hogan buf = pdata; 212634b664a2SJames Hogan } 212734b664a2SJames Hogan /* put anything remaining in the part_buf */ 212834b664a2SJames Hogan if (cnt) { 212934b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2130cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2131cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2132cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 213376184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2134f95f3850SWill Newton } 2135f95f3850SWill Newton } 2136f95f3850SWill Newton 2137f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2138f95f3850SWill Newton { 213934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 214034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 214134b664a2SJames Hogan while (cnt >= 4) { 214234b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 214334b664a2SJames Hogan u32 aligned_buf[32]; 214434b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 214534b664a2SJames Hogan int items = len >> 2; 214634b664a2SJames Hogan int i; 21470e3a22c0SShawn Lin 214834b664a2SJames Hogan for (i = 0; i < items; ++i) 214976184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 215034b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 215134b664a2SJames Hogan memcpy(buf, aligned_buf, len); 215234b664a2SJames Hogan buf += len; 215334b664a2SJames Hogan cnt -= len; 215434b664a2SJames Hogan } 215534b664a2SJames Hogan } else 215634b664a2SJames Hogan #endif 215734b664a2SJames Hogan { 215834b664a2SJames Hogan u32 *pdata = buf; 21590e3a22c0SShawn Lin 216034b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 216176184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 216234b664a2SJames Hogan buf = pdata; 216334b664a2SJames Hogan } 216434b664a2SJames Hogan if (cnt) { 216576184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 216634b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2167f95f3850SWill Newton } 2168f95f3850SWill Newton } 2169f95f3850SWill Newton 2170f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2171f95f3850SWill Newton { 2172cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2173cfbeb59cSMarkos Chandras int init_cnt = cnt; 2174cfbeb59cSMarkos Chandras 217534b664a2SJames Hogan /* try and push anything in the part_buf */ 217634b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 217734b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 21780e3a22c0SShawn Lin 217934b664a2SJames Hogan buf += len; 218034b664a2SJames Hogan cnt -= len; 2181c09fbd74SSeungwon Jeon 2182cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 218376184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 218434b664a2SJames Hogan host->part_buf_count = 0; 218534b664a2SJames Hogan } 218634b664a2SJames Hogan } 218734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 218834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 218934b664a2SJames Hogan while (cnt >= 8) { 219034b664a2SJames Hogan u64 aligned_buf[16]; 219134b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 219234b664a2SJames Hogan int items = len >> 3; 219334b664a2SJames Hogan int i; 219434b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 219534b664a2SJames Hogan memcpy(aligned_buf, buf, len); 219634b664a2SJames Hogan buf += len; 219734b664a2SJames Hogan cnt -= len; 219834b664a2SJames Hogan /* push data from aligned buffer into fifo */ 219934b664a2SJames Hogan for (i = 0; i < items; ++i) 220076184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 220134b664a2SJames Hogan } 220234b664a2SJames Hogan } else 220334b664a2SJames Hogan #endif 220434b664a2SJames Hogan { 220534b664a2SJames Hogan u64 *pdata = buf; 22060e3a22c0SShawn Lin 220734b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 220876184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 220934b664a2SJames Hogan buf = pdata; 221034b664a2SJames Hogan } 221134b664a2SJames Hogan /* put anything remaining in the part_buf */ 221234b664a2SJames Hogan if (cnt) { 221334b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2214cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2215cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2216cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 221776184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2218f95f3850SWill Newton } 2219f95f3850SWill Newton } 2220f95f3850SWill Newton 2221f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2222f95f3850SWill Newton { 222334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 222434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 222534b664a2SJames Hogan while (cnt >= 8) { 222634b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 222734b664a2SJames Hogan u64 aligned_buf[16]; 222834b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 222934b664a2SJames Hogan int items = len >> 3; 223034b664a2SJames Hogan int i; 22310e3a22c0SShawn Lin 223234b664a2SJames Hogan for (i = 0; i < items; ++i) 223376184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 223476184ac1SBen Dooks 223534b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 223634b664a2SJames Hogan memcpy(buf, aligned_buf, len); 223734b664a2SJames Hogan buf += len; 223834b664a2SJames Hogan cnt -= len; 2239f95f3850SWill Newton } 224034b664a2SJames Hogan } else 224134b664a2SJames Hogan #endif 224234b664a2SJames Hogan { 224334b664a2SJames Hogan u64 *pdata = buf; 22440e3a22c0SShawn Lin 224534b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 224676184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 224734b664a2SJames Hogan buf = pdata; 224834b664a2SJames Hogan } 224934b664a2SJames Hogan if (cnt) { 225076184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 225134b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 225234b664a2SJames Hogan } 225334b664a2SJames Hogan } 225434b664a2SJames Hogan 225534b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 225634b664a2SJames Hogan { 225734b664a2SJames Hogan int len; 225834b664a2SJames Hogan 225934b664a2SJames Hogan /* get remaining partial bytes */ 226034b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 226134b664a2SJames Hogan if (unlikely(len == cnt)) 226234b664a2SJames Hogan return; 226334b664a2SJames Hogan buf += len; 226434b664a2SJames Hogan cnt -= len; 226534b664a2SJames Hogan 226634b664a2SJames Hogan /* get the rest of the data */ 226734b664a2SJames Hogan host->pull_data(host, buf, cnt); 2268f95f3850SWill Newton } 2269f95f3850SWill Newton 227087a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2271f95f3850SWill Newton { 2272f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2273f9c2a0dcSSeungwon Jeon void *buf; 2274f9c2a0dcSSeungwon Jeon unsigned int offset; 2275f95f3850SWill Newton struct mmc_data *data = host->data; 2276f95f3850SWill Newton int shift = host->data_shift; 2277f95f3850SWill Newton u32 status; 22783e4b0d8bSMarkos Chandras unsigned int len; 2279f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2280f95f3850SWill Newton 2281f95f3850SWill Newton do { 2282f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2283f9c2a0dcSSeungwon Jeon goto done; 2284f95f3850SWill Newton 22854225fc85SImre Deak host->sg = sg_miter->piter.sg; 2286f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2287f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2288f9c2a0dcSSeungwon Jeon offset = 0; 2289f9c2a0dcSSeungwon Jeon 2290f9c2a0dcSSeungwon Jeon do { 2291f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2292f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2293f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2294f9c2a0dcSSeungwon Jeon if (!len) 2295f9c2a0dcSSeungwon Jeon break; 2296f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 22973e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2298f95f3850SWill Newton offset += len; 2299f9c2a0dcSSeungwon Jeon remain -= len; 2300f9c2a0dcSSeungwon Jeon } while (remain); 2301f95f3850SWill Newton 2302e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2303f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2304f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 230587a74d39SKyoungil Kim /* if the RXDR is ready read again */ 230687a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 230787a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2308f9c2a0dcSSeungwon Jeon 2309f9c2a0dcSSeungwon Jeon if (!remain) { 2310f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2311f9c2a0dcSSeungwon Jeon goto done; 2312f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2313f9c2a0dcSSeungwon Jeon } 2314f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2315f95f3850SWill Newton return; 2316f95f3850SWill Newton 2317f95f3850SWill Newton done: 2318f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2319f9c2a0dcSSeungwon Jeon host->sg = NULL; 23200e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2321f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2322f95f3850SWill Newton } 2323f95f3850SWill Newton 2324f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2325f95f3850SWill Newton { 2326f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2327f9c2a0dcSSeungwon Jeon void *buf; 2328f9c2a0dcSSeungwon Jeon unsigned int offset; 2329f95f3850SWill Newton struct mmc_data *data = host->data; 2330f95f3850SWill Newton int shift = host->data_shift; 2331f95f3850SWill Newton u32 status; 23323e4b0d8bSMarkos Chandras unsigned int len; 2333f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2334f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2335f95f3850SWill Newton 2336f95f3850SWill Newton do { 2337f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2338f9c2a0dcSSeungwon Jeon goto done; 2339f95f3850SWill Newton 23404225fc85SImre Deak host->sg = sg_miter->piter.sg; 2341f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2342f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2343f9c2a0dcSSeungwon Jeon offset = 0; 2344f9c2a0dcSSeungwon Jeon 2345f9c2a0dcSSeungwon Jeon do { 2346f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2347f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2348f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2349f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2350f9c2a0dcSSeungwon Jeon if (!len) 2351f9c2a0dcSSeungwon Jeon break; 2352f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 23533e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2354f95f3850SWill Newton offset += len; 2355f9c2a0dcSSeungwon Jeon remain -= len; 2356f9c2a0dcSSeungwon Jeon } while (remain); 2357f95f3850SWill Newton 2358e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2359f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2360f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2361f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2362f9c2a0dcSSeungwon Jeon 2363f9c2a0dcSSeungwon Jeon if (!remain) { 2364f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2365f9c2a0dcSSeungwon Jeon goto done; 2366f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2367f9c2a0dcSSeungwon Jeon } 2368f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2369f95f3850SWill Newton return; 2370f95f3850SWill Newton 2371f95f3850SWill Newton done: 2372f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2373f9c2a0dcSSeungwon Jeon host->sg = NULL; 23740e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2375f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2376f95f3850SWill Newton } 2377f95f3850SWill Newton 2378f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2379f95f3850SWill Newton { 2380f95f3850SWill Newton if (!host->cmd_status) 2381f95f3850SWill Newton host->cmd_status = status; 2382f95f3850SWill Newton 23830e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2384f95f3850SWill Newton 2385f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2386f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2387f95f3850SWill Newton } 2388f95f3850SWill Newton 23896130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 23906130e7a9SDoug Anderson { 23916130e7a9SDoug Anderson int i; 23926130e7a9SDoug Anderson 23936130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 23946130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 23956130e7a9SDoug Anderson 23966130e7a9SDoug Anderson if (!slot) 23976130e7a9SDoug Anderson continue; 23986130e7a9SDoug Anderson 23996130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 24006130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 24016130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 24026130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 24036130e7a9SDoug Anderson } 24046130e7a9SDoug Anderson } 24056130e7a9SDoug Anderson 2406f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2407f95f3850SWill Newton { 2408f95f3850SWill Newton struct dw_mci *host = dev_id; 2409182c9081SSeungwon Jeon u32 pending; 24101a5c8e1fSShashidhar Hiremath int i; 2411f95f3850SWill Newton 2412f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2413f95f3850SWill Newton 2414476d79f1SDoug Anderson if (pending) { 241501730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 241601730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 241701730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 241849ba0302SDoug Anderson unsigned long irqflags; 24195c935165SDoug Anderson 242001730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 242101730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 242249ba0302SDoug Anderson 242349ba0302SDoug Anderson /* 242449ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 242549ba0302SDoug Anderson * off after the lock is released, so safe to delete. 242649ba0302SDoug Anderson */ 242749ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 242801730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 242949ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 243049ba0302SDoug Anderson 243149ba0302SDoug Anderson del_timer(&host->cmd11_timer); 243201730558SDoug Anderson } 243301730558SDoug Anderson 2434f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2435f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2436182c9081SSeungwon Jeon host->cmd_status = pending; 24370e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2438f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2439f95f3850SWill Newton } 2440f95f3850SWill Newton 2441f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2442f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2443f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2444182c9081SSeungwon Jeon host->data_status = pending; 24450e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2446f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2447f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2448f95f3850SWill Newton } 2449f95f3850SWill Newton 2450f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 245157e10486SAddy Ke del_timer(&host->dto_timer); 245257e10486SAddy Ke 2453f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2454f95f3850SWill Newton if (!host->data_status) 2455182c9081SSeungwon Jeon host->data_status = pending; 24560e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2457f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2458f95f3850SWill Newton if (host->sg != NULL) 245987a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2460f95f3850SWill Newton } 2461f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2462f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2463f95f3850SWill Newton } 2464f95f3850SWill Newton 2465f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2466f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2467b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 246887a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2469f95f3850SWill Newton } 2470f95f3850SWill Newton 2471f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2472f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2473b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2474f95f3850SWill Newton dw_mci_write_data_pio(host); 2475f95f3850SWill Newton } 2476f95f3850SWill Newton 2477f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2478f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2479182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2480f95f3850SWill Newton } 2481f95f3850SWill Newton 2482f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2483f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 24846130e7a9SDoug Anderson dw_mci_handle_cd(host); 2485f95f3850SWill Newton } 2486f95f3850SWill Newton 24871a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 24881a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 24891a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 2490ed2540efSDoug Anderson 2491ed2540efSDoug Anderson if (!slot) 2492ed2540efSDoug Anderson continue; 2493ed2540efSDoug Anderson 249476756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 249576756234SAddy Ke mci_writel(host, RINTSTS, 249676756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 24971a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 24981a5c8e1fSShashidhar Hiremath } 24991a5c8e1fSShashidhar Hiremath } 25001a5c8e1fSShashidhar Hiremath 25011fb5f68aSMarkos Chandras } 2502f95f3850SWill Newton 25033fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 25043fc7eaefSShawn Lin return IRQ_HANDLED; 25053fc7eaefSShawn Lin 25063fc7eaefSShawn Lin /* Handle IDMA interrupts */ 250769d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 250869d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 250969d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 251069d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 251169d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 251269d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2513faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 25143fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 251569d99fdcSPrabu Thangamuthu } 251669d99fdcSPrabu Thangamuthu } else { 2517f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2518f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 251969d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 252069d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2521f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2522faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 25233fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2524f95f3850SWill Newton } 252569d99fdcSPrabu Thangamuthu } 2526f95f3850SWill Newton 2527f95f3850SWill Newton return IRQ_HANDLED; 2528f95f3850SWill Newton } 2529f95f3850SWill Newton 253036c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2531f95f3850SWill Newton { 2532f95f3850SWill Newton struct mmc_host *mmc; 2533f95f3850SWill Newton struct dw_mci_slot *slot; 2534e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2535800d78bfSThomas Abraham int ctrl_id, ret; 25361f44a2a5SSeungwon Jeon u32 freq[2]; 2537f95f3850SWill Newton 25384a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2539f95f3850SWill Newton if (!mmc) 2540f95f3850SWill Newton return -ENOMEM; 2541f95f3850SWill Newton 2542f95f3850SWill Newton slot = mmc_priv(mmc); 2543f95f3850SWill Newton slot->id = id; 254476756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2545f95f3850SWill Newton slot->mmc = mmc; 2546f95f3850SWill Newton slot->host = host; 2547c91eab4bSThomas Abraham host->slot[id] = slot; 2548f95f3850SWill Newton 2549f95f3850SWill Newton mmc->ops = &dw_mci_ops; 25501f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 25511f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 25521f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 25531f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 25541f44a2a5SSeungwon Jeon } else { 25551f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 25561f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 25571f44a2a5SSeungwon Jeon } 2558f95f3850SWill Newton 255951da2240SYuvaraj CD /*if there are external regulators, get them*/ 256051da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 256151da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 25623cf890fcSDoug Anderson goto err_host_allocated; 256351da2240SYuvaraj CD 256451da2240SYuvaraj CD if (!mmc->ocr_avail) 2565f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2566f95f3850SWill Newton 2567fc3d7720SJaehoon Chung if (host->pdata->caps) 2568fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2569fc3d7720SJaehoon Chung 25706024e166SJaehoon Chung /* 25716024e166SJaehoon Chung * Support MMC_CAP_ERASE by default. 25726024e166SJaehoon Chung * It needs to use trim/discard/erase commands. 25736024e166SJaehoon Chung */ 25746024e166SJaehoon Chung mmc->caps |= MMC_CAP_ERASE; 25756024e166SJaehoon Chung 2576ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2577ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2578ab269128SAbhilash Kesavan 2579800d78bfSThomas Abraham if (host->dev->of_node) { 2580800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2581800d78bfSThomas Abraham if (ctrl_id < 0) 2582800d78bfSThomas Abraham ctrl_id = 0; 2583800d78bfSThomas Abraham } else { 2584800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2585800d78bfSThomas Abraham } 2586cb27a843SJames Hogan if (drv_data && drv_data->caps) 2587cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2588800d78bfSThomas Abraham 25894f408cc6SSeungwon Jeon if (host->pdata->caps2) 25904f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 25914f408cc6SSeungwon Jeon 25923cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 25933cf890fcSDoug Anderson if (ret) 25943cf890fcSDoug Anderson goto err_host_allocated; 2595f95f3850SWill Newton 2596f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 25973fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2598a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2599225faf87SJaehoon Chung mmc->max_blk_size = 65535; 2600575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 26011a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 26021a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 26033fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 26043fc7eaefSShawn Lin mmc->max_segs = 64; 2605225faf87SJaehoon Chung mmc->max_blk_size = 65535; 26063fc7eaefSShawn Lin mmc->max_blk_count = 65535; 26073fc7eaefSShawn Lin mmc->max_req_size = 26083fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 26093fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2610575c319dSHeiko Stuebner } else { 26113fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2612f95f3850SWill Newton mmc->max_segs = 64; 2613225faf87SJaehoon Chung mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2614f95f3850SWill Newton mmc->max_blk_count = 512; 2615575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2616575c319dSHeiko Stuebner mmc->max_blk_count; 2617f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2618575c319dSHeiko Stuebner } 2619f95f3850SWill Newton 2620c0834a58SShawn Lin dw_mci_get_cd(mmc); 2621ae0eb348SJaehoon Chung 26220cea529dSJaehoon Chung ret = mmc_add_host(mmc); 26230cea529dSJaehoon Chung if (ret) 26243cf890fcSDoug Anderson goto err_host_allocated; 2625f95f3850SWill Newton 2626f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2627f95f3850SWill Newton dw_mci_init_debugfs(slot); 2628f95f3850SWill Newton #endif 2629f95f3850SWill Newton 2630f95f3850SWill Newton return 0; 2631800d78bfSThomas Abraham 26323cf890fcSDoug Anderson err_host_allocated: 2633800d78bfSThomas Abraham mmc_free_host(mmc); 263451da2240SYuvaraj CD return ret; 2635f95f3850SWill Newton } 2636f95f3850SWill Newton 2637f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2638f95f3850SWill Newton { 2639f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2640f95f3850SWill Newton mmc_remove_host(slot->mmc); 2641f95f3850SWill Newton slot->host->slot[id] = NULL; 2642f95f3850SWill Newton mmc_free_host(slot->mmc); 2643f95f3850SWill Newton } 2644f95f3850SWill Newton 2645f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2646f95f3850SWill Newton { 264769d99fdcSPrabu Thangamuthu int addr_config; 26483fc7eaefSShawn Lin struct device *dev = host->dev; 26493fc7eaefSShawn Lin struct device_node *np = dev->of_node; 26503fc7eaefSShawn Lin 26513fc7eaefSShawn Lin /* 26523fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 26533fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 26543fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 26553fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 26563fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 26573fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 26583fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 26593fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 26603fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 26613fc7eaefSShawn Lin */ 26623fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 26633fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 26643fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 26653fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 26663fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 26673fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 26683fc7eaefSShawn Lin } else { 26693fc7eaefSShawn Lin goto no_dma; 26703fc7eaefSShawn Lin } 26713fc7eaefSShawn Lin 26723fc7eaefSShawn Lin /* Determine which DMA interface to use */ 26733fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 26743fc7eaefSShawn Lin /* 26753fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 26763fc7eaefSShawn Lin * IDMAC address bus width 26773fc7eaefSShawn Lin */ 267870692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 267969d99fdcSPrabu Thangamuthu 268069d99fdcSPrabu Thangamuthu if (addr_config == 1) { 268169d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 268269d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 26833fc7eaefSShawn Lin dev_info(host->dev, 26843fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 268569d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 26863fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 26873fc7eaefSShawn Lin DMA_BIT_MASK(64)); 268869d99fdcSPrabu Thangamuthu } else { 268969d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 269069d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 26913fc7eaefSShawn Lin dev_info(host->dev, 26923fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 269369d99fdcSPrabu Thangamuthu } 269469d99fdcSPrabu Thangamuthu 2695f95f3850SWill Newton /* Alloc memory for sg translation */ 2696780f22afSSeungwon Jeon host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2697f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2698f95f3850SWill Newton if (!host->sg_cpu) { 26993fc7eaefSShawn Lin dev_err(host->dev, 27003fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2701f95f3850SWill Newton __func__); 2702f95f3850SWill Newton goto no_dma; 2703f95f3850SWill Newton } 2704f95f3850SWill Newton 2705f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 270600956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 27073fc7eaefSShawn Lin } else { 27083fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 27093fc7eaefSShawn Lin if ((of_property_count_strings(np, "dma-names") < 0) || 27103fc7eaefSShawn Lin (!of_find_property(np, "dmas", NULL))) { 2711f95f3850SWill Newton goto no_dma; 27123fc7eaefSShawn Lin } 27133fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 27143fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 27153fc7eaefSShawn Lin } 2716f95f3850SWill Newton 2717e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2718e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2719f95f3850SWill Newton if (host->dma_ops->init(host)) { 27200e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 27210e3a22c0SShawn Lin __func__); 2722f95f3850SWill Newton goto no_dma; 2723f95f3850SWill Newton } 2724f95f3850SWill Newton } else { 27254a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2726f95f3850SWill Newton goto no_dma; 2727f95f3850SWill Newton } 2728f95f3850SWill Newton 2729f95f3850SWill Newton return; 2730f95f3850SWill Newton 2731f95f3850SWill Newton no_dma: 27324a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 27333fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 2734f95f3850SWill Newton } 2735f95f3850SWill Newton 273631bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2737f95f3850SWill Newton { 2738f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 273931bff450SSeungwon Jeon u32 ctrl; 2740f95f3850SWill Newton 274131bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 274231bff450SSeungwon Jeon ctrl |= reset; 274331bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2744f95f3850SWill Newton 2745f95f3850SWill Newton /* wait till resets clear */ 2746f95f3850SWill Newton do { 2747f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 274831bff450SSeungwon Jeon if (!(ctrl & reset)) 2749f95f3850SWill Newton return true; 2750f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2751f95f3850SWill Newton 275231bff450SSeungwon Jeon dev_err(host->dev, 275331bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 275431bff450SSeungwon Jeon ctrl & reset); 2755f95f3850SWill Newton 2756f95f3850SWill Newton return false; 2757f95f3850SWill Newton } 2758f95f3850SWill Newton 27593a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 276031bff450SSeungwon Jeon { 27613a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 27623a33a94cSSonny Rao bool ret = false; 27633a33a94cSSonny Rao 276431bff450SSeungwon Jeon /* 276531bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 276631bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 276731bff450SSeungwon Jeon */ 276831bff450SSeungwon Jeon if (host->sg) { 276931bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 277031bff450SSeungwon Jeon host->sg = NULL; 277131bff450SSeungwon Jeon } 277231bff450SSeungwon Jeon 27733a33a94cSSonny Rao if (host->use_dma) 27743a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 27753a33a94cSSonny Rao 27763a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 27773a33a94cSSonny Rao /* 27783a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 27793a33a94cSSonny Rao * interrupts. 27803a33a94cSSonny Rao */ 27813a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 27823a33a94cSSonny Rao 27833a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 27843a33a94cSSonny Rao if (host->use_dma) { 27853a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 27863a33a94cSSonny Rao u32 status; 27870e3a22c0SShawn Lin 27883a33a94cSSonny Rao do { 27893a33a94cSSonny Rao status = mci_readl(host, STATUS); 27903a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 27913a33a94cSSonny Rao break; 27923a33a94cSSonny Rao cpu_relax(); 27933a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 27943a33a94cSSonny Rao 27953a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 27963a33a94cSSonny Rao dev_err(host->dev, 27970e3a22c0SShawn Lin "%s: Timeout waiting for dma_req to clear during reset\n", 27980e3a22c0SShawn Lin __func__); 27993a33a94cSSonny Rao goto ciu_out; 280031bff450SSeungwon Jeon } 280131bff450SSeungwon Jeon 28023a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 28033a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 28043a33a94cSSonny Rao goto ciu_out; 28053a33a94cSSonny Rao } 28063a33a94cSSonny Rao } else { 28073a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 28083a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 28090e3a22c0SShawn Lin dev_err(host->dev, 28100e3a22c0SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 28113a33a94cSSonny Rao __func__); 28123a33a94cSSonny Rao goto ciu_out; 28133a33a94cSSonny Rao } 28143a33a94cSSonny Rao } 28153a33a94cSSonny Rao 28163fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 28173a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 28183a33a94cSSonny Rao dw_mci_idmac_reset(host); 28193a33a94cSSonny Rao 28203a33a94cSSonny Rao ret = true; 28213a33a94cSSonny Rao 28223a33a94cSSonny Rao ciu_out: 28233a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 28243a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 28253a33a94cSSonny Rao 28263a33a94cSSonny Rao return ret; 282731bff450SSeungwon Jeon } 282831bff450SSeungwon Jeon 28295c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 28305c935165SDoug Anderson { 28315c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 28325c935165SDoug Anderson 2833fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 2834fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2835fd674198SDoug Anderson return; 2836fd674198SDoug Anderson } 28375c935165SDoug Anderson 28385c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 28395c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 28405c935165SDoug Anderson tasklet_schedule(&host->tasklet); 28415c935165SDoug Anderson } 28425c935165SDoug Anderson 284357e10486SAddy Ke static void dw_mci_dto_timer(unsigned long arg) 284457e10486SAddy Ke { 284557e10486SAddy Ke struct dw_mci *host = (struct dw_mci *)arg; 284657e10486SAddy Ke 284757e10486SAddy Ke switch (host->state) { 284857e10486SAddy Ke case STATE_SENDING_DATA: 284957e10486SAddy Ke case STATE_DATA_BUSY: 285057e10486SAddy Ke /* 285157e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 285257e10486SAddy Ke * we should notify the driver to terminate current transfer 285357e10486SAddy Ke * and report a data timeout to the core. 285457e10486SAddy Ke */ 285557e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 285657e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 285757e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 285857e10486SAddy Ke tasklet_schedule(&host->tasklet); 285957e10486SAddy Ke break; 286057e10486SAddy Ke default: 286157e10486SAddy Ke break; 286257e10486SAddy Ke } 286357e10486SAddy Ke } 286457e10486SAddy Ke 2865c91eab4bSThomas Abraham #ifdef CONFIG_OF 2866c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2867c91eab4bSThomas Abraham { 2868c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2869c91eab4bSThomas Abraham struct device *dev = host->dev; 2870c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2871e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2872e8cc37b8SShawn Lin int ret; 28733c6d89eaSDoug Anderson u32 clock_frequency; 2874c91eab4bSThomas Abraham 2875c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2876bf3707eaSBeomho Seo if (!pdata) 2877c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2878c91eab4bSThomas Abraham 2879d6786fefSGuodong Xu /* find reset controller when exist */ 2880d6786fefSGuodong Xu pdata->rstc = devm_reset_control_get_optional(dev, NULL); 2881d6786fefSGuodong Xu if (IS_ERR(pdata->rstc)) { 2882d6786fefSGuodong Xu if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 2883d6786fefSGuodong Xu return ERR_PTR(-EPROBE_DEFER); 2884d6786fefSGuodong Xu } 2885d6786fefSGuodong Xu 2886c91eab4bSThomas Abraham /* find out number of slots supported */ 28878a629d26SShawn Lin of_property_read_u32(np, "num-slots", &pdata->num_slots); 2888c91eab4bSThomas Abraham 2889c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 28900e3a22c0SShawn Lin dev_info(dev, 28910e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 2892c91eab4bSThomas Abraham 2893c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2894c91eab4bSThomas Abraham 28953c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 28963c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 28973c6d89eaSDoug Anderson 2898cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2899cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2900800d78bfSThomas Abraham if (ret) 2901800d78bfSThomas Abraham return ERR_PTR(ret); 2902800d78bfSThomas Abraham } 2903800d78bfSThomas Abraham 290440a7a463SJaehoon Chung if (of_find_property(np, "supports-highspeed", NULL)) { 290540a7a463SJaehoon Chung dev_info(dev, "supports-highspeed property is deprecated.\n"); 290610b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 290740a7a463SJaehoon Chung } 290810b49841SSeungwon Jeon 2909c91eab4bSThomas Abraham return pdata; 2910c91eab4bSThomas Abraham } 2911c91eab4bSThomas Abraham 2912c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2913c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2914c91eab4bSThomas Abraham { 2915c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2916c91eab4bSThomas Abraham } 2917c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2918c91eab4bSThomas Abraham 2919fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 2920fa0c3283SDoug Anderson { 2921fa0c3283SDoug Anderson unsigned long irqflags; 2922fa0c3283SDoug Anderson u32 temp; 2923fa0c3283SDoug Anderson int i; 2924e8cc37b8SShawn Lin struct dw_mci_slot *slot; 2925fa0c3283SDoug Anderson 2926e8cc37b8SShawn Lin /* 2927e8cc37b8SShawn Lin * No need for CD if all slots have a non-error GPIO 2928e8cc37b8SShawn Lin * as well as broken card detection is found. 2929e8cc37b8SShawn Lin */ 2930fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 2931e8cc37b8SShawn Lin slot = host->slot[i]; 2932e8cc37b8SShawn Lin if (slot->mmc->caps & MMC_CAP_NEEDS_POLL) 2933e8cc37b8SShawn Lin return; 2934fa0c3283SDoug Anderson 2935287980e4SArnd Bergmann if (mmc_gpio_get_cd(slot->mmc) < 0) 2936fa0c3283SDoug Anderson break; 2937fa0c3283SDoug Anderson } 2938fa0c3283SDoug Anderson if (i == host->num_slots) 2939fa0c3283SDoug Anderson return; 2940fa0c3283SDoug Anderson 2941fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 2942fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 2943fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 2944fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 2945fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2946fa0c3283SDoug Anderson } 2947fa0c3283SDoug Anderson 294862ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 2949f95f3850SWill Newton { 2950e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 295162ca8034SShashidhar Hiremath int width, i, ret = 0; 2952f95f3850SWill Newton u32 fifo_size; 29531c2215b7SThomas Abraham int init_slots = 0; 2954f95f3850SWill Newton 2955c91eab4bSThomas Abraham if (!host->pdata) { 2956c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 2957d6786fefSGuodong Xu if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 2958d6786fefSGuodong Xu return -EPROBE_DEFER; 2959d6786fefSGuodong Xu } else if (IS_ERR(host->pdata)) { 2960c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 2961c91eab4bSThomas Abraham return -EINVAL; 2962c91eab4bSThomas Abraham } 2963f95f3850SWill Newton } 2964f95f3850SWill Newton 2965780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 2966f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 2967f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 2968f90a0612SThomas Abraham } else { 2969f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 2970f90a0612SThomas Abraham if (ret) { 2971f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 2972f90a0612SThomas Abraham return ret; 2973f90a0612SThomas Abraham } 2974f95f3850SWill Newton } 2975f95f3850SWill Newton 2976780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2977f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 2978f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 29793c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 2980f90a0612SThomas Abraham } else { 2981f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 2982f90a0612SThomas Abraham if (ret) { 2983f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 2984f90a0612SThomas Abraham goto err_clk_biu; 2985f90a0612SThomas Abraham } 2986f90a0612SThomas Abraham 29873c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 29883c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 29893c6d89eaSDoug Anderson if (ret) 29903c6d89eaSDoug Anderson dev_warn(host->dev, 2991612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 29923c6d89eaSDoug Anderson host->pdata->bus_hz); 29933c6d89eaSDoug Anderson } 2994f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 29953c6d89eaSDoug Anderson } 2996f90a0612SThomas Abraham 2997612de4c1SJaehoon Chung if (!host->bus_hz) { 2998612de4c1SJaehoon Chung dev_err(host->dev, 2999612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3000612de4c1SJaehoon Chung ret = -ENODEV; 3001612de4c1SJaehoon Chung goto err_clk_ciu; 3002612de4c1SJaehoon Chung } 3003612de4c1SJaehoon Chung 3004002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3005002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3006002f0d5cSYuvaraj Kumar C D if (ret) { 3007002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3008002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3009002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3010002f0d5cSYuvaraj Kumar C D } 3011002f0d5cSYuvaraj Kumar C D } 3012002f0d5cSYuvaraj Kumar C D 3013d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) { 3014d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3015d6786fefSGuodong Xu usleep_range(10, 50); 3016d6786fefSGuodong Xu reset_control_deassert(host->pdata->rstc); 3017d6786fefSGuodong Xu } 3018d6786fefSGuodong Xu 30195c935165SDoug Anderson setup_timer(&host->cmd11_timer, 30205c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 30215c935165SDoug Anderson 302257e10486SAddy Ke setup_timer(&host->dto_timer, 302357e10486SAddy Ke dw_mci_dto_timer, (unsigned long)host); 302457e10486SAddy Ke 3025f95f3850SWill Newton spin_lock_init(&host->lock); 3026f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3027f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3028f95f3850SWill Newton 3029f95f3850SWill Newton /* 3030f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3031f95f3850SWill Newton * the correct values. 3032f95f3850SWill Newton */ 303370692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3034f95f3850SWill Newton if (!i) { 3035f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3036f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3037f95f3850SWill Newton width = 16; 3038f95f3850SWill Newton host->data_shift = 1; 3039f95f3850SWill Newton } else if (i == 2) { 3040f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3041f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3042f95f3850SWill Newton width = 64; 3043f95f3850SWill Newton host->data_shift = 3; 3044f95f3850SWill Newton } else { 3045f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3046f95f3850SWill Newton WARN((i != 1), 3047f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3048f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3049f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3050f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3051f95f3850SWill Newton width = 32; 3052f95f3850SWill Newton host->data_shift = 2; 3053f95f3850SWill Newton } 3054f95f3850SWill Newton 3055f95f3850SWill Newton /* Reset all blocks */ 30563744415cSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 30573744415cSShawn Lin ret = -ENODEV; 30583744415cSShawn Lin goto err_clk_ciu; 30593744415cSShawn Lin } 3060141a712aSSeungwon Jeon 3061141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3062141a712aSSeungwon Jeon dw_mci_init_dma(host); 3063f95f3850SWill Newton 3064f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3065f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3066f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3067f95f3850SWill Newton 3068f95f3850SWill Newton /* Put in max timeout */ 3069f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3070f95f3850SWill Newton 3071f95f3850SWill Newton /* 3072f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3073f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3074f95f3850SWill Newton */ 3075b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3076b86d8253SJames Hogan /* 3077b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3078b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3079b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3080b86d8253SJames Hogan * should put it in the platform data. 3081b86d8253SJames Hogan */ 3082f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 30838234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3084b86d8253SJames Hogan } else { 3085b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3086b86d8253SJames Hogan } 3087b86d8253SJames Hogan host->fifo_depth = fifo_size; 308852426899SSeungwon Jeon host->fifoth_val = 308952426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3090e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3091f95f3850SWill Newton 3092f95f3850SWill Newton /* disable clock to CIU */ 3093f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3094f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3095f95f3850SWill Newton 309663008768SJames Hogan /* 309763008768SJames Hogan * In 2.40a spec, Data offset is changed. 309863008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 309963008768SJames Hogan */ 310063008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 310163008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 310263008768SJames Hogan 310363008768SJames Hogan if (host->verid < DW_MMC_240A) 310476184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 310563008768SJames Hogan else 310676184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 310763008768SJames Hogan 3108f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3109780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3110780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3111f95f3850SWill Newton if (ret) 31126130e7a9SDoug Anderson goto err_dmaunmap; 3113f95f3850SWill Newton 3114f95f3850SWill Newton if (host->pdata->num_slots) 3115f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 3116f95f3850SWill Newton else 31178a629d26SShawn Lin host->num_slots = 1; 31188a629d26SShawn Lin 31198a629d26SShawn Lin if (host->num_slots < 1 || 31208a629d26SShawn Lin host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) { 31218a629d26SShawn Lin dev_err(host->dev, 31228a629d26SShawn Lin "Platform data must supply correct num_slots.\n"); 31238a629d26SShawn Lin ret = -ENODEV; 31248a629d26SShawn Lin goto err_clk_ciu; 31258a629d26SShawn Lin } 3126f95f3850SWill Newton 31272da1d7f2SYuvaraj CD /* 3128fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 31292da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 31302da1d7f2SYuvaraj CD */ 31312da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 31322da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3133fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 31340e3a22c0SShawn Lin /* Enable mci interrupt */ 31350e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 31362da1d7f2SYuvaraj CD 31370e3a22c0SShawn Lin dev_info(host->dev, 31380e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 31392da1d7f2SYuvaraj CD host->irq, width, fifo_size); 31402da1d7f2SYuvaraj CD 3141f95f3850SWill Newton /* We need at least one slot to succeed */ 3142f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3143f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 31441c2215b7SThomas Abraham if (ret) 31451c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 31461c2215b7SThomas Abraham else 31471c2215b7SThomas Abraham init_slots++; 3148f95f3850SWill Newton } 31491c2215b7SThomas Abraham 31501c2215b7SThomas Abraham if (init_slots) { 31511c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 31521c2215b7SThomas Abraham } else { 31530e3a22c0SShawn Lin dev_dbg(host->dev, 31540e3a22c0SShawn Lin "attempted to initialize %d slots, but failed on all\n", 31550e3a22c0SShawn Lin host->num_slots); 31566130e7a9SDoug Anderson goto err_dmaunmap; 3157f95f3850SWill Newton } 3158f95f3850SWill Newton 3159b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3160b793f658SDoug Anderson dw_mci_enable_cd(host); 3161b793f658SDoug Anderson 3162f95f3850SWill Newton return 0; 3163f95f3850SWill Newton 3164f95f3850SWill Newton err_dmaunmap: 3165f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3166f95f3850SWill Newton host->dma_ops->exit(host); 3167f90a0612SThomas Abraham 3168d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3169d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3170d6786fefSGuodong Xu 3171f90a0612SThomas Abraham err_clk_ciu: 3172f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3173780f22afSSeungwon Jeon 3174f90a0612SThomas Abraham err_clk_biu: 3175f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3176780f22afSSeungwon Jeon 3177f95f3850SWill Newton return ret; 3178f95f3850SWill Newton } 317962ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3180f95f3850SWill Newton 318162ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3182f95f3850SWill Newton { 3183f95f3850SWill Newton int i; 3184f95f3850SWill Newton 3185f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 31864a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 3187f95f3850SWill Newton if (host->slot[i]) 3188f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 3189f95f3850SWill Newton } 3190f95f3850SWill Newton 3191048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3192048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3193048fd7e6SPrabu Thangamuthu 3194f95f3850SWill Newton /* disable clock to CIU */ 3195f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3196f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3197f95f3850SWill Newton 3198f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3199f95f3850SWill Newton host->dma_ops->exit(host); 3200f95f3850SWill Newton 3201d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3202d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3203d6786fefSGuodong Xu 3204f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3205f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3206f95f3850SWill Newton } 320762ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 320862ca8034SShashidhar Hiremath 320962ca8034SShashidhar Hiremath 3210f95f3850SWill Newton 32116fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 3212f95f3850SWill Newton /* 3213f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 3214f95f3850SWill Newton */ 321562ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 3216f95f3850SWill Newton { 32173fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 32183fc7eaefSShawn Lin host->dma_ops->exit(host); 32193fc7eaefSShawn Lin 3220f95f3850SWill Newton return 0; 3221f95f3850SWill Newton } 322262ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 3223f95f3850SWill Newton 322462ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 3225f95f3850SWill Newton { 3226f95f3850SWill Newton int i, ret; 3227f95f3850SWill Newton 32283a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3229e61cf118SJaehoon Chung ret = -ENODEV; 3230e61cf118SJaehoon Chung return ret; 3231e61cf118SJaehoon Chung } 3232e61cf118SJaehoon Chung 32333bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3234141a712aSSeungwon Jeon host->dma_ops->init(host); 3235141a712aSSeungwon Jeon 323652426899SSeungwon Jeon /* 323752426899SSeungwon Jeon * Restore the initial value at FIFOTH register 323852426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 323952426899SSeungwon Jeon */ 3240e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 324152426899SSeungwon Jeon host->prev_blksz = 0; 3242e61cf118SJaehoon Chung 32432eb2944fSDoug Anderson /* Put in max timeout */ 32442eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 32452eb2944fSDoug Anderson 3246e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3247e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3248e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3249fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3250e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3251e61cf118SJaehoon Chung 3252f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3253f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 32540e3a22c0SShawn Lin 3255f95f3850SWill Newton if (!slot) 3256f95f3850SWill Newton continue; 3257ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 3258ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3259ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 3260ab269128SAbhilash Kesavan } 3261f95f3850SWill Newton } 3262fa0c3283SDoug Anderson 3263fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3264fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3265fa0c3283SDoug Anderson 3266f95f3850SWill Newton return 0; 3267f95f3850SWill Newton } 326862ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 32696fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 32706fe8890dSJaehoon Chung 3271f95f3850SWill Newton static int __init dw_mci_init(void) 3272f95f3850SWill Newton { 32738e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 327462ca8034SShashidhar Hiremath return 0; 3275f95f3850SWill Newton } 3276f95f3850SWill Newton 3277f95f3850SWill Newton static void __exit dw_mci_exit(void) 3278f95f3850SWill Newton { 3279f95f3850SWill Newton } 3280f95f3850SWill Newton 3281f95f3850SWill Newton module_init(dw_mci_init); 3282f95f3850SWill Newton module_exit(dw_mci_exit); 3283f95f3850SWill Newton 3284f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3285f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3286f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3287f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3288