1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47f95f3850SWill Newton SDMMC_INT_EBE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49f95f3850SWill Newton SDMMC_INT_RESP_ERR) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51f95f3850SWill Newton DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 6569d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6669d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6769d99fdcSPrabu Thangamuthu 6869d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 6969d99fdcSPrabu Thangamuthu 7069d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7169d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 7269d99fdcSPrabu Thangamuthu ((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff)) 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7569d99fdcSPrabu Thangamuthu 7669d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7769d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8069d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8169d99fdcSPrabu Thangamuthu }; 8269d99fdcSPrabu Thangamuthu 83f95f3850SWill Newton struct idmac_desc { 84f95f3850SWill Newton u32 des0; /* Control Descriptor */ 85f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 86f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 87f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 88f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 89f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 90f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 91f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 92f95f3850SWill Newton 93f95f3850SWill Newton u32 des1; /* Buffer sizes */ 94f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 959b7bbe10SShashidhar Hiremath ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 96f95f3850SWill Newton 97f95f3850SWill Newton u32 des2; /* buffer 1 physical address */ 98f95f3850SWill Newton 99f95f3850SWill Newton u32 des3; /* buffer 2 physical address */ 100f95f3850SWill Newton }; 101f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 102f95f3850SWill Newton 1033a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 104536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 10531bff450SSeungwon Jeon 106f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 107f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 108f95f3850SWill Newton { 109f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 110f95f3850SWill Newton struct mmc_request *mrq; 111f95f3850SWill Newton struct mmc_command *cmd; 112f95f3850SWill Newton struct mmc_command *stop; 113f95f3850SWill Newton struct mmc_data *data; 114f95f3850SWill Newton 115f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 116f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 117f95f3850SWill Newton mrq = slot->mrq; 118f95f3850SWill Newton 119f95f3850SWill Newton if (mrq) { 120f95f3850SWill Newton cmd = mrq->cmd; 121f95f3850SWill Newton data = mrq->data; 122f95f3850SWill Newton stop = mrq->stop; 123f95f3850SWill Newton 124f95f3850SWill Newton if (cmd) 125f95f3850SWill Newton seq_printf(s, 126f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 127f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 128f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 129f95f3850SWill Newton cmd->resp[2], cmd->error); 130f95f3850SWill Newton if (data) 131f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 132f95f3850SWill Newton data->bytes_xfered, data->blocks, 133f95f3850SWill Newton data->blksz, data->flags, data->error); 134f95f3850SWill Newton if (stop) 135f95f3850SWill Newton seq_printf(s, 136f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 137f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 138f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 139f95f3850SWill Newton stop->resp[2], stop->error); 140f95f3850SWill Newton } 141f95f3850SWill Newton 142f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 143f95f3850SWill Newton 144f95f3850SWill Newton return 0; 145f95f3850SWill Newton } 146f95f3850SWill Newton 147f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 148f95f3850SWill Newton { 149f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 150f95f3850SWill Newton } 151f95f3850SWill Newton 152f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 153f95f3850SWill Newton .owner = THIS_MODULE, 154f95f3850SWill Newton .open = dw_mci_req_open, 155f95f3850SWill Newton .read = seq_read, 156f95f3850SWill Newton .llseek = seq_lseek, 157f95f3850SWill Newton .release = single_release, 158f95f3850SWill Newton }; 159f95f3850SWill Newton 160f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 161f95f3850SWill Newton { 162f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 163f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 164f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 165f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 166f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 167f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 168f95f3850SWill Newton 169f95f3850SWill Newton return 0; 170f95f3850SWill Newton } 171f95f3850SWill Newton 172f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 173f95f3850SWill Newton { 174f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 175f95f3850SWill Newton } 176f95f3850SWill Newton 177f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 178f95f3850SWill Newton .owner = THIS_MODULE, 179f95f3850SWill Newton .open = dw_mci_regs_open, 180f95f3850SWill Newton .read = seq_read, 181f95f3850SWill Newton .llseek = seq_lseek, 182f95f3850SWill Newton .release = single_release, 183f95f3850SWill Newton }; 184f95f3850SWill Newton 185f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 186f95f3850SWill Newton { 187f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 188f95f3850SWill Newton struct dw_mci *host = slot->host; 189f95f3850SWill Newton struct dentry *root; 190f95f3850SWill Newton struct dentry *node; 191f95f3850SWill Newton 192f95f3850SWill Newton root = mmc->debugfs_root; 193f95f3850SWill Newton if (!root) 194f95f3850SWill Newton return; 195f95f3850SWill Newton 196f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 197f95f3850SWill Newton &dw_mci_regs_fops); 198f95f3850SWill Newton if (!node) 199f95f3850SWill Newton goto err; 200f95f3850SWill Newton 201f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 202f95f3850SWill Newton &dw_mci_req_fops); 203f95f3850SWill Newton if (!node) 204f95f3850SWill Newton goto err; 205f95f3850SWill Newton 206f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 207f95f3850SWill Newton if (!node) 208f95f3850SWill Newton goto err; 209f95f3850SWill Newton 210f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 211f95f3850SWill Newton (u32 *)&host->pending_events); 212f95f3850SWill Newton if (!node) 213f95f3850SWill Newton goto err; 214f95f3850SWill Newton 215f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 216f95f3850SWill Newton (u32 *)&host->completed_events); 217f95f3850SWill Newton if (!node) 218f95f3850SWill Newton goto err; 219f95f3850SWill Newton 220f95f3850SWill Newton return; 221f95f3850SWill Newton 222f95f3850SWill Newton err: 223f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 224f95f3850SWill Newton } 225f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 226f95f3850SWill Newton 22701730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 22801730558SDoug Anderson 229f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 230f95f3850SWill Newton { 231f95f3850SWill Newton struct mmc_data *data; 232800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23301730558SDoug Anderson struct dw_mci *host = slot->host; 234e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 235f95f3850SWill Newton u32 cmdr; 236f95f3850SWill Newton cmd->error = -EINPROGRESS; 237f95f3850SWill Newton 238f95f3850SWill Newton cmdr = cmd->opcode; 239f95f3850SWill Newton 24090c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24190c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24290c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24390c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24490c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 245f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2464a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 247f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 248f95f3850SWill Newton 24901730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25001730558SDoug Anderson u32 clk_en_a; 25101730558SDoug Anderson 25201730558SDoug Anderson /* Special bit makes CMD11 not die */ 25301730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25401730558SDoug Anderson 25501730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 25601730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 25701730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 25801730558SDoug Anderson 25901730558SDoug Anderson /* 26001730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26101730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26201730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26301730558SDoug Anderson * voltage change dance. 26401730558SDoug Anderson * 26501730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 26601730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 26701730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 26801730558SDoug Anderson * until the voltage change is all done. 26901730558SDoug Anderson */ 27001730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27101730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27201730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27301730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27401730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 27501730558SDoug Anderson } 27601730558SDoug Anderson 277f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 278f95f3850SWill Newton /* We expect a response, so set this bit */ 279f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 280f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 281f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 282f95f3850SWill Newton } 283f95f3850SWill Newton 284f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 285f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 286f95f3850SWill Newton 287f95f3850SWill Newton data = cmd->data; 288f95f3850SWill Newton if (data) { 289f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 290f95f3850SWill Newton if (data->flags & MMC_DATA_STREAM) 291f95f3850SWill Newton cmdr |= SDMMC_CMD_STRM_MODE; 292f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 293f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 294f95f3850SWill Newton } 295f95f3850SWill Newton 296cb27a843SJames Hogan if (drv_data && drv_data->prepare_command) 297cb27a843SJames Hogan drv_data->prepare_command(slot->host, &cmdr); 298800d78bfSThomas Abraham 299f95f3850SWill Newton return cmdr; 300f95f3850SWill Newton } 301f95f3850SWill Newton 30290c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30390c2143aSSeungwon Jeon { 30490c2143aSSeungwon Jeon struct mmc_command *stop; 30590c2143aSSeungwon Jeon u32 cmdr; 30690c2143aSSeungwon Jeon 30790c2143aSSeungwon Jeon if (!cmd->data) 30890c2143aSSeungwon Jeon return 0; 30990c2143aSSeungwon Jeon 31090c2143aSSeungwon Jeon stop = &host->stop_abort; 31190c2143aSSeungwon Jeon cmdr = cmd->opcode; 31290c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31390c2143aSSeungwon Jeon 31490c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31590c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31690c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 31790c2143aSSeungwon Jeon cmdr == MMC_WRITE_MULTIPLE_BLOCK) { 31890c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 31990c2143aSSeungwon Jeon stop->arg = 0; 32090c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32190c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32290c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32390c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32490c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 32590c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 32690c2143aSSeungwon Jeon } else { 32790c2143aSSeungwon Jeon return 0; 32890c2143aSSeungwon Jeon } 32990c2143aSSeungwon Jeon 33090c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33190c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33290c2143aSSeungwon Jeon 33390c2143aSSeungwon Jeon return cmdr; 33490c2143aSSeungwon Jeon } 33590c2143aSSeungwon Jeon 336f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 337f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 338f95f3850SWill Newton { 339f95f3850SWill Newton host->cmd = cmd; 3404a90920cSThomas Abraham dev_vdbg(host->dev, 341f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 342f95f3850SWill Newton cmd->arg, cmd_flags); 343f95f3850SWill Newton 344f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 345f95f3850SWill Newton wmb(); 346f95f3850SWill Newton 347f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 348f95f3850SWill Newton } 349f95f3850SWill Newton 35090c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 351f95f3850SWill Newton { 35290c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 35390c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 354f95f3850SWill Newton } 355f95f3850SWill Newton 356f95f3850SWill Newton /* DMA interface functions */ 357f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 358f95f3850SWill Newton { 35903e8cb53SJames Hogan if (host->using_dma) { 360f95f3850SWill Newton host->dma_ops->stop(host); 361f95f3850SWill Newton host->dma_ops->cleanup(host); 362aa50f259SSeungwon Jeon } 363aa50f259SSeungwon Jeon 364f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 365f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 366f95f3850SWill Newton } 367f95f3850SWill Newton 3689aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 3699aa51408SSeungwon Jeon { 3709aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 3719aa51408SSeungwon Jeon return DMA_TO_DEVICE; 3729aa51408SSeungwon Jeon else 3739aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 3749aa51408SSeungwon Jeon } 3759aa51408SSeungwon Jeon 3769beee912SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 377f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 378f95f3850SWill Newton { 379f95f3850SWill Newton struct mmc_data *data = host->data; 380f95f3850SWill Newton 381f95f3850SWill Newton if (data) 3829aa51408SSeungwon Jeon if (!data->host_cookie) 3834a90920cSThomas Abraham dma_unmap_sg(host->dev, 3849aa51408SSeungwon Jeon data->sg, 3859aa51408SSeungwon Jeon data->sg_len, 3869aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 387f95f3850SWill Newton } 388f95f3850SWill Newton 3895ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 3905ce9d961SSeungwon Jeon { 3915ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 3925ce9d961SSeungwon Jeon /* Software reset of DMA */ 3935ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 3945ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 3955ce9d961SSeungwon Jeon } 3965ce9d961SSeungwon Jeon 397f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 398f95f3850SWill Newton { 399f95f3850SWill Newton u32 temp; 400f95f3850SWill Newton 401f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 402f95f3850SWill Newton temp = mci_readl(host, CTRL); 403f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 404f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 405f95f3850SWill Newton mci_writel(host, CTRL, temp); 406f95f3850SWill Newton 407f95f3850SWill Newton /* Stop the IDMAC running */ 408f95f3850SWill Newton temp = mci_readl(host, BMOD); 409a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4105ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 411f95f3850SWill Newton mci_writel(host, BMOD, temp); 412f95f3850SWill Newton } 413f95f3850SWill Newton 414f95f3850SWill Newton static void dw_mci_idmac_complete_dma(struct dw_mci *host) 415f95f3850SWill Newton { 416f95f3850SWill Newton struct mmc_data *data = host->data; 417f95f3850SWill Newton 4184a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 419f95f3850SWill Newton 420f95f3850SWill Newton host->dma_ops->cleanup(host); 421f95f3850SWill Newton 422f95f3850SWill Newton /* 423f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 424f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 425f95f3850SWill Newton */ 426f95f3850SWill Newton if (data) { 427f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 428f95f3850SWill Newton tasklet_schedule(&host->tasklet); 429f95f3850SWill Newton } 430f95f3850SWill Newton } 431f95f3850SWill Newton 432f95f3850SWill Newton static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 433f95f3850SWill Newton unsigned int sg_len) 434f95f3850SWill Newton { 435f95f3850SWill Newton int i; 43669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 43769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *desc = host->sg_cpu; 43869d99fdcSPrabu Thangamuthu 43969d99fdcSPrabu Thangamuthu for (i = 0; i < sg_len; i++, desc++) { 44069d99fdcSPrabu Thangamuthu unsigned int length = sg_dma_len(&data->sg[i]); 44169d99fdcSPrabu Thangamuthu u64 mem_addr = sg_dma_address(&data->sg[i]); 44269d99fdcSPrabu Thangamuthu 44369d99fdcSPrabu Thangamuthu /* 44469d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 44569d99fdcSPrabu Thangamuthu * descriptor 44669d99fdcSPrabu Thangamuthu */ 44769d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 44869d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 44969d99fdcSPrabu Thangamuthu /* Buffer length */ 45069d99fdcSPrabu Thangamuthu IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length); 45169d99fdcSPrabu Thangamuthu 45269d99fdcSPrabu Thangamuthu /* Physical address to DMA to/from */ 45369d99fdcSPrabu Thangamuthu desc->des4 = mem_addr & 0xffffffff; 45469d99fdcSPrabu Thangamuthu desc->des5 = mem_addr >> 32; 45569d99fdcSPrabu Thangamuthu } 45669d99fdcSPrabu Thangamuthu 45769d99fdcSPrabu Thangamuthu /* Set first descriptor */ 45869d99fdcSPrabu Thangamuthu desc = host->sg_cpu; 45969d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_FD; 46069d99fdcSPrabu Thangamuthu 46169d99fdcSPrabu Thangamuthu /* Set last descriptor */ 46269d99fdcSPrabu Thangamuthu desc = host->sg_cpu + (i - 1) * 46369d99fdcSPrabu Thangamuthu sizeof(struct idmac_desc_64addr); 46469d99fdcSPrabu Thangamuthu desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 46569d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_LD; 46669d99fdcSPrabu Thangamuthu 46769d99fdcSPrabu Thangamuthu } else { 468f95f3850SWill Newton struct idmac_desc *desc = host->sg_cpu; 469f95f3850SWill Newton 470f95f3850SWill Newton for (i = 0; i < sg_len; i++, desc++) { 471f95f3850SWill Newton unsigned int length = sg_dma_len(&data->sg[i]); 472f95f3850SWill Newton u32 mem_addr = sg_dma_address(&data->sg[i]); 473f95f3850SWill Newton 47469d99fdcSPrabu Thangamuthu /* 47569d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 47669d99fdcSPrabu Thangamuthu * descriptor 47769d99fdcSPrabu Thangamuthu */ 47869d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 47969d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 480f95f3850SWill Newton /* Buffer length */ 481f95f3850SWill Newton IDMAC_SET_BUFFER1_SIZE(desc, length); 482f95f3850SWill Newton 483f95f3850SWill Newton /* Physical address to DMA to/from */ 484f95f3850SWill Newton desc->des2 = mem_addr; 485f95f3850SWill Newton } 486f95f3850SWill Newton 487f95f3850SWill Newton /* Set first descriptor */ 488f95f3850SWill Newton desc = host->sg_cpu; 489f95f3850SWill Newton desc->des0 |= IDMAC_DES0_FD; 490f95f3850SWill Newton 491f95f3850SWill Newton /* Set last descriptor */ 492f95f3850SWill Newton desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 493f95f3850SWill Newton desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 494f95f3850SWill Newton desc->des0 |= IDMAC_DES0_LD; 49569d99fdcSPrabu Thangamuthu } 496f95f3850SWill Newton 497f95f3850SWill Newton wmb(); 498f95f3850SWill Newton } 499f95f3850SWill Newton 500f95f3850SWill Newton static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 501f95f3850SWill Newton { 502f95f3850SWill Newton u32 temp; 503f95f3850SWill Newton 504f95f3850SWill Newton dw_mci_translate_sglist(host, host->data, sg_len); 505f95f3850SWill Newton 506536f6b91SSonny Rao /* Make sure to reset DMA in case we did PIO before this */ 507536f6b91SSonny Rao dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 508536f6b91SSonny Rao dw_mci_idmac_reset(host); 509536f6b91SSonny Rao 510f95f3850SWill Newton /* Select IDMAC interface */ 511f95f3850SWill Newton temp = mci_readl(host, CTRL); 512f95f3850SWill Newton temp |= SDMMC_CTRL_USE_IDMAC; 513f95f3850SWill Newton mci_writel(host, CTRL, temp); 514f95f3850SWill Newton 515f95f3850SWill Newton wmb(); 516f95f3850SWill Newton 517f95f3850SWill Newton /* Enable the IDMAC */ 518f95f3850SWill Newton temp = mci_readl(host, BMOD); 519a5289a43SJaehoon Chung temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 520f95f3850SWill Newton mci_writel(host, BMOD, temp); 521f95f3850SWill Newton 522f95f3850SWill Newton /* Start it running */ 523f95f3850SWill Newton mci_writel(host, PLDMND, 1); 524f95f3850SWill Newton } 525f95f3850SWill Newton 526f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 527f95f3850SWill Newton { 528897b69e7SSeungwon Jeon int i; 529f95f3850SWill Newton 53069d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 53169d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 53269d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 53369d99fdcSPrabu Thangamuthu host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 53469d99fdcSPrabu Thangamuthu 53569d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 53669d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 53769d99fdcSPrabu Thangamuthu i++, p++) { 53869d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 53969d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 54069d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 54169d99fdcSPrabu Thangamuthu 54269d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 54369d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 54469d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 54569d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 54669d99fdcSPrabu Thangamuthu p->des1 = 0; 54769d99fdcSPrabu Thangamuthu p->des2 = 0; 54869d99fdcSPrabu Thangamuthu p->des3 = 0; 54969d99fdcSPrabu Thangamuthu } 55069d99fdcSPrabu Thangamuthu 55169d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 55269d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 55369d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 55469d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 55569d99fdcSPrabu Thangamuthu 55669d99fdcSPrabu Thangamuthu } else { 55769d99fdcSPrabu Thangamuthu struct idmac_desc *p; 558f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 559f95f3850SWill Newton host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 560f95f3850SWill Newton 561f95f3850SWill Newton /* Forward link the descriptor list */ 562f95f3850SWill Newton for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 56369d99fdcSPrabu Thangamuthu p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * 56469d99fdcSPrabu Thangamuthu (i + 1)); 565f95f3850SWill Newton 566f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 567f95f3850SWill Newton p->des3 = host->sg_dma; 568f95f3850SWill Newton p->des0 = IDMAC_DES0_ER; 56969d99fdcSPrabu Thangamuthu } 570f95f3850SWill Newton 5715ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 572141a712aSSeungwon Jeon 57369d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 57469d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 57569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 57669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 57769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 57869d99fdcSPrabu Thangamuthu 57969d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 58069d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 58169d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 58269d99fdcSPrabu Thangamuthu 58369d99fdcSPrabu Thangamuthu } else { 584f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 585fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 58669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 58769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 588f95f3850SWill Newton 589f95f3850SWill Newton /* Set the descriptor base address */ 590f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 59169d99fdcSPrabu Thangamuthu } 59269d99fdcSPrabu Thangamuthu 593f95f3850SWill Newton return 0; 594f95f3850SWill Newton } 595f95f3850SWill Newton 5968e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 597885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 598885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 599885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 600885c3e80SSeungwon Jeon .complete = dw_mci_idmac_complete_dma, 601885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 602885c3e80SSeungwon Jeon }; 603885c3e80SSeungwon Jeon #endif /* CONFIG_MMC_DW_IDMAC */ 604885c3e80SSeungwon Jeon 6059aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 6069aa51408SSeungwon Jeon struct mmc_data *data, 6079aa51408SSeungwon Jeon bool next) 608f95f3850SWill Newton { 609f95f3850SWill Newton struct scatterlist *sg; 6109aa51408SSeungwon Jeon unsigned int i, sg_len; 611f95f3850SWill Newton 6129aa51408SSeungwon Jeon if (!next && data->host_cookie) 6139aa51408SSeungwon Jeon return data->host_cookie; 614f95f3850SWill Newton 615f95f3850SWill Newton /* 616f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 617f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 618f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 619f95f3850SWill Newton */ 620f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 621f95f3850SWill Newton return -EINVAL; 6229aa51408SSeungwon Jeon 623f95f3850SWill Newton if (data->blksz & 3) 624f95f3850SWill Newton return -EINVAL; 625f95f3850SWill Newton 626f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 627f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 628f95f3850SWill Newton return -EINVAL; 629f95f3850SWill Newton } 630f95f3850SWill Newton 6314a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 6329aa51408SSeungwon Jeon data->sg, 6339aa51408SSeungwon Jeon data->sg_len, 6349aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 6359aa51408SSeungwon Jeon if (sg_len == 0) 6369aa51408SSeungwon Jeon return -EINVAL; 6379aa51408SSeungwon Jeon 6389aa51408SSeungwon Jeon if (next) 6399aa51408SSeungwon Jeon data->host_cookie = sg_len; 6409aa51408SSeungwon Jeon 6419aa51408SSeungwon Jeon return sg_len; 6429aa51408SSeungwon Jeon } 6439aa51408SSeungwon Jeon 6449aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 6459aa51408SSeungwon Jeon struct mmc_request *mrq, 6469aa51408SSeungwon Jeon bool is_first_req) 6479aa51408SSeungwon Jeon { 6489aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6499aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6509aa51408SSeungwon Jeon 6519aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 6529aa51408SSeungwon Jeon return; 6539aa51408SSeungwon Jeon 6549aa51408SSeungwon Jeon if (data->host_cookie) { 6559aa51408SSeungwon Jeon data->host_cookie = 0; 6569aa51408SSeungwon Jeon return; 6579aa51408SSeungwon Jeon } 6589aa51408SSeungwon Jeon 6599aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 6609aa51408SSeungwon Jeon data->host_cookie = 0; 6619aa51408SSeungwon Jeon } 6629aa51408SSeungwon Jeon 6639aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 6649aa51408SSeungwon Jeon struct mmc_request *mrq, 6659aa51408SSeungwon Jeon int err) 6669aa51408SSeungwon Jeon { 6679aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6689aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6699aa51408SSeungwon Jeon 6709aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 6719aa51408SSeungwon Jeon return; 6729aa51408SSeungwon Jeon 6739aa51408SSeungwon Jeon if (data->host_cookie) 6744a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 6759aa51408SSeungwon Jeon data->sg, 6769aa51408SSeungwon Jeon data->sg_len, 6779aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 6789aa51408SSeungwon Jeon data->host_cookie = 0; 6799aa51408SSeungwon Jeon } 6809aa51408SSeungwon Jeon 68152426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 68252426899SSeungwon Jeon { 68352426899SSeungwon Jeon #ifdef CONFIG_MMC_DW_IDMAC 68452426899SSeungwon Jeon unsigned int blksz = data->blksz; 68552426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 68652426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 68752426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 68852426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 68952426899SSeungwon Jeon int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1; 69052426899SSeungwon Jeon 69152426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 69252426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 69352426899SSeungwon Jeon 69452426899SSeungwon Jeon /* 69552426899SSeungwon Jeon * MSIZE is '1', 69652426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 69752426899SSeungwon Jeon */ 69852426899SSeungwon Jeon if (blksz % fifo_width) { 69952426899SSeungwon Jeon msize = 0; 70052426899SSeungwon Jeon rx_wmark = 1; 70152426899SSeungwon Jeon goto done; 70252426899SSeungwon Jeon } 70352426899SSeungwon Jeon 70452426899SSeungwon Jeon do { 70552426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 70652426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 70752426899SSeungwon Jeon msize = idx; 70852426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 70952426899SSeungwon Jeon break; 71052426899SSeungwon Jeon } 71152426899SSeungwon Jeon } while (--idx > 0); 71252426899SSeungwon Jeon /* 71352426899SSeungwon Jeon * If idx is '0', it won't be tried 71452426899SSeungwon Jeon * Thus, initial values are uesed 71552426899SSeungwon Jeon */ 71652426899SSeungwon Jeon done: 71752426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 71852426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 71952426899SSeungwon Jeon #endif 72052426899SSeungwon Jeon } 72152426899SSeungwon Jeon 722f1d2736cSSeungwon Jeon static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 723f1d2736cSSeungwon Jeon { 724f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 725f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 726f1d2736cSSeungwon Jeon u16 thld_size; 727f1d2736cSSeungwon Jeon 728f1d2736cSSeungwon Jeon WARN_ON(!(data->flags & MMC_DATA_READ)); 729f1d2736cSSeungwon Jeon 73066dfd101SJames Hogan /* 73166dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 73266dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 73366dfd101SJames Hogan */ 73466dfd101SJames Hogan if (host->verid < DW_MMC_240A) 73566dfd101SJames Hogan return; 73666dfd101SJames Hogan 737f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 738f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 739f1d2736cSSeungwon Jeon goto disable; 740f1d2736cSSeungwon Jeon 741f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 742f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 743f1d2736cSSeungwon Jeon 744f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 745f1d2736cSSeungwon Jeon goto disable; 746f1d2736cSSeungwon Jeon 747f1d2736cSSeungwon Jeon /* 748f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 749f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 750f1d2736cSSeungwon Jeon * Currently just choose blksz. 751f1d2736cSSeungwon Jeon */ 752f1d2736cSSeungwon Jeon thld_size = blksz; 753f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 754f1d2736cSSeungwon Jeon return; 755f1d2736cSSeungwon Jeon 756f1d2736cSSeungwon Jeon disable: 757f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 758f1d2736cSSeungwon Jeon } 759f1d2736cSSeungwon Jeon 7609aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 7619aa51408SSeungwon Jeon { 7629aa51408SSeungwon Jeon int sg_len; 7639aa51408SSeungwon Jeon u32 temp; 7649aa51408SSeungwon Jeon 7659aa51408SSeungwon Jeon host->using_dma = 0; 7669aa51408SSeungwon Jeon 7679aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 7689aa51408SSeungwon Jeon if (!host->use_dma) 7699aa51408SSeungwon Jeon return -ENODEV; 7709aa51408SSeungwon Jeon 7719aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 772a99aa9b9SSeungwon Jeon if (sg_len < 0) { 773a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 7749aa51408SSeungwon Jeon return sg_len; 775a99aa9b9SSeungwon Jeon } 7769aa51408SSeungwon Jeon 77703e8cb53SJames Hogan host->using_dma = 1; 77803e8cb53SJames Hogan 7794a90920cSThomas Abraham dev_vdbg(host->dev, 780f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 781f95f3850SWill Newton (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 782f95f3850SWill Newton sg_len); 783f95f3850SWill Newton 78452426899SSeungwon Jeon /* 78552426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 78652426899SSeungwon Jeon * If current block size is same with previous size, 78752426899SSeungwon Jeon * no need to update fifoth. 78852426899SSeungwon Jeon */ 78952426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 79052426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 79152426899SSeungwon Jeon 792f95f3850SWill Newton /* Enable the DMA interface */ 793f95f3850SWill Newton temp = mci_readl(host, CTRL); 794f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 795f95f3850SWill Newton mci_writel(host, CTRL, temp); 796f95f3850SWill Newton 797f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 798f95f3850SWill Newton temp = mci_readl(host, INTMASK); 799f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 800f95f3850SWill Newton mci_writel(host, INTMASK, temp); 801f95f3850SWill Newton 802f95f3850SWill Newton host->dma_ops->start(host, sg_len); 803f95f3850SWill Newton 804f95f3850SWill Newton return 0; 805f95f3850SWill Newton } 806f95f3850SWill Newton 807f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 808f95f3850SWill Newton { 809f95f3850SWill Newton u32 temp; 810f95f3850SWill Newton 811f95f3850SWill Newton data->error = -EINPROGRESS; 812f95f3850SWill Newton 813f95f3850SWill Newton WARN_ON(host->data); 814f95f3850SWill Newton host->sg = NULL; 815f95f3850SWill Newton host->data = data; 816f95f3850SWill Newton 817f1d2736cSSeungwon Jeon if (data->flags & MMC_DATA_READ) { 81855c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 819f1d2736cSSeungwon Jeon dw_mci_ctrl_rd_thld(host, data); 820f1d2736cSSeungwon Jeon } else { 82155c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 822f1d2736cSSeungwon Jeon } 82355c5efbcSJames Hogan 824f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 825f9c2a0dcSSeungwon Jeon int flags = SG_MITER_ATOMIC; 826f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 827f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 828f9c2a0dcSSeungwon Jeon else 829f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 830f9c2a0dcSSeungwon Jeon 831f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 832f95f3850SWill Newton host->sg = data->sg; 83334b664a2SJames Hogan host->part_buf_start = 0; 83434b664a2SJames Hogan host->part_buf_count = 0; 835f95f3850SWill Newton 836b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 837f95f3850SWill Newton temp = mci_readl(host, INTMASK); 838f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 839f95f3850SWill Newton mci_writel(host, INTMASK, temp); 840f95f3850SWill Newton 841f95f3850SWill Newton temp = mci_readl(host, CTRL); 842f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 843f95f3850SWill Newton mci_writel(host, CTRL, temp); 84452426899SSeungwon Jeon 84552426899SSeungwon Jeon /* 84652426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 84752426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 84852426899SSeungwon Jeon * prev_blksz should be invalidated. 84952426899SSeungwon Jeon */ 85052426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 85152426899SSeungwon Jeon host->prev_blksz = 0; 85252426899SSeungwon Jeon } else { 85352426899SSeungwon Jeon /* 85452426899SSeungwon Jeon * Keep the current block size. 85552426899SSeungwon Jeon * It will be used to decide whether to update 85652426899SSeungwon Jeon * fifoth register next time. 85752426899SSeungwon Jeon */ 85852426899SSeungwon Jeon host->prev_blksz = data->blksz; 859f95f3850SWill Newton } 860f95f3850SWill Newton } 861f95f3850SWill Newton 862f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 863f95f3850SWill Newton { 864f95f3850SWill Newton struct dw_mci *host = slot->host; 865f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 866f95f3850SWill Newton unsigned int cmd_status = 0; 867f95f3850SWill Newton 868f95f3850SWill Newton mci_writel(host, CMDARG, arg); 869f95f3850SWill Newton wmb(); 870f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 871f95f3850SWill Newton 872f95f3850SWill Newton while (time_before(jiffies, timeout)) { 873f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 874f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 875f95f3850SWill Newton return; 876f95f3850SWill Newton } 877f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 878f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 879f95f3850SWill Newton cmd, arg, cmd_status); 880f95f3850SWill Newton } 881f95f3850SWill Newton 882ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 883f95f3850SWill Newton { 884f95f3850SWill Newton struct dw_mci *host = slot->host; 885fdf492a1SDoug Anderson unsigned int clock = slot->clock; 886f95f3850SWill Newton u32 div; 8879623b5b9SDoug Anderson u32 clk_en_a; 88801730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 88901730558SDoug Anderson 89001730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 89101730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 89201730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 893f95f3850SWill Newton 894fdf492a1SDoug Anderson if (!clock) { 895fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 89601730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 897fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 898fdf492a1SDoug Anderson div = host->bus_hz / clock; 899fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 900f95f3850SWill Newton /* 901f95f3850SWill Newton * move the + 1 after the divide to prevent 902f95f3850SWill Newton * over-clocking the card. 903f95f3850SWill Newton */ 904e419990bSSeungwon Jeon div += 1; 905e419990bSSeungwon Jeon 906fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 907f95f3850SWill Newton 908fdf492a1SDoug Anderson if ((clock << div) != slot->__clk_old || force_clkinit) 909f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 910fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 911fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 912fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 913fdf492a1SDoug Anderson host->bus_hz, div); 914f95f3850SWill Newton 915f95f3850SWill Newton /* disable clock */ 916f95f3850SWill Newton mci_writel(host, CLKENA, 0); 917f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 918f95f3850SWill Newton 919f95f3850SWill Newton /* inform CIU */ 92001730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 921f95f3850SWill Newton 922f95f3850SWill Newton /* set clock to desired speed */ 923f95f3850SWill Newton mci_writel(host, CLKDIV, div); 924f95f3850SWill Newton 925f95f3850SWill Newton /* inform CIU */ 92601730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 927f95f3850SWill Newton 9289623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 9299623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 930b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 9319623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 9329623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 933f95f3850SWill Newton 934f95f3850SWill Newton /* inform CIU */ 93501730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 936f95f3850SWill Newton 937fdf492a1SDoug Anderson /* keep the clock with reflecting clock dividor */ 938fdf492a1SDoug Anderson slot->__clk_old = clock << div; 939f95f3850SWill Newton } 940f95f3850SWill Newton 941fdf492a1SDoug Anderson host->current_speed = clock; 942fdf492a1SDoug Anderson 943f95f3850SWill Newton /* Set the current slot bus width */ 9441d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 945f95f3850SWill Newton } 946f95f3850SWill Newton 947053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 948053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 949053b3ce6SSeungwon Jeon struct mmc_command *cmd) 950f95f3850SWill Newton { 951f95f3850SWill Newton struct mmc_request *mrq; 952f95f3850SWill Newton struct mmc_data *data; 953f95f3850SWill Newton u32 cmdflags; 954f95f3850SWill Newton 955f95f3850SWill Newton mrq = slot->mrq; 956f95f3850SWill Newton 957f95f3850SWill Newton host->cur_slot = slot; 958f95f3850SWill Newton host->mrq = mrq; 959f95f3850SWill Newton 960f95f3850SWill Newton host->pending_events = 0; 961f95f3850SWill Newton host->completed_events = 0; 962e352c813SSeungwon Jeon host->cmd_status = 0; 963f95f3850SWill Newton host->data_status = 0; 964e352c813SSeungwon Jeon host->dir_status = 0; 965f95f3850SWill Newton 966053b3ce6SSeungwon Jeon data = cmd->data; 967f95f3850SWill Newton if (data) { 968f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 969f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 970f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 971f95f3850SWill Newton } 972f95f3850SWill Newton 973f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 974f95f3850SWill Newton 975f95f3850SWill Newton /* this is the first command, send the initialization clock */ 976f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 977f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 978f95f3850SWill Newton 979f95f3850SWill Newton if (data) { 980f95f3850SWill Newton dw_mci_submit_data(host, data); 981f95f3850SWill Newton wmb(); 982f95f3850SWill Newton } 983f95f3850SWill Newton 984f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 985f95f3850SWill Newton 986f95f3850SWill Newton if (mrq->stop) 987f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 98890c2143aSSeungwon Jeon else 98990c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 990f95f3850SWill Newton } 991f95f3850SWill Newton 992053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 993053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 994053b3ce6SSeungwon Jeon { 995053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 996053b3ce6SSeungwon Jeon struct mmc_command *cmd; 997053b3ce6SSeungwon Jeon 998053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 999053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1000053b3ce6SSeungwon Jeon } 1001053b3ce6SSeungwon Jeon 10027456caaeSJames Hogan /* must be called with host->lock held */ 1003f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1004f95f3850SWill Newton struct mmc_request *mrq) 1005f95f3850SWill Newton { 1006f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1007f95f3850SWill Newton host->state); 1008f95f3850SWill Newton 1009f95f3850SWill Newton slot->mrq = mrq; 1010f95f3850SWill Newton 101101730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 101201730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 101301730558SDoug Anderson "Voltage change didn't complete\n"); 101401730558SDoug Anderson /* 101501730558SDoug Anderson * this case isn't expected to happen, so we can 101601730558SDoug Anderson * either crash here or just try to continue on 101701730558SDoug Anderson * in the closest possible state 101801730558SDoug Anderson */ 101901730558SDoug Anderson host->state = STATE_IDLE; 102001730558SDoug Anderson } 102101730558SDoug Anderson 1022f95f3850SWill Newton if (host->state == STATE_IDLE) { 1023f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1024f95f3850SWill Newton dw_mci_start_request(host, slot); 1025f95f3850SWill Newton } else { 1026f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1027f95f3850SWill Newton } 1028f95f3850SWill Newton } 1029f95f3850SWill Newton 1030f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1031f95f3850SWill Newton { 1032f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1033f95f3850SWill Newton struct dw_mci *host = slot->host; 1034f95f3850SWill Newton 1035f95f3850SWill Newton WARN_ON(slot->mrq); 1036f95f3850SWill Newton 10377456caaeSJames Hogan /* 10387456caaeSJames Hogan * The check for card presence and queueing of the request must be 10397456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 10407456caaeSJames Hogan * request wouldn't fail until another card was inserted. 10417456caaeSJames Hogan */ 10427456caaeSJames Hogan spin_lock_bh(&host->lock); 10437456caaeSJames Hogan 1044f95f3850SWill Newton if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 10457456caaeSJames Hogan spin_unlock_bh(&host->lock); 1046f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1047f95f3850SWill Newton mmc_request_done(mmc, mrq); 1048f95f3850SWill Newton return; 1049f95f3850SWill Newton } 1050f95f3850SWill Newton 1051f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 10527456caaeSJames Hogan 10537456caaeSJames Hogan spin_unlock_bh(&host->lock); 1054f95f3850SWill Newton } 1055f95f3850SWill Newton 1056f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1057f95f3850SWill Newton { 1058f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1059e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 106041babf75SJaehoon Chung u32 regs; 106151da2240SYuvaraj CD int ret; 1062f95f3850SWill Newton 1063f95f3850SWill Newton switch (ios->bus_width) { 1064f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1065f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1066f95f3850SWill Newton break; 1067c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1068c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1069c9b2a06fSJaehoon Chung break; 1070b2f7cb45SJaehoon Chung default: 1071b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1072b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1073f95f3850SWill Newton } 1074f95f3850SWill Newton 107541babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 10763f514291SSeungwon Jeon 10773f514291SSeungwon Jeon /* DDR mode set */ 1078cab3a802SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52) 1079c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 10803f514291SSeungwon Jeon else 1081c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 10823f514291SSeungwon Jeon 108341babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1084f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 108541babf75SJaehoon Chung 1086f95f3850SWill Newton /* 1087f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1088f95f3850SWill Newton * core ios update when finding the minimum. 1089f95f3850SWill Newton */ 1090f95f3850SWill Newton slot->clock = ios->clock; 1091f95f3850SWill Newton 1092cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1093cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1094800d78bfSThomas Abraham 1095bf7cb224SJaehoon Chung /* Slot specific timing and width adjustment */ 1096bf7cb224SJaehoon Chung dw_mci_setup_bus(slot, false); 1097bf7cb224SJaehoon Chung 109801730558SDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 109901730558SDoug Anderson slot->host->state = STATE_IDLE; 110001730558SDoug Anderson 1101f95f3850SWill Newton switch (ios->power_mode) { 1102f95f3850SWill Newton case MMC_POWER_UP: 110351da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 110451da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 110551da2240SYuvaraj CD ios->vdd); 110651da2240SYuvaraj CD if (ret) { 110751da2240SYuvaraj CD dev_err(slot->host->dev, 110851da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 110951da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 111051da2240SYuvaraj CD return; 111151da2240SYuvaraj CD } 111251da2240SYuvaraj CD } 111351da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) { 111451da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 111551da2240SYuvaraj CD if (ret < 0) 111651da2240SYuvaraj CD dev_err(slot->host->dev, 111751da2240SYuvaraj CD "failed to enable vqmmc regulator\n"); 111851da2240SYuvaraj CD else 111951da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 112051da2240SYuvaraj CD } 1121f95f3850SWill Newton set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 11224366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 11234366dcc5SJaehoon Chung regs |= (1 << slot->id); 11244366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1125e6f34e2fSJames Hogan break; 1126e6f34e2fSJames Hogan case MMC_POWER_OFF: 112751da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 112851da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 112951da2240SYuvaraj CD 113051da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) { 113151da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 113251da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 113351da2240SYuvaraj CD } 113451da2240SYuvaraj CD 11354366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 11364366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 11374366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1138f95f3850SWill Newton break; 1139f95f3850SWill Newton default: 1140f95f3850SWill Newton break; 1141f95f3850SWill Newton } 1142f95f3850SWill Newton } 1143f95f3850SWill Newton 114401730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 114501730558SDoug Anderson { 114601730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 114701730558SDoug Anderson u32 status; 114801730558SDoug Anderson 114901730558SDoug Anderson /* 115001730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 115101730558SDoug Anderson * (the data lines) are 0000 115201730558SDoug Anderson */ 115301730558SDoug Anderson status = mci_readl(slot->host, STATUS); 115401730558SDoug Anderson 115501730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 115601730558SDoug Anderson } 115701730558SDoug Anderson 115801730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 115901730558SDoug Anderson { 116001730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 116101730558SDoug Anderson struct dw_mci *host = slot->host; 116201730558SDoug Anderson u32 uhs; 116301730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 116401730558SDoug Anderson int min_uv, max_uv; 116501730558SDoug Anderson int ret; 116601730558SDoug Anderson 116701730558SDoug Anderson /* 116801730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 116901730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 117001730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 117101730558SDoug Anderson */ 117201730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 117301730558SDoug Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 117401730558SDoug Anderson min_uv = 2700000; 117501730558SDoug Anderson max_uv = 3600000; 117601730558SDoug Anderson uhs &= ~v18; 117701730558SDoug Anderson } else { 117801730558SDoug Anderson min_uv = 1700000; 117901730558SDoug Anderson max_uv = 1950000; 118001730558SDoug Anderson uhs |= v18; 118101730558SDoug Anderson } 118201730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 118301730558SDoug Anderson ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 118401730558SDoug Anderson 118501730558SDoug Anderson if (ret) { 1186b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 118701730558SDoug Anderson "Regulator set error %d: %d - %d\n", 118801730558SDoug Anderson ret, min_uv, max_uv); 118901730558SDoug Anderson return ret; 119001730558SDoug Anderson } 119101730558SDoug Anderson } 119201730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 119301730558SDoug Anderson 119401730558SDoug Anderson return 0; 119501730558SDoug Anderson } 119601730558SDoug Anderson 1197f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1198f95f3850SWill Newton { 1199f95f3850SWill Newton int read_only; 1200f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 12019795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1202f95f3850SWill Newton 1203f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 120426375b5cSJaehoon Chung if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) || 120526375b5cSJaehoon Chung (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)) 1206b4967aa5SThomas Abraham read_only = 0; 12079795a846SJaehoon Chung else if (!IS_ERR_VALUE(gpio_ro)) 12089795a846SJaehoon Chung read_only = gpio_ro; 1209f95f3850SWill Newton else 1210f95f3850SWill Newton read_only = 1211f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1212f95f3850SWill Newton 1213f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1214f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1215f95f3850SWill Newton 1216f95f3850SWill Newton return read_only; 1217f95f3850SWill Newton } 1218f95f3850SWill Newton 1219f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1220f95f3850SWill Newton { 1221f95f3850SWill Newton int present; 1222f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1223f95f3850SWill Newton struct dw_mci_board *brd = slot->host->pdata; 12247cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 12257cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1226f95f3850SWill Newton 1227f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 1228fc3d7720SJaehoon Chung if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 1229fc3d7720SJaehoon Chung present = 1; 1230bf626e55SZhangfei Gao else if (!IS_ERR_VALUE(gpio_cd)) 12317cf347bdSZhangfei Gao present = gpio_cd; 1232f95f3850SWill Newton else 1233f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1234f95f3850SWill Newton == 0 ? 1 : 0; 1235f95f3850SWill Newton 12367cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1237bf626e55SZhangfei Gao if (present) { 1238bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1239f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1240bf626e55SZhangfei Gao } else { 1241bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1242f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1243bf626e55SZhangfei Gao } 12447cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1245f95f3850SWill Newton 1246f95f3850SWill Newton return present; 1247f95f3850SWill Newton } 1248f95f3850SWill Newton 1249b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1250b24c8b26SDoug Anderson { 1251b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1252b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1253b24c8b26SDoug Anderson 12549623b5b9SDoug Anderson /* 12559623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 12569623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 12579623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 12589623b5b9SDoug Anderson */ 1259b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 12609623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1261b24c8b26SDoug Anderson u32 clk_en_a_old; 1262b24c8b26SDoug Anderson u32 clk_en_a; 12639623b5b9SDoug Anderson 1264b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 12659623b5b9SDoug Anderson 1266b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1267b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1268b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1269b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1270b24c8b26SDoug Anderson } else { 1271b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1272b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1273b24c8b26SDoug Anderson } 1274b24c8b26SDoug Anderson 1275b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1276b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 12779623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 12789623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 12799623b5b9SDoug Anderson } 12809623b5b9SDoug Anderson } 1281b24c8b26SDoug Anderson } 12829623b5b9SDoug Anderson 12831a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 12841a5c8e1fSShashidhar Hiremath { 12851a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 12861a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 12871a5c8e1fSShashidhar Hiremath u32 int_mask; 12881a5c8e1fSShashidhar Hiremath 12891a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 12901a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1291b24c8b26SDoug Anderson if (enb) 1292b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1293b24c8b26SDoug Anderson else 1294b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1295b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 12961a5c8e1fSShashidhar Hiremath } 12971a5c8e1fSShashidhar Hiremath 12980976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 12990976f16dSSeungwon Jeon { 13000976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 13010976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 13020976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 13030976f16dSSeungwon Jeon struct dw_mci_tuning_data tuning_data; 13040976f16dSSeungwon Jeon int err = -ENOSYS; 13050976f16dSSeungwon Jeon 13060976f16dSSeungwon Jeon if (opcode == MMC_SEND_TUNING_BLOCK_HS200) { 13070976f16dSSeungwon Jeon if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 13080976f16dSSeungwon Jeon tuning_data.blk_pattern = tuning_blk_pattern_8bit; 13090976f16dSSeungwon Jeon tuning_data.blksz = sizeof(tuning_blk_pattern_8bit); 13100976f16dSSeungwon Jeon } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) { 13110976f16dSSeungwon Jeon tuning_data.blk_pattern = tuning_blk_pattern_4bit; 13120976f16dSSeungwon Jeon tuning_data.blksz = sizeof(tuning_blk_pattern_4bit); 13130976f16dSSeungwon Jeon } else { 13140976f16dSSeungwon Jeon return -EINVAL; 13150976f16dSSeungwon Jeon } 13160976f16dSSeungwon Jeon } else if (opcode == MMC_SEND_TUNING_BLOCK) { 13170976f16dSSeungwon Jeon tuning_data.blk_pattern = tuning_blk_pattern_4bit; 13180976f16dSSeungwon Jeon tuning_data.blksz = sizeof(tuning_blk_pattern_4bit); 13190976f16dSSeungwon Jeon } else { 13200976f16dSSeungwon Jeon dev_err(host->dev, 13210976f16dSSeungwon Jeon "Undefined command(%d) for tuning\n", opcode); 13220976f16dSSeungwon Jeon return -EINVAL; 13230976f16dSSeungwon Jeon } 13240976f16dSSeungwon Jeon 13250976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 13260976f16dSSeungwon Jeon err = drv_data->execute_tuning(slot, opcode, &tuning_data); 13270976f16dSSeungwon Jeon return err; 13280976f16dSSeungwon Jeon } 13290976f16dSSeungwon Jeon 1330f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1331f95f3850SWill Newton .request = dw_mci_request, 13329aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 13339aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1334f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1335f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1336f95f3850SWill Newton .get_cd = dw_mci_get_cd, 13371a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 13380976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 133901730558SDoug Anderson .card_busy = dw_mci_card_busy, 134001730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1341b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 1342f95f3850SWill Newton }; 1343f95f3850SWill Newton 1344f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1345f95f3850SWill Newton __releases(&host->lock) 1346f95f3850SWill Newton __acquires(&host->lock) 1347f95f3850SWill Newton { 1348f95f3850SWill Newton struct dw_mci_slot *slot; 1349f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1350f95f3850SWill Newton 1351f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1352f95f3850SWill Newton 1353f95f3850SWill Newton host->cur_slot->mrq = NULL; 1354f95f3850SWill Newton host->mrq = NULL; 1355f95f3850SWill Newton if (!list_empty(&host->queue)) { 1356f95f3850SWill Newton slot = list_entry(host->queue.next, 1357f95f3850SWill Newton struct dw_mci_slot, queue_node); 1358f95f3850SWill Newton list_del(&slot->queue_node); 13594a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1360f95f3850SWill Newton mmc_hostname(slot->mmc)); 1361f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1362f95f3850SWill Newton dw_mci_start_request(host, slot); 1363f95f3850SWill Newton } else { 13644a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 136501730558SDoug Anderson 136601730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 136701730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 136801730558SDoug Anderson else 1369f95f3850SWill Newton host->state = STATE_IDLE; 1370f95f3850SWill Newton } 1371f95f3850SWill Newton 1372f95f3850SWill Newton spin_unlock(&host->lock); 1373f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1374f95f3850SWill Newton spin_lock(&host->lock); 1375f95f3850SWill Newton } 1376f95f3850SWill Newton 1377e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1378f95f3850SWill Newton { 1379f95f3850SWill Newton u32 status = host->cmd_status; 1380f95f3850SWill Newton 1381f95f3850SWill Newton host->cmd_status = 0; 1382f95f3850SWill Newton 1383f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1384f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1385f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1386f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1387f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1388f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1389f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1390f95f3850SWill Newton } else { 1391f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1392f95f3850SWill Newton cmd->resp[1] = 0; 1393f95f3850SWill Newton cmd->resp[2] = 0; 1394f95f3850SWill Newton cmd->resp[3] = 0; 1395f95f3850SWill Newton } 1396f95f3850SWill Newton } 1397f95f3850SWill Newton 1398f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1399f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1400f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1401f95f3850SWill Newton cmd->error = -EILSEQ; 1402f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1403f95f3850SWill Newton cmd->error = -EIO; 1404f95f3850SWill Newton else 1405f95f3850SWill Newton cmd->error = 0; 1406f95f3850SWill Newton 1407f95f3850SWill Newton if (cmd->error) { 1408f95f3850SWill Newton /* newer ip versions need a delay between retries */ 1409f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1410f95f3850SWill Newton mdelay(20); 1411f95f3850SWill Newton } 1412e352c813SSeungwon Jeon 1413e352c813SSeungwon Jeon return cmd->error; 1414e352c813SSeungwon Jeon } 1415e352c813SSeungwon Jeon 1416e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1417e352c813SSeungwon Jeon { 141831bff450SSeungwon Jeon u32 status = host->data_status; 1419e352c813SSeungwon Jeon 1420e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1421e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1422e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1423e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1424e352c813SSeungwon Jeon data->error = -EILSEQ; 1425e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1426e352c813SSeungwon Jeon if (host->dir_status == 1427e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1428e352c813SSeungwon Jeon /* 1429e352c813SSeungwon Jeon * No data CRC status was returned. 1430e352c813SSeungwon Jeon * The number of bytes transferred 1431e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1432e352c813SSeungwon Jeon */ 1433e352c813SSeungwon Jeon data->bytes_xfered = 0; 1434e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1435e352c813SSeungwon Jeon } else if (host->dir_status == 1436e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1437e352c813SSeungwon Jeon data->error = -EIO; 1438e352c813SSeungwon Jeon } 1439e352c813SSeungwon Jeon } else { 1440e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1441e352c813SSeungwon Jeon data->error = -EIO; 1442e352c813SSeungwon Jeon } 1443e352c813SSeungwon Jeon 1444e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1445e352c813SSeungwon Jeon 1446e352c813SSeungwon Jeon /* 1447e352c813SSeungwon Jeon * After an error, there may be data lingering 144831bff450SSeungwon Jeon * in the FIFO 1449e352c813SSeungwon Jeon */ 14503a33a94cSSonny Rao dw_mci_reset(host); 1451e352c813SSeungwon Jeon } else { 1452e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1453e352c813SSeungwon Jeon data->error = 0; 1454e352c813SSeungwon Jeon } 1455e352c813SSeungwon Jeon 1456e352c813SSeungwon Jeon return data->error; 1457f95f3850SWill Newton } 1458f95f3850SWill Newton 1459f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1460f95f3850SWill Newton { 1461f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1462f95f3850SWill Newton struct mmc_data *data; 1463f95f3850SWill Newton struct mmc_command *cmd; 1464e352c813SSeungwon Jeon struct mmc_request *mrq; 1465f95f3850SWill Newton enum dw_mci_state state; 1466f95f3850SWill Newton enum dw_mci_state prev_state; 1467e352c813SSeungwon Jeon unsigned int err; 1468f95f3850SWill Newton 1469f95f3850SWill Newton spin_lock(&host->lock); 1470f95f3850SWill Newton 1471f95f3850SWill Newton state = host->state; 1472f95f3850SWill Newton data = host->data; 1473e352c813SSeungwon Jeon mrq = host->mrq; 1474f95f3850SWill Newton 1475f95f3850SWill Newton do { 1476f95f3850SWill Newton prev_state = state; 1477f95f3850SWill Newton 1478f95f3850SWill Newton switch (state) { 1479f95f3850SWill Newton case STATE_IDLE: 148001730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1481f95f3850SWill Newton break; 1482f95f3850SWill Newton 148301730558SDoug Anderson case STATE_SENDING_CMD11: 1484f95f3850SWill Newton case STATE_SENDING_CMD: 1485f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1486f95f3850SWill Newton &host->pending_events)) 1487f95f3850SWill Newton break; 1488f95f3850SWill Newton 1489f95f3850SWill Newton cmd = host->cmd; 1490f95f3850SWill Newton host->cmd = NULL; 1491f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1492e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1493e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1494053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1495053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1496e352c813SSeungwon Jeon mrq->cmd); 1497053b3ce6SSeungwon Jeon goto unlock; 1498053b3ce6SSeungwon Jeon } 1499053b3ce6SSeungwon Jeon 1500e352c813SSeungwon Jeon if (cmd->data && err) { 150171abb133SSeungwon Jeon dw_mci_stop_dma(host); 150290c2143aSSeungwon Jeon send_stop_abort(host, data); 150371abb133SSeungwon Jeon state = STATE_SENDING_STOP; 150471abb133SSeungwon Jeon break; 150571abb133SSeungwon Jeon } 150671abb133SSeungwon Jeon 1507e352c813SSeungwon Jeon if (!cmd->data || err) { 1508e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1509f95f3850SWill Newton goto unlock; 1510f95f3850SWill Newton } 1511f95f3850SWill Newton 1512f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1513f95f3850SWill Newton /* fall through */ 1514f95f3850SWill Newton 1515f95f3850SWill Newton case STATE_SENDING_DATA: 15162aa35465SDoug Anderson /* 15172aa35465SDoug Anderson * We could get a data error and never a transfer 15182aa35465SDoug Anderson * complete so we'd better check for it here. 15192aa35465SDoug Anderson * 15202aa35465SDoug Anderson * Note that we don't really care if we also got a 15212aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 15222aa35465SDoug Anderson * abort won't hurt. 15232aa35465SDoug Anderson */ 1524f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1525f95f3850SWill Newton &host->pending_events)) { 1526f95f3850SWill Newton dw_mci_stop_dma(host); 152790c2143aSSeungwon Jeon send_stop_abort(host, data); 1528f95f3850SWill Newton state = STATE_DATA_ERROR; 1529f95f3850SWill Newton break; 1530f95f3850SWill Newton } 1531f95f3850SWill Newton 1532f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1533f95f3850SWill Newton &host->pending_events)) 1534f95f3850SWill Newton break; 1535f95f3850SWill Newton 1536f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 15372aa35465SDoug Anderson 15382aa35465SDoug Anderson /* 15392aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 15402aa35465SDoug Anderson * before the transfer completed. This might not have 15412aa35465SDoug Anderson * been caught by the check above because the interrupt 15422aa35465SDoug Anderson * could have gone off between the previous check and 15432aa35465SDoug Anderson * the check for transfer complete. 15442aa35465SDoug Anderson * 15452aa35465SDoug Anderson * Technically this ought not be needed assuming we 15462aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 15472aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 15482aa35465SDoug Anderson * 15492aa35465SDoug Anderson * This has the advantage of sending the stop command. 15502aa35465SDoug Anderson */ 15512aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 15522aa35465SDoug Anderson &host->pending_events)) { 15532aa35465SDoug Anderson dw_mci_stop_dma(host); 15542aa35465SDoug Anderson send_stop_abort(host, data); 15552aa35465SDoug Anderson state = STATE_DATA_ERROR; 15562aa35465SDoug Anderson break; 15572aa35465SDoug Anderson } 1558f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 15592aa35465SDoug Anderson 1560f95f3850SWill Newton /* fall through */ 1561f95f3850SWill Newton 1562f95f3850SWill Newton case STATE_DATA_BUSY: 1563f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1564f95f3850SWill Newton &host->pending_events)) 1565f95f3850SWill Newton break; 1566f95f3850SWill Newton 1567f95f3850SWill Newton host->data = NULL; 1568f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1569e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1570f95f3850SWill Newton 1571e352c813SSeungwon Jeon if (!err) { 1572e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 157317c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1574053b3ce6SSeungwon Jeon data->stop->error = 0; 1575e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1576053b3ce6SSeungwon Jeon goto unlock; 1577053b3ce6SSeungwon Jeon } 1578053b3ce6SSeungwon Jeon 157990c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1580e352c813SSeungwon Jeon if (data->stop) 158190c2143aSSeungwon Jeon send_stop_abort(host, data); 15822aa35465SDoug Anderson } else { 15832aa35465SDoug Anderson /* 15842aa35465SDoug Anderson * If we don't have a command complete now we'll 15852aa35465SDoug Anderson * never get one since we just reset everything; 15862aa35465SDoug Anderson * better end the request. 15872aa35465SDoug Anderson * 15882aa35465SDoug Anderson * If we do have a command complete we'll fall 15892aa35465SDoug Anderson * through to the SENDING_STOP command and 15902aa35465SDoug Anderson * everything will be peachy keen. 15912aa35465SDoug Anderson */ 15922aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 15932aa35465SDoug Anderson &host->pending_events)) { 15942aa35465SDoug Anderson host->cmd = NULL; 15952aa35465SDoug Anderson dw_mci_request_end(host, mrq); 15962aa35465SDoug Anderson goto unlock; 15972aa35465SDoug Anderson } 159890c2143aSSeungwon Jeon } 1599e352c813SSeungwon Jeon 1600e352c813SSeungwon Jeon /* 1601e352c813SSeungwon Jeon * If err has non-zero, 1602e352c813SSeungwon Jeon * stop-abort command has been already issued. 1603e352c813SSeungwon Jeon */ 1604e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1605e352c813SSeungwon Jeon 1606f95f3850SWill Newton /* fall through */ 1607f95f3850SWill Newton 1608f95f3850SWill Newton case STATE_SENDING_STOP: 1609f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1610f95f3850SWill Newton &host->pending_events)) 1611f95f3850SWill Newton break; 1612f95f3850SWill Newton 161371abb133SSeungwon Jeon /* CMD error in data command */ 161431bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 16153a33a94cSSonny Rao dw_mci_reset(host); 161671abb133SSeungwon Jeon 1617f95f3850SWill Newton host->cmd = NULL; 161871abb133SSeungwon Jeon host->data = NULL; 161990c2143aSSeungwon Jeon 1620e352c813SSeungwon Jeon if (mrq->stop) 1621e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 162290c2143aSSeungwon Jeon else 162390c2143aSSeungwon Jeon host->cmd_status = 0; 162490c2143aSSeungwon Jeon 1625e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1626f95f3850SWill Newton goto unlock; 1627f95f3850SWill Newton 1628f95f3850SWill Newton case STATE_DATA_ERROR: 1629f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1630f95f3850SWill Newton &host->pending_events)) 1631f95f3850SWill Newton break; 1632f95f3850SWill Newton 1633f95f3850SWill Newton state = STATE_DATA_BUSY; 1634f95f3850SWill Newton break; 1635f95f3850SWill Newton } 1636f95f3850SWill Newton } while (state != prev_state); 1637f95f3850SWill Newton 1638f95f3850SWill Newton host->state = state; 1639f95f3850SWill Newton unlock: 1640f95f3850SWill Newton spin_unlock(&host->lock); 1641f95f3850SWill Newton 1642f95f3850SWill Newton } 1643f95f3850SWill Newton 164434b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 164534b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 164634b664a2SJames Hogan { 164734b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 164834b664a2SJames Hogan host->part_buf_count = cnt; 164934b664a2SJames Hogan } 165034b664a2SJames Hogan 165134b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 165234b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 165334b664a2SJames Hogan { 165434b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 165534b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 165634b664a2SJames Hogan host->part_buf_count += cnt; 165734b664a2SJames Hogan return cnt; 165834b664a2SJames Hogan } 165934b664a2SJames Hogan 166034b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 166134b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 166234b664a2SJames Hogan { 166334b664a2SJames Hogan cnt = min(cnt, (int)host->part_buf_count); 166434b664a2SJames Hogan if (cnt) { 166534b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 166634b664a2SJames Hogan cnt); 166734b664a2SJames Hogan host->part_buf_count -= cnt; 166834b664a2SJames Hogan host->part_buf_start += cnt; 166934b664a2SJames Hogan } 167034b664a2SJames Hogan return cnt; 167134b664a2SJames Hogan } 167234b664a2SJames Hogan 167334b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 167434b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 167534b664a2SJames Hogan { 167634b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 167734b664a2SJames Hogan host->part_buf_start = cnt; 167834b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 167934b664a2SJames Hogan } 168034b664a2SJames Hogan 1681f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1682f95f3850SWill Newton { 1683cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1684cfbeb59cSMarkos Chandras int init_cnt = cnt; 1685cfbeb59cSMarkos Chandras 168634b664a2SJames Hogan /* try and push anything in the part_buf */ 168734b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 168834b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 168934b664a2SJames Hogan buf += len; 169034b664a2SJames Hogan cnt -= len; 1691cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 16924e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 16934e0a5adfSJaehoon Chung host->part_buf16); 169434b664a2SJames Hogan host->part_buf_count = 0; 169534b664a2SJames Hogan } 169634b664a2SJames Hogan } 169734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 169834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 169934b664a2SJames Hogan while (cnt >= 2) { 170034b664a2SJames Hogan u16 aligned_buf[64]; 170134b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 170234b664a2SJames Hogan int items = len >> 1; 170334b664a2SJames Hogan int i; 170434b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 170534b664a2SJames Hogan memcpy(aligned_buf, buf, len); 170634b664a2SJames Hogan buf += len; 170734b664a2SJames Hogan cnt -= len; 170834b664a2SJames Hogan /* push data from aligned buffer into fifo */ 170934b664a2SJames Hogan for (i = 0; i < items; ++i) 17104e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17114e0a5adfSJaehoon Chung aligned_buf[i]); 171234b664a2SJames Hogan } 171334b664a2SJames Hogan } else 171434b664a2SJames Hogan #endif 171534b664a2SJames Hogan { 171634b664a2SJames Hogan u16 *pdata = buf; 171734b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 17184e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), *pdata++); 171934b664a2SJames Hogan buf = pdata; 172034b664a2SJames Hogan } 172134b664a2SJames Hogan /* put anything remaining in the part_buf */ 172234b664a2SJames Hogan if (cnt) { 172334b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1724cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1725cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1726cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 17274e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17284e0a5adfSJaehoon Chung host->part_buf16); 1729f95f3850SWill Newton } 1730f95f3850SWill Newton } 1731f95f3850SWill Newton 1732f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1733f95f3850SWill Newton { 173434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 173534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 173634b664a2SJames Hogan while (cnt >= 2) { 173734b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 173834b664a2SJames Hogan u16 aligned_buf[64]; 173934b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 174034b664a2SJames Hogan int items = len >> 1; 174134b664a2SJames Hogan int i; 174234b664a2SJames Hogan for (i = 0; i < items; ++i) 17434e0a5adfSJaehoon Chung aligned_buf[i] = mci_readw(host, 17444e0a5adfSJaehoon Chung DATA(host->data_offset)); 174534b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 174634b664a2SJames Hogan memcpy(buf, aligned_buf, len); 174734b664a2SJames Hogan buf += len; 174834b664a2SJames Hogan cnt -= len; 174934b664a2SJames Hogan } 175034b664a2SJames Hogan } else 175134b664a2SJames Hogan #endif 175234b664a2SJames Hogan { 175334b664a2SJames Hogan u16 *pdata = buf; 175434b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 17554e0a5adfSJaehoon Chung *pdata++ = mci_readw(host, DATA(host->data_offset)); 175634b664a2SJames Hogan buf = pdata; 175734b664a2SJames Hogan } 175834b664a2SJames Hogan if (cnt) { 17594e0a5adfSJaehoon Chung host->part_buf16 = mci_readw(host, DATA(host->data_offset)); 176034b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1761f95f3850SWill Newton } 1762f95f3850SWill Newton } 1763f95f3850SWill Newton 1764f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1765f95f3850SWill Newton { 1766cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1767cfbeb59cSMarkos Chandras int init_cnt = cnt; 1768cfbeb59cSMarkos Chandras 176934b664a2SJames Hogan /* try and push anything in the part_buf */ 177034b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 177134b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 177234b664a2SJames Hogan buf += len; 177334b664a2SJames Hogan cnt -= len; 1774cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 17754e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 17764e0a5adfSJaehoon Chung host->part_buf32); 177734b664a2SJames Hogan host->part_buf_count = 0; 177834b664a2SJames Hogan } 177934b664a2SJames Hogan } 178034b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 178134b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 178234b664a2SJames Hogan while (cnt >= 4) { 178334b664a2SJames Hogan u32 aligned_buf[32]; 178434b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 178534b664a2SJames Hogan int items = len >> 2; 178634b664a2SJames Hogan int i; 178734b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 178834b664a2SJames Hogan memcpy(aligned_buf, buf, len); 178934b664a2SJames Hogan buf += len; 179034b664a2SJames Hogan cnt -= len; 179134b664a2SJames Hogan /* push data from aligned buffer into fifo */ 179234b664a2SJames Hogan for (i = 0; i < items; ++i) 17934e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 17944e0a5adfSJaehoon Chung aligned_buf[i]); 179534b664a2SJames Hogan } 179634b664a2SJames Hogan } else 179734b664a2SJames Hogan #endif 179834b664a2SJames Hogan { 179934b664a2SJames Hogan u32 *pdata = buf; 180034b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 18014e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), *pdata++); 180234b664a2SJames Hogan buf = pdata; 180334b664a2SJames Hogan } 180434b664a2SJames Hogan /* put anything remaining in the part_buf */ 180534b664a2SJames Hogan if (cnt) { 180634b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1807cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1808cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1809cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 18104e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18114e0a5adfSJaehoon Chung host->part_buf32); 1812f95f3850SWill Newton } 1813f95f3850SWill Newton } 1814f95f3850SWill Newton 1815f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1816f95f3850SWill Newton { 181734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 181834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 181934b664a2SJames Hogan while (cnt >= 4) { 182034b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 182134b664a2SJames Hogan u32 aligned_buf[32]; 182234b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 182334b664a2SJames Hogan int items = len >> 2; 182434b664a2SJames Hogan int i; 182534b664a2SJames Hogan for (i = 0; i < items; ++i) 18264e0a5adfSJaehoon Chung aligned_buf[i] = mci_readl(host, 18274e0a5adfSJaehoon Chung DATA(host->data_offset)); 182834b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 182934b664a2SJames Hogan memcpy(buf, aligned_buf, len); 183034b664a2SJames Hogan buf += len; 183134b664a2SJames Hogan cnt -= len; 183234b664a2SJames Hogan } 183334b664a2SJames Hogan } else 183434b664a2SJames Hogan #endif 183534b664a2SJames Hogan { 183634b664a2SJames Hogan u32 *pdata = buf; 183734b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 18384e0a5adfSJaehoon Chung *pdata++ = mci_readl(host, DATA(host->data_offset)); 183934b664a2SJames Hogan buf = pdata; 184034b664a2SJames Hogan } 184134b664a2SJames Hogan if (cnt) { 18424e0a5adfSJaehoon Chung host->part_buf32 = mci_readl(host, DATA(host->data_offset)); 184334b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1844f95f3850SWill Newton } 1845f95f3850SWill Newton } 1846f95f3850SWill Newton 1847f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1848f95f3850SWill Newton { 1849cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1850cfbeb59cSMarkos Chandras int init_cnt = cnt; 1851cfbeb59cSMarkos Chandras 185234b664a2SJames Hogan /* try and push anything in the part_buf */ 185334b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 185434b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 185534b664a2SJames Hogan buf += len; 185634b664a2SJames Hogan cnt -= len; 1857c09fbd74SSeungwon Jeon 1858cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 1859c09fbd74SSeungwon Jeon mci_writeq(host, DATA(host->data_offset), 18604e0a5adfSJaehoon Chung host->part_buf); 186134b664a2SJames Hogan host->part_buf_count = 0; 186234b664a2SJames Hogan } 186334b664a2SJames Hogan } 186434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 186534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 186634b664a2SJames Hogan while (cnt >= 8) { 186734b664a2SJames Hogan u64 aligned_buf[16]; 186834b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 186934b664a2SJames Hogan int items = len >> 3; 187034b664a2SJames Hogan int i; 187134b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 187234b664a2SJames Hogan memcpy(aligned_buf, buf, len); 187334b664a2SJames Hogan buf += len; 187434b664a2SJames Hogan cnt -= len; 187534b664a2SJames Hogan /* push data from aligned buffer into fifo */ 187634b664a2SJames Hogan for (i = 0; i < items; ++i) 18774e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), 18784e0a5adfSJaehoon Chung aligned_buf[i]); 187934b664a2SJames Hogan } 188034b664a2SJames Hogan } else 188134b664a2SJames Hogan #endif 188234b664a2SJames Hogan { 188334b664a2SJames Hogan u64 *pdata = buf; 188434b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 18854e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), *pdata++); 188634b664a2SJames Hogan buf = pdata; 188734b664a2SJames Hogan } 188834b664a2SJames Hogan /* put anything remaining in the part_buf */ 188934b664a2SJames Hogan if (cnt) { 189034b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1891cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1892cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1893cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 18944e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), 18954e0a5adfSJaehoon Chung host->part_buf); 1896f95f3850SWill Newton } 1897f95f3850SWill Newton } 1898f95f3850SWill Newton 1899f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1900f95f3850SWill Newton { 190134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 190234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 190334b664a2SJames Hogan while (cnt >= 8) { 190434b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 190534b664a2SJames Hogan u64 aligned_buf[16]; 190634b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 190734b664a2SJames Hogan int items = len >> 3; 190834b664a2SJames Hogan int i; 190934b664a2SJames Hogan for (i = 0; i < items; ++i) 19104e0a5adfSJaehoon Chung aligned_buf[i] = mci_readq(host, 19114e0a5adfSJaehoon Chung DATA(host->data_offset)); 191234b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 191334b664a2SJames Hogan memcpy(buf, aligned_buf, len); 191434b664a2SJames Hogan buf += len; 191534b664a2SJames Hogan cnt -= len; 1916f95f3850SWill Newton } 191734b664a2SJames Hogan } else 191834b664a2SJames Hogan #endif 191934b664a2SJames Hogan { 192034b664a2SJames Hogan u64 *pdata = buf; 192134b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 19224e0a5adfSJaehoon Chung *pdata++ = mci_readq(host, DATA(host->data_offset)); 192334b664a2SJames Hogan buf = pdata; 192434b664a2SJames Hogan } 192534b664a2SJames Hogan if (cnt) { 19264e0a5adfSJaehoon Chung host->part_buf = mci_readq(host, DATA(host->data_offset)); 192734b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 192834b664a2SJames Hogan } 192934b664a2SJames Hogan } 193034b664a2SJames Hogan 193134b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 193234b664a2SJames Hogan { 193334b664a2SJames Hogan int len; 193434b664a2SJames Hogan 193534b664a2SJames Hogan /* get remaining partial bytes */ 193634b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 193734b664a2SJames Hogan if (unlikely(len == cnt)) 193834b664a2SJames Hogan return; 193934b664a2SJames Hogan buf += len; 194034b664a2SJames Hogan cnt -= len; 194134b664a2SJames Hogan 194234b664a2SJames Hogan /* get the rest of the data */ 194334b664a2SJames Hogan host->pull_data(host, buf, cnt); 1944f95f3850SWill Newton } 1945f95f3850SWill Newton 194687a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 1947f95f3850SWill Newton { 1948f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 1949f9c2a0dcSSeungwon Jeon void *buf; 1950f9c2a0dcSSeungwon Jeon unsigned int offset; 1951f95f3850SWill Newton struct mmc_data *data = host->data; 1952f95f3850SWill Newton int shift = host->data_shift; 1953f95f3850SWill Newton u32 status; 19543e4b0d8bSMarkos Chandras unsigned int len; 1955f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 1956f95f3850SWill Newton 1957f95f3850SWill Newton do { 1958f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 1959f9c2a0dcSSeungwon Jeon goto done; 1960f95f3850SWill Newton 19614225fc85SImre Deak host->sg = sg_miter->piter.sg; 1962f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 1963f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 1964f9c2a0dcSSeungwon Jeon offset = 0; 1965f9c2a0dcSSeungwon Jeon 1966f9c2a0dcSSeungwon Jeon do { 1967f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 1968f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 1969f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 1970f9c2a0dcSSeungwon Jeon if (!len) 1971f9c2a0dcSSeungwon Jeon break; 1972f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 19733e4b0d8bSMarkos Chandras data->bytes_xfered += len; 1974f95f3850SWill Newton offset += len; 1975f9c2a0dcSSeungwon Jeon remain -= len; 1976f9c2a0dcSSeungwon Jeon } while (remain); 1977f95f3850SWill Newton 1978e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 1979f95f3850SWill Newton status = mci_readl(host, MINTSTS); 1980f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 198187a74d39SKyoungil Kim /* if the RXDR is ready read again */ 198287a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 198387a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 1984f9c2a0dcSSeungwon Jeon 1985f9c2a0dcSSeungwon Jeon if (!remain) { 1986f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 1987f9c2a0dcSSeungwon Jeon goto done; 1988f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 1989f9c2a0dcSSeungwon Jeon } 1990f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 1991f95f3850SWill Newton return; 1992f95f3850SWill Newton 1993f95f3850SWill Newton done: 1994f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 1995f9c2a0dcSSeungwon Jeon host->sg = NULL; 1996f95f3850SWill Newton smp_wmb(); 1997f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1998f95f3850SWill Newton } 1999f95f3850SWill Newton 2000f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2001f95f3850SWill Newton { 2002f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2003f9c2a0dcSSeungwon Jeon void *buf; 2004f9c2a0dcSSeungwon Jeon unsigned int offset; 2005f95f3850SWill Newton struct mmc_data *data = host->data; 2006f95f3850SWill Newton int shift = host->data_shift; 2007f95f3850SWill Newton u32 status; 20083e4b0d8bSMarkos Chandras unsigned int len; 2009f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2010f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2011f95f3850SWill Newton 2012f95f3850SWill Newton do { 2013f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2014f9c2a0dcSSeungwon Jeon goto done; 2015f95f3850SWill Newton 20164225fc85SImre Deak host->sg = sg_miter->piter.sg; 2017f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2018f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2019f9c2a0dcSSeungwon Jeon offset = 0; 2020f9c2a0dcSSeungwon Jeon 2021f9c2a0dcSSeungwon Jeon do { 2022f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2023f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2024f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2025f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2026f9c2a0dcSSeungwon Jeon if (!len) 2027f9c2a0dcSSeungwon Jeon break; 2028f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 20293e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2030f95f3850SWill Newton offset += len; 2031f9c2a0dcSSeungwon Jeon remain -= len; 2032f9c2a0dcSSeungwon Jeon } while (remain); 2033f95f3850SWill Newton 2034e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2035f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2036f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2037f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2038f9c2a0dcSSeungwon Jeon 2039f9c2a0dcSSeungwon Jeon if (!remain) { 2040f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2041f9c2a0dcSSeungwon Jeon goto done; 2042f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2043f9c2a0dcSSeungwon Jeon } 2044f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2045f95f3850SWill Newton return; 2046f95f3850SWill Newton 2047f95f3850SWill Newton done: 2048f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2049f9c2a0dcSSeungwon Jeon host->sg = NULL; 2050f95f3850SWill Newton smp_wmb(); 2051f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2052f95f3850SWill Newton } 2053f95f3850SWill Newton 2054f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2055f95f3850SWill Newton { 2056f95f3850SWill Newton if (!host->cmd_status) 2057f95f3850SWill Newton host->cmd_status = status; 2058f95f3850SWill Newton 2059f95f3850SWill Newton smp_wmb(); 2060f95f3850SWill Newton 2061f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2062f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2063f95f3850SWill Newton } 2064f95f3850SWill Newton 20656130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 20666130e7a9SDoug Anderson { 20676130e7a9SDoug Anderson int i; 20686130e7a9SDoug Anderson 20696130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 20706130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 20716130e7a9SDoug Anderson 20726130e7a9SDoug Anderson if (!slot) 20736130e7a9SDoug Anderson continue; 20746130e7a9SDoug Anderson 20756130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 20766130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 20776130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 20786130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 20796130e7a9SDoug Anderson } 20806130e7a9SDoug Anderson } 20816130e7a9SDoug Anderson 2082f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2083f95f3850SWill Newton { 2084f95f3850SWill Newton struct dw_mci *host = dev_id; 2085182c9081SSeungwon Jeon u32 pending; 20861a5c8e1fSShashidhar Hiremath int i; 2087f95f3850SWill Newton 2088f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2089f95f3850SWill Newton 2090f95f3850SWill Newton /* 2091f95f3850SWill Newton * DTO fix - version 2.10a and below, and only if internal DMA 2092f95f3850SWill Newton * is configured. 2093f95f3850SWill Newton */ 2094f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 2095f95f3850SWill Newton if (!pending && 2096f95f3850SWill Newton ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 2097f95f3850SWill Newton pending |= SDMMC_INT_DATA_OVER; 2098f95f3850SWill Newton } 2099f95f3850SWill Newton 2100476d79f1SDoug Anderson if (pending) { 210101730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 210201730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 210301730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 210401730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 210501730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 210601730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 210701730558SDoug Anderson } 210801730558SDoug Anderson 2109f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2110f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2111182c9081SSeungwon Jeon host->cmd_status = pending; 2112f95f3850SWill Newton smp_wmb(); 2113f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2114f95f3850SWill Newton } 2115f95f3850SWill Newton 2116f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2117f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2118f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2119182c9081SSeungwon Jeon host->data_status = pending; 2120f95f3850SWill Newton smp_wmb(); 2121f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2122f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2123f95f3850SWill Newton } 2124f95f3850SWill Newton 2125f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 2126f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2127f95f3850SWill Newton if (!host->data_status) 2128182c9081SSeungwon Jeon host->data_status = pending; 2129f95f3850SWill Newton smp_wmb(); 2130f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2131f95f3850SWill Newton if (host->sg != NULL) 213287a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2133f95f3850SWill Newton } 2134f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2135f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2136f95f3850SWill Newton } 2137f95f3850SWill Newton 2138f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2139f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2140b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 214187a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2142f95f3850SWill Newton } 2143f95f3850SWill Newton 2144f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2145f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2146b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2147f95f3850SWill Newton dw_mci_write_data_pio(host); 2148f95f3850SWill Newton } 2149f95f3850SWill Newton 2150f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2151f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2152182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2153f95f3850SWill Newton } 2154f95f3850SWill Newton 2155f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2156f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 21576130e7a9SDoug Anderson dw_mci_handle_cd(host); 2158f95f3850SWill Newton } 2159f95f3850SWill Newton 21601a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 21611a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 21621a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 216376756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 216476756234SAddy Ke mci_writel(host, RINTSTS, 216576756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 21661a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 21671a5c8e1fSShashidhar Hiremath } 21681a5c8e1fSShashidhar Hiremath } 21691a5c8e1fSShashidhar Hiremath 21701fb5f68aSMarkos Chandras } 2171f95f3850SWill Newton 2172f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2173f95f3850SWill Newton /* Handle DMA interrupts */ 217469d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 217569d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 217669d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 217769d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 217869d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 217969d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 218069d99fdcSPrabu Thangamuthu host->dma_ops->complete(host); 218169d99fdcSPrabu Thangamuthu } 218269d99fdcSPrabu Thangamuthu } else { 2183f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2184f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 218569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 218669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2187f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2188f95f3850SWill Newton host->dma_ops->complete(host); 2189f95f3850SWill Newton } 219069d99fdcSPrabu Thangamuthu } 2191f95f3850SWill Newton #endif 2192f95f3850SWill Newton 2193f95f3850SWill Newton return IRQ_HANDLED; 2194f95f3850SWill Newton } 2195f95f3850SWill Newton 2196c91eab4bSThomas Abraham #ifdef CONFIG_OF 2197c91eab4bSThomas Abraham /* given a slot id, find out the device node representing that slot */ 2198c91eab4bSThomas Abraham static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 2199c91eab4bSThomas Abraham { 2200c91eab4bSThomas Abraham struct device_node *np; 2201c91eab4bSThomas Abraham const __be32 *addr; 2202c91eab4bSThomas Abraham int len; 2203c91eab4bSThomas Abraham 2204c91eab4bSThomas Abraham if (!dev || !dev->of_node) 2205c91eab4bSThomas Abraham return NULL; 2206c91eab4bSThomas Abraham 2207c91eab4bSThomas Abraham for_each_child_of_node(dev->of_node, np) { 2208c91eab4bSThomas Abraham addr = of_get_property(np, "reg", &len); 2209c91eab4bSThomas Abraham if (!addr || (len < sizeof(int))) 2210c91eab4bSThomas Abraham continue; 2211c91eab4bSThomas Abraham if (be32_to_cpup(addr) == slot) 2212c91eab4bSThomas Abraham return np; 2213c91eab4bSThomas Abraham } 2214c91eab4bSThomas Abraham return NULL; 2215c91eab4bSThomas Abraham } 2216c91eab4bSThomas Abraham 2217a70aaa64SDoug Anderson static struct dw_mci_of_slot_quirks { 2218a70aaa64SDoug Anderson char *quirk; 2219a70aaa64SDoug Anderson int id; 2220a70aaa64SDoug Anderson } of_slot_quirks[] = { 2221a70aaa64SDoug Anderson { 2222a70aaa64SDoug Anderson .quirk = "disable-wp", 2223a70aaa64SDoug Anderson .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, 2224a70aaa64SDoug Anderson }, 2225a70aaa64SDoug Anderson }; 2226a70aaa64SDoug Anderson 2227a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2228a70aaa64SDoug Anderson { 2229a70aaa64SDoug Anderson struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 2230a70aaa64SDoug Anderson int quirks = 0; 2231a70aaa64SDoug Anderson int idx; 2232a70aaa64SDoug Anderson 2233a70aaa64SDoug Anderson /* get quirks */ 2234a70aaa64SDoug Anderson for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) 223526375b5cSJaehoon Chung if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) { 223626375b5cSJaehoon Chung dev_warn(dev, "Slot quirk %s is deprecated\n", 223726375b5cSJaehoon Chung of_slot_quirks[idx].quirk); 2238a70aaa64SDoug Anderson quirks |= of_slot_quirks[idx].id; 223926375b5cSJaehoon Chung } 2240a70aaa64SDoug Anderson 2241a70aaa64SDoug Anderson return quirks; 2242a70aaa64SDoug Anderson } 2243c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2244a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2245a70aaa64SDoug Anderson { 2246a70aaa64SDoug Anderson return 0; 2247a70aaa64SDoug Anderson } 2248c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2249c91eab4bSThomas Abraham 225036c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2251f95f3850SWill Newton { 2252f95f3850SWill Newton struct mmc_host *mmc; 2253f95f3850SWill Newton struct dw_mci_slot *slot; 2254e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2255800d78bfSThomas Abraham int ctrl_id, ret; 22561f44a2a5SSeungwon Jeon u32 freq[2]; 2257f95f3850SWill Newton 22584a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2259f95f3850SWill Newton if (!mmc) 2260f95f3850SWill Newton return -ENOMEM; 2261f95f3850SWill Newton 2262f95f3850SWill Newton slot = mmc_priv(mmc); 2263f95f3850SWill Newton slot->id = id; 226476756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2265f95f3850SWill Newton slot->mmc = mmc; 2266f95f3850SWill Newton slot->host = host; 2267c91eab4bSThomas Abraham host->slot[id] = slot; 2268f95f3850SWill Newton 2269a70aaa64SDoug Anderson slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); 2270a70aaa64SDoug Anderson 2271f95f3850SWill Newton mmc->ops = &dw_mci_ops; 22721f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 22731f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 22741f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 22751f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 22761f44a2a5SSeungwon Jeon } else { 22771f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 22781f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 22791f44a2a5SSeungwon Jeon } 2280f95f3850SWill Newton 228151da2240SYuvaraj CD /*if there are external regulators, get them*/ 228251da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 228351da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 22843cf890fcSDoug Anderson goto err_host_allocated; 228551da2240SYuvaraj CD 228651da2240SYuvaraj CD if (!mmc->ocr_avail) 2287f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2288f95f3850SWill Newton 2289fc3d7720SJaehoon Chung if (host->pdata->caps) 2290fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2291fc3d7720SJaehoon Chung 2292ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2293ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2294ab269128SAbhilash Kesavan 2295800d78bfSThomas Abraham if (host->dev->of_node) { 2296800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2297800d78bfSThomas Abraham if (ctrl_id < 0) 2298800d78bfSThomas Abraham ctrl_id = 0; 2299800d78bfSThomas Abraham } else { 2300800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2301800d78bfSThomas Abraham } 2302cb27a843SJames Hogan if (drv_data && drv_data->caps) 2303cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2304800d78bfSThomas Abraham 23054f408cc6SSeungwon Jeon if (host->pdata->caps2) 23064f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 23074f408cc6SSeungwon Jeon 23083cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 23093cf890fcSDoug Anderson if (ret) 23103cf890fcSDoug Anderson goto err_host_allocated; 2311f95f3850SWill Newton 2312f95f3850SWill Newton if (host->pdata->blk_settings) { 2313f95f3850SWill Newton mmc->max_segs = host->pdata->blk_settings->max_segs; 2314f95f3850SWill Newton mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 2315f95f3850SWill Newton mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 2316f95f3850SWill Newton mmc->max_req_size = host->pdata->blk_settings->max_req_size; 2317f95f3850SWill Newton mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 2318f95f3850SWill Newton } else { 2319f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 2320a39e5746SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 2321a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2322a39e5746SJaehoon Chung mmc->max_blk_size = 65536; 2323a39e5746SJaehoon Chung mmc->max_blk_count = host->ring_size; 2324a39e5746SJaehoon Chung mmc->max_seg_size = 0x1000; 2325a39e5746SJaehoon Chung mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; 2326a39e5746SJaehoon Chung #else 2327f95f3850SWill Newton mmc->max_segs = 64; 2328f95f3850SWill Newton mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2329f95f3850SWill Newton mmc->max_blk_count = 512; 2330f95f3850SWill Newton mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2331f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2332f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 2333a39e5746SJaehoon Chung } 2334f95f3850SWill Newton 2335ae0eb348SJaehoon Chung if (dw_mci_get_cd(mmc)) 2336ae0eb348SJaehoon Chung set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2337ae0eb348SJaehoon Chung else 2338ae0eb348SJaehoon Chung clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2339ae0eb348SJaehoon Chung 23400cea529dSJaehoon Chung ret = mmc_add_host(mmc); 23410cea529dSJaehoon Chung if (ret) 23423cf890fcSDoug Anderson goto err_host_allocated; 2343f95f3850SWill Newton 2344f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2345f95f3850SWill Newton dw_mci_init_debugfs(slot); 2346f95f3850SWill Newton #endif 2347f95f3850SWill Newton 2348f95f3850SWill Newton return 0; 2349800d78bfSThomas Abraham 23503cf890fcSDoug Anderson err_host_allocated: 2351800d78bfSThomas Abraham mmc_free_host(mmc); 235251da2240SYuvaraj CD return ret; 2353f95f3850SWill Newton } 2354f95f3850SWill Newton 2355f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2356f95f3850SWill Newton { 2357f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2358f95f3850SWill Newton mmc_remove_host(slot->mmc); 2359f95f3850SWill Newton slot->host->slot[id] = NULL; 2360f95f3850SWill Newton mmc_free_host(slot->mmc); 2361f95f3850SWill Newton } 2362f95f3850SWill Newton 2363f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2364f95f3850SWill Newton { 236569d99fdcSPrabu Thangamuthu int addr_config; 236669d99fdcSPrabu Thangamuthu /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */ 236769d99fdcSPrabu Thangamuthu addr_config = (mci_readl(host, HCON) >> 27) & 0x01; 236869d99fdcSPrabu Thangamuthu 236969d99fdcSPrabu Thangamuthu if (addr_config == 1) { 237069d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 237169d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 237269d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 64-bit address mode.\n"); 237369d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 237469d99fdcSPrabu Thangamuthu dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64)); 237569d99fdcSPrabu Thangamuthu } else { 237669d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 237769d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 237869d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 32-bit address mode.\n"); 237969d99fdcSPrabu Thangamuthu } 238069d99fdcSPrabu Thangamuthu 2381f95f3850SWill Newton /* Alloc memory for sg translation */ 2382780f22afSSeungwon Jeon host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2383f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2384f95f3850SWill Newton if (!host->sg_cpu) { 23854a90920cSThomas Abraham dev_err(host->dev, "%s: could not alloc DMA memory\n", 2386f95f3850SWill Newton __func__); 2387f95f3850SWill Newton goto no_dma; 2388f95f3850SWill Newton } 2389f95f3850SWill Newton 2390f95f3850SWill Newton /* Determine which DMA interface to use */ 2391f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2392f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 239300956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 2394f95f3850SWill Newton #endif 2395f95f3850SWill Newton 2396f95f3850SWill Newton if (!host->dma_ops) 2397f95f3850SWill Newton goto no_dma; 2398f95f3850SWill Newton 2399e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2400e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2401f95f3850SWill Newton if (host->dma_ops->init(host)) { 24024a90920cSThomas Abraham dev_err(host->dev, "%s: Unable to initialize " 2403f95f3850SWill Newton "DMA Controller.\n", __func__); 2404f95f3850SWill Newton goto no_dma; 2405f95f3850SWill Newton } 2406f95f3850SWill Newton } else { 24074a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2408f95f3850SWill Newton goto no_dma; 2409f95f3850SWill Newton } 2410f95f3850SWill Newton 2411f95f3850SWill Newton host->use_dma = 1; 2412f95f3850SWill Newton return; 2413f95f3850SWill Newton 2414f95f3850SWill Newton no_dma: 24154a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 2416f95f3850SWill Newton host->use_dma = 0; 2417f95f3850SWill Newton return; 2418f95f3850SWill Newton } 2419f95f3850SWill Newton 242031bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2421f95f3850SWill Newton { 2422f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 242331bff450SSeungwon Jeon u32 ctrl; 2424f95f3850SWill Newton 242531bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 242631bff450SSeungwon Jeon ctrl |= reset; 242731bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2428f95f3850SWill Newton 2429f95f3850SWill Newton /* wait till resets clear */ 2430f95f3850SWill Newton do { 2431f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 243231bff450SSeungwon Jeon if (!(ctrl & reset)) 2433f95f3850SWill Newton return true; 2434f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2435f95f3850SWill Newton 243631bff450SSeungwon Jeon dev_err(host->dev, 243731bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 243831bff450SSeungwon Jeon ctrl & reset); 2439f95f3850SWill Newton 2440f95f3850SWill Newton return false; 2441f95f3850SWill Newton } 2442f95f3850SWill Newton 24433a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 244431bff450SSeungwon Jeon { 24453a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 24463a33a94cSSonny Rao bool ret = false; 24473a33a94cSSonny Rao 244831bff450SSeungwon Jeon /* 244931bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 245031bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 245131bff450SSeungwon Jeon */ 245231bff450SSeungwon Jeon if (host->sg) { 245331bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 245431bff450SSeungwon Jeon host->sg = NULL; 245531bff450SSeungwon Jeon } 245631bff450SSeungwon Jeon 24573a33a94cSSonny Rao if (host->use_dma) 24583a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 24593a33a94cSSonny Rao 24603a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 24613a33a94cSSonny Rao /* 24623a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 24633a33a94cSSonny Rao * interrupts. 24643a33a94cSSonny Rao */ 24653a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 24663a33a94cSSonny Rao 24673a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 24683a33a94cSSonny Rao if (host->use_dma) { 24693a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 24703a33a94cSSonny Rao u32 status; 24713a33a94cSSonny Rao do { 24723a33a94cSSonny Rao status = mci_readl(host, STATUS); 24733a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 24743a33a94cSSonny Rao break; 24753a33a94cSSonny Rao cpu_relax(); 24763a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 24773a33a94cSSonny Rao 24783a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 24793a33a94cSSonny Rao dev_err(host->dev, 24803a33a94cSSonny Rao "%s: Timeout waiting for dma_req to " 24813a33a94cSSonny Rao "clear during reset\n", __func__); 24823a33a94cSSonny Rao goto ciu_out; 248331bff450SSeungwon Jeon } 248431bff450SSeungwon Jeon 24853a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 24863a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 24873a33a94cSSonny Rao goto ciu_out; 24883a33a94cSSonny Rao } 24893a33a94cSSonny Rao } else { 24903a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 24913a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 24923a33a94cSSonny Rao dev_err(host->dev, "%s: fifo/dma reset bits didn't " 24933a33a94cSSonny Rao "clear but ciu was reset, doing clock update\n", 24943a33a94cSSonny Rao __func__); 24953a33a94cSSonny Rao goto ciu_out; 24963a33a94cSSonny Rao } 24973a33a94cSSonny Rao } 24983a33a94cSSonny Rao 24993a33a94cSSonny Rao #if IS_ENABLED(CONFIG_MMC_DW_IDMAC) 25003a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 25013a33a94cSSonny Rao dw_mci_idmac_reset(host); 25023a33a94cSSonny Rao #endif 25033a33a94cSSonny Rao 25043a33a94cSSonny Rao ret = true; 25053a33a94cSSonny Rao 25063a33a94cSSonny Rao ciu_out: 25073a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 25083a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 25093a33a94cSSonny Rao 25103a33a94cSSonny Rao return ret; 251131bff450SSeungwon Jeon } 251231bff450SSeungwon Jeon 2513c91eab4bSThomas Abraham #ifdef CONFIG_OF 2514c91eab4bSThomas Abraham static struct dw_mci_of_quirks { 2515c91eab4bSThomas Abraham char *quirk; 2516c91eab4bSThomas Abraham int id; 2517c91eab4bSThomas Abraham } of_quirks[] = { 2518c91eab4bSThomas Abraham { 2519c91eab4bSThomas Abraham .quirk = "broken-cd", 2520c91eab4bSThomas Abraham .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 252126375b5cSJaehoon Chung }, { 252226375b5cSJaehoon Chung .quirk = "disable-wp", 252326375b5cSJaehoon Chung .id = DW_MCI_QUIRK_NO_WRITE_PROTECT, 2524c91eab4bSThomas Abraham }, 2525c91eab4bSThomas Abraham }; 2526c91eab4bSThomas Abraham 2527c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2528c91eab4bSThomas Abraham { 2529c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2530c91eab4bSThomas Abraham struct device *dev = host->dev; 2531c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2532e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2533800d78bfSThomas Abraham int idx, ret; 25343c6d89eaSDoug Anderson u32 clock_frequency; 2535c91eab4bSThomas Abraham 2536c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2537c91eab4bSThomas Abraham if (!pdata) { 2538c91eab4bSThomas Abraham dev_err(dev, "could not allocate memory for pdata\n"); 2539c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2540c91eab4bSThomas Abraham } 2541c91eab4bSThomas Abraham 2542c91eab4bSThomas Abraham /* find out number of slots supported */ 2543c91eab4bSThomas Abraham if (of_property_read_u32(dev->of_node, "num-slots", 2544c91eab4bSThomas Abraham &pdata->num_slots)) { 2545c91eab4bSThomas Abraham dev_info(dev, "num-slots property not found, " 2546c91eab4bSThomas Abraham "assuming 1 slot is available\n"); 2547c91eab4bSThomas Abraham pdata->num_slots = 1; 2548c91eab4bSThomas Abraham } 2549c91eab4bSThomas Abraham 2550c91eab4bSThomas Abraham /* get quirks */ 2551c91eab4bSThomas Abraham for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2552c91eab4bSThomas Abraham if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2553c91eab4bSThomas Abraham pdata->quirks |= of_quirks[idx].id; 2554c91eab4bSThomas Abraham 2555c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2556c91eab4bSThomas Abraham dev_info(dev, "fifo-depth property not found, using " 2557c91eab4bSThomas Abraham "value of FIFOTH register as default\n"); 2558c91eab4bSThomas Abraham 2559c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2560c91eab4bSThomas Abraham 25613c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 25623c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 25633c6d89eaSDoug Anderson 2564cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2565cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2566800d78bfSThomas Abraham if (ret) 2567800d78bfSThomas Abraham return ERR_PTR(ret); 2568800d78bfSThomas Abraham } 2569800d78bfSThomas Abraham 257010b49841SSeungwon Jeon if (of_find_property(np, "supports-highspeed", NULL)) 257110b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 257210b49841SSeungwon Jeon 2573c91eab4bSThomas Abraham return pdata; 2574c91eab4bSThomas Abraham } 2575c91eab4bSThomas Abraham 2576c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2577c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2578c91eab4bSThomas Abraham { 2579c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2580c91eab4bSThomas Abraham } 2581c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2582c91eab4bSThomas Abraham 258362ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 2584f95f3850SWill Newton { 2585e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 258662ca8034SShashidhar Hiremath int width, i, ret = 0; 2587f95f3850SWill Newton u32 fifo_size; 25881c2215b7SThomas Abraham int init_slots = 0; 2589f95f3850SWill Newton 2590c91eab4bSThomas Abraham if (!host->pdata) { 2591c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 2592c91eab4bSThomas Abraham if (IS_ERR(host->pdata)) { 2593c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 2594c91eab4bSThomas Abraham return -EINVAL; 2595c91eab4bSThomas Abraham } 2596f95f3850SWill Newton } 2597f95f3850SWill Newton 2598907abd51SJaehoon Chung if (host->pdata->num_slots > 1) { 25994a90920cSThomas Abraham dev_err(host->dev, 2600907abd51SJaehoon Chung "Platform data must supply num_slots.\n"); 260162ca8034SShashidhar Hiremath return -ENODEV; 2602f95f3850SWill Newton } 2603f95f3850SWill Newton 2604780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 2605f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 2606f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 2607f90a0612SThomas Abraham } else { 2608f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 2609f90a0612SThomas Abraham if (ret) { 2610f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 2611f90a0612SThomas Abraham return ret; 2612f90a0612SThomas Abraham } 2613f95f3850SWill Newton } 2614f95f3850SWill Newton 2615780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2616f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 2617f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 26183c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 2619f90a0612SThomas Abraham } else { 2620f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 2621f90a0612SThomas Abraham if (ret) { 2622f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 2623f90a0612SThomas Abraham goto err_clk_biu; 2624f90a0612SThomas Abraham } 2625f90a0612SThomas Abraham 26263c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 26273c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 26283c6d89eaSDoug Anderson if (ret) 26293c6d89eaSDoug Anderson dev_warn(host->dev, 2630612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 26313c6d89eaSDoug Anderson host->pdata->bus_hz); 26323c6d89eaSDoug Anderson } 2633f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 26343c6d89eaSDoug Anderson } 2635f90a0612SThomas Abraham 2636612de4c1SJaehoon Chung if (!host->bus_hz) { 2637612de4c1SJaehoon Chung dev_err(host->dev, 2638612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 2639612de4c1SJaehoon Chung ret = -ENODEV; 2640612de4c1SJaehoon Chung goto err_clk_ciu; 2641612de4c1SJaehoon Chung } 2642612de4c1SJaehoon Chung 2643002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 2644002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 2645002f0d5cSYuvaraj Kumar C D if (ret) { 2646002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 2647002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 2648002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 2649002f0d5cSYuvaraj Kumar C D } 2650002f0d5cSYuvaraj Kumar C D } 2651002f0d5cSYuvaraj Kumar C D 2652cb27a843SJames Hogan if (drv_data && drv_data->setup_clock) { 2653cb27a843SJames Hogan ret = drv_data->setup_clock(host); 2654800d78bfSThomas Abraham if (ret) { 2655800d78bfSThomas Abraham dev_err(host->dev, 2656800d78bfSThomas Abraham "implementation specific clock setup failed\n"); 2657800d78bfSThomas Abraham goto err_clk_ciu; 2658800d78bfSThomas Abraham } 2659800d78bfSThomas Abraham } 2660800d78bfSThomas Abraham 266162ca8034SShashidhar Hiremath host->quirks = host->pdata->quirks; 2662f95f3850SWill Newton 2663f95f3850SWill Newton spin_lock_init(&host->lock); 2664f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 2665f95f3850SWill Newton 2666f95f3850SWill Newton /* 2667f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 2668f95f3850SWill Newton * the correct values. 2669f95f3850SWill Newton */ 2670f95f3850SWill Newton i = (mci_readl(host, HCON) >> 7) & 0x7; 2671f95f3850SWill Newton if (!i) { 2672f95f3850SWill Newton host->push_data = dw_mci_push_data16; 2673f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 2674f95f3850SWill Newton width = 16; 2675f95f3850SWill Newton host->data_shift = 1; 2676f95f3850SWill Newton } else if (i == 2) { 2677f95f3850SWill Newton host->push_data = dw_mci_push_data64; 2678f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 2679f95f3850SWill Newton width = 64; 2680f95f3850SWill Newton host->data_shift = 3; 2681f95f3850SWill Newton } else { 2682f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 2683f95f3850SWill Newton WARN((i != 1), 2684f95f3850SWill Newton "HCON reports a reserved host data width!\n" 2685f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 2686f95f3850SWill Newton host->push_data = dw_mci_push_data32; 2687f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 2688f95f3850SWill Newton width = 32; 2689f95f3850SWill Newton host->data_shift = 2; 2690f95f3850SWill Newton } 2691f95f3850SWill Newton 2692f95f3850SWill Newton /* Reset all blocks */ 26933a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) 2694141a712aSSeungwon Jeon return -ENODEV; 2695141a712aSSeungwon Jeon 2696141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 2697141a712aSSeungwon Jeon dw_mci_init_dma(host); 2698f95f3850SWill Newton 2699f95f3850SWill Newton /* Clear the interrupts for the host controller */ 2700f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2701f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2702f95f3850SWill Newton 2703f95f3850SWill Newton /* Put in max timeout */ 2704f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 2705f95f3850SWill Newton 2706f95f3850SWill Newton /* 2707f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2708f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 2709f95f3850SWill Newton */ 2710b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 2711b86d8253SJames Hogan /* 2712b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2713b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 2714b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 2715b86d8253SJames Hogan * should put it in the platform data. 2716b86d8253SJames Hogan */ 2717f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 27188234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2719b86d8253SJames Hogan } else { 2720b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 2721b86d8253SJames Hogan } 2722b86d8253SJames Hogan host->fifo_depth = fifo_size; 272352426899SSeungwon Jeon host->fifoth_val = 272452426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 2725e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 2726f95f3850SWill Newton 2727f95f3850SWill Newton /* disable clock to CIU */ 2728f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2729f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2730f95f3850SWill Newton 273163008768SJames Hogan /* 273263008768SJames Hogan * In 2.40a spec, Data offset is changed. 273363008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 273463008768SJames Hogan */ 273563008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 273663008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 273763008768SJames Hogan 273863008768SJames Hogan if (host->verid < DW_MMC_240A) 273963008768SJames Hogan host->data_offset = DATA_OFFSET; 274063008768SJames Hogan else 274163008768SJames Hogan host->data_offset = DATA_240A_OFFSET; 274263008768SJames Hogan 2743f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2744780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2745780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 2746f95f3850SWill Newton if (ret) 27476130e7a9SDoug Anderson goto err_dmaunmap; 2748f95f3850SWill Newton 2749f95f3850SWill Newton if (host->pdata->num_slots) 2750f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 2751f95f3850SWill Newton else 2752f95f3850SWill Newton host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2753f95f3850SWill Newton 27542da1d7f2SYuvaraj CD /* 27552da1d7f2SYuvaraj CD * Enable interrupts for command done, data over, data empty, card det, 27562da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 27572da1d7f2SYuvaraj CD */ 27582da1d7f2SYuvaraj CD mci_writel(host, RINTSTS, 0xFFFFFFFF); 27592da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 27602da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 27612da1d7f2SYuvaraj CD DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 27622da1d7f2SYuvaraj CD mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 27632da1d7f2SYuvaraj CD 27642da1d7f2SYuvaraj CD dev_info(host->dev, "DW MMC controller at irq %d, " 27652da1d7f2SYuvaraj CD "%d bit host data width, " 27662da1d7f2SYuvaraj CD "%u deep fifo\n", 27672da1d7f2SYuvaraj CD host->irq, width, fifo_size); 27682da1d7f2SYuvaraj CD 2769f95f3850SWill Newton /* We need at least one slot to succeed */ 2770f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2771f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 27721c2215b7SThomas Abraham if (ret) 27731c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 27741c2215b7SThomas Abraham else 27751c2215b7SThomas Abraham init_slots++; 2776f95f3850SWill Newton } 27771c2215b7SThomas Abraham 27781c2215b7SThomas Abraham if (init_slots) { 27791c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 27801c2215b7SThomas Abraham } else { 27811c2215b7SThomas Abraham dev_dbg(host->dev, "attempted to initialize %d slots, " 27821c2215b7SThomas Abraham "but failed on all\n", host->num_slots); 27836130e7a9SDoug Anderson goto err_dmaunmap; 2784f95f3850SWill Newton } 2785f95f3850SWill Newton 2786f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 27874a90920cSThomas Abraham dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 2788f95f3850SWill Newton 2789f95f3850SWill Newton return 0; 2790f95f3850SWill Newton 2791f95f3850SWill Newton err_dmaunmap: 2792f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2793f95f3850SWill Newton host->dma_ops->exit(host); 2794f90a0612SThomas Abraham 2795f90a0612SThomas Abraham err_clk_ciu: 2796780f22afSSeungwon Jeon if (!IS_ERR(host->ciu_clk)) 2797f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2798780f22afSSeungwon Jeon 2799f90a0612SThomas Abraham err_clk_biu: 2800780f22afSSeungwon Jeon if (!IS_ERR(host->biu_clk)) 2801f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2802780f22afSSeungwon Jeon 2803f95f3850SWill Newton return ret; 2804f95f3850SWill Newton } 280562ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 2806f95f3850SWill Newton 280762ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 2808f95f3850SWill Newton { 2809f95f3850SWill Newton int i; 2810f95f3850SWill Newton 2811f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2812f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2813f95f3850SWill Newton 2814f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 28154a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 2816f95f3850SWill Newton if (host->slot[i]) 2817f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 2818f95f3850SWill Newton } 2819f95f3850SWill Newton 2820f95f3850SWill Newton /* disable clock to CIU */ 2821f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2822f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2823f95f3850SWill Newton 2824f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2825f95f3850SWill Newton host->dma_ops->exit(host); 2826f95f3850SWill Newton 2827f90a0612SThomas Abraham if (!IS_ERR(host->ciu_clk)) 2828f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2829780f22afSSeungwon Jeon 2830f90a0612SThomas Abraham if (!IS_ERR(host->biu_clk)) 2831f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2832f95f3850SWill Newton } 283362ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 283462ca8034SShashidhar Hiremath 283562ca8034SShashidhar Hiremath 2836f95f3850SWill Newton 28376fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 2838f95f3850SWill Newton /* 2839f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 2840f95f3850SWill Newton */ 284162ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 2842f95f3850SWill Newton { 2843f95f3850SWill Newton return 0; 2844f95f3850SWill Newton } 284562ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 2846f95f3850SWill Newton 284762ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 2848f95f3850SWill Newton { 2849f95f3850SWill Newton int i, ret; 2850f95f3850SWill Newton 28513a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 2852e61cf118SJaehoon Chung ret = -ENODEV; 2853e61cf118SJaehoon Chung return ret; 2854e61cf118SJaehoon Chung } 2855e61cf118SJaehoon Chung 28563bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 2857141a712aSSeungwon Jeon host->dma_ops->init(host); 2858141a712aSSeungwon Jeon 285952426899SSeungwon Jeon /* 286052426899SSeungwon Jeon * Restore the initial value at FIFOTH register 286152426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 286252426899SSeungwon Jeon */ 2863e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 286452426899SSeungwon Jeon host->prev_blksz = 0; 2865e61cf118SJaehoon Chung 28662eb2944fSDoug Anderson /* Put in max timeout */ 28672eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 28682eb2944fSDoug Anderson 2869e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 2870e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2871e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2872e61cf118SJaehoon Chung DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2873e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2874e61cf118SJaehoon Chung 2875f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2876f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 2877f95f3850SWill Newton if (!slot) 2878f95f3850SWill Newton continue; 2879ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 2880ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 2881ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 2882ab269128SAbhilash Kesavan } 2883f95f3850SWill Newton } 2884f95f3850SWill Newton return 0; 2885f95f3850SWill Newton } 288662ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 28876fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 28886fe8890dSJaehoon Chung 2889f95f3850SWill Newton static int __init dw_mci_init(void) 2890f95f3850SWill Newton { 28918e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 289262ca8034SShashidhar Hiremath return 0; 2893f95f3850SWill Newton } 2894f95f3850SWill Newton 2895f95f3850SWill Newton static void __exit dw_mci_exit(void) 2896f95f3850SWill Newton { 2897f95f3850SWill Newton } 2898f95f3850SWill Newton 2899f95f3850SWill Newton module_init(dw_mci_init); 2900f95f3850SWill Newton module_exit(dw_mci_exit); 2901f95f3850SWill Newton 2902f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 2903f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 2904f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 2905f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 2906