1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22b6d2d81cSShawn Lin #include <linux/iopoll.h> 23f95f3850SWill Newton #include <linux/ioport.h> 24f95f3850SWill Newton #include <linux/module.h> 25f95f3850SWill Newton #include <linux/platform_device.h> 26a6db2c86SDouglas Anderson #include <linux/pm_runtime.h> 27f95f3850SWill Newton #include <linux/seq_file.h> 28f95f3850SWill Newton #include <linux/slab.h> 29f95f3850SWill Newton #include <linux/stat.h> 30f95f3850SWill Newton #include <linux/delay.h> 31f95f3850SWill Newton #include <linux/irq.h> 32b24c8b26SDoug Anderson #include <linux/mmc/card.h> 33f95f3850SWill Newton #include <linux/mmc/host.h> 34f95f3850SWill Newton #include <linux/mmc/mmc.h> 3501730558SDoug Anderson #include <linux/mmc/sd.h> 3690c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 37f95f3850SWill Newton #include <linux/bitops.h> 38c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 39c91eab4bSThomas Abraham #include <linux/of.h> 4055a6ceb2SDoug Anderson #include <linux/of_gpio.h> 41bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 42f95f3850SWill Newton 43f95f3850SWill Newton #include "dw_mmc.h" 44f95f3850SWill Newton 45f95f3850SWill Newton /* Common flag combinations */ 463f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 47f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 487a3c5677SDoug Anderson SDMMC_INT_EBE | SDMMC_INT_HLE) 49f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 507a3c5677SDoug Anderson SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 51f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 527a3c5677SDoug Anderson DW_MCI_CMD_ERROR_FLAGS) 53f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 54f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 55f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 56f95f3850SWill Newton 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 5872e83577SJaehoon Chung #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 591f44a2a5SSeungwon Jeon 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 65cc190d4cSShawn Lin #define DESC_RING_BUF_SZ PAGE_SIZE 66cc190d4cSShawn Lin 6769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6869d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 69b6d2d81cSShawn Lin #define IDMAC_OWN_CLR64(x) \ 70b6d2d81cSShawn Lin !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 7169d99fdcSPrabu Thangamuthu 7269d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7569d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 766687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 776687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 8069d99fdcSPrabu Thangamuthu 8169d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 8269d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 8369d99fdcSPrabu Thangamuthu 8469d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8569d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8669d99fdcSPrabu Thangamuthu }; 8769d99fdcSPrabu Thangamuthu 88f95f3850SWill Newton struct idmac_desc { 896687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 90f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 91f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 92f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 93f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 94f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 95f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 96f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 97f95f3850SWill Newton 986687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 99f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 100e5306c3aSBen Dooks ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 101f95f3850SWill Newton 1026687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 103f95f3850SWill Newton 1046687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 105f95f3850SWill Newton }; 1065959b32eSAlexey Brodkin 1075959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1085959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 109f95f3850SWill Newton 110f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 111f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 112f95f3850SWill Newton { 113f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 114f95f3850SWill Newton struct mmc_request *mrq; 115f95f3850SWill Newton struct mmc_command *cmd; 116f95f3850SWill Newton struct mmc_command *stop; 117f95f3850SWill Newton struct mmc_data *data; 118f95f3850SWill Newton 119f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 120f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 121f95f3850SWill Newton mrq = slot->mrq; 122f95f3850SWill Newton 123f95f3850SWill Newton if (mrq) { 124f95f3850SWill Newton cmd = mrq->cmd; 125f95f3850SWill Newton data = mrq->data; 126f95f3850SWill Newton stop = mrq->stop; 127f95f3850SWill Newton 128f95f3850SWill Newton if (cmd) 129f95f3850SWill Newton seq_printf(s, 130f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 132f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 133f95f3850SWill Newton cmd->resp[2], cmd->error); 134f95f3850SWill Newton if (data) 135f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136f95f3850SWill Newton data->bytes_xfered, data->blocks, 137f95f3850SWill Newton data->blksz, data->flags, data->error); 138f95f3850SWill Newton if (stop) 139f95f3850SWill Newton seq_printf(s, 140f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 142f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 143f95f3850SWill Newton stop->resp[2], stop->error); 144f95f3850SWill Newton } 145f95f3850SWill Newton 146f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 147f95f3850SWill Newton 148f95f3850SWill Newton return 0; 149f95f3850SWill Newton } 150f95f3850SWill Newton 151f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 152f95f3850SWill Newton { 153f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 154f95f3850SWill Newton } 155f95f3850SWill Newton 156f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 157f95f3850SWill Newton .owner = THIS_MODULE, 158f95f3850SWill Newton .open = dw_mci_req_open, 159f95f3850SWill Newton .read = seq_read, 160f95f3850SWill Newton .llseek = seq_lseek, 161f95f3850SWill Newton .release = single_release, 162f95f3850SWill Newton }; 163f95f3850SWill Newton 164f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 165f95f3850SWill Newton { 16621657ebdSJaehoon Chung struct dw_mci *host = s->private; 16721657ebdSJaehoon Chung 16821657ebdSJaehoon Chung seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 16921657ebdSJaehoon Chung seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 17021657ebdSJaehoon Chung seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 17121657ebdSJaehoon Chung seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 17221657ebdSJaehoon Chung seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 17321657ebdSJaehoon Chung seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 174f95f3850SWill Newton 175f95f3850SWill Newton return 0; 176f95f3850SWill Newton } 177f95f3850SWill Newton 178f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 179f95f3850SWill Newton { 180f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 181f95f3850SWill Newton } 182f95f3850SWill Newton 183f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 184f95f3850SWill Newton .owner = THIS_MODULE, 185f95f3850SWill Newton .open = dw_mci_regs_open, 186f95f3850SWill Newton .read = seq_read, 187f95f3850SWill Newton .llseek = seq_lseek, 188f95f3850SWill Newton .release = single_release, 189f95f3850SWill Newton }; 190f95f3850SWill Newton 191f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 192f95f3850SWill Newton { 193f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 194f95f3850SWill Newton struct dw_mci *host = slot->host; 195f95f3850SWill Newton struct dentry *root; 196f95f3850SWill Newton struct dentry *node; 197f95f3850SWill Newton 198f95f3850SWill Newton root = mmc->debugfs_root; 199f95f3850SWill Newton if (!root) 200f95f3850SWill Newton return; 201f95f3850SWill Newton 202f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 203f95f3850SWill Newton &dw_mci_regs_fops); 204f95f3850SWill Newton if (!node) 205f95f3850SWill Newton goto err; 206f95f3850SWill Newton 207f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 208f95f3850SWill Newton &dw_mci_req_fops); 209f95f3850SWill Newton if (!node) 210f95f3850SWill Newton goto err; 211f95f3850SWill Newton 212f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 213f95f3850SWill Newton if (!node) 214f95f3850SWill Newton goto err; 215f95f3850SWill Newton 216f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 217f95f3850SWill Newton (u32 *)&host->pending_events); 218f95f3850SWill Newton if (!node) 219f95f3850SWill Newton goto err; 220f95f3850SWill Newton 221f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 222f95f3850SWill Newton (u32 *)&host->completed_events); 223f95f3850SWill Newton if (!node) 224f95f3850SWill Newton goto err; 225f95f3850SWill Newton 226f95f3850SWill Newton return; 227f95f3850SWill Newton 228f95f3850SWill Newton err: 229f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 230f95f3850SWill Newton } 231f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 232f95f3850SWill Newton 2338e6db1f6SShawn Lin static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2348e6db1f6SShawn Lin { 2358e6db1f6SShawn Lin u32 ctrl; 2368e6db1f6SShawn Lin 2378e6db1f6SShawn Lin ctrl = mci_readl(host, CTRL); 2388e6db1f6SShawn Lin ctrl |= reset; 2398e6db1f6SShawn Lin mci_writel(host, CTRL, ctrl); 2408e6db1f6SShawn Lin 2418e6db1f6SShawn Lin /* wait till resets clear */ 2428e6db1f6SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 2438e6db1f6SShawn Lin !(ctrl & reset), 2448e6db1f6SShawn Lin 1, 500 * USEC_PER_MSEC)) { 2458e6db1f6SShawn Lin dev_err(host->dev, 2468e6db1f6SShawn Lin "Timeout resetting block (ctrl reset %#x)\n", 2478e6db1f6SShawn Lin ctrl & reset); 2488e6db1f6SShawn Lin return false; 2498e6db1f6SShawn Lin } 2508e6db1f6SShawn Lin 2518e6db1f6SShawn Lin return true; 2528e6db1f6SShawn Lin } 25301730558SDoug Anderson 2544dba18deSShawn Lin static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 2554dba18deSShawn Lin { 2564dba18deSShawn Lin u32 status; 2574dba18deSShawn Lin 2584dba18deSShawn Lin /* 2594dba18deSShawn Lin * Databook says that before issuing a new data transfer command 2604dba18deSShawn Lin * we need to check to see if the card is busy. Data transfer commands 2614dba18deSShawn Lin * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 2624dba18deSShawn Lin * 2634dba18deSShawn Lin * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 2644dba18deSShawn Lin * expected. 2654dba18deSShawn Lin */ 2664dba18deSShawn Lin if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 2674dba18deSShawn Lin !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 2684dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 2694dba18deSShawn Lin status, 2704dba18deSShawn Lin !(status & SDMMC_STATUS_BUSY), 2714dba18deSShawn Lin 10, 500 * USEC_PER_MSEC)) 2724dba18deSShawn Lin dev_err(host->dev, "Busy; trying anyway\n"); 2734dba18deSShawn Lin } 2744dba18deSShawn Lin } 2754dba18deSShawn Lin 2764dba18deSShawn Lin static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 2774dba18deSShawn Lin { 2784dba18deSShawn Lin struct dw_mci *host = slot->host; 2794dba18deSShawn Lin unsigned int cmd_status = 0; 2804dba18deSShawn Lin 2814dba18deSShawn Lin mci_writel(host, CMDARG, arg); 2824dba18deSShawn Lin wmb(); /* drain writebuffer */ 2834dba18deSShawn Lin dw_mci_wait_while_busy(host, cmd); 2844dba18deSShawn Lin mci_writel(host, CMD, SDMMC_CMD_START | cmd); 2854dba18deSShawn Lin 2864dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 2874dba18deSShawn Lin !(cmd_status & SDMMC_CMD_START), 2884dba18deSShawn Lin 1, 500 * USEC_PER_MSEC)) 2894dba18deSShawn Lin dev_err(&slot->mmc->class_dev, 2904dba18deSShawn Lin "Timeout sending command (cmd %#x arg %#x status %#x)\n", 2914dba18deSShawn Lin cmd, arg, cmd_status); 2924dba18deSShawn Lin } 2934dba18deSShawn Lin 294f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 295f95f3850SWill Newton { 296800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 29701730558SDoug Anderson struct dw_mci *host = slot->host; 298f95f3850SWill Newton u32 cmdr; 299f95f3850SWill Newton 3000e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 301f95f3850SWill Newton cmdr = cmd->opcode; 302f95f3850SWill Newton 30390c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 30490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 30590c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 30690c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 30790c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 308f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 3094a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 310f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 311f95f3850SWill Newton 31201730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 31301730558SDoug Anderson u32 clk_en_a; 31401730558SDoug Anderson 31501730558SDoug Anderson /* Special bit makes CMD11 not die */ 31601730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 31701730558SDoug Anderson 31801730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 31901730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 32001730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 32101730558SDoug Anderson 32201730558SDoug Anderson /* 32301730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 32401730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 32501730558SDoug Anderson * since stopping the clock is a specific part of the UHS 32601730558SDoug Anderson * voltage change dance. 32701730558SDoug Anderson * 32801730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 32901730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 33001730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 33101730558SDoug Anderson * until the voltage change is all done. 33201730558SDoug Anderson */ 33301730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 33401730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 33501730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 33601730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 33701730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 33801730558SDoug Anderson } 33901730558SDoug Anderson 340f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 341f95f3850SWill Newton /* We expect a response, so set this bit */ 342f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 343f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 344f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 345f95f3850SWill Newton } 346f95f3850SWill Newton 347f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 348f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 349f95f3850SWill Newton 3500349c085SJaehoon Chung if (cmd->data) { 351f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 3520349c085SJaehoon Chung if (cmd->data->flags & MMC_DATA_WRITE) 353f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 354f95f3850SWill Newton } 355f95f3850SWill Newton 356aaaaeb7aSJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 357aaaaeb7aSJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 358800d78bfSThomas Abraham 359f95f3850SWill Newton return cmdr; 360f95f3850SWill Newton } 361f95f3850SWill Newton 36290c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 36390c2143aSSeungwon Jeon { 36490c2143aSSeungwon Jeon struct mmc_command *stop; 36590c2143aSSeungwon Jeon u32 cmdr; 36690c2143aSSeungwon Jeon 36790c2143aSSeungwon Jeon if (!cmd->data) 36890c2143aSSeungwon Jeon return 0; 36990c2143aSSeungwon Jeon 37090c2143aSSeungwon Jeon stop = &host->stop_abort; 37190c2143aSSeungwon Jeon cmdr = cmd->opcode; 37290c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 37390c2143aSSeungwon Jeon 37490c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 37590c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 37690c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3776c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3786c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3796c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 38090c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 38190c2143aSSeungwon Jeon stop->arg = 0; 38290c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 38390c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 38490c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 38590c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 38690c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 38790c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 38890c2143aSSeungwon Jeon } else { 38990c2143aSSeungwon Jeon return 0; 39090c2143aSSeungwon Jeon } 39190c2143aSSeungwon Jeon 39290c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 39390c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 39490c2143aSSeungwon Jeon 3958c005b40SJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags)) 3968c005b40SJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 3978c005b40SJaehoon Chung 39890c2143aSSeungwon Jeon return cmdr; 39990c2143aSSeungwon Jeon } 40090c2143aSSeungwon Jeon 401f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 402f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 403f95f3850SWill Newton { 404f95f3850SWill Newton host->cmd = cmd; 4054a90920cSThomas Abraham dev_vdbg(host->dev, 406f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 407f95f3850SWill Newton cmd->arg, cmd_flags); 408f95f3850SWill Newton 409f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 4100e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 4110bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 412f95f3850SWill Newton 413f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 414f95f3850SWill Newton } 415f95f3850SWill Newton 41690c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 417f95f3850SWill Newton { 418e13c3c08SJaehoon Chung struct mmc_command *stop = &host->stop_abort; 4190e3a22c0SShawn Lin 42090c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 421f95f3850SWill Newton } 422f95f3850SWill Newton 423f95f3850SWill Newton /* DMA interface functions */ 424f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 425f95f3850SWill Newton { 42603e8cb53SJames Hogan if (host->using_dma) { 427f95f3850SWill Newton host->dma_ops->stop(host); 428f95f3850SWill Newton host->dma_ops->cleanup(host); 429aa50f259SSeungwon Jeon } 430aa50f259SSeungwon Jeon 431f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 432f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 433f95f3850SWill Newton } 434f95f3850SWill Newton 435f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 436f95f3850SWill Newton { 437f95f3850SWill Newton struct mmc_data *data = host->data; 438f95f3850SWill Newton 439a4cc7eb4SJaehoon Chung if (data && data->host_cookie == COOKIE_MAPPED) { 4404a90920cSThomas Abraham dma_unmap_sg(host->dev, 4419aa51408SSeungwon Jeon data->sg, 4429aa51408SSeungwon Jeon data->sg_len, 443feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 444a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 445a4cc7eb4SJaehoon Chung } 446f95f3850SWill Newton } 447f95f3850SWill Newton 4485ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4495ce9d961SSeungwon Jeon { 4505ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4515ce9d961SSeungwon Jeon /* Software reset of DMA */ 4525ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4535ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4545ce9d961SSeungwon Jeon } 4555ce9d961SSeungwon Jeon 456f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 457f95f3850SWill Newton { 458f95f3850SWill Newton u32 temp; 459f95f3850SWill Newton 460f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 461f95f3850SWill Newton temp = mci_readl(host, CTRL); 462f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 463f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 464f95f3850SWill Newton mci_writel(host, CTRL, temp); 465f95f3850SWill Newton 466f95f3850SWill Newton /* Stop the IDMAC running */ 467f95f3850SWill Newton temp = mci_readl(host, BMOD); 468a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4695ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 470f95f3850SWill Newton mci_writel(host, BMOD, temp); 471f95f3850SWill Newton } 472f95f3850SWill Newton 4733fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 474f95f3850SWill Newton { 4753fc7eaefSShawn Lin struct dw_mci *host = arg; 476f95f3850SWill Newton struct mmc_data *data = host->data; 477f95f3850SWill Newton 4784a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 479f95f3850SWill Newton 4803fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 4813fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 4823fc7eaefSShawn Lin /* Invalidate cache after read */ 4833fc7eaefSShawn Lin dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), 4843fc7eaefSShawn Lin data->sg, 4853fc7eaefSShawn Lin data->sg_len, 4863fc7eaefSShawn Lin DMA_FROM_DEVICE); 4873fc7eaefSShawn Lin 488f95f3850SWill Newton host->dma_ops->cleanup(host); 489f95f3850SWill Newton 490f95f3850SWill Newton /* 491f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 492f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 493f95f3850SWill Newton */ 494f95f3850SWill Newton if (data) { 495f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 496f95f3850SWill Newton tasklet_schedule(&host->tasklet); 497f95f3850SWill Newton } 498f95f3850SWill Newton } 499f95f3850SWill Newton 500f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 501f95f3850SWill Newton { 502897b69e7SSeungwon Jeon int i; 503f95f3850SWill Newton 50469d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 50569d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 50669d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 507cc190d4cSShawn Lin host->ring_size = 508cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 50969d99fdcSPrabu Thangamuthu 51069d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 51169d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 51269d99fdcSPrabu Thangamuthu i++, p++) { 51369d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 51469d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 51569d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 51669d99fdcSPrabu Thangamuthu 51769d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 51869d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 51969d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 52069d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 52169d99fdcSPrabu Thangamuthu p->des1 = 0; 52269d99fdcSPrabu Thangamuthu p->des2 = 0; 52369d99fdcSPrabu Thangamuthu p->des3 = 0; 52469d99fdcSPrabu Thangamuthu } 52569d99fdcSPrabu Thangamuthu 52669d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 52769d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 52869d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 52969d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 53069d99fdcSPrabu Thangamuthu 53169d99fdcSPrabu Thangamuthu } else { 53269d99fdcSPrabu Thangamuthu struct idmac_desc *p; 533f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 534cc190d4cSShawn Lin host->ring_size = 535cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 536f95f3850SWill Newton 537f95f3850SWill Newton /* Forward link the descriptor list */ 5380e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 5390e3a22c0SShawn Lin i < host->ring_size - 1; 5400e3a22c0SShawn Lin i++, p++) { 5416687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 5426687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 5434b244724SZhangfei Gao p->des1 = 0; 5444b244724SZhangfei Gao } 545f95f3850SWill Newton 546f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 5476687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 5486687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 54969d99fdcSPrabu Thangamuthu } 550f95f3850SWill Newton 5515ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 552141a712aSSeungwon Jeon 55369d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 55469d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 55569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 55669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 55769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 55869d99fdcSPrabu Thangamuthu 55969d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 56069d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 56169d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 56269d99fdcSPrabu Thangamuthu 56369d99fdcSPrabu Thangamuthu } else { 564f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 565fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 56669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 56769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 568f95f3850SWill Newton 569f95f3850SWill Newton /* Set the descriptor base address */ 570f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 57169d99fdcSPrabu Thangamuthu } 57269d99fdcSPrabu Thangamuthu 573f95f3850SWill Newton return 0; 574f95f3850SWill Newton } 575f95f3850SWill Newton 5763b2a067bSShawn Lin static inline int dw_mci_prepare_desc64(struct dw_mci *host, 5773b2a067bSShawn Lin struct mmc_data *data, 5783b2a067bSShawn Lin unsigned int sg_len) 5793b2a067bSShawn Lin { 5803b2a067bSShawn Lin unsigned int desc_len; 5813b2a067bSShawn Lin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 582b6d2d81cSShawn Lin u32 val; 5833b2a067bSShawn Lin int i; 5843b2a067bSShawn Lin 5853b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 5863b2a067bSShawn Lin 5873b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 5883b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 5893b2a067bSShawn Lin 5903b2a067bSShawn Lin u64 mem_addr = sg_dma_address(&data->sg[i]); 5913b2a067bSShawn Lin 5923b2a067bSShawn Lin for ( ; length ; desc++) { 5933b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 5943b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 5953b2a067bSShawn Lin 5963b2a067bSShawn Lin length -= desc_len; 5973b2a067bSShawn Lin 5983b2a067bSShawn Lin /* 5993b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6003b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6013b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6023b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6033b2a067bSShawn Lin */ 604b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 605b6d2d81cSShawn Lin !(val & IDMAC_DES0_OWN), 606b6d2d81cSShawn Lin 10, 100 * USEC_PER_MSEC)) 6073b2a067bSShawn Lin goto err_own_bit; 6083b2a067bSShawn Lin 6093b2a067bSShawn Lin /* 6103b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6113b2a067bSShawn Lin * for this descriptor 6123b2a067bSShawn Lin */ 6133b2a067bSShawn Lin desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 6143b2a067bSShawn Lin IDMAC_DES0_CH; 6153b2a067bSShawn Lin 6163b2a067bSShawn Lin /* Buffer length */ 6173b2a067bSShawn Lin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 6183b2a067bSShawn Lin 6193b2a067bSShawn Lin /* Physical address to DMA to/from */ 6203b2a067bSShawn Lin desc->des4 = mem_addr & 0xffffffff; 6213b2a067bSShawn Lin desc->des5 = mem_addr >> 32; 6223b2a067bSShawn Lin 6233b2a067bSShawn Lin /* Update physical address for the next desc */ 6243b2a067bSShawn Lin mem_addr += desc_len; 6253b2a067bSShawn Lin 6263b2a067bSShawn Lin /* Save pointer to the last descriptor */ 6273b2a067bSShawn Lin desc_last = desc; 6283b2a067bSShawn Lin } 6293b2a067bSShawn Lin } 6303b2a067bSShawn Lin 6313b2a067bSShawn Lin /* Set first descriptor */ 6323b2a067bSShawn Lin desc_first->des0 |= IDMAC_DES0_FD; 6333b2a067bSShawn Lin 6343b2a067bSShawn Lin /* Set last descriptor */ 6353b2a067bSShawn Lin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 6363b2a067bSShawn Lin desc_last->des0 |= IDMAC_DES0_LD; 6373b2a067bSShawn Lin 6383b2a067bSShawn Lin return 0; 6393b2a067bSShawn Lin err_own_bit: 6403b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 64126be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 642cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 6433b2a067bSShawn Lin dw_mci_idmac_init(host); 6443b2a067bSShawn Lin return -EINVAL; 6453b2a067bSShawn Lin } 6463b2a067bSShawn Lin 6473b2a067bSShawn Lin 6483b2a067bSShawn Lin static inline int dw_mci_prepare_desc32(struct dw_mci *host, 6493b2a067bSShawn Lin struct mmc_data *data, 6503b2a067bSShawn Lin unsigned int sg_len) 6513b2a067bSShawn Lin { 6523b2a067bSShawn Lin unsigned int desc_len; 6533b2a067bSShawn Lin struct idmac_desc *desc_first, *desc_last, *desc; 654b6d2d81cSShawn Lin u32 val; 6553b2a067bSShawn Lin int i; 6563b2a067bSShawn Lin 6573b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 6583b2a067bSShawn Lin 6593b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 6603b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 6613b2a067bSShawn Lin 6623b2a067bSShawn Lin u32 mem_addr = sg_dma_address(&data->sg[i]); 6633b2a067bSShawn Lin 6643b2a067bSShawn Lin for ( ; length ; desc++) { 6653b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6663b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6673b2a067bSShawn Lin 6683b2a067bSShawn Lin length -= desc_len; 6693b2a067bSShawn Lin 6703b2a067bSShawn Lin /* 6713b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6723b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6733b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6743b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6753b2a067bSShawn Lin */ 676b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 677b6d2d81cSShawn Lin IDMAC_OWN_CLR64(val), 678b6d2d81cSShawn Lin 10, 679b6d2d81cSShawn Lin 100 * USEC_PER_MSEC)) 6803b2a067bSShawn Lin goto err_own_bit; 6813b2a067bSShawn Lin 6823b2a067bSShawn Lin /* 6833b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6843b2a067bSShawn Lin * for this descriptor 6853b2a067bSShawn Lin */ 6863b2a067bSShawn Lin desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 6873b2a067bSShawn Lin IDMAC_DES0_DIC | 6883b2a067bSShawn Lin IDMAC_DES0_CH); 6893b2a067bSShawn Lin 6903b2a067bSShawn Lin /* Buffer length */ 6913b2a067bSShawn Lin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 6923b2a067bSShawn Lin 6933b2a067bSShawn Lin /* Physical address to DMA to/from */ 6943b2a067bSShawn Lin desc->des2 = cpu_to_le32(mem_addr); 6953b2a067bSShawn Lin 6963b2a067bSShawn Lin /* Update physical address for the next desc */ 6973b2a067bSShawn Lin mem_addr += desc_len; 6983b2a067bSShawn Lin 6993b2a067bSShawn Lin /* Save pointer to the last descriptor */ 7003b2a067bSShawn Lin desc_last = desc; 7013b2a067bSShawn Lin } 7023b2a067bSShawn Lin } 7033b2a067bSShawn Lin 7043b2a067bSShawn Lin /* Set first descriptor */ 7053b2a067bSShawn Lin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 7063b2a067bSShawn Lin 7073b2a067bSShawn Lin /* Set last descriptor */ 7083b2a067bSShawn Lin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 7093b2a067bSShawn Lin IDMAC_DES0_DIC)); 7103b2a067bSShawn Lin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 7113b2a067bSShawn Lin 7123b2a067bSShawn Lin return 0; 7133b2a067bSShawn Lin err_own_bit: 7143b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 71526be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 716cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 7173b2a067bSShawn Lin dw_mci_idmac_init(host); 7183b2a067bSShawn Lin return -EINVAL; 7193b2a067bSShawn Lin } 7203b2a067bSShawn Lin 7213b2a067bSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 7223b2a067bSShawn Lin { 7233b2a067bSShawn Lin u32 temp; 7243b2a067bSShawn Lin int ret; 7253b2a067bSShawn Lin 7263b2a067bSShawn Lin if (host->dma_64bit_address == 1) 7273b2a067bSShawn Lin ret = dw_mci_prepare_desc64(host, host->data, sg_len); 7283b2a067bSShawn Lin else 7293b2a067bSShawn Lin ret = dw_mci_prepare_desc32(host, host->data, sg_len); 7303b2a067bSShawn Lin 7313b2a067bSShawn Lin if (ret) 7323b2a067bSShawn Lin goto out; 7333b2a067bSShawn Lin 7343b2a067bSShawn Lin /* drain writebuffer */ 7353b2a067bSShawn Lin wmb(); 7363b2a067bSShawn Lin 7373b2a067bSShawn Lin /* Make sure to reset DMA in case we did PIO before this */ 7383b2a067bSShawn Lin dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 7393b2a067bSShawn Lin dw_mci_idmac_reset(host); 7403b2a067bSShawn Lin 7413b2a067bSShawn Lin /* Select IDMAC interface */ 7423b2a067bSShawn Lin temp = mci_readl(host, CTRL); 7433b2a067bSShawn Lin temp |= SDMMC_CTRL_USE_IDMAC; 7443b2a067bSShawn Lin mci_writel(host, CTRL, temp); 7453b2a067bSShawn Lin 7463b2a067bSShawn Lin /* drain writebuffer */ 7473b2a067bSShawn Lin wmb(); 7483b2a067bSShawn Lin 7493b2a067bSShawn Lin /* Enable the IDMAC */ 7503b2a067bSShawn Lin temp = mci_readl(host, BMOD); 7513b2a067bSShawn Lin temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 7523b2a067bSShawn Lin mci_writel(host, BMOD, temp); 7533b2a067bSShawn Lin 7543b2a067bSShawn Lin /* Start it running */ 7553b2a067bSShawn Lin mci_writel(host, PLDMND, 1); 7563b2a067bSShawn Lin 7573b2a067bSShawn Lin out: 7583b2a067bSShawn Lin return ret; 7593b2a067bSShawn Lin } 7603b2a067bSShawn Lin 7618e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 762885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 763885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 764885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 7653fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 766885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 767885c3e80SSeungwon Jeon }; 7683fc7eaefSShawn Lin 7693fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 7703fc7eaefSShawn Lin { 771ab925a31SShawn Lin dmaengine_terminate_async(host->dms->ch); 7723fc7eaefSShawn Lin } 7733fc7eaefSShawn Lin 7743fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 7753fc7eaefSShawn Lin unsigned int sg_len) 7763fc7eaefSShawn Lin { 7773fc7eaefSShawn Lin struct dma_slave_config cfg; 7783fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 7793fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 7803fc7eaefSShawn Lin const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 7813fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 7823fc7eaefSShawn Lin u32 fifoth_val; 7833fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 7843fc7eaefSShawn Lin int ret = 0; 7853fc7eaefSShawn Lin 7863fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 787260b3164SArnd Bergmann cfg.dst_addr = host->phy_regs + fifo_offset; 7883fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 7893fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7903fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7913fc7eaefSShawn Lin 7923fc7eaefSShawn Lin /* Match burst msize with external dma config */ 7933fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 7943fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 7953fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 7963fc7eaefSShawn Lin 7973fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7983fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 7993fc7eaefSShawn Lin else 8003fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 8013fc7eaefSShawn Lin 8023fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 8033fc7eaefSShawn Lin if (ret) { 8043fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 8053fc7eaefSShawn Lin return -EBUSY; 8063fc7eaefSShawn Lin } 8073fc7eaefSShawn Lin 8083fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 8093fc7eaefSShawn Lin sg_len, cfg.direction, 8103fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 8113fc7eaefSShawn Lin if (!desc) { 8123fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 8133fc7eaefSShawn Lin return -EBUSY; 8143fc7eaefSShawn Lin } 8153fc7eaefSShawn Lin 8163fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 8173fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 8183fc7eaefSShawn Lin desc->callback_param = (void *)host; 8193fc7eaefSShawn Lin dmaengine_submit(desc); 8203fc7eaefSShawn Lin 8213fc7eaefSShawn Lin /* Flush cache before write */ 8223fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 8233fc7eaefSShawn Lin dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl, 8243fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 8253fc7eaefSShawn Lin 8263fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 8273fc7eaefSShawn Lin 8283fc7eaefSShawn Lin return 0; 8293fc7eaefSShawn Lin } 8303fc7eaefSShawn Lin 8313fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 8323fc7eaefSShawn Lin { 8333fc7eaefSShawn Lin /* Request external dma channel */ 8343fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 8353fc7eaefSShawn Lin if (!host->dms) 8363fc7eaefSShawn Lin return -ENOMEM; 8373fc7eaefSShawn Lin 8383fc7eaefSShawn Lin host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 8393fc7eaefSShawn Lin if (!host->dms->ch) { 8404539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 8413fc7eaefSShawn Lin kfree(host->dms); 8423fc7eaefSShawn Lin host->dms = NULL; 8433fc7eaefSShawn Lin return -ENXIO; 8443fc7eaefSShawn Lin } 8453fc7eaefSShawn Lin 8463fc7eaefSShawn Lin return 0; 8473fc7eaefSShawn Lin } 8483fc7eaefSShawn Lin 8493fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 8503fc7eaefSShawn Lin { 8513fc7eaefSShawn Lin if (host->dms) { 8523fc7eaefSShawn Lin if (host->dms->ch) { 8533fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 8543fc7eaefSShawn Lin host->dms->ch = NULL; 8553fc7eaefSShawn Lin } 8563fc7eaefSShawn Lin kfree(host->dms); 8573fc7eaefSShawn Lin host->dms = NULL; 8583fc7eaefSShawn Lin } 8593fc7eaefSShawn Lin } 8603fc7eaefSShawn Lin 8613fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 8623fc7eaefSShawn Lin .init = dw_mci_edmac_init, 8633fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 8643fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 8653fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 8663fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 8673fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 8683fc7eaefSShawn Lin }; 869885c3e80SSeungwon Jeon 8709aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 8719aa51408SSeungwon Jeon struct mmc_data *data, 872a4cc7eb4SJaehoon Chung int cookie) 873f95f3850SWill Newton { 874f95f3850SWill Newton struct scatterlist *sg; 8759aa51408SSeungwon Jeon unsigned int i, sg_len; 876f95f3850SWill Newton 877a4cc7eb4SJaehoon Chung if (data->host_cookie == COOKIE_PRE_MAPPED) 878a4cc7eb4SJaehoon Chung return data->sg_len; 879f95f3850SWill Newton 880f95f3850SWill Newton /* 881f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 882f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 883f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 884f95f3850SWill Newton */ 885f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 886f95f3850SWill Newton return -EINVAL; 8879aa51408SSeungwon Jeon 888f95f3850SWill Newton if (data->blksz & 3) 889f95f3850SWill Newton return -EINVAL; 890f95f3850SWill Newton 891f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 892f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 893f95f3850SWill Newton return -EINVAL; 894f95f3850SWill Newton } 895f95f3850SWill Newton 8964a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 8979aa51408SSeungwon Jeon data->sg, 8989aa51408SSeungwon Jeon data->sg_len, 899feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 9009aa51408SSeungwon Jeon if (sg_len == 0) 9019aa51408SSeungwon Jeon return -EINVAL; 9029aa51408SSeungwon Jeon 903a4cc7eb4SJaehoon Chung data->host_cookie = cookie; 9049aa51408SSeungwon Jeon 9059aa51408SSeungwon Jeon return sg_len; 9069aa51408SSeungwon Jeon } 9079aa51408SSeungwon Jeon 9089aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 909d3c6aac3SLinus Walleij struct mmc_request *mrq) 9109aa51408SSeungwon Jeon { 9119aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9129aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9139aa51408SSeungwon Jeon 9149aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9159aa51408SSeungwon Jeon return; 9169aa51408SSeungwon Jeon 917a4cc7eb4SJaehoon Chung /* This data might be unmapped at this time */ 918a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9199aa51408SSeungwon Jeon 920a4cc7eb4SJaehoon Chung if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 921a4cc7eb4SJaehoon Chung COOKIE_PRE_MAPPED) < 0) 922a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9239aa51408SSeungwon Jeon } 9249aa51408SSeungwon Jeon 9259aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 9269aa51408SSeungwon Jeon struct mmc_request *mrq, 9279aa51408SSeungwon Jeon int err) 9289aa51408SSeungwon Jeon { 9299aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9309aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9319aa51408SSeungwon Jeon 9329aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9339aa51408SSeungwon Jeon return; 9349aa51408SSeungwon Jeon 935a4cc7eb4SJaehoon Chung if (data->host_cookie != COOKIE_UNMAPPED) 9364a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 9379aa51408SSeungwon Jeon data->sg, 9389aa51408SSeungwon Jeon data->sg_len, 939feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 940a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9419aa51408SSeungwon Jeon } 9429aa51408SSeungwon Jeon 943671fa142SShawn Lin static int dw_mci_get_cd(struct mmc_host *mmc) 944671fa142SShawn Lin { 945671fa142SShawn Lin int present; 946671fa142SShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 947671fa142SShawn Lin struct dw_mci *host = slot->host; 948671fa142SShawn Lin int gpio_cd = mmc_gpio_get_cd(mmc); 949671fa142SShawn Lin 950671fa142SShawn Lin /* Use platform get_cd function, else try onboard card detect */ 951671fa142SShawn Lin if (((mmc->caps & MMC_CAP_NEEDS_POLL) 952671fa142SShawn Lin || !mmc_card_is_removable(mmc))) { 953671fa142SShawn Lin present = 1; 954671fa142SShawn Lin 955671fa142SShawn Lin if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 956671fa142SShawn Lin if (mmc->caps & MMC_CAP_NEEDS_POLL) { 957671fa142SShawn Lin dev_info(&mmc->class_dev, 958671fa142SShawn Lin "card is polling.\n"); 959671fa142SShawn Lin } else { 960671fa142SShawn Lin dev_info(&mmc->class_dev, 961671fa142SShawn Lin "card is non-removable.\n"); 962671fa142SShawn Lin } 963671fa142SShawn Lin set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 964671fa142SShawn Lin } 965671fa142SShawn Lin 966671fa142SShawn Lin return present; 967671fa142SShawn Lin } else if (gpio_cd >= 0) 968671fa142SShawn Lin present = gpio_cd; 969671fa142SShawn Lin else 970671fa142SShawn Lin present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 971671fa142SShawn Lin == 0 ? 1 : 0; 972671fa142SShawn Lin 973671fa142SShawn Lin spin_lock_bh(&host->lock); 974671fa142SShawn Lin if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 975671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is present\n"); 976671fa142SShawn Lin else if (!present && 977671fa142SShawn Lin !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 978671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is not present\n"); 979671fa142SShawn Lin spin_unlock_bh(&host->lock); 980671fa142SShawn Lin 981671fa142SShawn Lin return present; 982671fa142SShawn Lin } 983671fa142SShawn Lin 98452426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 98552426899SSeungwon Jeon { 98652426899SSeungwon Jeon unsigned int blksz = data->blksz; 98752426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 98852426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 98952426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 99052426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 9910e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 99252426899SSeungwon Jeon 9933fc7eaefSShawn Lin /* pio should ship this scenario */ 9943fc7eaefSShawn Lin if (!host->use_dma) 9953fc7eaefSShawn Lin return; 9963fc7eaefSShawn Lin 99752426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 99852426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 99952426899SSeungwon Jeon 100052426899SSeungwon Jeon /* 100152426899SSeungwon Jeon * MSIZE is '1', 100252426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 100352426899SSeungwon Jeon */ 100420753569SShawn Lin if (blksz % fifo_width) 100552426899SSeungwon Jeon goto done; 100652426899SSeungwon Jeon 100752426899SSeungwon Jeon do { 100852426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 100952426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 101052426899SSeungwon Jeon msize = idx; 101152426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 101252426899SSeungwon Jeon break; 101352426899SSeungwon Jeon } 101452426899SSeungwon Jeon } while (--idx > 0); 101552426899SSeungwon Jeon /* 101652426899SSeungwon Jeon * If idx is '0', it won't be tried 101752426899SSeungwon Jeon * Thus, initial values are uesed 101852426899SSeungwon Jeon */ 101952426899SSeungwon Jeon done: 102052426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 102152426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 102252426899SSeungwon Jeon } 102352426899SSeungwon Jeon 10247e4bf1bcSJaehoon Chung static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1025f1d2736cSSeungwon Jeon { 1026f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 1027f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 1028f1d2736cSSeungwon Jeon u16 thld_size; 10297e4bf1bcSJaehoon Chung u8 enable; 1030f1d2736cSSeungwon Jeon 103166dfd101SJames Hogan /* 103266dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 103366dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 103466dfd101SJames Hogan */ 10357e4bf1bcSJaehoon Chung if (host->verid < DW_MMC_240A || 10367e4bf1bcSJaehoon Chung (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 103766dfd101SJames Hogan return; 103866dfd101SJames Hogan 10397e4bf1bcSJaehoon Chung /* 10407e4bf1bcSJaehoon Chung * Card write Threshold is introduced since 2.80a 10417e4bf1bcSJaehoon Chung * It's used when HS400 mode is enabled. 10427e4bf1bcSJaehoon Chung */ 10437e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE && 10447e4bf1bcSJaehoon Chung !(host->timing != MMC_TIMING_MMC_HS400)) 10457e4bf1bcSJaehoon Chung return; 10467e4bf1bcSJaehoon Chung 10477e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE) 10487e4bf1bcSJaehoon Chung enable = SDMMC_CARD_WR_THR_EN; 10497e4bf1bcSJaehoon Chung else 10507e4bf1bcSJaehoon Chung enable = SDMMC_CARD_RD_THR_EN; 10517e4bf1bcSJaehoon Chung 1052f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 1053f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 1054f1d2736cSSeungwon Jeon goto disable; 1055f1d2736cSSeungwon Jeon 1056f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 1057f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 1058f1d2736cSSeungwon Jeon 1059f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 1060f1d2736cSSeungwon Jeon goto disable; 1061f1d2736cSSeungwon Jeon 1062f1d2736cSSeungwon Jeon /* 1063f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1064f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1065f1d2736cSSeungwon Jeon * Currently just choose blksz. 1066f1d2736cSSeungwon Jeon */ 1067f1d2736cSSeungwon Jeon thld_size = blksz; 10687e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1069f1d2736cSSeungwon Jeon return; 1070f1d2736cSSeungwon Jeon 1071f1d2736cSSeungwon Jeon disable: 10727e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, 0); 1073f1d2736cSSeungwon Jeon } 1074f1d2736cSSeungwon Jeon 10759aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 10769aa51408SSeungwon Jeon { 1077f8c58c11SDoug Anderson unsigned long irqflags; 10789aa51408SSeungwon Jeon int sg_len; 10799aa51408SSeungwon Jeon u32 temp; 10809aa51408SSeungwon Jeon 10819aa51408SSeungwon Jeon host->using_dma = 0; 10829aa51408SSeungwon Jeon 10839aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 10849aa51408SSeungwon Jeon if (!host->use_dma) 10859aa51408SSeungwon Jeon return -ENODEV; 10869aa51408SSeungwon Jeon 1087a4cc7eb4SJaehoon Chung sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1088a99aa9b9SSeungwon Jeon if (sg_len < 0) { 1089a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 10909aa51408SSeungwon Jeon return sg_len; 1091a99aa9b9SSeungwon Jeon } 10929aa51408SSeungwon Jeon 109303e8cb53SJames Hogan host->using_dma = 1; 109403e8cb53SJames Hogan 10953fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 10964a90920cSThomas Abraham dev_vdbg(host->dev, 1097f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 10983fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 10993fc7eaefSShawn Lin (unsigned long)host->sg_dma, 1100f95f3850SWill Newton sg_len); 1101f95f3850SWill Newton 110252426899SSeungwon Jeon /* 110352426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 110452426899SSeungwon Jeon * If current block size is same with previous size, 110552426899SSeungwon Jeon * no need to update fifoth. 110652426899SSeungwon Jeon */ 110752426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 110852426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 110952426899SSeungwon Jeon 1110f95f3850SWill Newton /* Enable the DMA interface */ 1111f95f3850SWill Newton temp = mci_readl(host, CTRL); 1112f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 1113f95f3850SWill Newton mci_writel(host, CTRL, temp); 1114f95f3850SWill Newton 1115f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 1116f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1117f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1118f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1119f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1120f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1121f95f3850SWill Newton 11223fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 1123647f80a1SJaehoon Chung host->dma_ops->stop(host); 1124d12d0cb1SShawn Lin /* We can't do DMA, try PIO for this one */ 1125d12d0cb1SShawn Lin dev_dbg(host->dev, 1126d12d0cb1SShawn Lin "%s: fall back to PIO mode for current transfer\n", 1127d12d0cb1SShawn Lin __func__); 11283fc7eaefSShawn Lin return -ENODEV; 11293fc7eaefSShawn Lin } 1130f95f3850SWill Newton 1131f95f3850SWill Newton return 0; 1132f95f3850SWill Newton } 1133f95f3850SWill Newton 1134f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1135f95f3850SWill Newton { 1136f8c58c11SDoug Anderson unsigned long irqflags; 11370e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1138f95f3850SWill Newton u32 temp; 1139f95f3850SWill Newton 1140f95f3850SWill Newton data->error = -EINPROGRESS; 1141f95f3850SWill Newton 1142f95f3850SWill Newton WARN_ON(host->data); 1143f95f3850SWill Newton host->sg = NULL; 1144f95f3850SWill Newton host->data = data; 1145f95f3850SWill Newton 11467e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_READ) 114755c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 11487e4bf1bcSJaehoon Chung else 114955c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 11507e4bf1bcSJaehoon Chung 11517e4bf1bcSJaehoon Chung dw_mci_ctrl_thld(host, data); 115255c5efbcSJames Hogan 1153f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1154f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1155f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1156f9c2a0dcSSeungwon Jeon else 1157f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1158f9c2a0dcSSeungwon Jeon 1159f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1160f95f3850SWill Newton host->sg = data->sg; 116134b664a2SJames Hogan host->part_buf_start = 0; 116234b664a2SJames Hogan host->part_buf_count = 0; 1163f95f3850SWill Newton 1164b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1165f8c58c11SDoug Anderson 1166f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1167f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1168f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1169f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1170f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1171f95f3850SWill Newton 1172f95f3850SWill Newton temp = mci_readl(host, CTRL); 1173f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1174f95f3850SWill Newton mci_writel(host, CTRL, temp); 117552426899SSeungwon Jeon 117652426899SSeungwon Jeon /* 1177d6fced83SJun Nie * Use the initial fifoth_val for PIO mode. If wm_algined 1178d6fced83SJun Nie * is set, we set watermark same as data size. 117952426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 118052426899SSeungwon Jeon * prev_blksz should be invalidated. 118152426899SSeungwon Jeon */ 1182d6fced83SJun Nie if (host->wm_aligned) 1183d6fced83SJun Nie dw_mci_adjust_fifoth(host, data); 1184d6fced83SJun Nie else 118552426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 118652426899SSeungwon Jeon host->prev_blksz = 0; 118752426899SSeungwon Jeon } else { 118852426899SSeungwon Jeon /* 118952426899SSeungwon Jeon * Keep the current block size. 119052426899SSeungwon Jeon * It will be used to decide whether to update 119152426899SSeungwon Jeon * fifoth register next time. 119252426899SSeungwon Jeon */ 119352426899SSeungwon Jeon host->prev_blksz = data->blksz; 1194f95f3850SWill Newton } 1195f95f3850SWill Newton } 1196f95f3850SWill Newton 1197ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1198f95f3850SWill Newton { 1199f95f3850SWill Newton struct dw_mci *host = slot->host; 1200fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1201f95f3850SWill Newton u32 div; 12029623b5b9SDoug Anderson u32 clk_en_a; 120301730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 120401730558SDoug Anderson 120501730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 120601730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 120701730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1208f95f3850SWill Newton 1209fdf492a1SDoug Anderson if (!clock) { 1210fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 121101730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1212fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1213fdf492a1SDoug Anderson div = host->bus_hz / clock; 1214fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1215f95f3850SWill Newton /* 1216f95f3850SWill Newton * move the + 1 after the divide to prevent 1217f95f3850SWill Newton * over-clocking the card. 1218f95f3850SWill Newton */ 1219e419990bSSeungwon Jeon div += 1; 1220e419990bSSeungwon Jeon 1221fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1222f95f3850SWill Newton 1223e6cd7a8eSJaehoon Chung if ((clock != slot->__clk_old && 1224e6cd7a8eSJaehoon Chung !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1225e6cd7a8eSJaehoon Chung force_clkinit) { 1226ce69e2feSShawn Lin /* Silent the verbose log if calling from PM context */ 1227ce69e2feSShawn Lin if (!force_clkinit) 1228f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1229fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1230fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1231fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1232fdf492a1SDoug Anderson host->bus_hz, div); 1233f95f3850SWill Newton 1234e6cd7a8eSJaehoon Chung /* 1235e6cd7a8eSJaehoon Chung * If card is polling, display the message only 1236e6cd7a8eSJaehoon Chung * one time at boot time. 1237e6cd7a8eSJaehoon Chung */ 1238e6cd7a8eSJaehoon Chung if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1239e6cd7a8eSJaehoon Chung slot->mmc->f_min == clock) 1240e6cd7a8eSJaehoon Chung set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1241e6cd7a8eSJaehoon Chung } 1242e6cd7a8eSJaehoon Chung 1243f95f3850SWill Newton /* disable clock */ 1244f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1245f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1246f95f3850SWill Newton 1247f95f3850SWill Newton /* inform CIU */ 124801730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1249f95f3850SWill Newton 1250f95f3850SWill Newton /* set clock to desired speed */ 1251f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1252f95f3850SWill Newton 1253f95f3850SWill Newton /* inform CIU */ 125401730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1255f95f3850SWill Newton 12569623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 12579623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1258b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 12599623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 12609623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1261f95f3850SWill Newton 1262f95f3850SWill Newton /* inform CIU */ 126301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1264005d675aSJaehoon Chung 1265005d675aSJaehoon Chung /* keep the last clock value that was requested from core */ 1266005d675aSJaehoon Chung slot->__clk_old = clock; 1267f95f3850SWill Newton } 1268f95f3850SWill Newton 1269fdf492a1SDoug Anderson host->current_speed = clock; 1270fdf492a1SDoug Anderson 1271f95f3850SWill Newton /* Set the current slot bus width */ 12721d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1273f95f3850SWill Newton } 1274f95f3850SWill Newton 1275053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1276053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1277053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1278f95f3850SWill Newton { 1279f95f3850SWill Newton struct mmc_request *mrq; 1280f95f3850SWill Newton struct mmc_data *data; 1281f95f3850SWill Newton u32 cmdflags; 1282f95f3850SWill Newton 1283f95f3850SWill Newton mrq = slot->mrq; 1284f95f3850SWill Newton 1285f95f3850SWill Newton host->cur_slot = slot; 1286f95f3850SWill Newton host->mrq = mrq; 1287f95f3850SWill Newton 1288f95f3850SWill Newton host->pending_events = 0; 1289f95f3850SWill Newton host->completed_events = 0; 1290e352c813SSeungwon Jeon host->cmd_status = 0; 1291f95f3850SWill Newton host->data_status = 0; 1292e352c813SSeungwon Jeon host->dir_status = 0; 1293f95f3850SWill Newton 1294053b3ce6SSeungwon Jeon data = cmd->data; 1295f95f3850SWill Newton if (data) { 1296f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1297f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1298f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1299f95f3850SWill Newton } 1300f95f3850SWill Newton 1301f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1302f95f3850SWill Newton 1303f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1304f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1305f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1306f95f3850SWill Newton 1307f95f3850SWill Newton if (data) { 1308f95f3850SWill Newton dw_mci_submit_data(host, data); 13090e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1310f95f3850SWill Newton } 1311f95f3850SWill Newton 1312f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1313f95f3850SWill Newton 13145c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 131549ba0302SDoug Anderson unsigned long irqflags; 131649ba0302SDoug Anderson 13175c935165SDoug Anderson /* 13188886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 13198886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 13208886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 13218886a6fdSDoug Anderson * is just about to roll over. 132249ba0302SDoug Anderson * 132349ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 132449ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 132549ba0302SDoug Anderson * already ran so we don't want the timeout). 13265c935165SDoug Anderson */ 132749ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 132849ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 13295c935165SDoug Anderson mod_timer(&host->cmd11_timer, 13308886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 133149ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13325c935165SDoug Anderson } 13335c935165SDoug Anderson 133490c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1335f95f3850SWill Newton } 1336f95f3850SWill Newton 1337053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1338053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1339053b3ce6SSeungwon Jeon { 1340053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1341053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1342053b3ce6SSeungwon Jeon 1343053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1344053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1345053b3ce6SSeungwon Jeon } 1346053b3ce6SSeungwon Jeon 13477456caaeSJames Hogan /* must be called with host->lock held */ 1348f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1349f95f3850SWill Newton struct mmc_request *mrq) 1350f95f3850SWill Newton { 1351f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1352f95f3850SWill Newton host->state); 1353f95f3850SWill Newton 1354f95f3850SWill Newton slot->mrq = mrq; 1355f95f3850SWill Newton 135601730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 135701730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 135801730558SDoug Anderson "Voltage change didn't complete\n"); 135901730558SDoug Anderson /* 136001730558SDoug Anderson * this case isn't expected to happen, so we can 136101730558SDoug Anderson * either crash here or just try to continue on 136201730558SDoug Anderson * in the closest possible state 136301730558SDoug Anderson */ 136401730558SDoug Anderson host->state = STATE_IDLE; 136501730558SDoug Anderson } 136601730558SDoug Anderson 1367f95f3850SWill Newton if (host->state == STATE_IDLE) { 1368f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1369f95f3850SWill Newton dw_mci_start_request(host, slot); 1370f95f3850SWill Newton } else { 1371f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1372f95f3850SWill Newton } 1373f95f3850SWill Newton } 1374f95f3850SWill Newton 1375f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1376f95f3850SWill Newton { 1377f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1378f95f3850SWill Newton struct dw_mci *host = slot->host; 1379f95f3850SWill Newton 1380f95f3850SWill Newton WARN_ON(slot->mrq); 1381f95f3850SWill Newton 13827456caaeSJames Hogan /* 13837456caaeSJames Hogan * The check for card presence and queueing of the request must be 13847456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 13857456caaeSJames Hogan * request wouldn't fail until another card was inserted. 13867456caaeSJames Hogan */ 13877456caaeSJames Hogan 138856f6911cSShawn Lin if (!dw_mci_get_cd(mmc)) { 1389f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1390f95f3850SWill Newton mmc_request_done(mmc, mrq); 1391f95f3850SWill Newton return; 1392f95f3850SWill Newton } 1393f95f3850SWill Newton 139456f6911cSShawn Lin spin_lock_bh(&host->lock); 139556f6911cSShawn Lin 1396f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 13977456caaeSJames Hogan 13987456caaeSJames Hogan spin_unlock_bh(&host->lock); 1399f95f3850SWill Newton } 1400f95f3850SWill Newton 1401f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1402f95f3850SWill Newton { 1403f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1404e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 140541babf75SJaehoon Chung u32 regs; 140651da2240SYuvaraj CD int ret; 1407f95f3850SWill Newton 1408f95f3850SWill Newton switch (ios->bus_width) { 1409f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1410f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1411f95f3850SWill Newton break; 1412c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1413c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1414c9b2a06fSJaehoon Chung break; 1415b2f7cb45SJaehoon Chung default: 1416b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1417b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1418f95f3850SWill Newton } 1419f95f3850SWill Newton 142041babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 14213f514291SSeungwon Jeon 14223f514291SSeungwon Jeon /* DDR mode set */ 142380113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 14247cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 142580113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1426c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 14273f514291SSeungwon Jeon else 1428c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 14293f514291SSeungwon Jeon 143041babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1431f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 143241babf75SJaehoon Chung 1433f95f3850SWill Newton /* 1434f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1435f95f3850SWill Newton * core ios update when finding the minimum. 1436f95f3850SWill Newton */ 1437f95f3850SWill Newton slot->clock = ios->clock; 1438f95f3850SWill Newton 1439cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1440cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1441800d78bfSThomas Abraham 1442f95f3850SWill Newton switch (ios->power_mode) { 1443f95f3850SWill Newton case MMC_POWER_UP: 144451da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 144551da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 144651da2240SYuvaraj CD ios->vdd); 144751da2240SYuvaraj CD if (ret) { 144851da2240SYuvaraj CD dev_err(slot->host->dev, 144951da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 145051da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 145151da2240SYuvaraj CD return; 145251da2240SYuvaraj CD } 145351da2240SYuvaraj CD } 145429d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 145529d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 145629d0d161SDoug Anderson regs |= (1 << slot->id); 145729d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 145829d0d161SDoug Anderson break; 145929d0d161SDoug Anderson case MMC_POWER_ON: 1460d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1461d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 146251da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 146351da2240SYuvaraj CD if (ret < 0) 146451da2240SYuvaraj CD dev_err(slot->host->dev, 1465d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 146651da2240SYuvaraj CD else 146751da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1468d1f1dd86SDoug Anderson 1469d1f1dd86SDoug Anderson } else { 1470d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1471d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1472d1f1dd86SDoug Anderson } 1473d1f1dd86SDoug Anderson 1474d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1475d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1476d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 147751da2240SYuvaraj CD } 1478655babbdSDoug Anderson 1479655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1480655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1481655babbdSDoug Anderson 1482e6f34e2fSJames Hogan break; 1483e6f34e2fSJames Hogan case MMC_POWER_OFF: 1484655babbdSDoug Anderson /* Turn clock off before power goes down */ 1485655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1486655babbdSDoug Anderson 148751da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 148851da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 148951da2240SYuvaraj CD 1490d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 149151da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 149251da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 149351da2240SYuvaraj CD 14944366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 14954366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 14964366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1497f95f3850SWill Newton break; 1498f95f3850SWill Newton default: 1499f95f3850SWill Newton break; 1500f95f3850SWill Newton } 1501655babbdSDoug Anderson 1502655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1503655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1504f95f3850SWill Newton } 1505f95f3850SWill Newton 150601730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 150701730558SDoug Anderson { 150801730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 150901730558SDoug Anderson u32 status; 151001730558SDoug Anderson 151101730558SDoug Anderson /* 151201730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 151301730558SDoug Anderson * (the data lines) are 0000 151401730558SDoug Anderson */ 151501730558SDoug Anderson status = mci_readl(slot->host, STATUS); 151601730558SDoug Anderson 151701730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 151801730558SDoug Anderson } 151901730558SDoug Anderson 152001730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 152101730558SDoug Anderson { 152201730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 152301730558SDoug Anderson struct dw_mci *host = slot->host; 15248f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 152501730558SDoug Anderson u32 uhs; 152601730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 152701730558SDoug Anderson int ret; 152801730558SDoug Anderson 15298f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 15308f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 15318f7849c4SZhangfei Gao 153201730558SDoug Anderson /* 153301730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 153401730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 153501730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 153601730558SDoug Anderson */ 153701730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1538e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 153901730558SDoug Anderson uhs &= ~v18; 1540e0848f5dSDouglas Anderson else 154101730558SDoug Anderson uhs |= v18; 1542e0848f5dSDouglas Anderson 154301730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1544e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 154501730558SDoug Anderson 154601730558SDoug Anderson if (ret) { 1547b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1548e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1549e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 155001730558SDoug Anderson return ret; 155101730558SDoug Anderson } 155201730558SDoug Anderson } 155301730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 155401730558SDoug Anderson 155501730558SDoug Anderson return 0; 155601730558SDoug Anderson } 155701730558SDoug Anderson 1558f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1559f95f3850SWill Newton { 1560f95f3850SWill Newton int read_only; 1561f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 15629795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1563f95f3850SWill Newton 1564f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1565287980e4SArnd Bergmann if (gpio_ro >= 0) 15669795a846SJaehoon Chung read_only = gpio_ro; 1567f95f3850SWill Newton else 1568f95f3850SWill Newton read_only = 1569f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1570f95f3850SWill Newton 1571f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1572f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1573f95f3850SWill Newton 1574f95f3850SWill Newton return read_only; 1575f95f3850SWill Newton } 1576f95f3850SWill Newton 1577935a665eSShawn Lin static void dw_mci_hw_reset(struct mmc_host *mmc) 1578935a665eSShawn Lin { 1579935a665eSShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 1580935a665eSShawn Lin struct dw_mci *host = slot->host; 1581935a665eSShawn Lin int reset; 1582935a665eSShawn Lin 1583935a665eSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 1584935a665eSShawn Lin dw_mci_idmac_reset(host); 1585935a665eSShawn Lin 1586935a665eSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1587935a665eSShawn Lin SDMMC_CTRL_FIFO_RESET)) 1588935a665eSShawn Lin return; 1589935a665eSShawn Lin 1590935a665eSShawn Lin /* 1591935a665eSShawn Lin * According to eMMC spec, card reset procedure: 1592935a665eSShawn Lin * tRstW >= 1us: RST_n pulse width 1593935a665eSShawn Lin * tRSCA >= 200us: RST_n to Command time 1594935a665eSShawn Lin * tRSTH >= 1us: RST_n high period 1595935a665eSShawn Lin */ 1596935a665eSShawn Lin reset = mci_readl(host, RST_N); 1597935a665eSShawn Lin reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1598935a665eSShawn Lin mci_writel(host, RST_N, reset); 1599935a665eSShawn Lin usleep_range(1, 2); 1600935a665eSShawn Lin reset |= SDMMC_RST_HWACTIVE << slot->id; 1601935a665eSShawn Lin mci_writel(host, RST_N, reset); 1602935a665eSShawn Lin usleep_range(200, 300); 1603935a665eSShawn Lin } 1604935a665eSShawn Lin 1605b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1606b24c8b26SDoug Anderson { 1607b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1608b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1609b24c8b26SDoug Anderson 16109623b5b9SDoug Anderson /* 16119623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 16129623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 16139623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 16149623b5b9SDoug Anderson */ 1615b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 16169623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1617b24c8b26SDoug Anderson u32 clk_en_a_old; 1618b24c8b26SDoug Anderson u32 clk_en_a; 16199623b5b9SDoug Anderson 1620b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 16219623b5b9SDoug Anderson 1622b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1623b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1624a6db2c86SDouglas Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) { 1625a6db2c86SDouglas Anderson pm_runtime_get_noresume(mmc->parent); 1626b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1627a6db2c86SDouglas Anderson } 1628b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1629b24c8b26SDoug Anderson } else { 1630a6db2c86SDouglas Anderson if (test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) { 1631a6db2c86SDouglas Anderson pm_runtime_put_noidle(mmc->parent); 1632b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1633a6db2c86SDouglas Anderson } 1634b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1635b24c8b26SDoug Anderson } 1636b24c8b26SDoug Anderson 1637b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1638b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 16399623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 16409623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 16419623b5b9SDoug Anderson } 16429623b5b9SDoug Anderson } 1643b24c8b26SDoug Anderson } 16449623b5b9SDoug Anderson 164532dba737SUlf Hansson static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 16461a5c8e1fSShashidhar Hiremath { 16471a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1648f8c58c11SDoug Anderson unsigned long irqflags; 16491a5c8e1fSShashidhar Hiremath u32 int_mask; 16501a5c8e1fSShashidhar Hiremath 1651f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1652f8c58c11SDoug Anderson 16531a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 16541a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1655b24c8b26SDoug Anderson if (enb) 1656b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1657b24c8b26SDoug Anderson else 1658b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1659b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1660f8c58c11SDoug Anderson 1661f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 16621a5c8e1fSShashidhar Hiremath } 16631a5c8e1fSShashidhar Hiremath 166432dba737SUlf Hansson static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 166532dba737SUlf Hansson { 166632dba737SUlf Hansson struct dw_mci_slot *slot = mmc_priv(mmc); 166732dba737SUlf Hansson 166832dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, enb); 166932dba737SUlf Hansson } 167032dba737SUlf Hansson 167132dba737SUlf Hansson static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 167232dba737SUlf Hansson { 167332dba737SUlf Hansson struct dw_mci_slot *slot = mmc_priv(mmc); 167432dba737SUlf Hansson 167532dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, 1); 167632dba737SUlf Hansson } 167732dba737SUlf Hansson 16780976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 16790976f16dSSeungwon Jeon { 16800976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 16810976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 16820976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 16830e3a22c0SShawn Lin int err = -EINVAL; 16840976f16dSSeungwon Jeon 16850976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 16869979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 16870976f16dSSeungwon Jeon return err; 16880976f16dSSeungwon Jeon } 16890976f16dSSeungwon Jeon 16900e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 16910e3a22c0SShawn Lin struct mmc_ios *ios) 169280113132SSeungwon Jeon { 169380113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 169480113132SSeungwon Jeon struct dw_mci *host = slot->host; 169580113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 169680113132SSeungwon Jeon 169780113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 169880113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 169980113132SSeungwon Jeon 170080113132SSeungwon Jeon return 0; 170180113132SSeungwon Jeon } 170280113132SSeungwon Jeon 17034e7392b2SShawn Lin static bool dw_mci_reset(struct dw_mci *host) 17044e7392b2SShawn Lin { 17054e7392b2SShawn Lin u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 17064e7392b2SShawn Lin bool ret = false; 1707bc2dcc1aSShawn Lin u32 status = 0; 17084e7392b2SShawn Lin 17094e7392b2SShawn Lin /* 17104e7392b2SShawn Lin * Resetting generates a block interrupt, hence setting 17114e7392b2SShawn Lin * the scatter-gather pointer to NULL. 17124e7392b2SShawn Lin */ 17134e7392b2SShawn Lin if (host->sg) { 17144e7392b2SShawn Lin sg_miter_stop(&host->sg_miter); 17154e7392b2SShawn Lin host->sg = NULL; 17164e7392b2SShawn Lin } 17174e7392b2SShawn Lin 17184e7392b2SShawn Lin if (host->use_dma) 17194e7392b2SShawn Lin flags |= SDMMC_CTRL_DMA_RESET; 17204e7392b2SShawn Lin 17214e7392b2SShawn Lin if (dw_mci_ctrl_reset(host, flags)) { 17224e7392b2SShawn Lin /* 1723bc2dcc1aSShawn Lin * In all cases we clear the RAWINTS 1724bc2dcc1aSShawn Lin * register to clear any interrupts. 17254e7392b2SShawn Lin */ 17264e7392b2SShawn Lin mci_writel(host, RINTSTS, 0xFFFFFFFF); 17274e7392b2SShawn Lin 1728bc2dcc1aSShawn Lin if (!host->use_dma) { 1729bc2dcc1aSShawn Lin ret = true; 1730bc2dcc1aSShawn Lin goto ciu_out; 1731bc2dcc1aSShawn Lin } 17324e7392b2SShawn Lin 1733bc2dcc1aSShawn Lin /* Wait for dma_req to be cleared */ 17344e7392b2SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 17354e7392b2SShawn Lin status, 17364e7392b2SShawn Lin !(status & SDMMC_STATUS_DMA_REQ), 17374e7392b2SShawn Lin 1, 500 * USEC_PER_MSEC)) { 17384e7392b2SShawn Lin dev_err(host->dev, 1739bc2dcc1aSShawn Lin "%s: Timeout waiting for dma_req to be cleared\n", 17404e7392b2SShawn Lin __func__); 17414e7392b2SShawn Lin goto ciu_out; 17424e7392b2SShawn Lin } 17434e7392b2SShawn Lin 17444e7392b2SShawn Lin /* when using DMA next we reset the fifo again */ 17454e7392b2SShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 17464e7392b2SShawn Lin goto ciu_out; 17474e7392b2SShawn Lin } else { 17484e7392b2SShawn Lin /* if the controller reset bit did clear, then set clock regs */ 17494e7392b2SShawn Lin if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 17504e7392b2SShawn Lin dev_err(host->dev, 17514e7392b2SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 17524e7392b2SShawn Lin __func__); 17534e7392b2SShawn Lin goto ciu_out; 17544e7392b2SShawn Lin } 17554e7392b2SShawn Lin } 17564e7392b2SShawn Lin 17574e7392b2SShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 17584e7392b2SShawn Lin /* It is also recommended that we reset and reprogram idmac */ 17594e7392b2SShawn Lin dw_mci_idmac_reset(host); 17604e7392b2SShawn Lin 17614e7392b2SShawn Lin ret = true; 17624e7392b2SShawn Lin 17634e7392b2SShawn Lin ciu_out: 17644e7392b2SShawn Lin /* After a CTRL reset we need to have CIU set clock registers */ 17654e7392b2SShawn Lin mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 17664e7392b2SShawn Lin 17674e7392b2SShawn Lin return ret; 17684e7392b2SShawn Lin } 17694e7392b2SShawn Lin 1770f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1771f95f3850SWill Newton .request = dw_mci_request, 17729aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 17739aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1774f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1775f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1776f95f3850SWill Newton .get_cd = dw_mci_get_cd, 1777935a665eSShawn Lin .hw_reset = dw_mci_hw_reset, 17781a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 177932dba737SUlf Hansson .ack_sdio_irq = dw_mci_ack_sdio_irq, 17800976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 178101730558SDoug Anderson .card_busy = dw_mci_card_busy, 178201730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1783b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 178480113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1785f95f3850SWill Newton }; 1786f95f3850SWill Newton 1787f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1788f95f3850SWill Newton __releases(&host->lock) 1789f95f3850SWill Newton __acquires(&host->lock) 1790f95f3850SWill Newton { 1791f95f3850SWill Newton struct dw_mci_slot *slot; 1792f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1793f95f3850SWill Newton 1794f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1795f95f3850SWill Newton 1796f95f3850SWill Newton host->cur_slot->mrq = NULL; 1797f95f3850SWill Newton host->mrq = NULL; 1798f95f3850SWill Newton if (!list_empty(&host->queue)) { 1799f95f3850SWill Newton slot = list_entry(host->queue.next, 1800f95f3850SWill Newton struct dw_mci_slot, queue_node); 1801f95f3850SWill Newton list_del(&slot->queue_node); 18024a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1803f95f3850SWill Newton mmc_hostname(slot->mmc)); 1804f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1805f95f3850SWill Newton dw_mci_start_request(host, slot); 1806f95f3850SWill Newton } else { 18074a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 180801730558SDoug Anderson 180901730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 181001730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 181101730558SDoug Anderson else 1812f95f3850SWill Newton host->state = STATE_IDLE; 1813f95f3850SWill Newton } 1814f95f3850SWill Newton 1815f95f3850SWill Newton spin_unlock(&host->lock); 1816f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1817f95f3850SWill Newton spin_lock(&host->lock); 1818f95f3850SWill Newton } 1819f95f3850SWill Newton 1820e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1821f95f3850SWill Newton { 1822f95f3850SWill Newton u32 status = host->cmd_status; 1823f95f3850SWill Newton 1824f95f3850SWill Newton host->cmd_status = 0; 1825f95f3850SWill Newton 1826f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1827f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1828f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1829f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1830f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1831f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1832f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1833f95f3850SWill Newton } else { 1834f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1835f95f3850SWill Newton cmd->resp[1] = 0; 1836f95f3850SWill Newton cmd->resp[2] = 0; 1837f95f3850SWill Newton cmd->resp[3] = 0; 1838f95f3850SWill Newton } 1839f95f3850SWill Newton } 1840f95f3850SWill Newton 1841f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1842f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1843f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1844f95f3850SWill Newton cmd->error = -EILSEQ; 1845f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1846f95f3850SWill Newton cmd->error = -EIO; 1847f95f3850SWill Newton else 1848f95f3850SWill Newton cmd->error = 0; 1849f95f3850SWill Newton 1850e352c813SSeungwon Jeon return cmd->error; 1851e352c813SSeungwon Jeon } 1852e352c813SSeungwon Jeon 1853e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1854e352c813SSeungwon Jeon { 185531bff450SSeungwon Jeon u32 status = host->data_status; 1856e352c813SSeungwon Jeon 1857e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1858e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1859e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1860e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1861e352c813SSeungwon Jeon data->error = -EILSEQ; 1862e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1863e352c813SSeungwon Jeon if (host->dir_status == 1864e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1865e352c813SSeungwon Jeon /* 1866e352c813SSeungwon Jeon * No data CRC status was returned. 1867e352c813SSeungwon Jeon * The number of bytes transferred 1868e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1869e352c813SSeungwon Jeon */ 1870e352c813SSeungwon Jeon data->bytes_xfered = 0; 1871e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1872e352c813SSeungwon Jeon } else if (host->dir_status == 1873e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1874e7a1dec1SShawn Lin data->error = -EILSEQ; 1875e352c813SSeungwon Jeon } 1876e352c813SSeungwon Jeon } else { 1877e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1878e7a1dec1SShawn Lin data->error = -EILSEQ; 1879e352c813SSeungwon Jeon } 1880e352c813SSeungwon Jeon 1881e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1882e352c813SSeungwon Jeon 1883e352c813SSeungwon Jeon /* 1884e352c813SSeungwon Jeon * After an error, there may be data lingering 188531bff450SSeungwon Jeon * in the FIFO 1886e352c813SSeungwon Jeon */ 18873a33a94cSSonny Rao dw_mci_reset(host); 1888e352c813SSeungwon Jeon } else { 1889e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1890e352c813SSeungwon Jeon data->error = 0; 1891e352c813SSeungwon Jeon } 1892e352c813SSeungwon Jeon 1893e352c813SSeungwon Jeon return data->error; 1894f95f3850SWill Newton } 1895f95f3850SWill Newton 189657e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 189757e10486SAddy Ke { 189857e10486SAddy Ke unsigned int drto_clks; 189957e10486SAddy Ke unsigned int drto_ms; 190057e10486SAddy Ke 190157e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 190257e10486SAddy Ke drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 190357e10486SAddy Ke 190457e10486SAddy Ke /* add a bit spare time */ 190557e10486SAddy Ke drto_ms += 10; 190657e10486SAddy Ke 190757e10486SAddy Ke mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 190857e10486SAddy Ke } 190957e10486SAddy Ke 1910f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1911f95f3850SWill Newton { 1912f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1913f95f3850SWill Newton struct mmc_data *data; 1914f95f3850SWill Newton struct mmc_command *cmd; 1915e352c813SSeungwon Jeon struct mmc_request *mrq; 1916f95f3850SWill Newton enum dw_mci_state state; 1917f95f3850SWill Newton enum dw_mci_state prev_state; 1918e352c813SSeungwon Jeon unsigned int err; 1919f95f3850SWill Newton 1920f95f3850SWill Newton spin_lock(&host->lock); 1921f95f3850SWill Newton 1922f95f3850SWill Newton state = host->state; 1923f95f3850SWill Newton data = host->data; 1924e352c813SSeungwon Jeon mrq = host->mrq; 1925f95f3850SWill Newton 1926f95f3850SWill Newton do { 1927f95f3850SWill Newton prev_state = state; 1928f95f3850SWill Newton 1929f95f3850SWill Newton switch (state) { 1930f95f3850SWill Newton case STATE_IDLE: 193101730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1932f95f3850SWill Newton break; 1933f95f3850SWill Newton 193401730558SDoug Anderson case STATE_SENDING_CMD11: 1935f95f3850SWill Newton case STATE_SENDING_CMD: 1936f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1937f95f3850SWill Newton &host->pending_events)) 1938f95f3850SWill Newton break; 1939f95f3850SWill Newton 1940f95f3850SWill Newton cmd = host->cmd; 1941f95f3850SWill Newton host->cmd = NULL; 1942f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1943e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1944e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1945053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1946053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1947e352c813SSeungwon Jeon mrq->cmd); 1948053b3ce6SSeungwon Jeon goto unlock; 1949053b3ce6SSeungwon Jeon } 1950053b3ce6SSeungwon Jeon 1951e352c813SSeungwon Jeon if (cmd->data && err) { 195246d17952SDoug Anderson /* 195346d17952SDoug Anderson * During UHS tuning sequence, sending the stop 195446d17952SDoug Anderson * command after the response CRC error would 195546d17952SDoug Anderson * throw the system into a confused state 195646d17952SDoug Anderson * causing all future tuning phases to report 195746d17952SDoug Anderson * failure. 195846d17952SDoug Anderson * 195946d17952SDoug Anderson * In such case controller will move into a data 196046d17952SDoug Anderson * transfer state after a response error or 196146d17952SDoug Anderson * response CRC error. Let's let that finish 196246d17952SDoug Anderson * before trying to send a stop, so we'll go to 196346d17952SDoug Anderson * STATE_SENDING_DATA. 196446d17952SDoug Anderson * 196546d17952SDoug Anderson * Although letting the data transfer take place 196646d17952SDoug Anderson * will waste a bit of time (we already know 196746d17952SDoug Anderson * the command was bad), it can't cause any 196846d17952SDoug Anderson * errors since it's possible it would have 196946d17952SDoug Anderson * taken place anyway if this tasklet got 197046d17952SDoug Anderson * delayed. Allowing the transfer to take place 197146d17952SDoug Anderson * avoids races and keeps things simple. 197246d17952SDoug Anderson */ 197346d17952SDoug Anderson if ((err != -ETIMEDOUT) && 197446d17952SDoug Anderson (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 197546d17952SDoug Anderson state = STATE_SENDING_DATA; 197646d17952SDoug Anderson continue; 197746d17952SDoug Anderson } 197846d17952SDoug Anderson 197971abb133SSeungwon Jeon dw_mci_stop_dma(host); 198090c2143aSSeungwon Jeon send_stop_abort(host, data); 198171abb133SSeungwon Jeon state = STATE_SENDING_STOP; 198271abb133SSeungwon Jeon break; 198371abb133SSeungwon Jeon } 198471abb133SSeungwon Jeon 1985e352c813SSeungwon Jeon if (!cmd->data || err) { 1986e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1987f95f3850SWill Newton goto unlock; 1988f95f3850SWill Newton } 1989f95f3850SWill Newton 1990f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1991f95f3850SWill Newton /* fall through */ 1992f95f3850SWill Newton 1993f95f3850SWill Newton case STATE_SENDING_DATA: 19942aa35465SDoug Anderson /* 19952aa35465SDoug Anderson * We could get a data error and never a transfer 19962aa35465SDoug Anderson * complete so we'd better check for it here. 19972aa35465SDoug Anderson * 19982aa35465SDoug Anderson * Note that we don't really care if we also got a 19992aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 20002aa35465SDoug Anderson * abort won't hurt. 20012aa35465SDoug Anderson */ 2002f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 2003f95f3850SWill Newton &host->pending_events)) { 2004f95f3850SWill Newton dw_mci_stop_dma(host); 2005e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2006bdb9a90bSaddy ke SDMMC_INT_EBE))) 200790c2143aSSeungwon Jeon send_stop_abort(host, data); 2008f95f3850SWill Newton state = STATE_DATA_ERROR; 2009f95f3850SWill Newton break; 2010f95f3850SWill Newton } 2011f95f3850SWill Newton 2012f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 201357e10486SAddy Ke &host->pending_events)) { 201457e10486SAddy Ke /* 201557e10486SAddy Ke * If all data-related interrupts don't come 201657e10486SAddy Ke * within the given time in reading data state. 201757e10486SAddy Ke */ 201816a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 201957e10486SAddy Ke dw_mci_set_drto(host); 2020f95f3850SWill Newton break; 202157e10486SAddy Ke } 2022f95f3850SWill Newton 2023f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 20242aa35465SDoug Anderson 20252aa35465SDoug Anderson /* 20262aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 20272aa35465SDoug Anderson * before the transfer completed. This might not have 20282aa35465SDoug Anderson * been caught by the check above because the interrupt 20292aa35465SDoug Anderson * could have gone off between the previous check and 20302aa35465SDoug Anderson * the check for transfer complete. 20312aa35465SDoug Anderson * 20322aa35465SDoug Anderson * Technically this ought not be needed assuming we 20332aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 20342aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 20352aa35465SDoug Anderson * 20362aa35465SDoug Anderson * This has the advantage of sending the stop command. 20372aa35465SDoug Anderson */ 20382aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 20392aa35465SDoug Anderson &host->pending_events)) { 20402aa35465SDoug Anderson dw_mci_stop_dma(host); 2041e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2042bdb9a90bSaddy ke SDMMC_INT_EBE))) 20432aa35465SDoug Anderson send_stop_abort(host, data); 20442aa35465SDoug Anderson state = STATE_DATA_ERROR; 20452aa35465SDoug Anderson break; 20462aa35465SDoug Anderson } 2047f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 20482aa35465SDoug Anderson 2049f95f3850SWill Newton /* fall through */ 2050f95f3850SWill Newton 2051f95f3850SWill Newton case STATE_DATA_BUSY: 2052f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 205357e10486SAddy Ke &host->pending_events)) { 205457e10486SAddy Ke /* 205557e10486SAddy Ke * If data error interrupt comes but data over 205657e10486SAddy Ke * interrupt doesn't come within the given time. 205757e10486SAddy Ke * in reading data state. 205857e10486SAddy Ke */ 205916a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 206057e10486SAddy Ke dw_mci_set_drto(host); 2061f95f3850SWill Newton break; 206257e10486SAddy Ke } 2063f95f3850SWill Newton 2064f95f3850SWill Newton host->data = NULL; 2065f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2066e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 2067f95f3850SWill Newton 2068e352c813SSeungwon Jeon if (!err) { 2069e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 207017c8bc85SSachin Kamat if (mrq->sbc && data->stop) 2071053b3ce6SSeungwon Jeon data->stop->error = 0; 2072e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2073053b3ce6SSeungwon Jeon goto unlock; 2074053b3ce6SSeungwon Jeon } 2075053b3ce6SSeungwon Jeon 207690c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 2077e352c813SSeungwon Jeon if (data->stop) 207890c2143aSSeungwon Jeon send_stop_abort(host, data); 20792aa35465SDoug Anderson } else { 20802aa35465SDoug Anderson /* 20812aa35465SDoug Anderson * If we don't have a command complete now we'll 20822aa35465SDoug Anderson * never get one since we just reset everything; 20832aa35465SDoug Anderson * better end the request. 20842aa35465SDoug Anderson * 20852aa35465SDoug Anderson * If we do have a command complete we'll fall 20862aa35465SDoug Anderson * through to the SENDING_STOP command and 20872aa35465SDoug Anderson * everything will be peachy keen. 20882aa35465SDoug Anderson */ 20892aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 20902aa35465SDoug Anderson &host->pending_events)) { 20912aa35465SDoug Anderson host->cmd = NULL; 20922aa35465SDoug Anderson dw_mci_request_end(host, mrq); 20932aa35465SDoug Anderson goto unlock; 20942aa35465SDoug Anderson } 209590c2143aSSeungwon Jeon } 2096e352c813SSeungwon Jeon 2097e352c813SSeungwon Jeon /* 2098e352c813SSeungwon Jeon * If err has non-zero, 2099e352c813SSeungwon Jeon * stop-abort command has been already issued. 2100e352c813SSeungwon Jeon */ 2101e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 2102e352c813SSeungwon Jeon 2103f95f3850SWill Newton /* fall through */ 2104f95f3850SWill Newton 2105f95f3850SWill Newton case STATE_SENDING_STOP: 2106f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 2107f95f3850SWill Newton &host->pending_events)) 2108f95f3850SWill Newton break; 2109f95f3850SWill Newton 211071abb133SSeungwon Jeon /* CMD error in data command */ 211131bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 21123a33a94cSSonny Rao dw_mci_reset(host); 211371abb133SSeungwon Jeon 2114f95f3850SWill Newton host->cmd = NULL; 211571abb133SSeungwon Jeon host->data = NULL; 211690c2143aSSeungwon Jeon 2117e13c3c08SJaehoon Chung if (!mrq->sbc && mrq->stop) 2118e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 211990c2143aSSeungwon Jeon else 212090c2143aSSeungwon Jeon host->cmd_status = 0; 212190c2143aSSeungwon Jeon 2122e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2123f95f3850SWill Newton goto unlock; 2124f95f3850SWill Newton 2125f95f3850SWill Newton case STATE_DATA_ERROR: 2126f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2127f95f3850SWill Newton &host->pending_events)) 2128f95f3850SWill Newton break; 2129f95f3850SWill Newton 2130f95f3850SWill Newton state = STATE_DATA_BUSY; 2131f95f3850SWill Newton break; 2132f95f3850SWill Newton } 2133f95f3850SWill Newton } while (state != prev_state); 2134f95f3850SWill Newton 2135f95f3850SWill Newton host->state = state; 2136f95f3850SWill Newton unlock: 2137f95f3850SWill Newton spin_unlock(&host->lock); 2138f95f3850SWill Newton 2139f95f3850SWill Newton } 2140f95f3850SWill Newton 214134b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 214234b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 214334b664a2SJames Hogan { 214434b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 214534b664a2SJames Hogan host->part_buf_count = cnt; 214634b664a2SJames Hogan } 214734b664a2SJames Hogan 214834b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 214934b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 215034b664a2SJames Hogan { 215134b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 215234b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 215334b664a2SJames Hogan host->part_buf_count += cnt; 215434b664a2SJames Hogan return cnt; 215534b664a2SJames Hogan } 215634b664a2SJames Hogan 215734b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 215834b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 215934b664a2SJames Hogan { 21600e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 216134b664a2SJames Hogan if (cnt) { 216234b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 216334b664a2SJames Hogan cnt); 216434b664a2SJames Hogan host->part_buf_count -= cnt; 216534b664a2SJames Hogan host->part_buf_start += cnt; 216634b664a2SJames Hogan } 216734b664a2SJames Hogan return cnt; 216834b664a2SJames Hogan } 216934b664a2SJames Hogan 217034b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 217134b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 217234b664a2SJames Hogan { 217334b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 217434b664a2SJames Hogan host->part_buf_start = cnt; 217534b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 217634b664a2SJames Hogan } 217734b664a2SJames Hogan 2178f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2179f95f3850SWill Newton { 2180cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2181cfbeb59cSMarkos Chandras int init_cnt = cnt; 2182cfbeb59cSMarkos Chandras 218334b664a2SJames Hogan /* try and push anything in the part_buf */ 218434b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 218534b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 21860e3a22c0SShawn Lin 218734b664a2SJames Hogan buf += len; 218834b664a2SJames Hogan cnt -= len; 2189cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 219076184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 219134b664a2SJames Hogan host->part_buf_count = 0; 219234b664a2SJames Hogan } 219334b664a2SJames Hogan } 219434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 219534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 219634b664a2SJames Hogan while (cnt >= 2) { 219734b664a2SJames Hogan u16 aligned_buf[64]; 219834b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 219934b664a2SJames Hogan int items = len >> 1; 220034b664a2SJames Hogan int i; 220134b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 220234b664a2SJames Hogan memcpy(aligned_buf, buf, len); 220334b664a2SJames Hogan buf += len; 220434b664a2SJames Hogan cnt -= len; 220534b664a2SJames Hogan /* push data from aligned buffer into fifo */ 220634b664a2SJames Hogan for (i = 0; i < items; ++i) 220776184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 220834b664a2SJames Hogan } 220934b664a2SJames Hogan } else 221034b664a2SJames Hogan #endif 221134b664a2SJames Hogan { 221234b664a2SJames Hogan u16 *pdata = buf; 22130e3a22c0SShawn Lin 221434b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 221576184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 221634b664a2SJames Hogan buf = pdata; 221734b664a2SJames Hogan } 221834b664a2SJames Hogan /* put anything remaining in the part_buf */ 221934b664a2SJames Hogan if (cnt) { 222034b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2221cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2222cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2223cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 222476184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 2225f95f3850SWill Newton } 2226f95f3850SWill Newton } 2227f95f3850SWill Newton 2228f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2229f95f3850SWill Newton { 223034b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 223134b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 223234b664a2SJames Hogan while (cnt >= 2) { 223334b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 223434b664a2SJames Hogan u16 aligned_buf[64]; 223534b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 223634b664a2SJames Hogan int items = len >> 1; 223734b664a2SJames Hogan int i; 22380e3a22c0SShawn Lin 223934b664a2SJames Hogan for (i = 0; i < items; ++i) 224076184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 224134b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 224234b664a2SJames Hogan memcpy(buf, aligned_buf, len); 224334b664a2SJames Hogan buf += len; 224434b664a2SJames Hogan cnt -= len; 224534b664a2SJames Hogan } 224634b664a2SJames Hogan } else 224734b664a2SJames Hogan #endif 224834b664a2SJames Hogan { 224934b664a2SJames Hogan u16 *pdata = buf; 22500e3a22c0SShawn Lin 225134b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 225276184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 225334b664a2SJames Hogan buf = pdata; 225434b664a2SJames Hogan } 225534b664a2SJames Hogan if (cnt) { 225676184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 225734b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2258f95f3850SWill Newton } 2259f95f3850SWill Newton } 2260f95f3850SWill Newton 2261f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2262f95f3850SWill Newton { 2263cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2264cfbeb59cSMarkos Chandras int init_cnt = cnt; 2265cfbeb59cSMarkos Chandras 226634b664a2SJames Hogan /* try and push anything in the part_buf */ 226734b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 226834b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 22690e3a22c0SShawn Lin 227034b664a2SJames Hogan buf += len; 227134b664a2SJames Hogan cnt -= len; 2272cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 227376184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 227434b664a2SJames Hogan host->part_buf_count = 0; 227534b664a2SJames Hogan } 227634b664a2SJames Hogan } 227734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 227834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 227934b664a2SJames Hogan while (cnt >= 4) { 228034b664a2SJames Hogan u32 aligned_buf[32]; 228134b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 228234b664a2SJames Hogan int items = len >> 2; 228334b664a2SJames Hogan int i; 228434b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 228534b664a2SJames Hogan memcpy(aligned_buf, buf, len); 228634b664a2SJames Hogan buf += len; 228734b664a2SJames Hogan cnt -= len; 228834b664a2SJames Hogan /* push data from aligned buffer into fifo */ 228934b664a2SJames Hogan for (i = 0; i < items; ++i) 229076184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 229134b664a2SJames Hogan } 229234b664a2SJames Hogan } else 229334b664a2SJames Hogan #endif 229434b664a2SJames Hogan { 229534b664a2SJames Hogan u32 *pdata = buf; 22960e3a22c0SShawn Lin 229734b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 229876184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 229934b664a2SJames Hogan buf = pdata; 230034b664a2SJames Hogan } 230134b664a2SJames Hogan /* put anything remaining in the part_buf */ 230234b664a2SJames Hogan if (cnt) { 230334b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2304cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2305cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2306cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 230776184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2308f95f3850SWill Newton } 2309f95f3850SWill Newton } 2310f95f3850SWill Newton 2311f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2312f95f3850SWill Newton { 231334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 231434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 231534b664a2SJames Hogan while (cnt >= 4) { 231634b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 231734b664a2SJames Hogan u32 aligned_buf[32]; 231834b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 231934b664a2SJames Hogan int items = len >> 2; 232034b664a2SJames Hogan int i; 23210e3a22c0SShawn Lin 232234b664a2SJames Hogan for (i = 0; i < items; ++i) 232376184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 232434b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 232534b664a2SJames Hogan memcpy(buf, aligned_buf, len); 232634b664a2SJames Hogan buf += len; 232734b664a2SJames Hogan cnt -= len; 232834b664a2SJames Hogan } 232934b664a2SJames Hogan } else 233034b664a2SJames Hogan #endif 233134b664a2SJames Hogan { 233234b664a2SJames Hogan u32 *pdata = buf; 23330e3a22c0SShawn Lin 233434b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 233576184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 233634b664a2SJames Hogan buf = pdata; 233734b664a2SJames Hogan } 233834b664a2SJames Hogan if (cnt) { 233976184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 234034b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2341f95f3850SWill Newton } 2342f95f3850SWill Newton } 2343f95f3850SWill Newton 2344f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2345f95f3850SWill Newton { 2346cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2347cfbeb59cSMarkos Chandras int init_cnt = cnt; 2348cfbeb59cSMarkos Chandras 234934b664a2SJames Hogan /* try and push anything in the part_buf */ 235034b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 235134b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 23520e3a22c0SShawn Lin 235334b664a2SJames Hogan buf += len; 235434b664a2SJames Hogan cnt -= len; 2355c09fbd74SSeungwon Jeon 2356cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 235776184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 235834b664a2SJames Hogan host->part_buf_count = 0; 235934b664a2SJames Hogan } 236034b664a2SJames Hogan } 236134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 236234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 236334b664a2SJames Hogan while (cnt >= 8) { 236434b664a2SJames Hogan u64 aligned_buf[16]; 236534b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 236634b664a2SJames Hogan int items = len >> 3; 236734b664a2SJames Hogan int i; 236834b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 236934b664a2SJames Hogan memcpy(aligned_buf, buf, len); 237034b664a2SJames Hogan buf += len; 237134b664a2SJames Hogan cnt -= len; 237234b664a2SJames Hogan /* push data from aligned buffer into fifo */ 237334b664a2SJames Hogan for (i = 0; i < items; ++i) 237476184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 237534b664a2SJames Hogan } 237634b664a2SJames Hogan } else 237734b664a2SJames Hogan #endif 237834b664a2SJames Hogan { 237934b664a2SJames Hogan u64 *pdata = buf; 23800e3a22c0SShawn Lin 238134b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 238276184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 238334b664a2SJames Hogan buf = pdata; 238434b664a2SJames Hogan } 238534b664a2SJames Hogan /* put anything remaining in the part_buf */ 238634b664a2SJames Hogan if (cnt) { 238734b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2388cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2389cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2390cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 239176184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2392f95f3850SWill Newton } 2393f95f3850SWill Newton } 2394f95f3850SWill Newton 2395f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2396f95f3850SWill Newton { 239734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 239834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 239934b664a2SJames Hogan while (cnt >= 8) { 240034b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 240134b664a2SJames Hogan u64 aligned_buf[16]; 240234b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 240334b664a2SJames Hogan int items = len >> 3; 240434b664a2SJames Hogan int i; 24050e3a22c0SShawn Lin 240634b664a2SJames Hogan for (i = 0; i < items; ++i) 240776184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 240876184ac1SBen Dooks 240934b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 241034b664a2SJames Hogan memcpy(buf, aligned_buf, len); 241134b664a2SJames Hogan buf += len; 241234b664a2SJames Hogan cnt -= len; 2413f95f3850SWill Newton } 241434b664a2SJames Hogan } else 241534b664a2SJames Hogan #endif 241634b664a2SJames Hogan { 241734b664a2SJames Hogan u64 *pdata = buf; 24180e3a22c0SShawn Lin 241934b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 242076184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 242134b664a2SJames Hogan buf = pdata; 242234b664a2SJames Hogan } 242334b664a2SJames Hogan if (cnt) { 242476184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 242534b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 242634b664a2SJames Hogan } 242734b664a2SJames Hogan } 242834b664a2SJames Hogan 242934b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 243034b664a2SJames Hogan { 243134b664a2SJames Hogan int len; 243234b664a2SJames Hogan 243334b664a2SJames Hogan /* get remaining partial bytes */ 243434b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 243534b664a2SJames Hogan if (unlikely(len == cnt)) 243634b664a2SJames Hogan return; 243734b664a2SJames Hogan buf += len; 243834b664a2SJames Hogan cnt -= len; 243934b664a2SJames Hogan 244034b664a2SJames Hogan /* get the rest of the data */ 244134b664a2SJames Hogan host->pull_data(host, buf, cnt); 2442f95f3850SWill Newton } 2443f95f3850SWill Newton 244487a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2445f95f3850SWill Newton { 2446f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2447f9c2a0dcSSeungwon Jeon void *buf; 2448f9c2a0dcSSeungwon Jeon unsigned int offset; 2449f95f3850SWill Newton struct mmc_data *data = host->data; 2450f95f3850SWill Newton int shift = host->data_shift; 2451f95f3850SWill Newton u32 status; 24523e4b0d8bSMarkos Chandras unsigned int len; 2453f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2454f95f3850SWill Newton 2455f95f3850SWill Newton do { 2456f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2457f9c2a0dcSSeungwon Jeon goto done; 2458f95f3850SWill Newton 24594225fc85SImre Deak host->sg = sg_miter->piter.sg; 2460f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2461f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2462f9c2a0dcSSeungwon Jeon offset = 0; 2463f9c2a0dcSSeungwon Jeon 2464f9c2a0dcSSeungwon Jeon do { 2465f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2466f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2467f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2468f9c2a0dcSSeungwon Jeon if (!len) 2469f9c2a0dcSSeungwon Jeon break; 2470f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 24713e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2472f95f3850SWill Newton offset += len; 2473f9c2a0dcSSeungwon Jeon remain -= len; 2474f9c2a0dcSSeungwon Jeon } while (remain); 2475f95f3850SWill Newton 2476e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2477f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2478f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 247987a74d39SKyoungil Kim /* if the RXDR is ready read again */ 248087a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 248187a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2482f9c2a0dcSSeungwon Jeon 2483f9c2a0dcSSeungwon Jeon if (!remain) { 2484f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2485f9c2a0dcSSeungwon Jeon goto done; 2486f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2487f9c2a0dcSSeungwon Jeon } 2488f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2489f95f3850SWill Newton return; 2490f95f3850SWill Newton 2491f95f3850SWill Newton done: 2492f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2493f9c2a0dcSSeungwon Jeon host->sg = NULL; 24940e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2495f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2496f95f3850SWill Newton } 2497f95f3850SWill Newton 2498f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2499f95f3850SWill Newton { 2500f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2501f9c2a0dcSSeungwon Jeon void *buf; 2502f9c2a0dcSSeungwon Jeon unsigned int offset; 2503f95f3850SWill Newton struct mmc_data *data = host->data; 2504f95f3850SWill Newton int shift = host->data_shift; 2505f95f3850SWill Newton u32 status; 25063e4b0d8bSMarkos Chandras unsigned int len; 2507f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2508f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2509f95f3850SWill Newton 2510f95f3850SWill Newton do { 2511f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2512f9c2a0dcSSeungwon Jeon goto done; 2513f95f3850SWill Newton 25144225fc85SImre Deak host->sg = sg_miter->piter.sg; 2515f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2516f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2517f9c2a0dcSSeungwon Jeon offset = 0; 2518f9c2a0dcSSeungwon Jeon 2519f9c2a0dcSSeungwon Jeon do { 2520f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2521f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2522f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2523f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2524f9c2a0dcSSeungwon Jeon if (!len) 2525f9c2a0dcSSeungwon Jeon break; 2526f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 25273e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2528f95f3850SWill Newton offset += len; 2529f9c2a0dcSSeungwon Jeon remain -= len; 2530f9c2a0dcSSeungwon Jeon } while (remain); 2531f95f3850SWill Newton 2532e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2533f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2534f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2535f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2536f9c2a0dcSSeungwon Jeon 2537f9c2a0dcSSeungwon Jeon if (!remain) { 2538f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2539f9c2a0dcSSeungwon Jeon goto done; 2540f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2541f9c2a0dcSSeungwon Jeon } 2542f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2543f95f3850SWill Newton return; 2544f95f3850SWill Newton 2545f95f3850SWill Newton done: 2546f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2547f9c2a0dcSSeungwon Jeon host->sg = NULL; 25480e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2549f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2550f95f3850SWill Newton } 2551f95f3850SWill Newton 2552f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2553f95f3850SWill Newton { 2554f95f3850SWill Newton if (!host->cmd_status) 2555f95f3850SWill Newton host->cmd_status = status; 2556f95f3850SWill Newton 25570e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2558f95f3850SWill Newton 2559f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2560f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2561f95f3850SWill Newton } 2562f95f3850SWill Newton 25636130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 25646130e7a9SDoug Anderson { 25656130e7a9SDoug Anderson int i; 25666130e7a9SDoug Anderson 25676130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 25686130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 25696130e7a9SDoug Anderson 25706130e7a9SDoug Anderson if (!slot) 25716130e7a9SDoug Anderson continue; 25726130e7a9SDoug Anderson 25736130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 25746130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 25756130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 25766130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 25776130e7a9SDoug Anderson } 25786130e7a9SDoug Anderson } 25796130e7a9SDoug Anderson 2580f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2581f95f3850SWill Newton { 2582f95f3850SWill Newton struct dw_mci *host = dev_id; 2583182c9081SSeungwon Jeon u32 pending; 25841a5c8e1fSShashidhar Hiremath int i; 2585f95f3850SWill Newton 2586f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2587f95f3850SWill Newton 2588476d79f1SDoug Anderson if (pending) { 258901730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 259001730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 259101730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 259249ba0302SDoug Anderson unsigned long irqflags; 25935c935165SDoug Anderson 259401730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 259501730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 259649ba0302SDoug Anderson 259749ba0302SDoug Anderson /* 259849ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 259949ba0302SDoug Anderson * off after the lock is released, so safe to delete. 260049ba0302SDoug Anderson */ 260149ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 260201730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 260349ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 260449ba0302SDoug Anderson 260549ba0302SDoug Anderson del_timer(&host->cmd11_timer); 260601730558SDoug Anderson } 260701730558SDoug Anderson 2608f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2609f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2610182c9081SSeungwon Jeon host->cmd_status = pending; 26110e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2612f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2613f95f3850SWill Newton } 2614f95f3850SWill Newton 2615f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2616f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2617f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2618182c9081SSeungwon Jeon host->data_status = pending; 26190e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2620f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2621f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2622f95f3850SWill Newton } 2623f95f3850SWill Newton 2624f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 262557e10486SAddy Ke del_timer(&host->dto_timer); 262657e10486SAddy Ke 2627f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2628f95f3850SWill Newton if (!host->data_status) 2629182c9081SSeungwon Jeon host->data_status = pending; 26300e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2631f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2632f95f3850SWill Newton if (host->sg != NULL) 263387a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2634f95f3850SWill Newton } 2635f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2636f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2637f95f3850SWill Newton } 2638f95f3850SWill Newton 2639f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2640f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2641b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 264287a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2643f95f3850SWill Newton } 2644f95f3850SWill Newton 2645f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2646f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2647b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2648f95f3850SWill Newton dw_mci_write_data_pio(host); 2649f95f3850SWill Newton } 2650f95f3850SWill Newton 2651f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2652f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2653182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2654f95f3850SWill Newton } 2655f95f3850SWill Newton 2656f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2657f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 26586130e7a9SDoug Anderson dw_mci_handle_cd(host); 2659f95f3850SWill Newton } 2660f95f3850SWill Newton 26611a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 26621a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 26631a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 2664ed2540efSDoug Anderson 2665ed2540efSDoug Anderson if (!slot) 2666ed2540efSDoug Anderson continue; 2667ed2540efSDoug Anderson 266876756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 266976756234SAddy Ke mci_writel(host, RINTSTS, 267076756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 267132dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, 0); 267232dba737SUlf Hansson sdio_signal_irq(slot->mmc); 26731a5c8e1fSShashidhar Hiremath } 26741a5c8e1fSShashidhar Hiremath } 26751a5c8e1fSShashidhar Hiremath 26761fb5f68aSMarkos Chandras } 2677f95f3850SWill Newton 26783fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 26793fc7eaefSShawn Lin return IRQ_HANDLED; 26803fc7eaefSShawn Lin 26813fc7eaefSShawn Lin /* Handle IDMA interrupts */ 268269d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 268369d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 268469d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 268569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 268669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 268769d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2688faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 26893fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 269069d99fdcSPrabu Thangamuthu } 269169d99fdcSPrabu Thangamuthu } else { 2692f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2693f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 269469d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 269569d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2696f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2697faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 26983fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2699f95f3850SWill Newton } 270069d99fdcSPrabu Thangamuthu } 2701f95f3850SWill Newton 2702f95f3850SWill Newton return IRQ_HANDLED; 2703f95f3850SWill Newton } 2704f95f3850SWill Newton 270536c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2706f95f3850SWill Newton { 2707f95f3850SWill Newton struct mmc_host *mmc; 2708f95f3850SWill Newton struct dw_mci_slot *slot; 2709e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2710800d78bfSThomas Abraham int ctrl_id, ret; 27111f44a2a5SSeungwon Jeon u32 freq[2]; 2712f95f3850SWill Newton 27134a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2714f95f3850SWill Newton if (!mmc) 2715f95f3850SWill Newton return -ENOMEM; 2716f95f3850SWill Newton 2717f95f3850SWill Newton slot = mmc_priv(mmc); 2718f95f3850SWill Newton slot->id = id; 271976756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2720f95f3850SWill Newton slot->mmc = mmc; 2721f95f3850SWill Newton slot->host = host; 2722c91eab4bSThomas Abraham host->slot[id] = slot; 2723f95f3850SWill Newton 2724f95f3850SWill Newton mmc->ops = &dw_mci_ops; 27251f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 27261f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 27271f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 27281f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 27291f44a2a5SSeungwon Jeon } else { 2730b023030fSJaehoon Chung dev_info(host->dev, 2731b023030fSJaehoon Chung "'clock-freq-min-max' property was deprecated.\n"); 27321f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 27331f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 27341f44a2a5SSeungwon Jeon } 2735f95f3850SWill Newton 273651da2240SYuvaraj CD /*if there are external regulators, get them*/ 273751da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 273851da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 27393cf890fcSDoug Anderson goto err_host_allocated; 274051da2240SYuvaraj CD 274151da2240SYuvaraj CD if (!mmc->ocr_avail) 2742f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2743f95f3850SWill Newton 2744fc3d7720SJaehoon Chung if (host->pdata->caps) 2745fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2746fc3d7720SJaehoon Chung 27476024e166SJaehoon Chung /* 27486024e166SJaehoon Chung * Support MMC_CAP_ERASE by default. 27496024e166SJaehoon Chung * It needs to use trim/discard/erase commands. 27506024e166SJaehoon Chung */ 27516024e166SJaehoon Chung mmc->caps |= MMC_CAP_ERASE; 27526024e166SJaehoon Chung 2753ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2754ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2755ab269128SAbhilash Kesavan 2756800d78bfSThomas Abraham if (host->dev->of_node) { 2757800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2758800d78bfSThomas Abraham if (ctrl_id < 0) 2759800d78bfSThomas Abraham ctrl_id = 0; 2760800d78bfSThomas Abraham } else { 2761800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2762800d78bfSThomas Abraham } 2763cb27a843SJames Hogan if (drv_data && drv_data->caps) 2764cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2765800d78bfSThomas Abraham 27664f408cc6SSeungwon Jeon if (host->pdata->caps2) 27674f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 27684f408cc6SSeungwon Jeon 27693cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 27703cf890fcSDoug Anderson if (ret) 27713cf890fcSDoug Anderson goto err_host_allocated; 2772f95f3850SWill Newton 277332dba737SUlf Hansson /* Process SDIO IRQs through the sdio_irq_work. */ 277432dba737SUlf Hansson if (mmc->caps & MMC_CAP_SDIO_IRQ) 277532dba737SUlf Hansson mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 277632dba737SUlf Hansson 2777f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 27783fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2779a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2780225faf87SJaehoon Chung mmc->max_blk_size = 65535; 2781575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 27821a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 27831a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 27843fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 27853fc7eaefSShawn Lin mmc->max_segs = 64; 2786225faf87SJaehoon Chung mmc->max_blk_size = 65535; 27873fc7eaefSShawn Lin mmc->max_blk_count = 65535; 27883fc7eaefSShawn Lin mmc->max_req_size = 27893fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 27903fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2791575c319dSHeiko Stuebner } else { 27923fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2793f95f3850SWill Newton mmc->max_segs = 64; 2794225faf87SJaehoon Chung mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2795f95f3850SWill Newton mmc->max_blk_count = 512; 2796575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2797575c319dSHeiko Stuebner mmc->max_blk_count; 2798f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2799575c319dSHeiko Stuebner } 2800f95f3850SWill Newton 2801c0834a58SShawn Lin dw_mci_get_cd(mmc); 2802ae0eb348SJaehoon Chung 28030cea529dSJaehoon Chung ret = mmc_add_host(mmc); 28040cea529dSJaehoon Chung if (ret) 28053cf890fcSDoug Anderson goto err_host_allocated; 2806f95f3850SWill Newton 2807f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2808f95f3850SWill Newton dw_mci_init_debugfs(slot); 2809f95f3850SWill Newton #endif 2810f95f3850SWill Newton 2811f95f3850SWill Newton return 0; 2812800d78bfSThomas Abraham 28133cf890fcSDoug Anderson err_host_allocated: 2814800d78bfSThomas Abraham mmc_free_host(mmc); 281551da2240SYuvaraj CD return ret; 2816f95f3850SWill Newton } 2817f95f3850SWill Newton 2818f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2819f95f3850SWill Newton { 2820f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2821f95f3850SWill Newton mmc_remove_host(slot->mmc); 2822f95f3850SWill Newton slot->host->slot[id] = NULL; 2823f95f3850SWill Newton mmc_free_host(slot->mmc); 2824f95f3850SWill Newton } 2825f95f3850SWill Newton 2826f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2827f95f3850SWill Newton { 282869d99fdcSPrabu Thangamuthu int addr_config; 28293fc7eaefSShawn Lin struct device *dev = host->dev; 28303fc7eaefSShawn Lin struct device_node *np = dev->of_node; 28313fc7eaefSShawn Lin 28323fc7eaefSShawn Lin /* 28333fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 28343fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 28353fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 28363fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 28373fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 28383fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 28393fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 28403fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 28413fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 28423fc7eaefSShawn Lin */ 28433fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 28443fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 28453fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 28463fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 28473fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 28483fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 28493fc7eaefSShawn Lin } else { 28503fc7eaefSShawn Lin goto no_dma; 28513fc7eaefSShawn Lin } 28523fc7eaefSShawn Lin 28533fc7eaefSShawn Lin /* Determine which DMA interface to use */ 28543fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 28553fc7eaefSShawn Lin /* 28563fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 28573fc7eaefSShawn Lin * IDMAC address bus width 28583fc7eaefSShawn Lin */ 285970692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 286069d99fdcSPrabu Thangamuthu 286169d99fdcSPrabu Thangamuthu if (addr_config == 1) { 286269d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 286369d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 28643fc7eaefSShawn Lin dev_info(host->dev, 28653fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 286669d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 28673fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 28683fc7eaefSShawn Lin DMA_BIT_MASK(64)); 286969d99fdcSPrabu Thangamuthu } else { 287069d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 287169d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 28723fc7eaefSShawn Lin dev_info(host->dev, 28733fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 287469d99fdcSPrabu Thangamuthu } 287569d99fdcSPrabu Thangamuthu 2876f95f3850SWill Newton /* Alloc memory for sg translation */ 2877cc190d4cSShawn Lin host->sg_cpu = dmam_alloc_coherent(host->dev, 2878cc190d4cSShawn Lin DESC_RING_BUF_SZ, 2879f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2880f95f3850SWill Newton if (!host->sg_cpu) { 28813fc7eaefSShawn Lin dev_err(host->dev, 28823fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2883f95f3850SWill Newton __func__); 2884f95f3850SWill Newton goto no_dma; 2885f95f3850SWill Newton } 2886f95f3850SWill Newton 2887f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 288800956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 28893fc7eaefSShawn Lin } else { 28903fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 28913fc7eaefSShawn Lin if ((of_property_count_strings(np, "dma-names") < 0) || 28923fc7eaefSShawn Lin (!of_find_property(np, "dmas", NULL))) { 2893f95f3850SWill Newton goto no_dma; 28943fc7eaefSShawn Lin } 28953fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 28963fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 28973fc7eaefSShawn Lin } 2898f95f3850SWill Newton 2899e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2900e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2901f95f3850SWill Newton if (host->dma_ops->init(host)) { 29020e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 29030e3a22c0SShawn Lin __func__); 2904f95f3850SWill Newton goto no_dma; 2905f95f3850SWill Newton } 2906f95f3850SWill Newton } else { 29074a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2908f95f3850SWill Newton goto no_dma; 2909f95f3850SWill Newton } 2910f95f3850SWill Newton 2911f95f3850SWill Newton return; 2912f95f3850SWill Newton 2913f95f3850SWill Newton no_dma: 29144a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 29153fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 2916f95f3850SWill Newton } 2917f95f3850SWill Newton 29185c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 29195c935165SDoug Anderson { 29205c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 29215c935165SDoug Anderson 2922fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 2923fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2924fd674198SDoug Anderson return; 2925fd674198SDoug Anderson } 29265c935165SDoug Anderson 29275c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 29285c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 29295c935165SDoug Anderson tasklet_schedule(&host->tasklet); 29305c935165SDoug Anderson } 29315c935165SDoug Anderson 293257e10486SAddy Ke static void dw_mci_dto_timer(unsigned long arg) 293357e10486SAddy Ke { 293457e10486SAddy Ke struct dw_mci *host = (struct dw_mci *)arg; 293557e10486SAddy Ke 293657e10486SAddy Ke switch (host->state) { 293757e10486SAddy Ke case STATE_SENDING_DATA: 293857e10486SAddy Ke case STATE_DATA_BUSY: 293957e10486SAddy Ke /* 294057e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 294157e10486SAddy Ke * we should notify the driver to terminate current transfer 294257e10486SAddy Ke * and report a data timeout to the core. 294357e10486SAddy Ke */ 294457e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 294557e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 294657e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 294757e10486SAddy Ke tasklet_schedule(&host->tasklet); 294857e10486SAddy Ke break; 294957e10486SAddy Ke default: 295057e10486SAddy Ke break; 295157e10486SAddy Ke } 295257e10486SAddy Ke } 295357e10486SAddy Ke 2954c91eab4bSThomas Abraham #ifdef CONFIG_OF 2955c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2956c91eab4bSThomas Abraham { 2957c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2958c91eab4bSThomas Abraham struct device *dev = host->dev; 2959c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2960e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2961e8cc37b8SShawn Lin int ret; 29623c6d89eaSDoug Anderson u32 clock_frequency; 2963c91eab4bSThomas Abraham 2964c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2965bf3707eaSBeomho Seo if (!pdata) 2966c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2967c91eab4bSThomas Abraham 2968d6786fefSGuodong Xu /* find reset controller when exist */ 29693a667e3fSJaehoon Chung pdata->rstc = devm_reset_control_get_optional(dev, "reset"); 2970d6786fefSGuodong Xu if (IS_ERR(pdata->rstc)) { 2971d6786fefSGuodong Xu if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 2972d6786fefSGuodong Xu return ERR_PTR(-EPROBE_DEFER); 2973d6786fefSGuodong Xu } 2974d6786fefSGuodong Xu 2975c91eab4bSThomas Abraham /* find out number of slots supported */ 29768a629d26SShawn Lin of_property_read_u32(np, "num-slots", &pdata->num_slots); 2977c91eab4bSThomas Abraham 2978c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 29790e3a22c0SShawn Lin dev_info(dev, 29800e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 2981c91eab4bSThomas Abraham 2982c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2983c91eab4bSThomas Abraham 2984a0361c1aSJun Nie of_property_read_u32(np, "data-addr", &host->data_addr_override); 2985a0361c1aSJun Nie 2986d6fced83SJun Nie if (of_get_property(np, "fifo-watermark-aligned", NULL)) 2987d6fced83SJun Nie host->wm_aligned = true; 2988d6fced83SJun Nie 29893c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 29903c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 29913c6d89eaSDoug Anderson 2992cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2993cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2994800d78bfSThomas Abraham if (ret) 2995800d78bfSThomas Abraham return ERR_PTR(ret); 2996800d78bfSThomas Abraham } 2997800d78bfSThomas Abraham 2998c91eab4bSThomas Abraham return pdata; 2999c91eab4bSThomas Abraham } 3000c91eab4bSThomas Abraham 3001c91eab4bSThomas Abraham #else /* CONFIG_OF */ 3002c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3003c91eab4bSThomas Abraham { 3004c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 3005c91eab4bSThomas Abraham } 3006c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 3007c91eab4bSThomas Abraham 3008fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 3009fa0c3283SDoug Anderson { 3010fa0c3283SDoug Anderson unsigned long irqflags; 3011fa0c3283SDoug Anderson u32 temp; 3012fa0c3283SDoug Anderson int i; 3013e8cc37b8SShawn Lin struct dw_mci_slot *slot; 3014fa0c3283SDoug Anderson 3015e8cc37b8SShawn Lin /* 3016e8cc37b8SShawn Lin * No need for CD if all slots have a non-error GPIO 3017e8cc37b8SShawn Lin * as well as broken card detection is found. 3018e8cc37b8SShawn Lin */ 3019fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 3020e8cc37b8SShawn Lin slot = host->slot[i]; 3021e8cc37b8SShawn Lin if (slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3022e8cc37b8SShawn Lin return; 3023fa0c3283SDoug Anderson 3024287980e4SArnd Bergmann if (mmc_gpio_get_cd(slot->mmc) < 0) 3025fa0c3283SDoug Anderson break; 3026fa0c3283SDoug Anderson } 3027fa0c3283SDoug Anderson if (i == host->num_slots) 3028fa0c3283SDoug Anderson return; 3029fa0c3283SDoug Anderson 3030fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 3031fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 3032fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 3033fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 3034fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 3035fa0c3283SDoug Anderson } 3036fa0c3283SDoug Anderson 303762ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 3038f95f3850SWill Newton { 3039e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 304062ca8034SShashidhar Hiremath int width, i, ret = 0; 3041f95f3850SWill Newton u32 fifo_size; 30421c2215b7SThomas Abraham int init_slots = 0; 3043f95f3850SWill Newton 3044c91eab4bSThomas Abraham if (!host->pdata) { 3045c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 3046d6786fefSGuodong Xu if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3047d6786fefSGuodong Xu return -EPROBE_DEFER; 3048d6786fefSGuodong Xu } else if (IS_ERR(host->pdata)) { 3049c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 3050c91eab4bSThomas Abraham return -EINVAL; 3051c91eab4bSThomas Abraham } 3052f95f3850SWill Newton } 3053f95f3850SWill Newton 3054780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 3055f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 3056f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 3057f90a0612SThomas Abraham } else { 3058f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 3059f90a0612SThomas Abraham if (ret) { 3060f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 3061f90a0612SThomas Abraham return ret; 3062f90a0612SThomas Abraham } 3063f95f3850SWill Newton } 3064f95f3850SWill Newton 3065780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3066f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 3067f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 30683c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 3069f90a0612SThomas Abraham } else { 3070f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 3071f90a0612SThomas Abraham if (ret) { 3072f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 3073f90a0612SThomas Abraham goto err_clk_biu; 3074f90a0612SThomas Abraham } 3075f90a0612SThomas Abraham 30763c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 30773c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 30783c6d89eaSDoug Anderson if (ret) 30793c6d89eaSDoug Anderson dev_warn(host->dev, 3080612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 30813c6d89eaSDoug Anderson host->pdata->bus_hz); 30823c6d89eaSDoug Anderson } 3083f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 30843c6d89eaSDoug Anderson } 3085f90a0612SThomas Abraham 3086612de4c1SJaehoon Chung if (!host->bus_hz) { 3087612de4c1SJaehoon Chung dev_err(host->dev, 3088612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3089612de4c1SJaehoon Chung ret = -ENODEV; 3090612de4c1SJaehoon Chung goto err_clk_ciu; 3091612de4c1SJaehoon Chung } 3092612de4c1SJaehoon Chung 3093002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3094002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3095002f0d5cSYuvaraj Kumar C D if (ret) { 3096002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3097002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3098002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3099002f0d5cSYuvaraj Kumar C D } 3100002f0d5cSYuvaraj Kumar C D } 3101002f0d5cSYuvaraj Kumar C D 3102d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) { 3103d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3104d6786fefSGuodong Xu usleep_range(10, 50); 3105d6786fefSGuodong Xu reset_control_deassert(host->pdata->rstc); 3106d6786fefSGuodong Xu } 3107d6786fefSGuodong Xu 31085c935165SDoug Anderson setup_timer(&host->cmd11_timer, 31095c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 31105c935165SDoug Anderson 311157e10486SAddy Ke setup_timer(&host->dto_timer, 311257e10486SAddy Ke dw_mci_dto_timer, (unsigned long)host); 311357e10486SAddy Ke 3114f95f3850SWill Newton spin_lock_init(&host->lock); 3115f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3116f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3117f95f3850SWill Newton 3118f95f3850SWill Newton /* 3119f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3120f95f3850SWill Newton * the correct values. 3121f95f3850SWill Newton */ 312270692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3123f95f3850SWill Newton if (!i) { 3124f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3125f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3126f95f3850SWill Newton width = 16; 3127f95f3850SWill Newton host->data_shift = 1; 3128f95f3850SWill Newton } else if (i == 2) { 3129f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3130f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3131f95f3850SWill Newton width = 64; 3132f95f3850SWill Newton host->data_shift = 3; 3133f95f3850SWill Newton } else { 3134f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3135f95f3850SWill Newton WARN((i != 1), 3136f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3137f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3138f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3139f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3140f95f3850SWill Newton width = 32; 3141f95f3850SWill Newton host->data_shift = 2; 3142f95f3850SWill Newton } 3143f95f3850SWill Newton 3144f95f3850SWill Newton /* Reset all blocks */ 31453744415cSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 31463744415cSShawn Lin ret = -ENODEV; 31473744415cSShawn Lin goto err_clk_ciu; 31483744415cSShawn Lin } 3149141a712aSSeungwon Jeon 3150141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3151141a712aSSeungwon Jeon dw_mci_init_dma(host); 3152f95f3850SWill Newton 3153f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3154f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3155f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3156f95f3850SWill Newton 3157f95f3850SWill Newton /* Put in max timeout */ 3158f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3159f95f3850SWill Newton 3160f95f3850SWill Newton /* 3161f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3162f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3163f95f3850SWill Newton */ 3164b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3165b86d8253SJames Hogan /* 3166b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3167b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3168b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3169b86d8253SJames Hogan * should put it in the platform data. 3170b86d8253SJames Hogan */ 3171f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 31728234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3173b86d8253SJames Hogan } else { 3174b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3175b86d8253SJames Hogan } 3176b86d8253SJames Hogan host->fifo_depth = fifo_size; 317752426899SSeungwon Jeon host->fifoth_val = 317852426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3179e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3180f95f3850SWill Newton 3181f95f3850SWill Newton /* disable clock to CIU */ 3182f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3183f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3184f95f3850SWill Newton 318563008768SJames Hogan /* 318663008768SJames Hogan * In 2.40a spec, Data offset is changed. 318763008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 318863008768SJames Hogan */ 318963008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 319063008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 319163008768SJames Hogan 3192a0361c1aSJun Nie if (host->data_addr_override) 3193a0361c1aSJun Nie host->fifo_reg = host->regs + host->data_addr_override; 3194a0361c1aSJun Nie else if (host->verid < DW_MMC_240A) 319576184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 319663008768SJames Hogan else 319776184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 319863008768SJames Hogan 3199f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3200780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3201780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3202f95f3850SWill Newton if (ret) 32036130e7a9SDoug Anderson goto err_dmaunmap; 3204f95f3850SWill Newton 3205f95f3850SWill Newton if (host->pdata->num_slots) 3206f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 3207f95f3850SWill Newton else 32088a629d26SShawn Lin host->num_slots = 1; 32098a629d26SShawn Lin 32108a629d26SShawn Lin if (host->num_slots < 1 || 32118a629d26SShawn Lin host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) { 32128a629d26SShawn Lin dev_err(host->dev, 32138a629d26SShawn Lin "Platform data must supply correct num_slots.\n"); 32148a629d26SShawn Lin ret = -ENODEV; 32158a629d26SShawn Lin goto err_clk_ciu; 32168a629d26SShawn Lin } 3217f95f3850SWill Newton 32182da1d7f2SYuvaraj CD /* 3219fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 32202da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 32212da1d7f2SYuvaraj CD */ 32222da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 32232da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3224fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 32250e3a22c0SShawn Lin /* Enable mci interrupt */ 32260e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 32272da1d7f2SYuvaraj CD 32280e3a22c0SShawn Lin dev_info(host->dev, 32290e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 32302da1d7f2SYuvaraj CD host->irq, width, fifo_size); 32312da1d7f2SYuvaraj CD 3232f95f3850SWill Newton /* We need at least one slot to succeed */ 3233f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3234f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 32351c2215b7SThomas Abraham if (ret) 32361c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 32371c2215b7SThomas Abraham else 32381c2215b7SThomas Abraham init_slots++; 3239f95f3850SWill Newton } 32401c2215b7SThomas Abraham 32411c2215b7SThomas Abraham if (init_slots) { 32421c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 32431c2215b7SThomas Abraham } else { 32440e3a22c0SShawn Lin dev_dbg(host->dev, 32450e3a22c0SShawn Lin "attempted to initialize %d slots, but failed on all\n", 32460e3a22c0SShawn Lin host->num_slots); 32476130e7a9SDoug Anderson goto err_dmaunmap; 3248f95f3850SWill Newton } 3249f95f3850SWill Newton 3250b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3251b793f658SDoug Anderson dw_mci_enable_cd(host); 3252b793f658SDoug Anderson 3253f95f3850SWill Newton return 0; 3254f95f3850SWill Newton 3255f95f3850SWill Newton err_dmaunmap: 3256f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3257f95f3850SWill Newton host->dma_ops->exit(host); 3258f90a0612SThomas Abraham 3259d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3260d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3261d6786fefSGuodong Xu 3262f90a0612SThomas Abraham err_clk_ciu: 3263f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3264780f22afSSeungwon Jeon 3265f90a0612SThomas Abraham err_clk_biu: 3266f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3267780f22afSSeungwon Jeon 3268f95f3850SWill Newton return ret; 3269f95f3850SWill Newton } 327062ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3271f95f3850SWill Newton 327262ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3273f95f3850SWill Newton { 3274f95f3850SWill Newton int i; 3275f95f3850SWill Newton 3276f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 32774a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 3278f95f3850SWill Newton if (host->slot[i]) 3279f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 3280f95f3850SWill Newton } 3281f95f3850SWill Newton 3282048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3283048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3284048fd7e6SPrabu Thangamuthu 3285f95f3850SWill Newton /* disable clock to CIU */ 3286f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3287f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3288f95f3850SWill Newton 3289f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3290f95f3850SWill Newton host->dma_ops->exit(host); 3291f95f3850SWill Newton 3292d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3293d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3294d6786fefSGuodong Xu 3295f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3296f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3297f95f3850SWill Newton } 329862ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 329962ca8034SShashidhar Hiremath 330062ca8034SShashidhar Hiremath 3301f95f3850SWill Newton 3302e9ed8835SShawn Lin #ifdef CONFIG_PM 3303ed24e1ffSShawn Lin int dw_mci_runtime_suspend(struct device *dev) 3304f95f3850SWill Newton { 3305ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3306ed24e1ffSShawn Lin 33073fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 33083fc7eaefSShawn Lin host->dma_ops->exit(host); 33093fc7eaefSShawn Lin 3310ed24e1ffSShawn Lin clk_disable_unprepare(host->ciu_clk); 3311ed24e1ffSShawn Lin 3312ed24e1ffSShawn Lin if (host->cur_slot && 3313ed24e1ffSShawn Lin (mmc_can_gpio_cd(host->cur_slot->mmc) || 3314ed24e1ffSShawn Lin !mmc_card_is_removable(host->cur_slot->mmc))) 3315ed24e1ffSShawn Lin clk_disable_unprepare(host->biu_clk); 3316ed24e1ffSShawn Lin 3317f95f3850SWill Newton return 0; 3318f95f3850SWill Newton } 3319ed24e1ffSShawn Lin EXPORT_SYMBOL(dw_mci_runtime_suspend); 3320f95f3850SWill Newton 3321ed24e1ffSShawn Lin int dw_mci_runtime_resume(struct device *dev) 3322f95f3850SWill Newton { 3323ed24e1ffSShawn Lin int i, ret = 0; 3324ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3325f95f3850SWill Newton 3326ed24e1ffSShawn Lin if (host->cur_slot && 3327ed24e1ffSShawn Lin (mmc_can_gpio_cd(host->cur_slot->mmc) || 3328ed24e1ffSShawn Lin !mmc_card_is_removable(host->cur_slot->mmc))) { 3329ed24e1ffSShawn Lin ret = clk_prepare_enable(host->biu_clk); 3330ed24e1ffSShawn Lin if (ret) 3331e61cf118SJaehoon Chung return ret; 3332e61cf118SJaehoon Chung } 3333e61cf118SJaehoon Chung 3334ed24e1ffSShawn Lin ret = clk_prepare_enable(host->ciu_clk); 3335ed24e1ffSShawn Lin if (ret) 3336df9bcc2bSJoonyoung Shim goto err; 3337df9bcc2bSJoonyoung Shim 3338df9bcc2bSJoonyoung Shim if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3339df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->ciu_clk); 3340df9bcc2bSJoonyoung Shim ret = -ENODEV; 3341df9bcc2bSJoonyoung Shim goto err; 3342df9bcc2bSJoonyoung Shim } 3343ed24e1ffSShawn Lin 33443bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3345141a712aSSeungwon Jeon host->dma_ops->init(host); 3346141a712aSSeungwon Jeon 334752426899SSeungwon Jeon /* 334852426899SSeungwon Jeon * Restore the initial value at FIFOTH register 334952426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 335052426899SSeungwon Jeon */ 3351e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 335252426899SSeungwon Jeon host->prev_blksz = 0; 3353e61cf118SJaehoon Chung 33542eb2944fSDoug Anderson /* Put in max timeout */ 33552eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 33562eb2944fSDoug Anderson 3357e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3358e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3359e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3360fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3361e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3362e61cf118SJaehoon Chung 3363f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3364f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 33650e3a22c0SShawn Lin 3366f95f3850SWill Newton if (!slot) 3367f95f3850SWill Newton continue; 3368e9748e03SZiyuan Xu if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3369ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3370e9748e03SZiyuan Xu 3371e9748e03SZiyuan Xu /* Force setup bus to guarantee available clock output */ 3372ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 3373ab269128SAbhilash Kesavan } 3374fa0c3283SDoug Anderson 3375fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3376fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3377fa0c3283SDoug Anderson 3378df9bcc2bSJoonyoung Shim return 0; 3379df9bcc2bSJoonyoung Shim 3380df9bcc2bSJoonyoung Shim err: 3381df9bcc2bSJoonyoung Shim if (host->cur_slot && 3382df9bcc2bSJoonyoung Shim (mmc_can_gpio_cd(host->cur_slot->mmc) || 3383df9bcc2bSJoonyoung Shim !mmc_card_is_removable(host->cur_slot->mmc))) 3384df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->biu_clk); 3385df9bcc2bSJoonyoung Shim 33861f5c51d7SShawn Lin return ret; 33871f5c51d7SShawn Lin } 3388e9ed8835SShawn Lin EXPORT_SYMBOL(dw_mci_runtime_resume); 3389e9ed8835SShawn Lin #endif /* CONFIG_PM */ 33906fe8890dSJaehoon Chung 3391f95f3850SWill Newton static int __init dw_mci_init(void) 3392f95f3850SWill Newton { 33938e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 339462ca8034SShashidhar Hiremath return 0; 3395f95f3850SWill Newton } 3396f95f3850SWill Newton 3397f95f3850SWill Newton static void __exit dw_mci_exit(void) 3398f95f3850SWill Newton { 3399f95f3850SWill Newton } 3400f95f3850SWill Newton 3401f95f3850SWill Newton module_init(dw_mci_init); 3402f95f3850SWill Newton module_exit(dw_mci_exit); 3403f95f3850SWill Newton 3404f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3405f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3406f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3407f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3408