1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4  */
5 
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/clk.h>
9 #include <linux/mmc/host.h>
10 #include <linux/of_address.h>
11 #include <linux/mmc/slot-gpio.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/slab.h>
14 
15 #include "dw_mmc.h"
16 #include "dw_mmc-pltfm.h"
17 
18 #define RK3288_CLKGEN_DIV	2
19 
20 static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
21 
22 struct dw_mci_rockchip_priv_data {
23 	struct clk		*drv_clk;
24 	struct clk		*sample_clk;
25 	int			default_sample_phase;
26 	int			num_phases;
27 };
28 
29 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
30 {
31 	struct dw_mci_rockchip_priv_data *priv = host->priv;
32 	int ret;
33 	unsigned int cclkin;
34 	u32 bus_hz;
35 
36 	if (ios->clock == 0)
37 		return;
38 
39 	/*
40 	 * cclkin: source clock of mmc controller
41 	 * bus_hz: card interface clock generated by CLKGEN
42 	 * bus_hz = cclkin / RK3288_CLKGEN_DIV
43 	 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
44 	 *
45 	 * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
46 	 * DDR52 8-bit mode.
47 	 */
48 	if (ios->bus_width == MMC_BUS_WIDTH_8 &&
49 	    ios->timing == MMC_TIMING_MMC_DDR52)
50 		cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
51 	else
52 		cclkin = ios->clock * RK3288_CLKGEN_DIV;
53 
54 	ret = clk_set_rate(host->ciu_clk, cclkin);
55 	if (ret)
56 		dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
57 
58 	bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
59 	if (bus_hz != host->bus_hz) {
60 		host->bus_hz = bus_hz;
61 		/* force dw_mci_setup_bus() */
62 		host->current_speed = 0;
63 	}
64 
65 	/* Make sure we use phases which we can enumerate with */
66 	if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS)
67 		clk_set_phase(priv->sample_clk, priv->default_sample_phase);
68 
69 	/*
70 	 * Set the drive phase offset based on speed mode to achieve hold times.
71 	 *
72 	 * NOTE: this is _not_ a value that is dynamically tuned and is also
73 	 * _not_ a value that will vary from board to board.  It is a value
74 	 * that could vary between different SoC models if they had massively
75 	 * different output clock delays inside their dw_mmc IP block (delay_o),
76 	 * but since it's OK to overshoot a little we don't need to do complex
77 	 * calculations and can pick values that will just work for everyone.
78 	 *
79 	 * When picking values we'll stick with picking 0/90/180/270 since
80 	 * those can be made very accurately on all known Rockchip SoCs.
81 	 *
82 	 * Note that these values match values from the DesignWare Databook
83 	 * tables for the most part except for SDR12 and "ID mode".  For those
84 	 * two modes the databook calculations assume a clock in of 50MHz.  As
85 	 * seen above, we always use a clock in rate that is exactly the
86 	 * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
87 	 * back out before the controller sees it).
88 	 *
89 	 * From measurement of a single device, it appears that delay_o is
90 	 * about .5 ns.  Since we try to leave a bit of margin, it's expected
91 	 * that numbers here will be fine even with much larger delay_o
92 	 * (the 1.4 ns assumed by the DesignWare Databook would result in the
93 	 * same results, for instance).
94 	 */
95 	if (!IS_ERR(priv->drv_clk)) {
96 		int phase;
97 
98 		/*
99 		 * In almost all cases a 90 degree phase offset will provide
100 		 * sufficient hold times across all valid input clock rates
101 		 * assuming delay_o is not absurd for a given SoC.  We'll use
102 		 * that as a default.
103 		 */
104 		phase = 90;
105 
106 		switch (ios->timing) {
107 		case MMC_TIMING_MMC_DDR52:
108 			/*
109 			 * Since clock in rate with MMC_DDR52 is doubled when
110 			 * bus width is 8 we need to double the phase offset
111 			 * to get the same timings.
112 			 */
113 			if (ios->bus_width == MMC_BUS_WIDTH_8)
114 				phase = 180;
115 			break;
116 		case MMC_TIMING_UHS_SDR104:
117 		case MMC_TIMING_MMC_HS200:
118 			/*
119 			 * In the case of 150 MHz clock (typical max for
120 			 * Rockchip SoCs), 90 degree offset will add a delay
121 			 * of 1.67 ns.  That will meet min hold time of .8 ns
122 			 * as long as clock output delay is < .87 ns.  On
123 			 * SoCs measured this seems to be OK, but it doesn't
124 			 * hurt to give margin here, so we use 180.
125 			 */
126 			phase = 180;
127 			break;
128 		}
129 
130 		clk_set_phase(priv->drv_clk, phase);
131 	}
132 }
133 
134 #define TUNING_ITERATION_TO_PHASE(i, num_phases) \
135 		(DIV_ROUND_UP((i) * 360, num_phases))
136 
137 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
138 {
139 	struct dw_mci *host = slot->host;
140 	struct dw_mci_rockchip_priv_data *priv = host->priv;
141 	struct mmc_host *mmc = slot->mmc;
142 	int ret = 0;
143 	int i;
144 	bool v, prev_v = 0, first_v;
145 	struct range_t {
146 		int start;
147 		int end; /* inclusive */
148 	};
149 	struct range_t *ranges;
150 	unsigned int range_count = 0;
151 	int longest_range_len = -1;
152 	int longest_range = -1;
153 	int middle_phase;
154 
155 	if (IS_ERR(priv->sample_clk)) {
156 		dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
157 		return -EIO;
158 	}
159 
160 	ranges = kmalloc_array(priv->num_phases / 2 + 1,
161 			       sizeof(*ranges), GFP_KERNEL);
162 	if (!ranges)
163 		return -ENOMEM;
164 
165 	/* Try each phase and extract good ranges */
166 	for (i = 0; i < priv->num_phases; ) {
167 		clk_set_phase(priv->sample_clk,
168 			      TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
169 
170 		v = !mmc_send_tuning(mmc, opcode, NULL);
171 
172 		if (i == 0)
173 			first_v = v;
174 
175 		if ((!prev_v) && v) {
176 			range_count++;
177 			ranges[range_count-1].start = i;
178 		}
179 		if (v) {
180 			ranges[range_count-1].end = i;
181 			i++;
182 		} else if (i == priv->num_phases - 1) {
183 			/* No extra skipping rules if we're at the end */
184 			i++;
185 		} else {
186 			/*
187 			 * No need to check too close to an invalid
188 			 * one since testing bad phases is slow.  Skip
189 			 * 20 degrees.
190 			 */
191 			i += DIV_ROUND_UP(20 * priv->num_phases, 360);
192 
193 			/* Always test the last one */
194 			if (i >= priv->num_phases)
195 				i = priv->num_phases - 1;
196 		}
197 
198 		prev_v = v;
199 	}
200 
201 	if (range_count == 0) {
202 		dev_warn(host->dev, "All phases bad!");
203 		ret = -EIO;
204 		goto free;
205 	}
206 
207 	/* wrap around case, merge the end points */
208 	if ((range_count > 1) && first_v && v) {
209 		ranges[0].start = ranges[range_count-1].start;
210 		range_count--;
211 	}
212 
213 	if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
214 		clk_set_phase(priv->sample_clk, priv->default_sample_phase);
215 		dev_info(host->dev, "All phases work, using default phase %d.",
216 			 priv->default_sample_phase);
217 		goto free;
218 	}
219 
220 	/* Find the longest range */
221 	for (i = 0; i < range_count; i++) {
222 		int len = (ranges[i].end - ranges[i].start + 1);
223 
224 		if (len < 0)
225 			len += priv->num_phases;
226 
227 		if (longest_range_len < len) {
228 			longest_range_len = len;
229 			longest_range = i;
230 		}
231 
232 		dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
233 			TUNING_ITERATION_TO_PHASE(ranges[i].start,
234 						  priv->num_phases),
235 			TUNING_ITERATION_TO_PHASE(ranges[i].end,
236 						  priv->num_phases),
237 			len
238 		);
239 	}
240 
241 	dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
242 		TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
243 					  priv->num_phases),
244 		TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
245 					  priv->num_phases),
246 		longest_range_len
247 	);
248 
249 	middle_phase = ranges[longest_range].start + longest_range_len / 2;
250 	middle_phase %= priv->num_phases;
251 	dev_info(host->dev, "Successfully tuned phase to %d\n",
252 		 TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases));
253 
254 	clk_set_phase(priv->sample_clk,
255 		      TUNING_ITERATION_TO_PHASE(middle_phase,
256 						priv->num_phases));
257 
258 free:
259 	kfree(ranges);
260 	return ret;
261 }
262 
263 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
264 {
265 	struct device_node *np = host->dev->of_node;
266 	struct dw_mci_rockchip_priv_data *priv;
267 
268 	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
269 	if (!priv)
270 		return -ENOMEM;
271 
272 	if (of_property_read_u32(np, "rockchip,desired-num-phases",
273 					&priv->num_phases))
274 		priv->num_phases = 360;
275 
276 	if (of_property_read_u32(np, "rockchip,default-sample-phase",
277 					&priv->default_sample_phase))
278 		priv->default_sample_phase = 0;
279 
280 	priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
281 	if (IS_ERR(priv->drv_clk))
282 		dev_dbg(host->dev, "ciu-drive not available\n");
283 
284 	priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
285 	if (IS_ERR(priv->sample_clk))
286 		dev_dbg(host->dev, "ciu-sample not available\n");
287 
288 	host->priv = priv;
289 
290 	return 0;
291 }
292 
293 static int dw_mci_rockchip_init(struct dw_mci *host)
294 {
295 	int ret, i;
296 
297 	/* It is slot 8 on Rockchip SoCs */
298 	host->sdio_id0 = 8;
299 
300 	if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
301 		host->bus_hz /= RK3288_CLKGEN_DIV;
302 
303 		/* clock driver will fail if the clock is less than the lowest source clock
304 		 * divided by the internal clock divider. Test for the lowest available
305 		 * clock and set the minimum freq to clock / clock divider.
306 		 */
307 
308 		for (i = 0; i < ARRAY_SIZE(freqs); i++) {
309 			ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
310 			if (ret > 0) {
311 				host->minimum_speed = ret / RK3288_CLKGEN_DIV;
312 				break;
313 			}
314 		}
315 		if (ret < 0)
316 			dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
317 	}
318 
319 	return 0;
320 }
321 
322 static const struct dw_mci_drv_data rk2928_drv_data = {
323 	.init			= dw_mci_rockchip_init,
324 };
325 
326 static const struct dw_mci_drv_data rk3288_drv_data = {
327 	.common_caps		= MMC_CAP_CMD23,
328 	.set_ios		= dw_mci_rk3288_set_ios,
329 	.execute_tuning		= dw_mci_rk3288_execute_tuning,
330 	.parse_dt		= dw_mci_rk3288_parse_dt,
331 	.init			= dw_mci_rockchip_init,
332 };
333 
334 static const struct of_device_id dw_mci_rockchip_match[] = {
335 	{ .compatible = "rockchip,rk2928-dw-mshc",
336 		.data = &rk2928_drv_data },
337 	{ .compatible = "rockchip,rk3288-dw-mshc",
338 		.data = &rk3288_drv_data },
339 	{},
340 };
341 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
342 
343 static int dw_mci_rockchip_probe(struct platform_device *pdev)
344 {
345 	const struct dw_mci_drv_data *drv_data;
346 	const struct of_device_id *match;
347 	int ret;
348 
349 	if (!pdev->dev.of_node)
350 		return -ENODEV;
351 
352 	match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
353 	drv_data = match->data;
354 
355 	pm_runtime_get_noresume(&pdev->dev);
356 	pm_runtime_set_active(&pdev->dev);
357 	pm_runtime_enable(&pdev->dev);
358 	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
359 	pm_runtime_use_autosuspend(&pdev->dev);
360 
361 	ret = dw_mci_pltfm_register(pdev, drv_data);
362 	if (ret) {
363 		pm_runtime_disable(&pdev->dev);
364 		pm_runtime_set_suspended(&pdev->dev);
365 		pm_runtime_put_noidle(&pdev->dev);
366 		return ret;
367 	}
368 
369 	pm_runtime_put_autosuspend(&pdev->dev);
370 
371 	return 0;
372 }
373 
374 static int dw_mci_rockchip_remove(struct platform_device *pdev)
375 {
376 	pm_runtime_get_sync(&pdev->dev);
377 	pm_runtime_disable(&pdev->dev);
378 	pm_runtime_put_noidle(&pdev->dev);
379 
380 	return dw_mci_pltfm_remove(pdev);
381 }
382 
383 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
384 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
385 				pm_runtime_force_resume)
386 	SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
387 			   dw_mci_runtime_resume,
388 			   NULL)
389 };
390 
391 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
392 	.probe		= dw_mci_rockchip_probe,
393 	.remove		= dw_mci_rockchip_remove,
394 	.driver		= {
395 		.name		= "dwmmc_rockchip",
396 		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
397 		.of_match_table	= dw_mci_rockchip_match,
398 		.pm		= &dw_mci_rockchip_dev_pm_ops,
399 	},
400 };
401 
402 module_platform_driver(dw_mci_rockchip_pltfm_driver);
403 
404 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
405 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
406 MODULE_ALIAS("platform:dwmmc_rockchip");
407 MODULE_LICENSE("GPL v2");
408