1 /* 2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/clk.h> 13 #include <linux/mmc/host.h> 14 #include <linux/of_address.h> 15 #include <linux/mmc/slot-gpio.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/slab.h> 18 19 #include "dw_mmc.h" 20 #include "dw_mmc-pltfm.h" 21 22 #define RK3288_CLKGEN_DIV 2 23 24 struct dw_mci_rockchip_priv_data { 25 struct clk *drv_clk; 26 struct clk *sample_clk; 27 int default_sample_phase; 28 }; 29 30 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) 31 { 32 struct dw_mci_rockchip_priv_data *priv = host->priv; 33 int ret; 34 unsigned int cclkin; 35 u32 bus_hz; 36 37 if (ios->clock == 0) 38 return; 39 40 /* 41 * cclkin: source clock of mmc controller 42 * bus_hz: card interface clock generated by CLKGEN 43 * bus_hz = cclkin / RK3288_CLKGEN_DIV 44 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) 45 * 46 * Note: div can only be 0 or 1 47 * if DDR50 8bit mode(only emmc work in 8bit mode), 48 * div must be set 1 49 */ 50 if (ios->bus_width == MMC_BUS_WIDTH_8 && 51 ios->timing == MMC_TIMING_MMC_DDR52) 52 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; 53 else 54 cclkin = ios->clock * RK3288_CLKGEN_DIV; 55 56 ret = clk_set_rate(host->ciu_clk, cclkin); 57 if (ret) 58 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); 59 60 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; 61 if (bus_hz != host->bus_hz) { 62 host->bus_hz = bus_hz; 63 /* force dw_mci_setup_bus() */ 64 host->current_speed = 0; 65 } 66 67 /* Make sure we use phases which we can enumerate with */ 68 if (!IS_ERR(priv->sample_clk)) 69 clk_set_phase(priv->sample_clk, priv->default_sample_phase); 70 71 /* 72 * Set the drive phase offset based on speed mode to achieve hold times. 73 * 74 * NOTE: this is _not_ a value that is dynamically tuned and is also 75 * _not_ a value that will vary from board to board. It is a value 76 * that could vary between different SoC models if they had massively 77 * different output clock delays inside their dw_mmc IP block (delay_o), 78 * but since it's OK to overshoot a little we don't need to do complex 79 * calculations and can pick values that will just work for everyone. 80 * 81 * When picking values we'll stick with picking 0/90/180/270 since 82 * those can be made very accurately on all known Rockchip SoCs. 83 * 84 * Note that these values match values from the DesignWare Databook 85 * tables for the most part except for SDR12 and "ID mode". For those 86 * two modes the databook calculations assume a clock in of 50MHz. As 87 * seen above, we always use a clock in rate that is exactly the 88 * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided 89 * back out before the controller sees it). 90 * 91 * From measurement of a single device, it appears that delay_o is 92 * about .5 ns. Since we try to leave a bit of margin, it's expected 93 * that numbers here will be fine even with much larger delay_o 94 * (the 1.4 ns assumed by the DesignWare Databook would result in the 95 * same results, for instance). 96 */ 97 if (!IS_ERR(priv->drv_clk)) { 98 int phase; 99 100 /* 101 * In almost all cases a 90 degree phase offset will provide 102 * sufficient hold times across all valid input clock rates 103 * assuming delay_o is not absurd for a given SoC. We'll use 104 * that as a default. 105 */ 106 phase = 90; 107 108 switch (ios->timing) { 109 case MMC_TIMING_MMC_DDR52: 110 /* 111 * Since clock in rate with MMC_DDR52 is doubled when 112 * bus width is 8 we need to double the phase offset 113 * to get the same timings. 114 */ 115 if (ios->bus_width == MMC_BUS_WIDTH_8) 116 phase = 180; 117 break; 118 case MMC_TIMING_UHS_SDR104: 119 case MMC_TIMING_MMC_HS200: 120 /* 121 * In the case of 150 MHz clock (typical max for 122 * Rockchip SoCs), 90 degree offset will add a delay 123 * of 1.67 ns. That will meet min hold time of .8 ns 124 * as long as clock output delay is < .87 ns. On 125 * SoCs measured this seems to be OK, but it doesn't 126 * hurt to give margin here, so we use 180. 127 */ 128 phase = 180; 129 break; 130 } 131 132 clk_set_phase(priv->drv_clk, phase); 133 } 134 } 135 136 #define NUM_PHASES 360 137 #define TUNING_ITERATION_TO_PHASE(i) (DIV_ROUND_UP((i) * 360, NUM_PHASES)) 138 139 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 140 { 141 struct dw_mci *host = slot->host; 142 struct dw_mci_rockchip_priv_data *priv = host->priv; 143 struct mmc_host *mmc = slot->mmc; 144 int ret = 0; 145 int i; 146 bool v, prev_v = 0, first_v; 147 struct range_t { 148 int start; 149 int end; /* inclusive */ 150 }; 151 struct range_t *ranges; 152 unsigned int range_count = 0; 153 int longest_range_len = -1; 154 int longest_range = -1; 155 int middle_phase; 156 157 if (IS_ERR(priv->sample_clk)) { 158 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); 159 return -EIO; 160 } 161 162 ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL); 163 if (!ranges) 164 return -ENOMEM; 165 166 /* Try each phase and extract good ranges */ 167 for (i = 0; i < NUM_PHASES; ) { 168 clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(i)); 169 170 v = !mmc_send_tuning(mmc, opcode, NULL); 171 172 if (i == 0) 173 first_v = v; 174 175 if ((!prev_v) && v) { 176 range_count++; 177 ranges[range_count-1].start = i; 178 } 179 if (v) { 180 ranges[range_count-1].end = i; 181 i++; 182 } else if (i == NUM_PHASES - 1) { 183 /* No extra skipping rules if we're at the end */ 184 i++; 185 } else { 186 /* 187 * No need to check too close to an invalid 188 * one since testing bad phases is slow. Skip 189 * 20 degrees. 190 */ 191 i += DIV_ROUND_UP(20 * NUM_PHASES, 360); 192 193 /* Always test the last one */ 194 if (i >= NUM_PHASES) 195 i = NUM_PHASES - 1; 196 } 197 198 prev_v = v; 199 } 200 201 if (range_count == 0) { 202 dev_warn(host->dev, "All phases bad!"); 203 ret = -EIO; 204 goto free; 205 } 206 207 /* wrap around case, merge the end points */ 208 if ((range_count > 1) && first_v && v) { 209 ranges[0].start = ranges[range_count-1].start; 210 range_count--; 211 } 212 213 if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) { 214 clk_set_phase(priv->sample_clk, priv->default_sample_phase); 215 dev_info(host->dev, "All phases work, using default phase %d.", 216 priv->default_sample_phase); 217 goto free; 218 } 219 220 /* Find the longest range */ 221 for (i = 0; i < range_count; i++) { 222 int len = (ranges[i].end - ranges[i].start + 1); 223 224 if (len < 0) 225 len += NUM_PHASES; 226 227 if (longest_range_len < len) { 228 longest_range_len = len; 229 longest_range = i; 230 } 231 232 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n", 233 TUNING_ITERATION_TO_PHASE(ranges[i].start), 234 TUNING_ITERATION_TO_PHASE(ranges[i].end), 235 len 236 ); 237 } 238 239 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n", 240 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start), 241 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end), 242 longest_range_len 243 ); 244 245 middle_phase = ranges[longest_range].start + longest_range_len / 2; 246 middle_phase %= NUM_PHASES; 247 dev_info(host->dev, "Successfully tuned phase to %d\n", 248 TUNING_ITERATION_TO_PHASE(middle_phase)); 249 250 clk_set_phase(priv->sample_clk, 251 TUNING_ITERATION_TO_PHASE(middle_phase)); 252 253 free: 254 kfree(ranges); 255 return ret; 256 } 257 258 static int dw_mci_rk3288_parse_dt(struct dw_mci *host) 259 { 260 struct device_node *np = host->dev->of_node; 261 struct dw_mci_rockchip_priv_data *priv; 262 263 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 264 if (!priv) 265 return -ENOMEM; 266 267 if (of_property_read_u32(np, "rockchip,default-sample-phase", 268 &priv->default_sample_phase)) 269 priv->default_sample_phase = 0; 270 271 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); 272 if (IS_ERR(priv->drv_clk)) 273 dev_dbg(host->dev, "ciu_drv not available\n"); 274 275 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); 276 if (IS_ERR(priv->sample_clk)) 277 dev_dbg(host->dev, "ciu_sample not available\n"); 278 279 host->priv = priv; 280 281 return 0; 282 } 283 284 static int dw_mci_rockchip_init(struct dw_mci *host) 285 { 286 /* It is slot 8 on Rockchip SoCs */ 287 host->sdio_id0 = 8; 288 289 if (of_device_is_compatible(host->dev->of_node, 290 "rockchip,rk3288-dw-mshc")) 291 host->bus_hz /= RK3288_CLKGEN_DIV; 292 293 return 0; 294 } 295 296 /* Common capabilities of RK3288 SoC */ 297 static unsigned long dw_mci_rk3288_dwmmc_caps[4] = { 298 MMC_CAP_CMD23, 299 MMC_CAP_CMD23, 300 MMC_CAP_CMD23, 301 MMC_CAP_CMD23, 302 }; 303 304 static const struct dw_mci_drv_data rk2928_drv_data = { 305 .init = dw_mci_rockchip_init, 306 }; 307 308 static const struct dw_mci_drv_data rk3288_drv_data = { 309 .caps = dw_mci_rk3288_dwmmc_caps, 310 .set_ios = dw_mci_rk3288_set_ios, 311 .execute_tuning = dw_mci_rk3288_execute_tuning, 312 .parse_dt = dw_mci_rk3288_parse_dt, 313 .init = dw_mci_rockchip_init, 314 }; 315 316 static const struct of_device_id dw_mci_rockchip_match[] = { 317 { .compatible = "rockchip,rk2928-dw-mshc", 318 .data = &rk2928_drv_data }, 319 { .compatible = "rockchip,rk3288-dw-mshc", 320 .data = &rk3288_drv_data }, 321 {}, 322 }; 323 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); 324 325 static int dw_mci_rockchip_probe(struct platform_device *pdev) 326 { 327 const struct dw_mci_drv_data *drv_data; 328 const struct of_device_id *match; 329 int ret; 330 331 if (!pdev->dev.of_node) 332 return -ENODEV; 333 334 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); 335 drv_data = match->data; 336 337 pm_runtime_get_noresume(&pdev->dev); 338 pm_runtime_set_active(&pdev->dev); 339 pm_runtime_enable(&pdev->dev); 340 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 341 pm_runtime_use_autosuspend(&pdev->dev); 342 343 ret = dw_mci_pltfm_register(pdev, drv_data); 344 if (ret) { 345 pm_runtime_disable(&pdev->dev); 346 pm_runtime_set_suspended(&pdev->dev); 347 pm_runtime_put_noidle(&pdev->dev); 348 return ret; 349 } 350 351 pm_runtime_put_autosuspend(&pdev->dev); 352 353 return 0; 354 } 355 356 static int dw_mci_rockchip_remove(struct platform_device *pdev) 357 { 358 pm_runtime_get_sync(&pdev->dev); 359 pm_runtime_disable(&pdev->dev); 360 pm_runtime_put_noidle(&pdev->dev); 361 362 return dw_mci_pltfm_remove(pdev); 363 } 364 365 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = { 366 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 367 pm_runtime_force_resume) 368 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend, 369 dw_mci_runtime_resume, 370 NULL) 371 }; 372 373 static struct platform_driver dw_mci_rockchip_pltfm_driver = { 374 .probe = dw_mci_rockchip_probe, 375 .remove = dw_mci_rockchip_remove, 376 .driver = { 377 .name = "dwmmc_rockchip", 378 .of_match_table = dw_mci_rockchip_match, 379 .pm = &dw_mci_rockchip_dev_pm_ops, 380 }, 381 }; 382 383 module_platform_driver(dw_mci_rockchip_pltfm_driver); 384 385 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 386 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension"); 387 MODULE_ALIAS("platform:dwmmc_rockchip"); 388 MODULE_LICENSE("GPL v2"); 389