1 /* 2 * Copyright (c) 2013 Linaro Ltd. 3 * Copyright (c) 2013 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/mmc/host.h> 16 #include <linux/module.h> 17 #include <linux/of_address.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 23 #include "dw_mmc.h" 24 #include "dw_mmc-pltfm.h" 25 26 /* 27 * hi6220 sd only support io voltage 1.8v and 3v 28 * Also need config AO_SCTRL_SEL18 accordingly 29 */ 30 #define AO_SCTRL_SEL18 BIT(10) 31 #define AO_SCTRL_CTRL3 0x40C 32 33 #define DWMMC_SDIO_ID 2 34 35 #define SOC_SCTRL_SCPERCTRL5 (0x314) 36 #define SDCARD_IO_SEL18 BIT(2) 37 38 #define SDCARD_RD_THRESHOLD (512) 39 40 #define GENCLK_DIV (7) 41 42 #define GPIO_CLK_ENABLE BIT(16) 43 #define GPIO_CLK_DIV_MASK GENMASK(11, 8) 44 #define GPIO_USE_SAMPLE_DLY_MASK GENMASK(13, 13) 45 #define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16) 46 #define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK GENMASK(25, 21) 47 #define UHS_REG_EXT_SAMPLE_DLY_MASK GENMASK(30, 26) 48 49 #define TIMING_MODE 3 50 #define TIMING_CFG_NUM 10 51 52 #define NUM_PHASES (40) 53 54 #define ENABLE_SHIFT_MIN_SMPL (4) 55 #define ENABLE_SHIFT_MAX_SMPL (12) 56 #define USE_DLY_MIN_SMPL (11) 57 #define USE_DLY_MAX_SMPL (14) 58 59 struct k3_priv { 60 int ctrl_id; 61 u32 cur_speed; 62 struct regmap *reg; 63 }; 64 65 static unsigned long dw_mci_hi6220_caps[] = { 66 MMC_CAP_CMD23, 67 MMC_CAP_CMD23, 68 0 69 }; 70 71 struct hs_timing { 72 u32 drv_phase; 73 u32 smpl_dly; 74 u32 smpl_phase_max; 75 u32 smpl_phase_min; 76 }; 77 78 static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = { 79 { /* reserved */ }, 80 { /* SD */ 81 {7, 0, 15, 15,}, /* 0: LEGACY 400k */ 82 {6, 0, 4, 4,}, /* 1: MMC_HS */ 83 {6, 0, 3, 3,}, /* 2: SD_HS */ 84 {6, 0, 15, 15,}, /* 3: SDR12 */ 85 {6, 0, 2, 2,}, /* 4: SDR25 */ 86 {4, 0, 11, 0,}, /* 5: SDR50 */ 87 {6, 4, 15, 0,}, /* 6: SDR104 */ 88 {0}, /* 7: DDR50 */ 89 {0}, /* 8: DDR52 */ 90 {0}, /* 9: HS200 */ 91 }, 92 { /* SDIO */ 93 {7, 0, 15, 15,}, /* 0: LEGACY 400k */ 94 {0}, /* 1: MMC_HS */ 95 {6, 0, 15, 15,}, /* 2: SD_HS */ 96 {6, 0, 15, 15,}, /* 3: SDR12 */ 97 {6, 0, 0, 0,}, /* 4: SDR25 */ 98 {4, 0, 12, 0,}, /* 5: SDR50 */ 99 {5, 4, 15, 0,}, /* 6: SDR104 */ 100 {0}, /* 7: DDR50 */ 101 {0}, /* 8: DDR52 */ 102 {0}, /* 9: HS200 */ 103 } 104 }; 105 106 static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios) 107 { 108 int ret; 109 110 ret = clk_set_rate(host->ciu_clk, ios->clock); 111 if (ret) 112 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); 113 114 host->bus_hz = clk_get_rate(host->ciu_clk); 115 } 116 117 static const struct dw_mci_drv_data k3_drv_data = { 118 .set_ios = dw_mci_k3_set_ios, 119 }; 120 121 static int dw_mci_hi6220_parse_dt(struct dw_mci *host) 122 { 123 struct k3_priv *priv; 124 125 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 126 if (!priv) 127 return -ENOMEM; 128 129 priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node, 130 "hisilicon,peripheral-syscon"); 131 if (IS_ERR(priv->reg)) 132 priv->reg = NULL; 133 134 priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 135 if (priv->ctrl_id < 0) 136 priv->ctrl_id = 0; 137 138 if (priv->ctrl_id >= TIMING_MODE) 139 return -EINVAL; 140 141 host->priv = priv; 142 return 0; 143 } 144 145 static int dw_mci_hi6220_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 146 { 147 struct dw_mci_slot *slot = mmc_priv(mmc); 148 struct k3_priv *priv; 149 struct dw_mci *host; 150 int min_uv, max_uv; 151 int ret; 152 153 host = slot->host; 154 priv = host->priv; 155 156 if (!priv || !priv->reg) 157 return 0; 158 159 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 160 ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3, 161 AO_SCTRL_SEL18, 0); 162 min_uv = 3000000; 163 max_uv = 3000000; 164 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 165 ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3, 166 AO_SCTRL_SEL18, AO_SCTRL_SEL18); 167 min_uv = 1800000; 168 max_uv = 1800000; 169 } else { 170 dev_dbg(host->dev, "voltage not supported\n"); 171 return -EINVAL; 172 } 173 174 if (ret) { 175 dev_dbg(host->dev, "switch voltage failed\n"); 176 return ret; 177 } 178 179 if (IS_ERR_OR_NULL(mmc->supply.vqmmc)) 180 return 0; 181 182 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 183 if (ret) { 184 dev_dbg(host->dev, "Regulator set error %d: %d - %d\n", 185 ret, min_uv, max_uv); 186 return ret; 187 } 188 189 return 0; 190 } 191 192 static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios) 193 { 194 int ret; 195 unsigned int clock; 196 197 clock = (ios->clock <= 25000000) ? 25000000 : ios->clock; 198 199 ret = clk_set_rate(host->biu_clk, clock); 200 if (ret) 201 dev_warn(host->dev, "failed to set rate %uHz\n", clock); 202 203 host->bus_hz = clk_get_rate(host->biu_clk); 204 } 205 206 static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 207 { 208 return 0; 209 } 210 211 static const struct dw_mci_drv_data hi6220_data = { 212 .caps = dw_mci_hi6220_caps, 213 .num_caps = ARRAY_SIZE(dw_mci_hi6220_caps), 214 .switch_voltage = dw_mci_hi6220_switch_voltage, 215 .set_ios = dw_mci_hi6220_set_ios, 216 .parse_dt = dw_mci_hi6220_parse_dt, 217 .execute_tuning = dw_mci_hi6220_execute_tuning, 218 }; 219 220 static void dw_mci_hs_set_timing(struct dw_mci *host, int timing, 221 int smpl_phase) 222 { 223 u32 drv_phase; 224 u32 smpl_dly; 225 u32 use_smpl_dly = 0; 226 u32 enable_shift = 0; 227 u32 reg_value; 228 int ctrl_id; 229 struct k3_priv *priv; 230 231 priv = host->priv; 232 ctrl_id = priv->ctrl_id; 233 234 drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase; 235 smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly; 236 if (smpl_phase == -1) 237 smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max + 238 hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2; 239 240 switch (timing) { 241 case MMC_TIMING_UHS_SDR104: 242 if (smpl_phase >= USE_DLY_MIN_SMPL && 243 smpl_phase <= USE_DLY_MAX_SMPL) 244 use_smpl_dly = 1; 245 /* fallthrough */ 246 case MMC_TIMING_UHS_SDR50: 247 if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL && 248 smpl_phase <= ENABLE_SHIFT_MAX_SMPL) 249 enable_shift = 1; 250 break; 251 } 252 253 mci_writel(host, GPIO, 0x0); 254 usleep_range(5, 10); 255 256 reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) | 257 FIELD_PREP(UHS_REG_EXT_SAMPLE_DLY_MASK, smpl_dly) | 258 FIELD_PREP(UHS_REG_EXT_SAMPLE_DRVPHASE_MASK, drv_phase); 259 mci_writel(host, UHS_REG_EXT, reg_value); 260 261 mci_writel(host, ENABLE_SHIFT, enable_shift); 262 263 reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) | 264 FIELD_PREP(GPIO_USE_SAMPLE_DLY_MASK, use_smpl_dly); 265 mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE); 266 267 /* We should delay 1ms wait for timing setting finished. */ 268 usleep_range(1000, 2000); 269 } 270 271 static int dw_mci_hi3660_init(struct dw_mci *host) 272 { 273 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD, 274 SDMMC_CARD_RD_THR_EN)); 275 276 dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1); 277 host->bus_hz /= (GENCLK_DIV + 1); 278 279 return 0; 280 } 281 282 static int dw_mci_set_sel18(struct dw_mci *host, bool set) 283 { 284 int ret; 285 unsigned int val; 286 struct k3_priv *priv; 287 288 priv = host->priv; 289 290 val = set ? SDCARD_IO_SEL18 : 0; 291 ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5, 292 SDCARD_IO_SEL18, val); 293 if (ret) { 294 dev_err(host->dev, "sel18 %u error\n", val); 295 return ret; 296 } 297 298 return 0; 299 } 300 301 static void dw_mci_hi3660_set_ios(struct dw_mci *host, struct mmc_ios *ios) 302 { 303 int ret; 304 unsigned long wanted; 305 unsigned long actual; 306 struct k3_priv *priv = host->priv; 307 308 if (!ios->clock || ios->clock == priv->cur_speed) 309 return; 310 311 wanted = ios->clock * (GENCLK_DIV + 1); 312 ret = clk_set_rate(host->ciu_clk, wanted); 313 if (ret) { 314 dev_err(host->dev, "failed to set rate %luHz\n", wanted); 315 return; 316 } 317 actual = clk_get_rate(host->ciu_clk); 318 319 dw_mci_hs_set_timing(host, ios->timing, -1); 320 host->bus_hz = actual / (GENCLK_DIV + 1); 321 host->current_speed = 0; 322 priv->cur_speed = host->bus_hz; 323 } 324 325 static int dw_mci_get_best_clksmpl(unsigned int sample_flag) 326 { 327 int i; 328 int interval; 329 unsigned int v; 330 unsigned int len; 331 unsigned int range_start = 0; 332 unsigned int range_length = 0; 333 unsigned int middle_range = 0; 334 335 if (!sample_flag) 336 return -EIO; 337 338 if (~sample_flag == 0) 339 return 0; 340 341 i = ffs(sample_flag) - 1; 342 343 /* 344 * A clock cycle is divided into 32 phases, 345 * each of which is represented by a bit, 346 * finding the optimal phase. 347 */ 348 while (i < 32) { 349 v = ror32(sample_flag, i); 350 len = ffs(~v) - 1; 351 352 if (len > range_length) { 353 range_length = len; 354 range_start = i; 355 } 356 357 interval = ffs(v >> len) - 1; 358 if (interval < 0) 359 break; 360 361 i += len + interval; 362 } 363 364 middle_range = range_start + range_length / 2; 365 if (middle_range >= 32) 366 middle_range %= 32; 367 368 return middle_range; 369 } 370 371 static int dw_mci_hi3660_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 372 { 373 int i = 0; 374 struct dw_mci *host = slot->host; 375 struct mmc_host *mmc = slot->mmc; 376 int smpl_phase = 0; 377 u32 tuning_sample_flag = 0; 378 int best_clksmpl = 0; 379 380 for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) { 381 smpl_phase %= 32; 382 383 mci_writel(host, TMOUT, ~0); 384 dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase); 385 386 if (!mmc_send_tuning(mmc, opcode, NULL)) 387 tuning_sample_flag |= (1 << smpl_phase); 388 else 389 tuning_sample_flag &= ~(1 << smpl_phase); 390 } 391 392 best_clksmpl = dw_mci_get_best_clksmpl(tuning_sample_flag); 393 if (best_clksmpl < 0) { 394 dev_err(host->dev, "All phases bad!\n"); 395 return -EIO; 396 } 397 398 dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl); 399 400 dev_info(host->dev, "tuning ok best_clksmpl %u tuning_sample_flag %x\n", 401 best_clksmpl, tuning_sample_flag); 402 return 0; 403 } 404 405 static int dw_mci_hi3660_switch_voltage(struct mmc_host *mmc, 406 struct mmc_ios *ios) 407 { 408 int ret = 0; 409 struct dw_mci_slot *slot = mmc_priv(mmc); 410 struct k3_priv *priv; 411 struct dw_mci *host; 412 413 host = slot->host; 414 priv = host->priv; 415 416 if (!priv || !priv->reg) 417 return 0; 418 419 if (priv->ctrl_id == DWMMC_SDIO_ID) 420 return 0; 421 422 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 423 ret = dw_mci_set_sel18(host, 0); 424 else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 425 ret = dw_mci_set_sel18(host, 1); 426 if (ret) 427 return ret; 428 429 if (!IS_ERR(mmc->supply.vqmmc)) { 430 ret = mmc_regulator_set_vqmmc(mmc, ios); 431 if (ret) { 432 dev_err(host->dev, "Regulator set error %d\n", ret); 433 return ret; 434 } 435 } 436 437 return 0; 438 } 439 440 static const struct dw_mci_drv_data hi3660_data = { 441 .init = dw_mci_hi3660_init, 442 .set_ios = dw_mci_hi3660_set_ios, 443 .parse_dt = dw_mci_hi6220_parse_dt, 444 .execute_tuning = dw_mci_hi3660_execute_tuning, 445 .switch_voltage = dw_mci_hi3660_switch_voltage, 446 }; 447 448 static const struct of_device_id dw_mci_k3_match[] = { 449 { .compatible = "hisilicon,hi3660-dw-mshc", .data = &hi3660_data, }, 450 { .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, }, 451 { .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, }, 452 {}, 453 }; 454 MODULE_DEVICE_TABLE(of, dw_mci_k3_match); 455 456 static int dw_mci_k3_probe(struct platform_device *pdev) 457 { 458 const struct dw_mci_drv_data *drv_data; 459 const struct of_device_id *match; 460 461 match = of_match_node(dw_mci_k3_match, pdev->dev.of_node); 462 drv_data = match->data; 463 464 return dw_mci_pltfm_register(pdev, drv_data); 465 } 466 467 static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = { 468 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 469 pm_runtime_force_resume) 470 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend, 471 dw_mci_runtime_resume, 472 NULL) 473 }; 474 475 static struct platform_driver dw_mci_k3_pltfm_driver = { 476 .probe = dw_mci_k3_probe, 477 .remove = dw_mci_pltfm_remove, 478 .driver = { 479 .name = "dwmmc_k3", 480 .of_match_table = dw_mci_k3_match, 481 .pm = &dw_mci_k3_dev_pm_ops, 482 }, 483 }; 484 485 module_platform_driver(dw_mci_k3_pltfm_driver); 486 487 MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension"); 488 MODULE_LICENSE("GPL v2"); 489 MODULE_ALIAS("platform:dwmmc_k3"); 490