1 /* 2 * Copyright (c) 2013 Linaro Ltd. 3 * Copyright (c) 2013 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/mmc/host.h> 16 #include <linux/module.h> 17 #include <linux/of_address.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 23 #include "dw_mmc.h" 24 #include "dw_mmc-pltfm.h" 25 26 /* 27 * hi6220 sd only support io voltage 1.8v and 3v 28 * Also need config AO_SCTRL_SEL18 accordingly 29 */ 30 #define AO_SCTRL_SEL18 BIT(10) 31 #define AO_SCTRL_CTRL3 0x40C 32 33 #define DWMMC_SDIO_ID 2 34 35 #define SOC_SCTRL_SCPERCTRL5 (0x314) 36 #define SDCARD_IO_SEL18 BIT(2) 37 38 #define SDCARD_RD_THRESHOLD (512) 39 40 #define GENCLK_DIV (7) 41 42 #define GPIO_CLK_ENABLE BIT(16) 43 #define GPIO_CLK_DIV_MASK GENMASK(11, 8) 44 #define GPIO_USE_SAMPLE_DLY_MASK GENMASK(13, 13) 45 #define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16) 46 #define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK GENMASK(25, 21) 47 #define UHS_REG_EXT_SAMPLE_DLY_MASK GENMASK(30, 26) 48 49 #define TIMING_MODE 3 50 #define TIMING_CFG_NUM 10 51 52 #define NUM_PHASES (40) 53 54 #define ENABLE_SHIFT_MIN_SMPL (4) 55 #define ENABLE_SHIFT_MAX_SMPL (12) 56 #define USE_DLY_MIN_SMPL (11) 57 #define USE_DLY_MAX_SMPL (14) 58 59 struct k3_priv { 60 int ctrl_id; 61 u32 cur_speed; 62 struct regmap *reg; 63 }; 64 65 static unsigned long dw_mci_hi6220_caps[] = { 66 MMC_CAP_CMD23, 67 MMC_CAP_CMD23, 68 0 69 }; 70 71 struct hs_timing { 72 u32 drv_phase; 73 u32 smpl_dly; 74 u32 smpl_phase_max; 75 u32 smpl_phase_min; 76 }; 77 78 static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = { 79 { /* reserved */ }, 80 { /* SD */ 81 {7, 0, 15, 15,}, /* 0: LEGACY 400k */ 82 {6, 0, 4, 4,}, /* 1: MMC_HS */ 83 {6, 0, 3, 3,}, /* 2: SD_HS */ 84 {6, 0, 15, 15,}, /* 3: SDR12 */ 85 {6, 0, 2, 2,}, /* 4: SDR25 */ 86 {4, 0, 11, 0,}, /* 5: SDR50 */ 87 {6, 4, 15, 0,}, /* 6: SDR104 */ 88 {0}, /* 7: DDR50 */ 89 {0}, /* 8: DDR52 */ 90 {0}, /* 9: HS200 */ 91 }, 92 { /* SDIO */ 93 {7, 0, 15, 15,}, /* 0: LEGACY 400k */ 94 {0}, /* 1: MMC_HS */ 95 {6, 0, 15, 15,}, /* 2: SD_HS */ 96 {6, 0, 15, 15,}, /* 3: SDR12 */ 97 {6, 0, 0, 0,}, /* 4: SDR25 */ 98 {4, 0, 12, 0,}, /* 5: SDR50 */ 99 {5, 4, 15, 0,}, /* 6: SDR104 */ 100 {0}, /* 7: DDR50 */ 101 {0}, /* 8: DDR52 */ 102 {0}, /* 9: HS200 */ 103 } 104 }; 105 106 static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios) 107 { 108 int ret; 109 110 ret = clk_set_rate(host->ciu_clk, ios->clock); 111 if (ret) 112 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); 113 114 host->bus_hz = clk_get_rate(host->ciu_clk); 115 } 116 117 static const struct dw_mci_drv_data k3_drv_data = { 118 .set_ios = dw_mci_k3_set_ios, 119 }; 120 121 static int dw_mci_hi6220_parse_dt(struct dw_mci *host) 122 { 123 struct k3_priv *priv; 124 125 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 126 if (!priv) 127 return -ENOMEM; 128 129 priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node, 130 "hisilicon,peripheral-syscon"); 131 if (IS_ERR(priv->reg)) 132 priv->reg = NULL; 133 134 priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 135 if (priv->ctrl_id < 0) 136 priv->ctrl_id = 0; 137 138 if (priv->ctrl_id >= TIMING_MODE) 139 return -EINVAL; 140 141 host->priv = priv; 142 return 0; 143 } 144 145 static int dw_mci_hi6220_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 146 { 147 struct dw_mci_slot *slot = mmc_priv(mmc); 148 struct k3_priv *priv; 149 struct dw_mci *host; 150 int min_uv, max_uv; 151 int ret; 152 153 host = slot->host; 154 priv = host->priv; 155 156 if (!priv || !priv->reg) 157 return 0; 158 159 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 160 ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3, 161 AO_SCTRL_SEL18, 0); 162 min_uv = 3000000; 163 max_uv = 3000000; 164 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 165 ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3, 166 AO_SCTRL_SEL18, AO_SCTRL_SEL18); 167 min_uv = 1800000; 168 max_uv = 1800000; 169 } else { 170 dev_dbg(host->dev, "voltage not supported\n"); 171 return -EINVAL; 172 } 173 174 if (ret) { 175 dev_dbg(host->dev, "switch voltage failed\n"); 176 return ret; 177 } 178 179 if (IS_ERR_OR_NULL(mmc->supply.vqmmc)) 180 return 0; 181 182 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 183 if (ret) { 184 dev_dbg(host->dev, "Regulator set error %d: %d - %d\n", 185 ret, min_uv, max_uv); 186 return ret; 187 } 188 189 return 0; 190 } 191 192 static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios) 193 { 194 int ret; 195 unsigned int clock; 196 197 clock = (ios->clock <= 25000000) ? 25000000 : ios->clock; 198 199 ret = clk_set_rate(host->biu_clk, clock); 200 if (ret) 201 dev_warn(host->dev, "failed to set rate %uHz\n", clock); 202 203 host->bus_hz = clk_get_rate(host->biu_clk); 204 } 205 206 static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 207 { 208 return 0; 209 } 210 211 static const struct dw_mci_drv_data hi6220_data = { 212 .caps = dw_mci_hi6220_caps, 213 .switch_voltage = dw_mci_hi6220_switch_voltage, 214 .set_ios = dw_mci_hi6220_set_ios, 215 .parse_dt = dw_mci_hi6220_parse_dt, 216 .execute_tuning = dw_mci_hi6220_execute_tuning, 217 }; 218 219 static void dw_mci_hs_set_timing(struct dw_mci *host, int timing, 220 int smpl_phase) 221 { 222 u32 drv_phase; 223 u32 smpl_dly; 224 u32 use_smpl_dly = 0; 225 u32 enable_shift = 0; 226 u32 reg_value; 227 int ctrl_id; 228 struct k3_priv *priv; 229 230 priv = host->priv; 231 ctrl_id = priv->ctrl_id; 232 233 drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase; 234 smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly; 235 if (smpl_phase == -1) 236 smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max + 237 hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2; 238 239 switch (timing) { 240 case MMC_TIMING_UHS_SDR104: 241 if (smpl_phase >= USE_DLY_MIN_SMPL && 242 smpl_phase <= USE_DLY_MAX_SMPL) 243 use_smpl_dly = 1; 244 /* fallthrough */ 245 case MMC_TIMING_UHS_SDR50: 246 if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL && 247 smpl_phase <= ENABLE_SHIFT_MAX_SMPL) 248 enable_shift = 1; 249 break; 250 } 251 252 mci_writel(host, GPIO, 0x0); 253 usleep_range(5, 10); 254 255 reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) | 256 FIELD_PREP(UHS_REG_EXT_SAMPLE_DLY_MASK, smpl_dly) | 257 FIELD_PREP(UHS_REG_EXT_SAMPLE_DRVPHASE_MASK, drv_phase); 258 mci_writel(host, UHS_REG_EXT, reg_value); 259 260 mci_writel(host, ENABLE_SHIFT, enable_shift); 261 262 reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) | 263 FIELD_PREP(GPIO_USE_SAMPLE_DLY_MASK, use_smpl_dly); 264 mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE); 265 266 /* We should delay 1ms wait for timing setting finished. */ 267 usleep_range(1000, 2000); 268 } 269 270 static int dw_mci_hi3660_init(struct dw_mci *host) 271 { 272 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD, 273 SDMMC_CARD_RD_THR_EN)); 274 275 dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1); 276 host->bus_hz /= (GENCLK_DIV + 1); 277 278 return 0; 279 } 280 281 static int dw_mci_set_sel18(struct dw_mci *host, bool set) 282 { 283 int ret; 284 unsigned int val; 285 struct k3_priv *priv; 286 287 priv = host->priv; 288 289 val = set ? SDCARD_IO_SEL18 : 0; 290 ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5, 291 SDCARD_IO_SEL18, val); 292 if (ret) { 293 dev_err(host->dev, "sel18 %u error\n", val); 294 return ret; 295 } 296 297 return 0; 298 } 299 300 static void dw_mci_hi3660_set_ios(struct dw_mci *host, struct mmc_ios *ios) 301 { 302 int ret; 303 unsigned long wanted; 304 unsigned long actual; 305 struct k3_priv *priv = host->priv; 306 307 if (!ios->clock || ios->clock == priv->cur_speed) 308 return; 309 310 wanted = ios->clock * (GENCLK_DIV + 1); 311 ret = clk_set_rate(host->ciu_clk, wanted); 312 if (ret) { 313 dev_err(host->dev, "failed to set rate %luHz\n", wanted); 314 return; 315 } 316 actual = clk_get_rate(host->ciu_clk); 317 318 dw_mci_hs_set_timing(host, ios->timing, -1); 319 host->bus_hz = actual / (GENCLK_DIV + 1); 320 host->current_speed = 0; 321 priv->cur_speed = host->bus_hz; 322 } 323 324 static int dw_mci_get_best_clksmpl(unsigned int sample_flag) 325 { 326 int i; 327 int interval; 328 unsigned int v; 329 unsigned int len; 330 unsigned int range_start = 0; 331 unsigned int range_length = 0; 332 unsigned int middle_range = 0; 333 334 if (!sample_flag) 335 return -EIO; 336 337 if (~sample_flag == 0) 338 return 0; 339 340 i = ffs(sample_flag) - 1; 341 342 /* 343 * A clock cycle is divided into 32 phases, 344 * each of which is represented by a bit, 345 * finding the optimal phase. 346 */ 347 while (i < 32) { 348 v = ror32(sample_flag, i); 349 len = ffs(~v) - 1; 350 351 if (len > range_length) { 352 range_length = len; 353 range_start = i; 354 } 355 356 interval = ffs(v >> len) - 1; 357 if (interval < 0) 358 break; 359 360 i += len + interval; 361 } 362 363 middle_range = range_start + range_length / 2; 364 if (middle_range >= 32) 365 middle_range %= 32; 366 367 return middle_range; 368 } 369 370 static int dw_mci_hi3660_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 371 { 372 int i = 0; 373 struct dw_mci *host = slot->host; 374 struct mmc_host *mmc = slot->mmc; 375 int smpl_phase = 0; 376 u32 tuning_sample_flag = 0; 377 int best_clksmpl = 0; 378 379 for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) { 380 smpl_phase %= 32; 381 382 mci_writel(host, TMOUT, ~0); 383 dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase); 384 385 if (!mmc_send_tuning(mmc, opcode, NULL)) 386 tuning_sample_flag |= (1 << smpl_phase); 387 else 388 tuning_sample_flag &= ~(1 << smpl_phase); 389 } 390 391 best_clksmpl = dw_mci_get_best_clksmpl(tuning_sample_flag); 392 if (best_clksmpl < 0) { 393 dev_err(host->dev, "All phases bad!\n"); 394 return -EIO; 395 } 396 397 dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl); 398 399 dev_info(host->dev, "tuning ok best_clksmpl %u tuning_sample_flag %x\n", 400 best_clksmpl, tuning_sample_flag); 401 return 0; 402 } 403 404 static int dw_mci_hi3660_switch_voltage(struct mmc_host *mmc, 405 struct mmc_ios *ios) 406 { 407 int ret = 0; 408 struct dw_mci_slot *slot = mmc_priv(mmc); 409 struct k3_priv *priv; 410 struct dw_mci *host; 411 412 host = slot->host; 413 priv = host->priv; 414 415 if (!priv || !priv->reg) 416 return 0; 417 418 if (priv->ctrl_id == DWMMC_SDIO_ID) 419 return 0; 420 421 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 422 ret = dw_mci_set_sel18(host, 0); 423 else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 424 ret = dw_mci_set_sel18(host, 1); 425 if (ret) 426 return ret; 427 428 if (!IS_ERR(mmc->supply.vqmmc)) { 429 ret = mmc_regulator_set_vqmmc(mmc, ios); 430 if (ret) { 431 dev_err(host->dev, "Regulator set error %d\n", ret); 432 return ret; 433 } 434 } 435 436 return 0; 437 } 438 439 static const struct dw_mci_drv_data hi3660_data = { 440 .init = dw_mci_hi3660_init, 441 .set_ios = dw_mci_hi3660_set_ios, 442 .parse_dt = dw_mci_hi6220_parse_dt, 443 .execute_tuning = dw_mci_hi3660_execute_tuning, 444 .switch_voltage = dw_mci_hi3660_switch_voltage, 445 }; 446 447 static const struct of_device_id dw_mci_k3_match[] = { 448 { .compatible = "hisilicon,hi3660-dw-mshc", .data = &hi3660_data, }, 449 { .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, }, 450 { .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, }, 451 {}, 452 }; 453 MODULE_DEVICE_TABLE(of, dw_mci_k3_match); 454 455 static int dw_mci_k3_probe(struct platform_device *pdev) 456 { 457 const struct dw_mci_drv_data *drv_data; 458 const struct of_device_id *match; 459 460 match = of_match_node(dw_mci_k3_match, pdev->dev.of_node); 461 drv_data = match->data; 462 463 return dw_mci_pltfm_register(pdev, drv_data); 464 } 465 466 static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = { 467 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 468 pm_runtime_force_resume) 469 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend, 470 dw_mci_runtime_resume, 471 NULL) 472 }; 473 474 static struct platform_driver dw_mci_k3_pltfm_driver = { 475 .probe = dw_mci_k3_probe, 476 .remove = dw_mci_pltfm_remove, 477 .driver = { 478 .name = "dwmmc_k3", 479 .of_match_table = dw_mci_k3_match, 480 .pm = &dw_mci_k3_dev_pm_ops, 481 }, 482 }; 483 484 module_platform_driver(dw_mci_k3_pltfm_driver); 485 486 MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension"); 487 MODULE_LICENSE("GPL v2"); 488 MODULE_ALIAS("platform:dwmmc_k3"); 489