1 /* 2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 3 * 4 * Copyright (C) 2012, Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mmc/dw_mmc.h> 17 #include <linux/mmc/mmc.h> 18 #include <linux/of.h> 19 #include <linux/of_gpio.h> 20 #include <linux/slab.h> 21 22 #include "dw_mmc.h" 23 #include "dw_mmc-pltfm.h" 24 #include "dw_mmc-exynos.h" 25 26 /* Variations in Exynos specific dw-mshc controller */ 27 enum dw_mci_exynos_type { 28 DW_MCI_TYPE_EXYNOS4210, 29 DW_MCI_TYPE_EXYNOS4412, 30 DW_MCI_TYPE_EXYNOS5250, 31 DW_MCI_TYPE_EXYNOS5420, 32 DW_MCI_TYPE_EXYNOS5420_SMU, 33 DW_MCI_TYPE_EXYNOS7, 34 DW_MCI_TYPE_EXYNOS7_SMU, 35 }; 36 37 /* Exynos implementation specific driver private data */ 38 struct dw_mci_exynos_priv_data { 39 enum dw_mci_exynos_type ctrl_type; 40 u8 ciu_div; 41 u32 sdr_timing; 42 u32 ddr_timing; 43 u32 hs400_timing; 44 u32 tuned_sample; 45 u32 cur_speed; 46 u32 dqs_delay; 47 u32 saved_dqs_en; 48 u32 saved_strobe_ctrl; 49 }; 50 51 static struct dw_mci_exynos_compatible { 52 char *compatible; 53 enum dw_mci_exynos_type ctrl_type; 54 } exynos_compat[] = { 55 { 56 .compatible = "samsung,exynos4210-dw-mshc", 57 .ctrl_type = DW_MCI_TYPE_EXYNOS4210, 58 }, { 59 .compatible = "samsung,exynos4412-dw-mshc", 60 .ctrl_type = DW_MCI_TYPE_EXYNOS4412, 61 }, { 62 .compatible = "samsung,exynos5250-dw-mshc", 63 .ctrl_type = DW_MCI_TYPE_EXYNOS5250, 64 }, { 65 .compatible = "samsung,exynos5420-dw-mshc", 66 .ctrl_type = DW_MCI_TYPE_EXYNOS5420, 67 }, { 68 .compatible = "samsung,exynos5420-dw-mshc-smu", 69 .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU, 70 }, { 71 .compatible = "samsung,exynos7-dw-mshc", 72 .ctrl_type = DW_MCI_TYPE_EXYNOS7, 73 }, { 74 .compatible = "samsung,exynos7-dw-mshc-smu", 75 .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, 76 }, 77 }; 78 79 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) 80 { 81 struct dw_mci_exynos_priv_data *priv = host->priv; 82 83 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 84 return EXYNOS4412_FIXED_CIU_CLK_DIV; 85 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 86 return EXYNOS4210_FIXED_CIU_CLK_DIV; 87 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 88 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 89 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; 90 else 91 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; 92 } 93 94 static void dw_mci_exynos_config_smu(struct dw_mci *host) 95 { 96 struct dw_mci_exynos_priv_data *priv = host->priv; 97 98 /* 99 * If Exynos is provided the Security management, 100 * set for non-ecryption mode at this time. 101 */ 102 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || 103 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { 104 mci_writel(host, MPSBEGIN0, 0); 105 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); 106 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | 107 SDMMC_MPSCTRL_NON_SECURE_READ_BIT | 108 SDMMC_MPSCTRL_VALID | 109 SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); 110 } 111 } 112 113 static int dw_mci_exynos_priv_init(struct dw_mci *host) 114 { 115 struct dw_mci_exynos_priv_data *priv = host->priv; 116 117 dw_mci_exynos_config_smu(host); 118 119 if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) { 120 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL); 121 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN); 122 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR; 123 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en); 124 if (!priv->dqs_delay) 125 priv->dqs_delay = 126 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); 127 } 128 129 host->bus_hz /= (priv->ciu_div + 1); 130 131 return 0; 132 } 133 134 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) 135 { 136 struct dw_mci_exynos_priv_data *priv = host->priv; 137 u32 clksel; 138 139 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 140 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 141 clksel = mci_readl(host, CLKSEL64); 142 else 143 clksel = mci_readl(host, CLKSEL); 144 145 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; 146 147 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 148 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 149 mci_writel(host, CLKSEL64, clksel); 150 else 151 mci_writel(host, CLKSEL, clksel); 152 153 /* 154 * Exynos4412 and Exynos5250 extends the use of CMD register with the 155 * use of bit 29 (which is reserved on standard MSHC controllers) for 156 * optionally bypassing the HOLD register for command and data. The 157 * HOLD register should be bypassed in case there is no phase shift 158 * applied on CMD/DATA that is sent to the card. 159 */ 160 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->cur_slot) 161 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags); 162 } 163 164 #ifdef CONFIG_PM_SLEEP 165 static int dw_mci_exynos_suspend(struct device *dev) 166 { 167 struct dw_mci *host = dev_get_drvdata(dev); 168 169 return dw_mci_suspend(host); 170 } 171 172 static int dw_mci_exynos_resume(struct device *dev) 173 { 174 struct dw_mci *host = dev_get_drvdata(dev); 175 176 dw_mci_exynos_config_smu(host); 177 return dw_mci_resume(host); 178 } 179 180 /** 181 * dw_mci_exynos_resume_noirq - Exynos-specific resume code 182 * 183 * On exynos5420 there is a silicon errata that will sometimes leave the 184 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate 185 * that it fired and we can clear it by writing a 1 back. Clear it to prevent 186 * interrupts from going off constantly. 187 * 188 * We run this code on all exynos variants because it doesn't hurt. 189 */ 190 191 static int dw_mci_exynos_resume_noirq(struct device *dev) 192 { 193 struct dw_mci *host = dev_get_drvdata(dev); 194 struct dw_mci_exynos_priv_data *priv = host->priv; 195 u32 clksel; 196 197 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 198 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 199 clksel = mci_readl(host, CLKSEL64); 200 else 201 clksel = mci_readl(host, CLKSEL); 202 203 if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { 204 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 205 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 206 mci_writel(host, CLKSEL64, clksel); 207 else 208 mci_writel(host, CLKSEL, clksel); 209 } 210 211 return 0; 212 } 213 #else 214 #define dw_mci_exynos_suspend NULL 215 #define dw_mci_exynos_resume NULL 216 #define dw_mci_exynos_resume_noirq NULL 217 #endif /* CONFIG_PM_SLEEP */ 218 219 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) 220 { 221 struct dw_mci_exynos_priv_data *priv = host->priv; 222 u32 dqs, strobe; 223 224 /* 225 * Not supported to configure register 226 * related to HS400 227 */ 228 if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) { 229 if (timing == MMC_TIMING_MMC_HS400) 230 dev_warn(host->dev, 231 "cannot configure HS400, unsupported chipset\n"); 232 return; 233 } 234 235 dqs = priv->saved_dqs_en; 236 strobe = priv->saved_strobe_ctrl; 237 238 if (timing == MMC_TIMING_MMC_HS400) { 239 dqs |= DATA_STROBE_EN; 240 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay); 241 } else { 242 dqs &= ~DATA_STROBE_EN; 243 } 244 245 mci_writel(host, HS400_DQS_EN, dqs); 246 mci_writel(host, HS400_DLINE_CTRL, strobe); 247 } 248 249 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted) 250 { 251 struct dw_mci_exynos_priv_data *priv = host->priv; 252 unsigned long actual; 253 u8 div; 254 int ret; 255 /* 256 * Don't care if wanted clock is zero or 257 * ciu clock is unavailable 258 */ 259 if (!wanted || IS_ERR(host->ciu_clk)) 260 return; 261 262 /* Guaranteed minimum frequency for cclkin */ 263 if (wanted < EXYNOS_CCLKIN_MIN) 264 wanted = EXYNOS_CCLKIN_MIN; 265 266 if (wanted == priv->cur_speed) 267 return; 268 269 div = dw_mci_exynos_get_ciu_div(host); 270 ret = clk_set_rate(host->ciu_clk, wanted * div); 271 if (ret) 272 dev_warn(host->dev, 273 "failed to set clk-rate %u error: %d\n", 274 wanted * div, ret); 275 actual = clk_get_rate(host->ciu_clk); 276 host->bus_hz = actual / div; 277 priv->cur_speed = wanted; 278 host->current_speed = 0; 279 } 280 281 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) 282 { 283 struct dw_mci_exynos_priv_data *priv = host->priv; 284 unsigned int wanted = ios->clock; 285 u32 timing = ios->timing, clksel; 286 287 switch (timing) { 288 case MMC_TIMING_MMC_HS400: 289 /* Update tuned sample timing */ 290 clksel = SDMMC_CLKSEL_UP_SAMPLE( 291 priv->hs400_timing, priv->tuned_sample); 292 wanted <<= 1; 293 break; 294 case MMC_TIMING_MMC_DDR52: 295 clksel = priv->ddr_timing; 296 /* Should be double rate for DDR mode */ 297 if (ios->bus_width == MMC_BUS_WIDTH_8) 298 wanted <<= 1; 299 break; 300 default: 301 clksel = priv->sdr_timing; 302 } 303 304 /* Set clock timing for the requested speed mode*/ 305 dw_mci_exynos_set_clksel_timing(host, clksel); 306 307 /* Configure setting for HS400 */ 308 dw_mci_exynos_config_hs400(host, timing); 309 310 /* Configure clock rate */ 311 dw_mci_exynos_adjust_clock(host, wanted); 312 } 313 314 static int dw_mci_exynos_parse_dt(struct dw_mci *host) 315 { 316 struct dw_mci_exynos_priv_data *priv; 317 struct device_node *np = host->dev->of_node; 318 u32 timing[2]; 319 u32 div = 0; 320 int idx; 321 int ret; 322 323 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 324 if (!priv) 325 return -ENOMEM; 326 327 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) { 328 if (of_device_is_compatible(np, exynos_compat[idx].compatible)) 329 priv->ctrl_type = exynos_compat[idx].ctrl_type; 330 } 331 332 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 333 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; 334 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 335 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; 336 else { 337 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); 338 priv->ciu_div = div; 339 } 340 341 ret = of_property_read_u32_array(np, 342 "samsung,dw-mshc-sdr-timing", timing, 2); 343 if (ret) 344 return ret; 345 346 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 347 348 ret = of_property_read_u32_array(np, 349 "samsung,dw-mshc-ddr-timing", timing, 2); 350 if (ret) 351 return ret; 352 353 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 354 355 ret = of_property_read_u32_array(np, 356 "samsung,dw-mshc-hs400-timing", timing, 2); 357 if (!ret && of_property_read_u32(np, 358 "samsung,read-strobe-delay", &priv->dqs_delay)) 359 dev_dbg(host->dev, 360 "read-strobe-delay is not found, assuming usage of default value\n"); 361 362 priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], 363 HS400_FIXED_CIU_CLK_DIV); 364 host->priv = priv; 365 return 0; 366 } 367 368 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) 369 { 370 struct dw_mci_exynos_priv_data *priv = host->priv; 371 372 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 373 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 374 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); 375 else 376 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL)); 377 } 378 379 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) 380 { 381 u32 clksel; 382 struct dw_mci_exynos_priv_data *priv = host->priv; 383 384 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 385 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 386 clksel = mci_readl(host, CLKSEL64); 387 else 388 clksel = mci_readl(host, CLKSEL); 389 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); 390 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 391 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 392 mci_writel(host, CLKSEL64, clksel); 393 else 394 mci_writel(host, CLKSEL, clksel); 395 } 396 397 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) 398 { 399 struct dw_mci_exynos_priv_data *priv = host->priv; 400 u32 clksel; 401 u8 sample; 402 403 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 404 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 405 clksel = mci_readl(host, CLKSEL64); 406 else 407 clksel = mci_readl(host, CLKSEL); 408 409 sample = (clksel + 1) & 0x7; 410 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); 411 412 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 413 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 414 mci_writel(host, CLKSEL64, clksel); 415 else 416 mci_writel(host, CLKSEL, clksel); 417 418 return sample; 419 } 420 421 static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates) 422 { 423 const u8 iter = 8; 424 u8 __c; 425 s8 i, loc = -1; 426 427 for (i = 0; i < iter; i++) { 428 __c = ror8(candiates, i); 429 if ((__c & 0xc7) == 0xc7) { 430 loc = i; 431 goto out; 432 } 433 } 434 435 for (i = 0; i < iter; i++) { 436 __c = ror8(candiates, i); 437 if ((__c & 0x83) == 0x83) { 438 loc = i; 439 goto out; 440 } 441 } 442 443 out: 444 return loc; 445 } 446 447 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 448 { 449 struct dw_mci *host = slot->host; 450 struct dw_mci_exynos_priv_data *priv = host->priv; 451 struct mmc_host *mmc = slot->mmc; 452 u8 start_smpl, smpl, candiates = 0; 453 s8 found = -1; 454 int ret = 0; 455 456 start_smpl = dw_mci_exynos_get_clksmpl(host); 457 458 do { 459 mci_writel(host, TMOUT, ~0); 460 smpl = dw_mci_exynos_move_next_clksmpl(host); 461 462 if (!mmc_send_tuning(mmc, opcode, NULL)) 463 candiates |= (1 << smpl); 464 465 } while (start_smpl != smpl); 466 467 found = dw_mci_exynos_get_best_clksmpl(candiates); 468 if (found >= 0) { 469 dw_mci_exynos_set_clksmpl(host, found); 470 priv->tuned_sample = found; 471 } else { 472 ret = -EIO; 473 } 474 475 return ret; 476 } 477 478 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host, 479 struct mmc_ios *ios) 480 { 481 struct dw_mci_exynos_priv_data *priv = host->priv; 482 483 dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing); 484 dw_mci_exynos_adjust_clock(host, (ios->clock) << 1); 485 486 return 0; 487 } 488 489 /* Common capabilities of Exynos4/Exynos5 SoC */ 490 static unsigned long exynos_dwmmc_caps[4] = { 491 MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, 492 MMC_CAP_CMD23, 493 MMC_CAP_CMD23, 494 MMC_CAP_CMD23, 495 }; 496 497 static const struct dw_mci_drv_data exynos_drv_data = { 498 .caps = exynos_dwmmc_caps, 499 .init = dw_mci_exynos_priv_init, 500 .set_ios = dw_mci_exynos_set_ios, 501 .parse_dt = dw_mci_exynos_parse_dt, 502 .execute_tuning = dw_mci_exynos_execute_tuning, 503 .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning, 504 }; 505 506 static const struct of_device_id dw_mci_exynos_match[] = { 507 { .compatible = "samsung,exynos4412-dw-mshc", 508 .data = &exynos_drv_data, }, 509 { .compatible = "samsung,exynos5250-dw-mshc", 510 .data = &exynos_drv_data, }, 511 { .compatible = "samsung,exynos5420-dw-mshc", 512 .data = &exynos_drv_data, }, 513 { .compatible = "samsung,exynos5420-dw-mshc-smu", 514 .data = &exynos_drv_data, }, 515 { .compatible = "samsung,exynos7-dw-mshc", 516 .data = &exynos_drv_data, }, 517 { .compatible = "samsung,exynos7-dw-mshc-smu", 518 .data = &exynos_drv_data, }, 519 {}, 520 }; 521 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match); 522 523 static int dw_mci_exynos_probe(struct platform_device *pdev) 524 { 525 const struct dw_mci_drv_data *drv_data; 526 const struct of_device_id *match; 527 528 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node); 529 drv_data = match->data; 530 return dw_mci_pltfm_register(pdev, drv_data); 531 } 532 533 static const struct dev_pm_ops dw_mci_exynos_pmops = { 534 SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume) 535 .resume_noirq = dw_mci_exynos_resume_noirq, 536 .thaw_noirq = dw_mci_exynos_resume_noirq, 537 .restore_noirq = dw_mci_exynos_resume_noirq, 538 }; 539 540 static struct platform_driver dw_mci_exynos_pltfm_driver = { 541 .probe = dw_mci_exynos_probe, 542 .remove = dw_mci_pltfm_remove, 543 .driver = { 544 .name = "dwmmc_exynos", 545 .of_match_table = dw_mci_exynos_match, 546 .pm = &dw_mci_exynos_pmops, 547 }, 548 }; 549 550 module_platform_driver(dw_mci_exynos_pltfm_driver); 551 552 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension"); 553 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com"); 554 MODULE_LICENSE("GPL v2"); 555 MODULE_ALIAS("platform:dwmmc_exynos"); 556