1 /* 2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 3 * 4 * Copyright (C) 2012, Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mmc/dw_mmc.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 20 #include "dw_mmc.h" 21 #include "dw_mmc-pltfm.h" 22 23 #define NUM_PINS(x) (x + 2) 24 25 #define SDMMC_CLKSEL 0x09C 26 #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) 27 #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) 28 #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) 29 #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) 30 #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ 31 SDMMC_CLKSEL_CCLK_DRIVE(y) | \ 32 SDMMC_CLKSEL_CCLK_DIVIDER(z)) 33 34 #define EXYNOS4210_FIXED_CIU_CLK_DIV 2 35 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4 36 37 /* Variations in Exynos specific dw-mshc controller */ 38 enum dw_mci_exynos_type { 39 DW_MCI_TYPE_EXYNOS4210, 40 DW_MCI_TYPE_EXYNOS4412, 41 DW_MCI_TYPE_EXYNOS5250, 42 DW_MCI_TYPE_EXYNOS5420, 43 }; 44 45 /* Exynos implementation specific driver private data */ 46 struct dw_mci_exynos_priv_data { 47 enum dw_mci_exynos_type ctrl_type; 48 u8 ciu_div; 49 u32 sdr_timing; 50 u32 ddr_timing; 51 }; 52 53 static struct dw_mci_exynos_compatible { 54 char *compatible; 55 enum dw_mci_exynos_type ctrl_type; 56 } exynos_compat[] = { 57 { 58 .compatible = "samsung,exynos4210-dw-mshc", 59 .ctrl_type = DW_MCI_TYPE_EXYNOS4210, 60 }, { 61 .compatible = "samsung,exynos4412-dw-mshc", 62 .ctrl_type = DW_MCI_TYPE_EXYNOS4412, 63 }, { 64 .compatible = "samsung,exynos5250-dw-mshc", 65 .ctrl_type = DW_MCI_TYPE_EXYNOS5250, 66 }, { 67 .compatible = "samsung,exynos5420-dw-mshc", 68 .ctrl_type = DW_MCI_TYPE_EXYNOS5420, 69 }, 70 }; 71 72 static int dw_mci_exynos_priv_init(struct dw_mci *host) 73 { 74 struct dw_mci_exynos_priv_data *priv; 75 int idx; 76 77 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 78 if (!priv) { 79 dev_err(host->dev, "mem alloc failed for private data\n"); 80 return -ENOMEM; 81 } 82 83 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) { 84 if (of_device_is_compatible(host->dev->of_node, 85 exynos_compat[idx].compatible)) 86 priv->ctrl_type = exynos_compat[idx].ctrl_type; 87 } 88 89 host->priv = priv; 90 return 0; 91 } 92 93 static int dw_mci_exynos_setup_clock(struct dw_mci *host) 94 { 95 struct dw_mci_exynos_priv_data *priv = host->priv; 96 97 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 || 98 priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) 99 host->bus_hz /= (priv->ciu_div + 1); 100 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 101 host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV; 102 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 103 host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV; 104 105 return 0; 106 } 107 108 static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr) 109 { 110 /* 111 * Exynos4412 and Exynos5250 extends the use of CMD register with the 112 * use of bit 29 (which is reserved on standard MSHC controllers) for 113 * optionally bypassing the HOLD register for command and data. The 114 * HOLD register should be bypassed in case there is no phase shift 115 * applied on CMD/DATA that is sent to the card. 116 */ 117 if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL))) 118 *cmdr |= SDMMC_CMD_USE_HOLD_REG; 119 } 120 121 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) 122 { 123 struct dw_mci_exynos_priv_data *priv = host->priv; 124 125 if (ios->timing == MMC_TIMING_UHS_DDR50) 126 mci_writel(host, CLKSEL, priv->ddr_timing); 127 else 128 mci_writel(host, CLKSEL, priv->sdr_timing); 129 } 130 131 static int dw_mci_exynos_parse_dt(struct dw_mci *host) 132 { 133 struct dw_mci_exynos_priv_data *priv = host->priv; 134 struct device_node *np = host->dev->of_node; 135 u32 timing[2]; 136 u32 div = 0; 137 int ret; 138 139 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); 140 priv->ciu_div = div; 141 142 ret = of_property_read_u32_array(np, 143 "samsung,dw-mshc-sdr-timing", timing, 2); 144 if (ret) 145 return ret; 146 147 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 148 149 ret = of_property_read_u32_array(np, 150 "samsung,dw-mshc-ddr-timing", timing, 2); 151 if (ret) 152 return ret; 153 154 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 155 return 0; 156 } 157 158 /* Common capabilities of Exynos4/Exynos5 SoC */ 159 static unsigned long exynos_dwmmc_caps[4] = { 160 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | 161 MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, 162 MMC_CAP_CMD23, 163 MMC_CAP_CMD23, 164 MMC_CAP_CMD23, 165 }; 166 167 static const struct dw_mci_drv_data exynos_drv_data = { 168 .caps = exynos_dwmmc_caps, 169 .init = dw_mci_exynos_priv_init, 170 .setup_clock = dw_mci_exynos_setup_clock, 171 .prepare_command = dw_mci_exynos_prepare_command, 172 .set_ios = dw_mci_exynos_set_ios, 173 .parse_dt = dw_mci_exynos_parse_dt, 174 }; 175 176 static const struct of_device_id dw_mci_exynos_match[] = { 177 { .compatible = "samsung,exynos4412-dw-mshc", 178 .data = &exynos_drv_data, }, 179 { .compatible = "samsung,exynos5250-dw-mshc", 180 .data = &exynos_drv_data, }, 181 { .compatible = "samsung,exynos5420-dw-mshc", 182 .data = &exynos_drv_data, }, 183 {}, 184 }; 185 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match); 186 187 static int dw_mci_exynos_probe(struct platform_device *pdev) 188 { 189 const struct dw_mci_drv_data *drv_data; 190 const struct of_device_id *match; 191 192 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node); 193 drv_data = match->data; 194 return dw_mci_pltfm_register(pdev, drv_data); 195 } 196 197 static struct platform_driver dw_mci_exynos_pltfm_driver = { 198 .probe = dw_mci_exynos_probe, 199 .remove = __exit_p(dw_mci_pltfm_remove), 200 .driver = { 201 .name = "dwmmc_exynos", 202 .of_match_table = dw_mci_exynos_match, 203 .pm = &dw_mci_pltfm_pmops, 204 }, 205 }; 206 207 module_platform_driver(dw_mci_exynos_pltfm_driver); 208 209 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension"); 210 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com"); 211 MODULE_LICENSE("GPL v2"); 212 MODULE_ALIAS("platform:dwmmc-exynos"); 213