1 /* 2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 3 * 4 * Copyright (C) 2012, Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mmc/mmc.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 22 #include "dw_mmc.h" 23 #include "dw_mmc-pltfm.h" 24 #include "dw_mmc-exynos.h" 25 26 /* Variations in Exynos specific dw-mshc controller */ 27 enum dw_mci_exynos_type { 28 DW_MCI_TYPE_EXYNOS4210, 29 DW_MCI_TYPE_EXYNOS4412, 30 DW_MCI_TYPE_EXYNOS5250, 31 DW_MCI_TYPE_EXYNOS5420, 32 DW_MCI_TYPE_EXYNOS5420_SMU, 33 DW_MCI_TYPE_EXYNOS7, 34 DW_MCI_TYPE_EXYNOS7_SMU, 35 }; 36 37 /* Exynos implementation specific driver private data */ 38 struct dw_mci_exynos_priv_data { 39 enum dw_mci_exynos_type ctrl_type; 40 u8 ciu_div; 41 u32 sdr_timing; 42 u32 ddr_timing; 43 u32 hs400_timing; 44 u32 tuned_sample; 45 u32 cur_speed; 46 u32 dqs_delay; 47 u32 saved_dqs_en; 48 u32 saved_strobe_ctrl; 49 }; 50 51 static struct dw_mci_exynos_compatible { 52 char *compatible; 53 enum dw_mci_exynos_type ctrl_type; 54 } exynos_compat[] = { 55 { 56 .compatible = "samsung,exynos4210-dw-mshc", 57 .ctrl_type = DW_MCI_TYPE_EXYNOS4210, 58 }, { 59 .compatible = "samsung,exynos4412-dw-mshc", 60 .ctrl_type = DW_MCI_TYPE_EXYNOS4412, 61 }, { 62 .compatible = "samsung,exynos5250-dw-mshc", 63 .ctrl_type = DW_MCI_TYPE_EXYNOS5250, 64 }, { 65 .compatible = "samsung,exynos5420-dw-mshc", 66 .ctrl_type = DW_MCI_TYPE_EXYNOS5420, 67 }, { 68 .compatible = "samsung,exynos5420-dw-mshc-smu", 69 .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU, 70 }, { 71 .compatible = "samsung,exynos7-dw-mshc", 72 .ctrl_type = DW_MCI_TYPE_EXYNOS7, 73 }, { 74 .compatible = "samsung,exynos7-dw-mshc-smu", 75 .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, 76 }, 77 }; 78 79 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) 80 { 81 struct dw_mci_exynos_priv_data *priv = host->priv; 82 83 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 84 return EXYNOS4412_FIXED_CIU_CLK_DIV; 85 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 86 return EXYNOS4210_FIXED_CIU_CLK_DIV; 87 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 88 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 89 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; 90 else 91 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; 92 } 93 94 static void dw_mci_exynos_config_smu(struct dw_mci *host) 95 { 96 struct dw_mci_exynos_priv_data *priv = host->priv; 97 98 /* 99 * If Exynos is provided the Security management, 100 * set for non-ecryption mode at this time. 101 */ 102 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || 103 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { 104 mci_writel(host, MPSBEGIN0, 0); 105 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); 106 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | 107 SDMMC_MPSCTRL_NON_SECURE_READ_BIT | 108 SDMMC_MPSCTRL_VALID | 109 SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); 110 } 111 } 112 113 static int dw_mci_exynos_priv_init(struct dw_mci *host) 114 { 115 struct dw_mci_exynos_priv_data *priv = host->priv; 116 117 dw_mci_exynos_config_smu(host); 118 119 if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) { 120 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL); 121 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN); 122 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR; 123 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en); 124 if (!priv->dqs_delay) 125 priv->dqs_delay = 126 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); 127 } 128 129 host->bus_hz /= (priv->ciu_div + 1); 130 131 return 0; 132 } 133 134 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) 135 { 136 struct dw_mci_exynos_priv_data *priv = host->priv; 137 u32 clksel; 138 139 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 140 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 141 clksel = mci_readl(host, CLKSEL64); 142 else 143 clksel = mci_readl(host, CLKSEL); 144 145 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; 146 147 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 148 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 149 mci_writel(host, CLKSEL64, clksel); 150 else 151 mci_writel(host, CLKSEL, clksel); 152 153 /* 154 * Exynos4412 and Exynos5250 extends the use of CMD register with the 155 * use of bit 29 (which is reserved on standard MSHC controllers) for 156 * optionally bypassing the HOLD register for command and data. The 157 * HOLD register should be bypassed in case there is no phase shift 158 * applied on CMD/DATA that is sent to the card. 159 */ 160 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) 161 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags); 162 } 163 164 #ifdef CONFIG_PM 165 static int dw_mci_exynos_runtime_resume(struct device *dev) 166 { 167 struct dw_mci *host = dev_get_drvdata(dev); 168 int ret; 169 170 ret = dw_mci_runtime_resume(dev); 171 if (ret) 172 return ret; 173 174 dw_mci_exynos_config_smu(host); 175 176 return ret; 177 } 178 #endif /* CONFIG_PM */ 179 180 #ifdef CONFIG_PM_SLEEP 181 /** 182 * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code 183 * 184 * This ensures that device will be in runtime active state in 185 * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume() 186 */ 187 static int dw_mci_exynos_suspend_noirq(struct device *dev) 188 { 189 pm_runtime_get_noresume(dev); 190 return pm_runtime_force_suspend(dev); 191 } 192 193 /** 194 * dw_mci_exynos_resume_noirq - Exynos-specific resume code 195 * 196 * On exynos5420 there is a silicon errata that will sometimes leave the 197 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate 198 * that it fired and we can clear it by writing a 1 back. Clear it to prevent 199 * interrupts from going off constantly. 200 * 201 * We run this code on all exynos variants because it doesn't hurt. 202 */ 203 static int dw_mci_exynos_resume_noirq(struct device *dev) 204 { 205 struct dw_mci *host = dev_get_drvdata(dev); 206 struct dw_mci_exynos_priv_data *priv = host->priv; 207 u32 clksel; 208 int ret; 209 210 ret = pm_runtime_force_resume(dev); 211 if (ret) 212 return ret; 213 214 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 215 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 216 clksel = mci_readl(host, CLKSEL64); 217 else 218 clksel = mci_readl(host, CLKSEL); 219 220 if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { 221 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 222 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 223 mci_writel(host, CLKSEL64, clksel); 224 else 225 mci_writel(host, CLKSEL, clksel); 226 } 227 228 pm_runtime_put(dev); 229 230 return 0; 231 } 232 #endif /* CONFIG_PM_SLEEP */ 233 234 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) 235 { 236 struct dw_mci_exynos_priv_data *priv = host->priv; 237 u32 dqs, strobe; 238 239 /* 240 * Not supported to configure register 241 * related to HS400 242 */ 243 if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) { 244 if (timing == MMC_TIMING_MMC_HS400) 245 dev_warn(host->dev, 246 "cannot configure HS400, unsupported chipset\n"); 247 return; 248 } 249 250 dqs = priv->saved_dqs_en; 251 strobe = priv->saved_strobe_ctrl; 252 253 if (timing == MMC_TIMING_MMC_HS400) { 254 dqs |= DATA_STROBE_EN; 255 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay); 256 } else if (timing == MMC_TIMING_UHS_SDR104) { 257 dqs &= 0xffffff00; 258 } else { 259 dqs &= ~DATA_STROBE_EN; 260 } 261 262 mci_writel(host, HS400_DQS_EN, dqs); 263 mci_writel(host, HS400_DLINE_CTRL, strobe); 264 } 265 266 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted) 267 { 268 struct dw_mci_exynos_priv_data *priv = host->priv; 269 unsigned long actual; 270 u8 div; 271 int ret; 272 /* 273 * Don't care if wanted clock is zero or 274 * ciu clock is unavailable 275 */ 276 if (!wanted || IS_ERR(host->ciu_clk)) 277 return; 278 279 /* Guaranteed minimum frequency for cclkin */ 280 if (wanted < EXYNOS_CCLKIN_MIN) 281 wanted = EXYNOS_CCLKIN_MIN; 282 283 if (wanted == priv->cur_speed) 284 return; 285 286 div = dw_mci_exynos_get_ciu_div(host); 287 ret = clk_set_rate(host->ciu_clk, wanted * div); 288 if (ret) 289 dev_warn(host->dev, 290 "failed to set clk-rate %u error: %d\n", 291 wanted * div, ret); 292 actual = clk_get_rate(host->ciu_clk); 293 host->bus_hz = actual / div; 294 priv->cur_speed = wanted; 295 host->current_speed = 0; 296 } 297 298 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) 299 { 300 struct dw_mci_exynos_priv_data *priv = host->priv; 301 unsigned int wanted = ios->clock; 302 u32 timing = ios->timing, clksel; 303 304 switch (timing) { 305 case MMC_TIMING_MMC_HS400: 306 /* Update tuned sample timing */ 307 clksel = SDMMC_CLKSEL_UP_SAMPLE( 308 priv->hs400_timing, priv->tuned_sample); 309 wanted <<= 1; 310 break; 311 case MMC_TIMING_MMC_DDR52: 312 clksel = priv->ddr_timing; 313 /* Should be double rate for DDR mode */ 314 if (ios->bus_width == MMC_BUS_WIDTH_8) 315 wanted <<= 1; 316 break; 317 case MMC_TIMING_UHS_SDR104: 318 case MMC_TIMING_UHS_SDR50: 319 clksel = (priv->sdr_timing & 0xfff8ffff) | 320 (priv->ciu_div << 16); 321 break; 322 case MMC_TIMING_UHS_DDR50: 323 clksel = (priv->ddr_timing & 0xfff8ffff) | 324 (priv->ciu_div << 16); 325 break; 326 default: 327 clksel = priv->sdr_timing; 328 } 329 330 /* Set clock timing for the requested speed mode*/ 331 dw_mci_exynos_set_clksel_timing(host, clksel); 332 333 /* Configure setting for HS400 */ 334 dw_mci_exynos_config_hs400(host, timing); 335 336 /* Configure clock rate */ 337 dw_mci_exynos_adjust_clock(host, wanted); 338 } 339 340 static int dw_mci_exynos_parse_dt(struct dw_mci *host) 341 { 342 struct dw_mci_exynos_priv_data *priv; 343 struct device_node *np = host->dev->of_node; 344 u32 timing[2]; 345 u32 div = 0; 346 int idx; 347 int ret; 348 349 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 350 if (!priv) 351 return -ENOMEM; 352 353 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) { 354 if (of_device_is_compatible(np, exynos_compat[idx].compatible)) 355 priv->ctrl_type = exynos_compat[idx].ctrl_type; 356 } 357 358 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 359 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; 360 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 361 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; 362 else { 363 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); 364 priv->ciu_div = div; 365 } 366 367 ret = of_property_read_u32_array(np, 368 "samsung,dw-mshc-sdr-timing", timing, 2); 369 if (ret) 370 return ret; 371 372 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 373 374 ret = of_property_read_u32_array(np, 375 "samsung,dw-mshc-ddr-timing", timing, 2); 376 if (ret) 377 return ret; 378 379 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 380 381 ret = of_property_read_u32_array(np, 382 "samsung,dw-mshc-hs400-timing", timing, 2); 383 if (!ret && of_property_read_u32(np, 384 "samsung,read-strobe-delay", &priv->dqs_delay)) 385 dev_dbg(host->dev, 386 "read-strobe-delay is not found, assuming usage of default value\n"); 387 388 priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], 389 HS400_FIXED_CIU_CLK_DIV); 390 host->priv = priv; 391 return 0; 392 } 393 394 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) 395 { 396 struct dw_mci_exynos_priv_data *priv = host->priv; 397 398 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 399 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 400 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); 401 else 402 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL)); 403 } 404 405 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) 406 { 407 u32 clksel; 408 struct dw_mci_exynos_priv_data *priv = host->priv; 409 410 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 411 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 412 clksel = mci_readl(host, CLKSEL64); 413 else 414 clksel = mci_readl(host, CLKSEL); 415 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); 416 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 417 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 418 mci_writel(host, CLKSEL64, clksel); 419 else 420 mci_writel(host, CLKSEL, clksel); 421 } 422 423 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) 424 { 425 struct dw_mci_exynos_priv_data *priv = host->priv; 426 u32 clksel; 427 u8 sample; 428 429 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 430 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 431 clksel = mci_readl(host, CLKSEL64); 432 else 433 clksel = mci_readl(host, CLKSEL); 434 435 sample = (clksel + 1) & 0x7; 436 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); 437 438 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 439 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 440 mci_writel(host, CLKSEL64, clksel); 441 else 442 mci_writel(host, CLKSEL, clksel); 443 444 return sample; 445 } 446 447 static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates) 448 { 449 const u8 iter = 8; 450 u8 __c; 451 s8 i, loc = -1; 452 453 for (i = 0; i < iter; i++) { 454 __c = ror8(candiates, i); 455 if ((__c & 0xc7) == 0xc7) { 456 loc = i; 457 goto out; 458 } 459 } 460 461 for (i = 0; i < iter; i++) { 462 __c = ror8(candiates, i); 463 if ((__c & 0x83) == 0x83) { 464 loc = i; 465 goto out; 466 } 467 } 468 469 out: 470 return loc; 471 } 472 473 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 474 { 475 struct dw_mci *host = slot->host; 476 struct dw_mci_exynos_priv_data *priv = host->priv; 477 struct mmc_host *mmc = slot->mmc; 478 u8 start_smpl, smpl, candiates = 0; 479 s8 found = -1; 480 int ret = 0; 481 482 start_smpl = dw_mci_exynos_get_clksmpl(host); 483 484 do { 485 mci_writel(host, TMOUT, ~0); 486 smpl = dw_mci_exynos_move_next_clksmpl(host); 487 488 if (!mmc_send_tuning(mmc, opcode, NULL)) 489 candiates |= (1 << smpl); 490 491 } while (start_smpl != smpl); 492 493 found = dw_mci_exynos_get_best_clksmpl(candiates); 494 if (found >= 0) { 495 dw_mci_exynos_set_clksmpl(host, found); 496 priv->tuned_sample = found; 497 } else { 498 ret = -EIO; 499 } 500 501 return ret; 502 } 503 504 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host, 505 struct mmc_ios *ios) 506 { 507 struct dw_mci_exynos_priv_data *priv = host->priv; 508 509 dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing); 510 dw_mci_exynos_adjust_clock(host, (ios->clock) << 1); 511 512 return 0; 513 } 514 515 /* Common capabilities of Exynos4/Exynos5 SoC */ 516 static unsigned long exynos_dwmmc_caps[4] = { 517 MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, 518 MMC_CAP_CMD23, 519 MMC_CAP_CMD23, 520 MMC_CAP_CMD23, 521 }; 522 523 static const struct dw_mci_drv_data exynos_drv_data = { 524 .caps = exynos_dwmmc_caps, 525 .num_caps = ARRAY_SIZE(exynos_dwmmc_caps), 526 .init = dw_mci_exynos_priv_init, 527 .set_ios = dw_mci_exynos_set_ios, 528 .parse_dt = dw_mci_exynos_parse_dt, 529 .execute_tuning = dw_mci_exynos_execute_tuning, 530 .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning, 531 }; 532 533 static const struct of_device_id dw_mci_exynos_match[] = { 534 { .compatible = "samsung,exynos4412-dw-mshc", 535 .data = &exynos_drv_data, }, 536 { .compatible = "samsung,exynos5250-dw-mshc", 537 .data = &exynos_drv_data, }, 538 { .compatible = "samsung,exynos5420-dw-mshc", 539 .data = &exynos_drv_data, }, 540 { .compatible = "samsung,exynos5420-dw-mshc-smu", 541 .data = &exynos_drv_data, }, 542 { .compatible = "samsung,exynos7-dw-mshc", 543 .data = &exynos_drv_data, }, 544 { .compatible = "samsung,exynos7-dw-mshc-smu", 545 .data = &exynos_drv_data, }, 546 {}, 547 }; 548 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match); 549 550 static int dw_mci_exynos_probe(struct platform_device *pdev) 551 { 552 const struct dw_mci_drv_data *drv_data; 553 const struct of_device_id *match; 554 int ret; 555 556 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node); 557 drv_data = match->data; 558 559 pm_runtime_get_noresume(&pdev->dev); 560 pm_runtime_set_active(&pdev->dev); 561 pm_runtime_enable(&pdev->dev); 562 563 ret = dw_mci_pltfm_register(pdev, drv_data); 564 if (ret) { 565 pm_runtime_disable(&pdev->dev); 566 pm_runtime_set_suspended(&pdev->dev); 567 pm_runtime_put_noidle(&pdev->dev); 568 569 return ret; 570 } 571 572 return 0; 573 } 574 575 static int dw_mci_exynos_remove(struct platform_device *pdev) 576 { 577 pm_runtime_disable(&pdev->dev); 578 pm_runtime_set_suspended(&pdev->dev); 579 pm_runtime_put_noidle(&pdev->dev); 580 581 return dw_mci_pltfm_remove(pdev); 582 } 583 584 static const struct dev_pm_ops dw_mci_exynos_pmops = { 585 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend_noirq, 586 dw_mci_exynos_resume_noirq) 587 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend, 588 dw_mci_exynos_runtime_resume, 589 NULL) 590 }; 591 592 static struct platform_driver dw_mci_exynos_pltfm_driver = { 593 .probe = dw_mci_exynos_probe, 594 .remove = dw_mci_exynos_remove, 595 .driver = { 596 .name = "dwmmc_exynos", 597 .of_match_table = dw_mci_exynos_match, 598 .pm = &dw_mci_exynos_pmops, 599 }, 600 }; 601 602 module_platform_driver(dw_mci_exynos_pltfm_driver); 603 604 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension"); 605 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com"); 606 MODULE_LICENSE("GPL v2"); 607 MODULE_ALIAS("platform:dwmmc_exynos"); 608