1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 4 * 5 * Copyright (C) 2012, Samsung Electronics Co., Ltd. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/clk.h> 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/mmc.h> 13 #include <linux/of.h> 14 #include <linux/of_gpio.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/slab.h> 17 18 #include "dw_mmc.h" 19 #include "dw_mmc-pltfm.h" 20 #include "dw_mmc-exynos.h" 21 22 /* Variations in Exynos specific dw-mshc controller */ 23 enum dw_mci_exynos_type { 24 DW_MCI_TYPE_EXYNOS4210, 25 DW_MCI_TYPE_EXYNOS4412, 26 DW_MCI_TYPE_EXYNOS5250, 27 DW_MCI_TYPE_EXYNOS5420, 28 DW_MCI_TYPE_EXYNOS5420_SMU, 29 DW_MCI_TYPE_EXYNOS7, 30 DW_MCI_TYPE_EXYNOS7_SMU, 31 DW_MCI_TYPE_ARTPEC8, 32 }; 33 34 /* Exynos implementation specific driver private data */ 35 struct dw_mci_exynos_priv_data { 36 enum dw_mci_exynos_type ctrl_type; 37 u8 ciu_div; 38 u32 sdr_timing; 39 u32 ddr_timing; 40 u32 hs400_timing; 41 u32 tuned_sample; 42 u32 cur_speed; 43 u32 dqs_delay; 44 u32 saved_dqs_en; 45 u32 saved_strobe_ctrl; 46 }; 47 48 static struct dw_mci_exynos_compatible { 49 char *compatible; 50 enum dw_mci_exynos_type ctrl_type; 51 } exynos_compat[] = { 52 { 53 .compatible = "samsung,exynos4210-dw-mshc", 54 .ctrl_type = DW_MCI_TYPE_EXYNOS4210, 55 }, { 56 .compatible = "samsung,exynos4412-dw-mshc", 57 .ctrl_type = DW_MCI_TYPE_EXYNOS4412, 58 }, { 59 .compatible = "samsung,exynos5250-dw-mshc", 60 .ctrl_type = DW_MCI_TYPE_EXYNOS5250, 61 }, { 62 .compatible = "samsung,exynos5420-dw-mshc", 63 .ctrl_type = DW_MCI_TYPE_EXYNOS5420, 64 }, { 65 .compatible = "samsung,exynos5420-dw-mshc-smu", 66 .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU, 67 }, { 68 .compatible = "samsung,exynos7-dw-mshc", 69 .ctrl_type = DW_MCI_TYPE_EXYNOS7, 70 }, { 71 .compatible = "samsung,exynos7-dw-mshc-smu", 72 .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, 73 }, { 74 .compatible = "axis,artpec8-dw-mshc", 75 .ctrl_type = DW_MCI_TYPE_ARTPEC8, 76 }, 77 }; 78 79 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) 80 { 81 struct dw_mci_exynos_priv_data *priv = host->priv; 82 83 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 84 return EXYNOS4412_FIXED_CIU_CLK_DIV; 85 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 86 return EXYNOS4210_FIXED_CIU_CLK_DIV; 87 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 88 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 89 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 90 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; 91 else 92 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; 93 } 94 95 static void dw_mci_exynos_config_smu(struct dw_mci *host) 96 { 97 struct dw_mci_exynos_priv_data *priv = host->priv; 98 99 /* 100 * If Exynos is provided the Security management, 101 * set for non-ecryption mode at this time. 102 */ 103 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || 104 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { 105 mci_writel(host, MPSBEGIN0, 0); 106 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); 107 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | 108 SDMMC_MPSCTRL_NON_SECURE_READ_BIT | 109 SDMMC_MPSCTRL_VALID | 110 SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); 111 } 112 } 113 114 static int dw_mci_exynos_priv_init(struct dw_mci *host) 115 { 116 struct dw_mci_exynos_priv_data *priv = host->priv; 117 118 dw_mci_exynos_config_smu(host); 119 120 if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) { 121 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL); 122 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN); 123 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR; 124 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en); 125 if (!priv->dqs_delay) 126 priv->dqs_delay = 127 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); 128 } 129 130 host->bus_hz /= (priv->ciu_div + 1); 131 132 return 0; 133 } 134 135 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) 136 { 137 struct dw_mci_exynos_priv_data *priv = host->priv; 138 u32 clksel; 139 140 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 141 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 142 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 143 clksel = mci_readl(host, CLKSEL64); 144 else 145 clksel = mci_readl(host, CLKSEL); 146 147 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; 148 149 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 150 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 151 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 152 mci_writel(host, CLKSEL64, clksel); 153 else 154 mci_writel(host, CLKSEL, clksel); 155 156 /* 157 * Exynos4412 and Exynos5250 extends the use of CMD register with the 158 * use of bit 29 (which is reserved on standard MSHC controllers) for 159 * optionally bypassing the HOLD register for command and data. The 160 * HOLD register should be bypassed in case there is no phase shift 161 * applied on CMD/DATA that is sent to the card. 162 */ 163 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) 164 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags); 165 } 166 167 #ifdef CONFIG_PM 168 static int dw_mci_exynos_runtime_resume(struct device *dev) 169 { 170 struct dw_mci *host = dev_get_drvdata(dev); 171 int ret; 172 173 ret = dw_mci_runtime_resume(dev); 174 if (ret) 175 return ret; 176 177 dw_mci_exynos_config_smu(host); 178 179 return ret; 180 } 181 #endif /* CONFIG_PM */ 182 183 #ifdef CONFIG_PM_SLEEP 184 /** 185 * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code 186 * @dev: Device to suspend (this device) 187 * 188 * This ensures that device will be in runtime active state in 189 * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume() 190 */ 191 static int dw_mci_exynos_suspend_noirq(struct device *dev) 192 { 193 pm_runtime_get_noresume(dev); 194 return pm_runtime_force_suspend(dev); 195 } 196 197 /** 198 * dw_mci_exynos_resume_noirq - Exynos-specific resume code 199 * @dev: Device to resume (this device) 200 * 201 * On exynos5420 there is a silicon errata that will sometimes leave the 202 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate 203 * that it fired and we can clear it by writing a 1 back. Clear it to prevent 204 * interrupts from going off constantly. 205 * 206 * We run this code on all exynos variants because it doesn't hurt. 207 */ 208 static int dw_mci_exynos_resume_noirq(struct device *dev) 209 { 210 struct dw_mci *host = dev_get_drvdata(dev); 211 struct dw_mci_exynos_priv_data *priv = host->priv; 212 u32 clksel; 213 int ret; 214 215 ret = pm_runtime_force_resume(dev); 216 if (ret) 217 return ret; 218 219 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 220 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 221 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 222 clksel = mci_readl(host, CLKSEL64); 223 else 224 clksel = mci_readl(host, CLKSEL); 225 226 if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { 227 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 228 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 229 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 230 mci_writel(host, CLKSEL64, clksel); 231 else 232 mci_writel(host, CLKSEL, clksel); 233 } 234 235 pm_runtime_put(dev); 236 237 return 0; 238 } 239 #endif /* CONFIG_PM_SLEEP */ 240 241 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) 242 { 243 struct dw_mci_exynos_priv_data *priv = host->priv; 244 u32 dqs, strobe; 245 246 /* 247 * Not supported to configure register 248 * related to HS400 249 */ 250 if ((priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) || 251 (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)) { 252 if (timing == MMC_TIMING_MMC_HS400) 253 dev_warn(host->dev, 254 "cannot configure HS400, unsupported chipset\n"); 255 return; 256 } 257 258 dqs = priv->saved_dqs_en; 259 strobe = priv->saved_strobe_ctrl; 260 261 if (timing == MMC_TIMING_MMC_HS400) { 262 dqs |= DATA_STROBE_EN; 263 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay); 264 } else if (timing == MMC_TIMING_UHS_SDR104) { 265 dqs &= 0xffffff00; 266 } else { 267 dqs &= ~DATA_STROBE_EN; 268 } 269 270 mci_writel(host, HS400_DQS_EN, dqs); 271 mci_writel(host, HS400_DLINE_CTRL, strobe); 272 } 273 274 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted) 275 { 276 struct dw_mci_exynos_priv_data *priv = host->priv; 277 unsigned long actual; 278 u8 div; 279 int ret; 280 /* 281 * Don't care if wanted clock is zero or 282 * ciu clock is unavailable 283 */ 284 if (!wanted || IS_ERR(host->ciu_clk)) 285 return; 286 287 /* Guaranteed minimum frequency for cclkin */ 288 if (wanted < EXYNOS_CCLKIN_MIN) 289 wanted = EXYNOS_CCLKIN_MIN; 290 291 if (wanted == priv->cur_speed) 292 return; 293 294 div = dw_mci_exynos_get_ciu_div(host); 295 ret = clk_set_rate(host->ciu_clk, wanted * div); 296 if (ret) 297 dev_warn(host->dev, 298 "failed to set clk-rate %u error: %d\n", 299 wanted * div, ret); 300 actual = clk_get_rate(host->ciu_clk); 301 host->bus_hz = actual / div; 302 priv->cur_speed = wanted; 303 host->current_speed = 0; 304 } 305 306 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) 307 { 308 struct dw_mci_exynos_priv_data *priv = host->priv; 309 unsigned int wanted = ios->clock; 310 u32 timing = ios->timing, clksel; 311 312 switch (timing) { 313 case MMC_TIMING_MMC_HS400: 314 /* Update tuned sample timing */ 315 clksel = SDMMC_CLKSEL_UP_SAMPLE( 316 priv->hs400_timing, priv->tuned_sample); 317 wanted <<= 1; 318 break; 319 case MMC_TIMING_MMC_DDR52: 320 clksel = priv->ddr_timing; 321 /* Should be double rate for DDR mode */ 322 if (ios->bus_width == MMC_BUS_WIDTH_8) 323 wanted <<= 1; 324 break; 325 case MMC_TIMING_UHS_SDR104: 326 case MMC_TIMING_UHS_SDR50: 327 clksel = (priv->sdr_timing & 0xfff8ffff) | 328 (priv->ciu_div << 16); 329 break; 330 case MMC_TIMING_UHS_DDR50: 331 clksel = (priv->ddr_timing & 0xfff8ffff) | 332 (priv->ciu_div << 16); 333 break; 334 default: 335 clksel = priv->sdr_timing; 336 } 337 338 /* Set clock timing for the requested speed mode*/ 339 dw_mci_exynos_set_clksel_timing(host, clksel); 340 341 /* Configure setting for HS400 */ 342 dw_mci_exynos_config_hs400(host, timing); 343 344 /* Configure clock rate */ 345 dw_mci_exynos_adjust_clock(host, wanted); 346 } 347 348 static int dw_mci_exynos_parse_dt(struct dw_mci *host) 349 { 350 struct dw_mci_exynos_priv_data *priv; 351 struct device_node *np = host->dev->of_node; 352 u32 timing[2]; 353 u32 div = 0; 354 int idx; 355 int ret; 356 357 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 358 if (!priv) 359 return -ENOMEM; 360 361 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) { 362 if (of_device_is_compatible(np, exynos_compat[idx].compatible)) 363 priv->ctrl_type = exynos_compat[idx].ctrl_type; 364 } 365 366 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 367 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; 368 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 369 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; 370 else { 371 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); 372 priv->ciu_div = div; 373 } 374 375 ret = of_property_read_u32_array(np, 376 "samsung,dw-mshc-sdr-timing", timing, 2); 377 if (ret) 378 return ret; 379 380 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 381 382 ret = of_property_read_u32_array(np, 383 "samsung,dw-mshc-ddr-timing", timing, 2); 384 if (ret) 385 return ret; 386 387 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 388 389 ret = of_property_read_u32_array(np, 390 "samsung,dw-mshc-hs400-timing", timing, 2); 391 if (!ret && of_property_read_u32(np, 392 "samsung,read-strobe-delay", &priv->dqs_delay)) 393 dev_dbg(host->dev, 394 "read-strobe-delay is not found, assuming usage of default value\n"); 395 396 priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], 397 HS400_FIXED_CIU_CLK_DIV); 398 host->priv = priv; 399 return 0; 400 } 401 402 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) 403 { 404 struct dw_mci_exynos_priv_data *priv = host->priv; 405 406 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 407 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 408 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 409 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); 410 else 411 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL)); 412 } 413 414 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) 415 { 416 u32 clksel; 417 struct dw_mci_exynos_priv_data *priv = host->priv; 418 419 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 420 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 421 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 422 clksel = mci_readl(host, CLKSEL64); 423 else 424 clksel = mci_readl(host, CLKSEL); 425 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); 426 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 427 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 428 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 429 mci_writel(host, CLKSEL64, clksel); 430 else 431 mci_writel(host, CLKSEL, clksel); 432 } 433 434 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) 435 { 436 struct dw_mci_exynos_priv_data *priv = host->priv; 437 u32 clksel; 438 u8 sample; 439 440 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 441 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 442 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 443 clksel = mci_readl(host, CLKSEL64); 444 else 445 clksel = mci_readl(host, CLKSEL); 446 447 sample = (clksel + 1) & 0x7; 448 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); 449 450 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 451 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || 452 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) 453 mci_writel(host, CLKSEL64, clksel); 454 else 455 mci_writel(host, CLKSEL, clksel); 456 457 return sample; 458 } 459 460 static s8 dw_mci_exynos_get_best_clksmpl(u8 candidates) 461 { 462 const u8 iter = 8; 463 u8 __c; 464 s8 i, loc = -1; 465 466 for (i = 0; i < iter; i++) { 467 __c = ror8(candidates, i); 468 if ((__c & 0xc7) == 0xc7) { 469 loc = i; 470 goto out; 471 } 472 } 473 474 for (i = 0; i < iter; i++) { 475 __c = ror8(candidates, i); 476 if ((__c & 0x83) == 0x83) { 477 loc = i; 478 goto out; 479 } 480 } 481 482 /* 483 * If there is no cadiates value, then it needs to return -EIO. 484 * If there are candidates values and don't find bset clk sample value, 485 * then use a first candidates clock sample value. 486 */ 487 for (i = 0; i < iter; i++) { 488 __c = ror8(candidates, i); 489 if ((__c & 0x1) == 0x1) { 490 loc = i; 491 goto out; 492 } 493 } 494 out: 495 return loc; 496 } 497 498 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 499 { 500 struct dw_mci *host = slot->host; 501 struct dw_mci_exynos_priv_data *priv = host->priv; 502 struct mmc_host *mmc = slot->mmc; 503 u8 start_smpl, smpl, candidates = 0; 504 s8 found; 505 int ret = 0; 506 507 start_smpl = dw_mci_exynos_get_clksmpl(host); 508 509 do { 510 mci_writel(host, TMOUT, ~0); 511 smpl = dw_mci_exynos_move_next_clksmpl(host); 512 513 if (!mmc_send_tuning(mmc, opcode, NULL)) 514 candidates |= (1 << smpl); 515 516 } while (start_smpl != smpl); 517 518 found = dw_mci_exynos_get_best_clksmpl(candidates); 519 if (found >= 0) { 520 dw_mci_exynos_set_clksmpl(host, found); 521 priv->tuned_sample = found; 522 } else { 523 ret = -EIO; 524 dev_warn(&mmc->class_dev, 525 "There is no candidates value about clksmpl!\n"); 526 } 527 528 return ret; 529 } 530 531 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host, 532 struct mmc_ios *ios) 533 { 534 struct dw_mci_exynos_priv_data *priv = host->priv; 535 536 dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing); 537 dw_mci_exynos_adjust_clock(host, (ios->clock) << 1); 538 539 return 0; 540 } 541 542 /* Common capabilities of Exynos4/Exynos5 SoC */ 543 static unsigned long exynos_dwmmc_caps[4] = { 544 MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA, 545 0, 546 0, 547 0, 548 }; 549 550 static const struct dw_mci_drv_data exynos_drv_data = { 551 .caps = exynos_dwmmc_caps, 552 .num_caps = ARRAY_SIZE(exynos_dwmmc_caps), 553 .common_caps = MMC_CAP_CMD23, 554 .init = dw_mci_exynos_priv_init, 555 .set_ios = dw_mci_exynos_set_ios, 556 .parse_dt = dw_mci_exynos_parse_dt, 557 .execute_tuning = dw_mci_exynos_execute_tuning, 558 .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning, 559 }; 560 561 static const struct dw_mci_drv_data artpec_drv_data = { 562 .common_caps = MMC_CAP_CMD23, 563 .init = dw_mci_exynos_priv_init, 564 .set_ios = dw_mci_exynos_set_ios, 565 .parse_dt = dw_mci_exynos_parse_dt, 566 .execute_tuning = dw_mci_exynos_execute_tuning, 567 }; 568 569 static const struct of_device_id dw_mci_exynos_match[] = { 570 { .compatible = "samsung,exynos4412-dw-mshc", 571 .data = &exynos_drv_data, }, 572 { .compatible = "samsung,exynos5250-dw-mshc", 573 .data = &exynos_drv_data, }, 574 { .compatible = "samsung,exynos5420-dw-mshc", 575 .data = &exynos_drv_data, }, 576 { .compatible = "samsung,exynos5420-dw-mshc-smu", 577 .data = &exynos_drv_data, }, 578 { .compatible = "samsung,exynos7-dw-mshc", 579 .data = &exynos_drv_data, }, 580 { .compatible = "samsung,exynos7-dw-mshc-smu", 581 .data = &exynos_drv_data, }, 582 { .compatible = "axis,artpec8-dw-mshc", 583 .data = &artpec_drv_data, }, 584 {}, 585 }; 586 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match); 587 588 static int dw_mci_exynos_probe(struct platform_device *pdev) 589 { 590 const struct dw_mci_drv_data *drv_data; 591 const struct of_device_id *match; 592 int ret; 593 594 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node); 595 drv_data = match->data; 596 597 pm_runtime_get_noresume(&pdev->dev); 598 pm_runtime_set_active(&pdev->dev); 599 pm_runtime_enable(&pdev->dev); 600 601 ret = dw_mci_pltfm_register(pdev, drv_data); 602 if (ret) { 603 pm_runtime_disable(&pdev->dev); 604 pm_runtime_set_suspended(&pdev->dev); 605 pm_runtime_put_noidle(&pdev->dev); 606 607 return ret; 608 } 609 610 return 0; 611 } 612 613 static int dw_mci_exynos_remove(struct platform_device *pdev) 614 { 615 pm_runtime_disable(&pdev->dev); 616 pm_runtime_set_suspended(&pdev->dev); 617 pm_runtime_put_noidle(&pdev->dev); 618 619 return dw_mci_pltfm_remove(pdev); 620 } 621 622 static const struct dev_pm_ops dw_mci_exynos_pmops = { 623 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend_noirq, 624 dw_mci_exynos_resume_noirq) 625 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend, 626 dw_mci_exynos_runtime_resume, 627 NULL) 628 }; 629 630 static struct platform_driver dw_mci_exynos_pltfm_driver = { 631 .probe = dw_mci_exynos_probe, 632 .remove = dw_mci_exynos_remove, 633 .driver = { 634 .name = "dwmmc_exynos", 635 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 636 .of_match_table = dw_mci_exynos_match, 637 .pm = &dw_mci_exynos_pmops, 638 }, 639 }; 640 641 module_platform_driver(dw_mci_exynos_pltfm_driver); 642 643 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension"); 644 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com"); 645 MODULE_LICENSE("GPL v2"); 646 MODULE_ALIAS("platform:dwmmc_exynos"); 647