1 /* 2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 3 * 4 * Copyright (C) 2012, Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mmc/dw_mmc.h> 17 #include <linux/mmc/mmc.h> 18 #include <linux/of.h> 19 #include <linux/of_gpio.h> 20 #include <linux/slab.h> 21 22 #include "dw_mmc.h" 23 #include "dw_mmc-pltfm.h" 24 #include "dw_mmc-exynos.h" 25 26 /* Variations in Exynos specific dw-mshc controller */ 27 enum dw_mci_exynos_type { 28 DW_MCI_TYPE_EXYNOS4210, 29 DW_MCI_TYPE_EXYNOS4412, 30 DW_MCI_TYPE_EXYNOS5250, 31 DW_MCI_TYPE_EXYNOS5420, 32 DW_MCI_TYPE_EXYNOS5420_SMU, 33 DW_MCI_TYPE_EXYNOS7, 34 DW_MCI_TYPE_EXYNOS7_SMU, 35 }; 36 37 /* Exynos implementation specific driver private data */ 38 struct dw_mci_exynos_priv_data { 39 enum dw_mci_exynos_type ctrl_type; 40 u8 ciu_div; 41 u32 sdr_timing; 42 u32 ddr_timing; 43 u32 hs400_timing; 44 u32 tuned_sample; 45 u32 cur_speed; 46 u32 dqs_delay; 47 u32 saved_dqs_en; 48 u32 saved_strobe_ctrl; 49 }; 50 51 static struct dw_mci_exynos_compatible { 52 char *compatible; 53 enum dw_mci_exynos_type ctrl_type; 54 } exynos_compat[] = { 55 { 56 .compatible = "samsung,exynos4210-dw-mshc", 57 .ctrl_type = DW_MCI_TYPE_EXYNOS4210, 58 }, { 59 .compatible = "samsung,exynos4412-dw-mshc", 60 .ctrl_type = DW_MCI_TYPE_EXYNOS4412, 61 }, { 62 .compatible = "samsung,exynos5250-dw-mshc", 63 .ctrl_type = DW_MCI_TYPE_EXYNOS5250, 64 }, { 65 .compatible = "samsung,exynos5420-dw-mshc", 66 .ctrl_type = DW_MCI_TYPE_EXYNOS5420, 67 }, { 68 .compatible = "samsung,exynos5420-dw-mshc-smu", 69 .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU, 70 }, { 71 .compatible = "samsung,exynos7-dw-mshc", 72 .ctrl_type = DW_MCI_TYPE_EXYNOS7, 73 }, { 74 .compatible = "samsung,exynos7-dw-mshc-smu", 75 .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, 76 }, 77 }; 78 79 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) 80 { 81 struct dw_mci_exynos_priv_data *priv = host->priv; 82 83 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 84 return EXYNOS4412_FIXED_CIU_CLK_DIV; 85 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 86 return EXYNOS4210_FIXED_CIU_CLK_DIV; 87 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 88 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 89 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; 90 else 91 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; 92 } 93 94 static void dw_mci_exynos_config_smu(struct dw_mci *host) 95 { 96 struct dw_mci_exynos_priv_data *priv = host->priv; 97 98 /* 99 * If Exynos is provided the Security management, 100 * set for non-ecryption mode at this time. 101 */ 102 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || 103 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { 104 mci_writel(host, MPSBEGIN0, 0); 105 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); 106 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | 107 SDMMC_MPSCTRL_NON_SECURE_READ_BIT | 108 SDMMC_MPSCTRL_VALID | 109 SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); 110 } 111 } 112 113 static int dw_mci_exynos_priv_init(struct dw_mci *host) 114 { 115 struct dw_mci_exynos_priv_data *priv = host->priv; 116 117 dw_mci_exynos_config_smu(host); 118 119 if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) { 120 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL); 121 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN); 122 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR; 123 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en); 124 if (!priv->dqs_delay) 125 priv->dqs_delay = 126 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); 127 } 128 129 return 0; 130 } 131 132 static int dw_mci_exynos_setup_clock(struct dw_mci *host) 133 { 134 struct dw_mci_exynos_priv_data *priv = host->priv; 135 136 host->bus_hz /= (priv->ciu_div + 1); 137 138 return 0; 139 } 140 141 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) 142 { 143 struct dw_mci_exynos_priv_data *priv = host->priv; 144 u32 clksel; 145 146 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 147 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 148 clksel = mci_readl(host, CLKSEL64); 149 else 150 clksel = mci_readl(host, CLKSEL); 151 152 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; 153 154 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 155 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 156 mci_writel(host, CLKSEL64, clksel); 157 else 158 mci_writel(host, CLKSEL, clksel); 159 160 /* 161 * Exynos4412 and Exynos5250 extends the use of CMD register with the 162 * use of bit 29 (which is reserved on standard MSHC controllers) for 163 * optionally bypassing the HOLD register for command and data. The 164 * HOLD register should be bypassed in case there is no phase shift 165 * applied on CMD/DATA that is sent to the card. 166 */ 167 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel)) 168 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags); 169 } 170 171 #ifdef CONFIG_PM_SLEEP 172 static int dw_mci_exynos_suspend(struct device *dev) 173 { 174 struct dw_mci *host = dev_get_drvdata(dev); 175 176 return dw_mci_suspend(host); 177 } 178 179 static int dw_mci_exynos_resume(struct device *dev) 180 { 181 struct dw_mci *host = dev_get_drvdata(dev); 182 183 dw_mci_exynos_config_smu(host); 184 return dw_mci_resume(host); 185 } 186 187 /** 188 * dw_mci_exynos_resume_noirq - Exynos-specific resume code 189 * 190 * On exynos5420 there is a silicon errata that will sometimes leave the 191 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate 192 * that it fired and we can clear it by writing a 1 back. Clear it to prevent 193 * interrupts from going off constantly. 194 * 195 * We run this code on all exynos variants because it doesn't hurt. 196 */ 197 198 static int dw_mci_exynos_resume_noirq(struct device *dev) 199 { 200 struct dw_mci *host = dev_get_drvdata(dev); 201 struct dw_mci_exynos_priv_data *priv = host->priv; 202 u32 clksel; 203 204 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 205 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 206 clksel = mci_readl(host, CLKSEL64); 207 else 208 clksel = mci_readl(host, CLKSEL); 209 210 if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { 211 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 212 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 213 mci_writel(host, CLKSEL64, clksel); 214 else 215 mci_writel(host, CLKSEL, clksel); 216 } 217 218 return 0; 219 } 220 #else 221 #define dw_mci_exynos_suspend NULL 222 #define dw_mci_exynos_resume NULL 223 #define dw_mci_exynos_resume_noirq NULL 224 #endif /* CONFIG_PM_SLEEP */ 225 226 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) 227 { 228 struct dw_mci_exynos_priv_data *priv = host->priv; 229 u32 dqs, strobe; 230 231 /* 232 * Not supported to configure register 233 * related to HS400 234 */ 235 if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) 236 return; 237 238 dqs = priv->saved_dqs_en; 239 strobe = priv->saved_strobe_ctrl; 240 241 if (timing == MMC_TIMING_MMC_HS400) { 242 dqs |= DATA_STROBE_EN; 243 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay); 244 } else { 245 dqs &= ~DATA_STROBE_EN; 246 } 247 248 mci_writel(host, HS400_DQS_EN, dqs); 249 mci_writel(host, HS400_DLINE_CTRL, strobe); 250 } 251 252 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted) 253 { 254 struct dw_mci_exynos_priv_data *priv = host->priv; 255 unsigned long actual; 256 u8 div; 257 int ret; 258 /* 259 * Don't care if wanted clock is zero or 260 * ciu clock is unavailable 261 */ 262 if (!wanted || IS_ERR(host->ciu_clk)) 263 return; 264 265 /* Guaranteed minimum frequency for cclkin */ 266 if (wanted < EXYNOS_CCLKIN_MIN) 267 wanted = EXYNOS_CCLKIN_MIN; 268 269 if (wanted == priv->cur_speed) 270 return; 271 272 div = dw_mci_exynos_get_ciu_div(host); 273 ret = clk_set_rate(host->ciu_clk, wanted * div); 274 if (ret) 275 dev_warn(host->dev, 276 "failed to set clk-rate %u error: %d\n", 277 wanted * div, ret); 278 actual = clk_get_rate(host->ciu_clk); 279 host->bus_hz = actual / div; 280 priv->cur_speed = wanted; 281 host->current_speed = 0; 282 } 283 284 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) 285 { 286 struct dw_mci_exynos_priv_data *priv = host->priv; 287 unsigned int wanted = ios->clock; 288 u32 timing = ios->timing, clksel; 289 290 switch (timing) { 291 case MMC_TIMING_MMC_HS400: 292 /* Update tuned sample timing */ 293 clksel = SDMMC_CLKSEL_UP_SAMPLE( 294 priv->hs400_timing, priv->tuned_sample); 295 wanted <<= 1; 296 break; 297 case MMC_TIMING_MMC_DDR52: 298 clksel = priv->ddr_timing; 299 /* Should be double rate for DDR mode */ 300 if (ios->bus_width == MMC_BUS_WIDTH_8) 301 wanted <<= 1; 302 break; 303 default: 304 clksel = priv->sdr_timing; 305 } 306 307 /* Set clock timing for the requested speed mode*/ 308 dw_mci_exynos_set_clksel_timing(host, clksel); 309 310 /* Configure setting for HS400 */ 311 dw_mci_exynos_config_hs400(host, timing); 312 313 /* Configure clock rate */ 314 dw_mci_exynos_adjust_clock(host, wanted); 315 } 316 317 static int dw_mci_exynos_parse_dt(struct dw_mci *host) 318 { 319 struct dw_mci_exynos_priv_data *priv; 320 struct device_node *np = host->dev->of_node; 321 u32 timing[2]; 322 u32 div = 0; 323 int idx; 324 int ret; 325 326 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 327 if (!priv) 328 return -ENOMEM; 329 330 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) { 331 if (of_device_is_compatible(np, exynos_compat[idx].compatible)) 332 priv->ctrl_type = exynos_compat[idx].ctrl_type; 333 } 334 335 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 336 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; 337 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 338 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; 339 else { 340 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); 341 priv->ciu_div = div; 342 } 343 344 ret = of_property_read_u32_array(np, 345 "samsung,dw-mshc-sdr-timing", timing, 2); 346 if (ret) 347 return ret; 348 349 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 350 351 ret = of_property_read_u32_array(np, 352 "samsung,dw-mshc-ddr-timing", timing, 2); 353 if (ret) 354 return ret; 355 356 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 357 358 ret = of_property_read_u32_array(np, 359 "samsung,dw-mshc-hs400-timing", timing, 2); 360 if (!ret && of_property_read_u32(np, 361 "samsung,read-strobe-delay", &priv->dqs_delay)) 362 dev_dbg(host->dev, 363 "read-strobe-delay is not found, assuming usage of default value\n"); 364 365 priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], 366 HS400_FIXED_CIU_CLK_DIV); 367 host->priv = priv; 368 return 0; 369 } 370 371 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) 372 { 373 struct dw_mci_exynos_priv_data *priv = host->priv; 374 375 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 376 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 377 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); 378 else 379 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL)); 380 } 381 382 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) 383 { 384 u32 clksel; 385 struct dw_mci_exynos_priv_data *priv = host->priv; 386 387 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 388 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 389 clksel = mci_readl(host, CLKSEL64); 390 else 391 clksel = mci_readl(host, CLKSEL); 392 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); 393 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 394 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 395 mci_writel(host, CLKSEL64, clksel); 396 else 397 mci_writel(host, CLKSEL, clksel); 398 } 399 400 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) 401 { 402 struct dw_mci_exynos_priv_data *priv = host->priv; 403 u32 clksel; 404 u8 sample; 405 406 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 407 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 408 clksel = mci_readl(host, CLKSEL64); 409 else 410 clksel = mci_readl(host, CLKSEL); 411 412 sample = (clksel + 1) & 0x7; 413 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); 414 415 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 416 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 417 mci_writel(host, CLKSEL64, clksel); 418 else 419 mci_writel(host, CLKSEL, clksel); 420 421 return sample; 422 } 423 424 static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates) 425 { 426 const u8 iter = 8; 427 u8 __c; 428 s8 i, loc = -1; 429 430 for (i = 0; i < iter; i++) { 431 __c = ror8(candiates, i); 432 if ((__c & 0xc7) == 0xc7) { 433 loc = i; 434 goto out; 435 } 436 } 437 438 for (i = 0; i < iter; i++) { 439 __c = ror8(candiates, i); 440 if ((__c & 0x83) == 0x83) { 441 loc = i; 442 goto out; 443 } 444 } 445 446 out: 447 return loc; 448 } 449 450 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 451 { 452 struct dw_mci *host = slot->host; 453 struct dw_mci_exynos_priv_data *priv = host->priv; 454 struct mmc_host *mmc = slot->mmc; 455 u8 start_smpl, smpl, candiates = 0; 456 s8 found = -1; 457 int ret = 0; 458 459 start_smpl = dw_mci_exynos_get_clksmpl(host); 460 461 do { 462 mci_writel(host, TMOUT, ~0); 463 smpl = dw_mci_exynos_move_next_clksmpl(host); 464 465 if (!mmc_send_tuning(mmc, opcode, NULL)) 466 candiates |= (1 << smpl); 467 468 } while (start_smpl != smpl); 469 470 found = dw_mci_exynos_get_best_clksmpl(candiates); 471 if (found >= 0) { 472 dw_mci_exynos_set_clksmpl(host, found); 473 priv->tuned_sample = found; 474 } else { 475 ret = -EIO; 476 } 477 478 return ret; 479 } 480 481 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host, 482 struct mmc_ios *ios) 483 { 484 struct dw_mci_exynos_priv_data *priv = host->priv; 485 486 dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing); 487 dw_mci_exynos_adjust_clock(host, (ios->clock) << 1); 488 489 return 0; 490 } 491 492 /* Common capabilities of Exynos4/Exynos5 SoC */ 493 static unsigned long exynos_dwmmc_caps[4] = { 494 MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, 495 MMC_CAP_CMD23, 496 MMC_CAP_CMD23, 497 MMC_CAP_CMD23, 498 }; 499 500 static const struct dw_mci_drv_data exynos_drv_data = { 501 .caps = exynos_dwmmc_caps, 502 .init = dw_mci_exynos_priv_init, 503 .setup_clock = dw_mci_exynos_setup_clock, 504 .set_ios = dw_mci_exynos_set_ios, 505 .parse_dt = dw_mci_exynos_parse_dt, 506 .execute_tuning = dw_mci_exynos_execute_tuning, 507 .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning, 508 }; 509 510 static const struct of_device_id dw_mci_exynos_match[] = { 511 { .compatible = "samsung,exynos4412-dw-mshc", 512 .data = &exynos_drv_data, }, 513 { .compatible = "samsung,exynos5250-dw-mshc", 514 .data = &exynos_drv_data, }, 515 { .compatible = "samsung,exynos5420-dw-mshc", 516 .data = &exynos_drv_data, }, 517 { .compatible = "samsung,exynos5420-dw-mshc-smu", 518 .data = &exynos_drv_data, }, 519 { .compatible = "samsung,exynos7-dw-mshc", 520 .data = &exynos_drv_data, }, 521 { .compatible = "samsung,exynos7-dw-mshc-smu", 522 .data = &exynos_drv_data, }, 523 {}, 524 }; 525 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match); 526 527 static int dw_mci_exynos_probe(struct platform_device *pdev) 528 { 529 const struct dw_mci_drv_data *drv_data; 530 const struct of_device_id *match; 531 532 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node); 533 drv_data = match->data; 534 return dw_mci_pltfm_register(pdev, drv_data); 535 } 536 537 static const struct dev_pm_ops dw_mci_exynos_pmops = { 538 SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume) 539 .resume_noirq = dw_mci_exynos_resume_noirq, 540 .thaw_noirq = dw_mci_exynos_resume_noirq, 541 .restore_noirq = dw_mci_exynos_resume_noirq, 542 }; 543 544 static struct platform_driver dw_mci_exynos_pltfm_driver = { 545 .probe = dw_mci_exynos_probe, 546 .remove = dw_mci_pltfm_remove, 547 .driver = { 548 .name = "dwmmc_exynos", 549 .of_match_table = dw_mci_exynos_match, 550 .pm = &dw_mci_exynos_pmops, 551 }, 552 }; 553 554 module_platform_driver(dw_mci_exynos_pltfm_driver); 555 556 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension"); 557 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com"); 558 MODULE_LICENSE("GPL v2"); 559 MODULE_ALIAS("platform:dwmmc_exynos"); 560