1c3665006SThomas Abraham /* 2c3665006SThomas Abraham * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 3c3665006SThomas Abraham * 4c3665006SThomas Abraham * Copyright (C) 2012, Samsung Electronics Co., Ltd. 5c3665006SThomas Abraham * 6c3665006SThomas Abraham * This program is free software; you can redistribute it and/or modify 7c3665006SThomas Abraham * it under the terms of the GNU General Public License as published by 8c3665006SThomas Abraham * the Free Software Foundation; either version 2 of the License, or 9c3665006SThomas Abraham * (at your option) any later version. 10c3665006SThomas Abraham */ 11c3665006SThomas Abraham 12c3665006SThomas Abraham #include <linux/module.h> 13c3665006SThomas Abraham #include <linux/platform_device.h> 14c3665006SThomas Abraham #include <linux/clk.h> 15c3665006SThomas Abraham #include <linux/mmc/host.h> 16c3665006SThomas Abraham #include <linux/mmc/dw_mmc.h> 17c537a1c5SSeungwon Jeon #include <linux/mmc/mmc.h> 18c3665006SThomas Abraham #include <linux/of.h> 19c3665006SThomas Abraham #include <linux/of_gpio.h> 20c537a1c5SSeungwon Jeon #include <linux/slab.h> 21c3665006SThomas Abraham 22c3665006SThomas Abraham #include "dw_mmc.h" 23c3665006SThomas Abraham #include "dw_mmc-pltfm.h" 240b5fce48SSeungwon Jeon #include "dw_mmc-exynos.h" 25c6d9dedaSSeungwon Jeon 26c3665006SThomas Abraham /* Variations in Exynos specific dw-mshc controller */ 27c3665006SThomas Abraham enum dw_mci_exynos_type { 28c3665006SThomas Abraham DW_MCI_TYPE_EXYNOS4210, 29c3665006SThomas Abraham DW_MCI_TYPE_EXYNOS4412, 30c3665006SThomas Abraham DW_MCI_TYPE_EXYNOS5250, 3100fd041bSYuvaraj Kumar C D DW_MCI_TYPE_EXYNOS5420, 326bce431cSYuvaraj Kumar C D DW_MCI_TYPE_EXYNOS5420_SMU, 3389ad2be7SAbhilash Kesavan DW_MCI_TYPE_EXYNOS7, 3489ad2be7SAbhilash Kesavan DW_MCI_TYPE_EXYNOS7_SMU, 35c3665006SThomas Abraham }; 36c3665006SThomas Abraham 37c3665006SThomas Abraham /* Exynos implementation specific driver private data */ 38c3665006SThomas Abraham struct dw_mci_exynos_priv_data { 39c3665006SThomas Abraham enum dw_mci_exynos_type ctrl_type; 40c3665006SThomas Abraham u8 ciu_div; 41c3665006SThomas Abraham u32 sdr_timing; 42c3665006SThomas Abraham u32 ddr_timing; 43c6d9dedaSSeungwon Jeon u32 cur_speed; 44c3665006SThomas Abraham }; 45c3665006SThomas Abraham 46c3665006SThomas Abraham static struct dw_mci_exynos_compatible { 47c3665006SThomas Abraham char *compatible; 48c3665006SThomas Abraham enum dw_mci_exynos_type ctrl_type; 49c3665006SThomas Abraham } exynos_compat[] = { 50c3665006SThomas Abraham { 51c3665006SThomas Abraham .compatible = "samsung,exynos4210-dw-mshc", 52c3665006SThomas Abraham .ctrl_type = DW_MCI_TYPE_EXYNOS4210, 53c3665006SThomas Abraham }, { 54c3665006SThomas Abraham .compatible = "samsung,exynos4412-dw-mshc", 55c3665006SThomas Abraham .ctrl_type = DW_MCI_TYPE_EXYNOS4412, 56c3665006SThomas Abraham }, { 57c3665006SThomas Abraham .compatible = "samsung,exynos5250-dw-mshc", 58c3665006SThomas Abraham .ctrl_type = DW_MCI_TYPE_EXYNOS5250, 5900fd041bSYuvaraj Kumar C D }, { 6000fd041bSYuvaraj Kumar C D .compatible = "samsung,exynos5420-dw-mshc", 6100fd041bSYuvaraj Kumar C D .ctrl_type = DW_MCI_TYPE_EXYNOS5420, 626bce431cSYuvaraj Kumar C D }, { 636bce431cSYuvaraj Kumar C D .compatible = "samsung,exynos5420-dw-mshc-smu", 646bce431cSYuvaraj Kumar C D .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU, 6589ad2be7SAbhilash Kesavan }, { 6689ad2be7SAbhilash Kesavan .compatible = "samsung,exynos7-dw-mshc", 6789ad2be7SAbhilash Kesavan .ctrl_type = DW_MCI_TYPE_EXYNOS7, 6889ad2be7SAbhilash Kesavan }, { 6989ad2be7SAbhilash Kesavan .compatible = "samsung,exynos7-dw-mshc-smu", 7089ad2be7SAbhilash Kesavan .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, 71c3665006SThomas Abraham }, 72c3665006SThomas Abraham }; 73c3665006SThomas Abraham 74c3665006SThomas Abraham static int dw_mci_exynos_priv_init(struct dw_mci *host) 75c3665006SThomas Abraham { 76e6c784edSYuvaraj Kumar C D struct dw_mci_exynos_priv_data *priv = host->priv; 77c3665006SThomas Abraham 7889ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || 7989ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { 806bce431cSYuvaraj Kumar C D mci_writel(host, MPSBEGIN0, 0); 810b5fce48SSeungwon Jeon mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); 820b5fce48SSeungwon Jeon mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | 830b5fce48SSeungwon Jeon SDMMC_MPSCTRL_NON_SECURE_READ_BIT | 840b5fce48SSeungwon Jeon SDMMC_MPSCTRL_VALID | 850b5fce48SSeungwon Jeon SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); 866bce431cSYuvaraj Kumar C D } 876bce431cSYuvaraj Kumar C D 88c3665006SThomas Abraham return 0; 89c3665006SThomas Abraham } 90c3665006SThomas Abraham 91c3665006SThomas Abraham static int dw_mci_exynos_setup_clock(struct dw_mci *host) 92c3665006SThomas Abraham { 93c3665006SThomas Abraham struct dw_mci_exynos_priv_data *priv = host->priv; 94c3665006SThomas Abraham 95a2a1fed8SSeungwon Jeon host->bus_hz /= (priv->ciu_div + 1); 96a2a1fed8SSeungwon Jeon 97c3665006SThomas Abraham return 0; 98c3665006SThomas Abraham } 99c3665006SThomas Abraham 100e2c63599SDoug Anderson #ifdef CONFIG_PM_SLEEP 101e2c63599SDoug Anderson static int dw_mci_exynos_suspend(struct device *dev) 102e2c63599SDoug Anderson { 103e2c63599SDoug Anderson struct dw_mci *host = dev_get_drvdata(dev); 104e2c63599SDoug Anderson 105e2c63599SDoug Anderson return dw_mci_suspend(host); 106e2c63599SDoug Anderson } 107e2c63599SDoug Anderson 108e2c63599SDoug Anderson static int dw_mci_exynos_resume(struct device *dev) 109e2c63599SDoug Anderson { 110e2c63599SDoug Anderson struct dw_mci *host = dev_get_drvdata(dev); 111e2c63599SDoug Anderson 1126bce431cSYuvaraj Kumar C D dw_mci_exynos_priv_init(host); 113e2c63599SDoug Anderson return dw_mci_resume(host); 114e2c63599SDoug Anderson } 115e2c63599SDoug Anderson 116e2c63599SDoug Anderson /** 117e2c63599SDoug Anderson * dw_mci_exynos_resume_noirq - Exynos-specific resume code 118e2c63599SDoug Anderson * 119e2c63599SDoug Anderson * On exynos5420 there is a silicon errata that will sometimes leave the 120e2c63599SDoug Anderson * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate 121e2c63599SDoug Anderson * that it fired and we can clear it by writing a 1 back. Clear it to prevent 122e2c63599SDoug Anderson * interrupts from going off constantly. 123e2c63599SDoug Anderson * 124e2c63599SDoug Anderson * We run this code on all exynos variants because it doesn't hurt. 125e2c63599SDoug Anderson */ 126e2c63599SDoug Anderson 127e2c63599SDoug Anderson static int dw_mci_exynos_resume_noirq(struct device *dev) 128e2c63599SDoug Anderson { 129e2c63599SDoug Anderson struct dw_mci *host = dev_get_drvdata(dev); 13089ad2be7SAbhilash Kesavan struct dw_mci_exynos_priv_data *priv = host->priv; 131e2c63599SDoug Anderson u32 clksel; 132e2c63599SDoug Anderson 13389ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 13489ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 13589ad2be7SAbhilash Kesavan clksel = mci_readl(host, CLKSEL64); 13689ad2be7SAbhilash Kesavan else 137e2c63599SDoug Anderson clksel = mci_readl(host, CLKSEL); 13889ad2be7SAbhilash Kesavan 13989ad2be7SAbhilash Kesavan if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { 14089ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 14189ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 14289ad2be7SAbhilash Kesavan mci_writel(host, CLKSEL64, clksel); 14389ad2be7SAbhilash Kesavan else 144e2c63599SDoug Anderson mci_writel(host, CLKSEL, clksel); 14589ad2be7SAbhilash Kesavan } 146e2c63599SDoug Anderson 147e2c63599SDoug Anderson return 0; 148e2c63599SDoug Anderson } 149e2c63599SDoug Anderson #else 150e2c63599SDoug Anderson #define dw_mci_exynos_suspend NULL 151e2c63599SDoug Anderson #define dw_mci_exynos_resume NULL 152e2c63599SDoug Anderson #define dw_mci_exynos_resume_noirq NULL 153e2c63599SDoug Anderson #endif /* CONFIG_PM_SLEEP */ 154e2c63599SDoug Anderson 155c3665006SThomas Abraham static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr) 156c3665006SThomas Abraham { 15789ad2be7SAbhilash Kesavan struct dw_mci_exynos_priv_data *priv = host->priv; 158c3665006SThomas Abraham /* 159c3665006SThomas Abraham * Exynos4412 and Exynos5250 extends the use of CMD register with the 160c3665006SThomas Abraham * use of bit 29 (which is reserved on standard MSHC controllers) for 161c3665006SThomas Abraham * optionally bypassing the HOLD register for command and data. The 162c3665006SThomas Abraham * HOLD register should be bypassed in case there is no phase shift 163c3665006SThomas Abraham * applied on CMD/DATA that is sent to the card. 164c3665006SThomas Abraham */ 16589ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 16689ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { 16789ad2be7SAbhilash Kesavan if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64))) 16889ad2be7SAbhilash Kesavan *cmdr |= SDMMC_CMD_USE_HOLD_REG; 16989ad2be7SAbhilash Kesavan } else { 170c3665006SThomas Abraham if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL))) 171c3665006SThomas Abraham *cmdr |= SDMMC_CMD_USE_HOLD_REG; 172c3665006SThomas Abraham } 17389ad2be7SAbhilash Kesavan } 174c3665006SThomas Abraham 175c3665006SThomas Abraham static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) 176c3665006SThomas Abraham { 177c3665006SThomas Abraham struct dw_mci_exynos_priv_data *priv = host->priv; 178c6d9dedaSSeungwon Jeon unsigned int wanted = ios->clock; 179c6d9dedaSSeungwon Jeon unsigned long actual; 180c6d9dedaSSeungwon Jeon u8 div = priv->ciu_div + 1; 181c3665006SThomas Abraham 182cab3a802SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52) { 18389ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 18489ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 18589ad2be7SAbhilash Kesavan mci_writel(host, CLKSEL64, priv->ddr_timing); 18689ad2be7SAbhilash Kesavan else 187c3665006SThomas Abraham mci_writel(host, CLKSEL, priv->ddr_timing); 188c6d9dedaSSeungwon Jeon /* Should be double rate for DDR mode */ 189c6d9dedaSSeungwon Jeon if (ios->bus_width == MMC_BUS_WIDTH_8) 190c6d9dedaSSeungwon Jeon wanted <<= 1; 191c6d9dedaSSeungwon Jeon } else { 19289ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 19389ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 19489ad2be7SAbhilash Kesavan mci_writel(host, CLKSEL64, priv->sdr_timing); 19589ad2be7SAbhilash Kesavan else 196c3665006SThomas Abraham mci_writel(host, CLKSEL, priv->sdr_timing); 197c3665006SThomas Abraham } 198c3665006SThomas Abraham 199a2a1fed8SSeungwon Jeon /* 200a2a1fed8SSeungwon Jeon * Don't care if wanted clock is zero or 201a2a1fed8SSeungwon Jeon * ciu clock is unavailable 202a2a1fed8SSeungwon Jeon */ 203a2a1fed8SSeungwon Jeon if (!wanted || IS_ERR(host->ciu_clk)) 204c6d9dedaSSeungwon Jeon return; 205c6d9dedaSSeungwon Jeon 206c6d9dedaSSeungwon Jeon /* Guaranteed minimum frequency for cclkin */ 207c6d9dedaSSeungwon Jeon if (wanted < EXYNOS_CCLKIN_MIN) 208c6d9dedaSSeungwon Jeon wanted = EXYNOS_CCLKIN_MIN; 209c6d9dedaSSeungwon Jeon 210c6d9dedaSSeungwon Jeon if (wanted != priv->cur_speed) { 211c6d9dedaSSeungwon Jeon int ret = clk_set_rate(host->ciu_clk, wanted * div); 212c6d9dedaSSeungwon Jeon if (ret) 213c6d9dedaSSeungwon Jeon dev_warn(host->dev, 214c6d9dedaSSeungwon Jeon "failed to set clk-rate %u error: %d\n", 215c6d9dedaSSeungwon Jeon wanted * div, ret); 216c6d9dedaSSeungwon Jeon actual = clk_get_rate(host->ciu_clk); 217c6d9dedaSSeungwon Jeon host->bus_hz = actual / div; 218c6d9dedaSSeungwon Jeon priv->cur_speed = wanted; 219c6d9dedaSSeungwon Jeon host->current_speed = 0; 220c6d9dedaSSeungwon Jeon } 221c6d9dedaSSeungwon Jeon } 222c6d9dedaSSeungwon Jeon 223c3665006SThomas Abraham static int dw_mci_exynos_parse_dt(struct dw_mci *host) 224c3665006SThomas Abraham { 225e6c784edSYuvaraj Kumar C D struct dw_mci_exynos_priv_data *priv; 226c3665006SThomas Abraham struct device_node *np = host->dev->of_node; 227c3665006SThomas Abraham u32 timing[2]; 228c3665006SThomas Abraham u32 div = 0; 229e6c784edSYuvaraj Kumar C D int idx; 230c3665006SThomas Abraham int ret; 231c3665006SThomas Abraham 232e6c784edSYuvaraj Kumar C D priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 233e6c784edSYuvaraj Kumar C D if (!priv) { 234e6c784edSYuvaraj Kumar C D dev_err(host->dev, "mem alloc failed for private data\n"); 235e6c784edSYuvaraj Kumar C D return -ENOMEM; 236e6c784edSYuvaraj Kumar C D } 237e6c784edSYuvaraj Kumar C D 238e6c784edSYuvaraj Kumar C D for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) { 239e6c784edSYuvaraj Kumar C D if (of_device_is_compatible(np, exynos_compat[idx].compatible)) 240e6c784edSYuvaraj Kumar C D priv->ctrl_type = exynos_compat[idx].ctrl_type; 241e6c784edSYuvaraj Kumar C D } 242e6c784edSYuvaraj Kumar C D 243c6d9dedaSSeungwon Jeon if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) 244c6d9dedaSSeungwon Jeon priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; 245c6d9dedaSSeungwon Jeon else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) 246c6d9dedaSSeungwon Jeon priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; 247c6d9dedaSSeungwon Jeon else { 248c3665006SThomas Abraham of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); 249c3665006SThomas Abraham priv->ciu_div = div; 250c6d9dedaSSeungwon Jeon } 251c3665006SThomas Abraham 252c3665006SThomas Abraham ret = of_property_read_u32_array(np, 253c3665006SThomas Abraham "samsung,dw-mshc-sdr-timing", timing, 2); 254c3665006SThomas Abraham if (ret) 255c3665006SThomas Abraham return ret; 256c3665006SThomas Abraham 2572d9f0bd1SYuvaraj Kumar C D priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 2582d9f0bd1SYuvaraj Kumar C D 259c3665006SThomas Abraham ret = of_property_read_u32_array(np, 260c3665006SThomas Abraham "samsung,dw-mshc-ddr-timing", timing, 2); 261c3665006SThomas Abraham if (ret) 262c3665006SThomas Abraham return ret; 263c3665006SThomas Abraham 264c3665006SThomas Abraham priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); 265e6c784edSYuvaraj Kumar C D host->priv = priv; 266c3665006SThomas Abraham return 0; 267c3665006SThomas Abraham } 268c3665006SThomas Abraham 269c537a1c5SSeungwon Jeon static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) 270c537a1c5SSeungwon Jeon { 27189ad2be7SAbhilash Kesavan struct dw_mci_exynos_priv_data *priv = host->priv; 27289ad2be7SAbhilash Kesavan 27389ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 27489ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 27589ad2be7SAbhilash Kesavan return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); 27689ad2be7SAbhilash Kesavan else 277c537a1c5SSeungwon Jeon return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL)); 278c537a1c5SSeungwon Jeon } 279c537a1c5SSeungwon Jeon 280c537a1c5SSeungwon Jeon static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) 281c537a1c5SSeungwon Jeon { 282c537a1c5SSeungwon Jeon u32 clksel; 28389ad2be7SAbhilash Kesavan struct dw_mci_exynos_priv_data *priv = host->priv; 28489ad2be7SAbhilash Kesavan 28589ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 28689ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 28789ad2be7SAbhilash Kesavan clksel = mci_readl(host, CLKSEL64); 28889ad2be7SAbhilash Kesavan else 289c537a1c5SSeungwon Jeon clksel = mci_readl(host, CLKSEL); 290c537a1c5SSeungwon Jeon clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample); 29189ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 29289ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 29389ad2be7SAbhilash Kesavan mci_writel(host, CLKSEL64, clksel); 29489ad2be7SAbhilash Kesavan else 295c537a1c5SSeungwon Jeon mci_writel(host, CLKSEL, clksel); 296c537a1c5SSeungwon Jeon } 297c537a1c5SSeungwon Jeon 298c537a1c5SSeungwon Jeon static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) 299c537a1c5SSeungwon Jeon { 30089ad2be7SAbhilash Kesavan struct dw_mci_exynos_priv_data *priv = host->priv; 301c537a1c5SSeungwon Jeon u32 clksel; 302c537a1c5SSeungwon Jeon u8 sample; 303c537a1c5SSeungwon Jeon 30489ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 30589ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 30689ad2be7SAbhilash Kesavan clksel = mci_readl(host, CLKSEL64); 30789ad2be7SAbhilash Kesavan else 308c537a1c5SSeungwon Jeon clksel = mci_readl(host, CLKSEL); 309c537a1c5SSeungwon Jeon sample = (clksel + 1) & 0x7; 310c537a1c5SSeungwon Jeon clksel = (clksel & ~0x7) | sample; 31189ad2be7SAbhilash Kesavan if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || 31289ad2be7SAbhilash Kesavan priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) 31389ad2be7SAbhilash Kesavan mci_writel(host, CLKSEL64, clksel); 31489ad2be7SAbhilash Kesavan else 315c537a1c5SSeungwon Jeon mci_writel(host, CLKSEL, clksel); 316c537a1c5SSeungwon Jeon return sample; 317c537a1c5SSeungwon Jeon } 318c537a1c5SSeungwon Jeon 319c537a1c5SSeungwon Jeon static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates) 320c537a1c5SSeungwon Jeon { 321c537a1c5SSeungwon Jeon const u8 iter = 8; 322c537a1c5SSeungwon Jeon u8 __c; 323c537a1c5SSeungwon Jeon s8 i, loc = -1; 324c537a1c5SSeungwon Jeon 325c537a1c5SSeungwon Jeon for (i = 0; i < iter; i++) { 326c537a1c5SSeungwon Jeon __c = ror8(candiates, i); 327c537a1c5SSeungwon Jeon if ((__c & 0xc7) == 0xc7) { 328c537a1c5SSeungwon Jeon loc = i; 329c537a1c5SSeungwon Jeon goto out; 330c537a1c5SSeungwon Jeon } 331c537a1c5SSeungwon Jeon } 332c537a1c5SSeungwon Jeon 333c537a1c5SSeungwon Jeon for (i = 0; i < iter; i++) { 334c537a1c5SSeungwon Jeon __c = ror8(candiates, i); 335c537a1c5SSeungwon Jeon if ((__c & 0x83) == 0x83) { 336c537a1c5SSeungwon Jeon loc = i; 337c537a1c5SSeungwon Jeon goto out; 338c537a1c5SSeungwon Jeon } 339c537a1c5SSeungwon Jeon } 340c537a1c5SSeungwon Jeon 341c537a1c5SSeungwon Jeon out: 342c537a1c5SSeungwon Jeon return loc; 343c537a1c5SSeungwon Jeon } 344c537a1c5SSeungwon Jeon 345c537a1c5SSeungwon Jeon static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode, 346c537a1c5SSeungwon Jeon struct dw_mci_tuning_data *tuning_data) 347c537a1c5SSeungwon Jeon { 348c537a1c5SSeungwon Jeon struct dw_mci *host = slot->host; 349c537a1c5SSeungwon Jeon struct mmc_host *mmc = slot->mmc; 350c537a1c5SSeungwon Jeon const u8 *blk_pattern = tuning_data->blk_pattern; 351c537a1c5SSeungwon Jeon u8 *blk_test; 352c537a1c5SSeungwon Jeon unsigned int blksz = tuning_data->blksz; 353c537a1c5SSeungwon Jeon u8 start_smpl, smpl, candiates = 0; 354c537a1c5SSeungwon Jeon s8 found = -1; 355c537a1c5SSeungwon Jeon int ret = 0; 356c537a1c5SSeungwon Jeon 357c537a1c5SSeungwon Jeon blk_test = kmalloc(blksz, GFP_KERNEL); 358c537a1c5SSeungwon Jeon if (!blk_test) 359c537a1c5SSeungwon Jeon return -ENOMEM; 360c537a1c5SSeungwon Jeon 361c537a1c5SSeungwon Jeon start_smpl = dw_mci_exynos_get_clksmpl(host); 362c537a1c5SSeungwon Jeon 363c537a1c5SSeungwon Jeon do { 364c537a1c5SSeungwon Jeon struct mmc_request mrq = {NULL}; 365c537a1c5SSeungwon Jeon struct mmc_command cmd = {0}; 366c537a1c5SSeungwon Jeon struct mmc_command stop = {0}; 367c537a1c5SSeungwon Jeon struct mmc_data data = {0}; 368c537a1c5SSeungwon Jeon struct scatterlist sg; 369c537a1c5SSeungwon Jeon 370c537a1c5SSeungwon Jeon cmd.opcode = opcode; 371c537a1c5SSeungwon Jeon cmd.arg = 0; 372c537a1c5SSeungwon Jeon cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 373c537a1c5SSeungwon Jeon 374c537a1c5SSeungwon Jeon stop.opcode = MMC_STOP_TRANSMISSION; 375c537a1c5SSeungwon Jeon stop.arg = 0; 376c537a1c5SSeungwon Jeon stop.flags = MMC_RSP_R1B | MMC_CMD_AC; 377c537a1c5SSeungwon Jeon 378c537a1c5SSeungwon Jeon data.blksz = blksz; 379c537a1c5SSeungwon Jeon data.blocks = 1; 380c537a1c5SSeungwon Jeon data.flags = MMC_DATA_READ; 381c537a1c5SSeungwon Jeon data.sg = &sg; 382c537a1c5SSeungwon Jeon data.sg_len = 1; 383c537a1c5SSeungwon Jeon 384c537a1c5SSeungwon Jeon sg_init_one(&sg, blk_test, blksz); 385c537a1c5SSeungwon Jeon mrq.cmd = &cmd; 386c537a1c5SSeungwon Jeon mrq.stop = &stop; 387c537a1c5SSeungwon Jeon mrq.data = &data; 388c537a1c5SSeungwon Jeon host->mrq = &mrq; 389c537a1c5SSeungwon Jeon 390c537a1c5SSeungwon Jeon mci_writel(host, TMOUT, ~0); 391c537a1c5SSeungwon Jeon smpl = dw_mci_exynos_move_next_clksmpl(host); 392c537a1c5SSeungwon Jeon 393c537a1c5SSeungwon Jeon mmc_wait_for_req(mmc, &mrq); 394c537a1c5SSeungwon Jeon 395c537a1c5SSeungwon Jeon if (!cmd.error && !data.error) { 396c537a1c5SSeungwon Jeon if (!memcmp(blk_pattern, blk_test, blksz)) 397c537a1c5SSeungwon Jeon candiates |= (1 << smpl); 398c537a1c5SSeungwon Jeon } else { 399c537a1c5SSeungwon Jeon dev_dbg(host->dev, 400c537a1c5SSeungwon Jeon "Tuning error: cmd.error:%d, data.error:%d\n", 401c537a1c5SSeungwon Jeon cmd.error, data.error); 402c537a1c5SSeungwon Jeon } 403c537a1c5SSeungwon Jeon } while (start_smpl != smpl); 404c537a1c5SSeungwon Jeon 405c537a1c5SSeungwon Jeon found = dw_mci_exynos_get_best_clksmpl(candiates); 406c537a1c5SSeungwon Jeon if (found >= 0) 407c537a1c5SSeungwon Jeon dw_mci_exynos_set_clksmpl(host, found); 408c537a1c5SSeungwon Jeon else 409c537a1c5SSeungwon Jeon ret = -EIO; 410c537a1c5SSeungwon Jeon 411c537a1c5SSeungwon Jeon kfree(blk_test); 412c537a1c5SSeungwon Jeon return ret; 413c537a1c5SSeungwon Jeon } 414c537a1c5SSeungwon Jeon 4150f6e73d0SDongjin Kim /* Common capabilities of Exynos4/Exynos5 SoC */ 4160f6e73d0SDongjin Kim static unsigned long exynos_dwmmc_caps[4] = { 417cab3a802SSeungwon Jeon MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, 418c3665006SThomas Abraham MMC_CAP_CMD23, 419c3665006SThomas Abraham MMC_CAP_CMD23, 420c3665006SThomas Abraham MMC_CAP_CMD23, 421c3665006SThomas Abraham }; 422c3665006SThomas Abraham 4230f6e73d0SDongjin Kim static const struct dw_mci_drv_data exynos_drv_data = { 4240f6e73d0SDongjin Kim .caps = exynos_dwmmc_caps, 425c3665006SThomas Abraham .init = dw_mci_exynos_priv_init, 426c3665006SThomas Abraham .setup_clock = dw_mci_exynos_setup_clock, 427c3665006SThomas Abraham .prepare_command = dw_mci_exynos_prepare_command, 428c3665006SThomas Abraham .set_ios = dw_mci_exynos_set_ios, 429c3665006SThomas Abraham .parse_dt = dw_mci_exynos_parse_dt, 430c537a1c5SSeungwon Jeon .execute_tuning = dw_mci_exynos_execute_tuning, 431c3665006SThomas Abraham }; 432c3665006SThomas Abraham 433c3665006SThomas Abraham static const struct of_device_id dw_mci_exynos_match[] = { 4340f6e73d0SDongjin Kim { .compatible = "samsung,exynos4412-dw-mshc", 4350f6e73d0SDongjin Kim .data = &exynos_drv_data, }, 436c3665006SThomas Abraham { .compatible = "samsung,exynos5250-dw-mshc", 4370f6e73d0SDongjin Kim .data = &exynos_drv_data, }, 43800fd041bSYuvaraj Kumar C D { .compatible = "samsung,exynos5420-dw-mshc", 43900fd041bSYuvaraj Kumar C D .data = &exynos_drv_data, }, 4406bce431cSYuvaraj Kumar C D { .compatible = "samsung,exynos5420-dw-mshc-smu", 4416bce431cSYuvaraj Kumar C D .data = &exynos_drv_data, }, 44289ad2be7SAbhilash Kesavan { .compatible = "samsung,exynos7-dw-mshc", 44389ad2be7SAbhilash Kesavan .data = &exynos_drv_data, }, 44489ad2be7SAbhilash Kesavan { .compatible = "samsung,exynos7-dw-mshc-smu", 44589ad2be7SAbhilash Kesavan .data = &exynos_drv_data, }, 446c3665006SThomas Abraham {}, 447c3665006SThomas Abraham }; 448517cb9f1SArnd Bergmann MODULE_DEVICE_TABLE(of, dw_mci_exynos_match); 449c3665006SThomas Abraham 4509665f7f2SSachin Kamat static int dw_mci_exynos_probe(struct platform_device *pdev) 451c3665006SThomas Abraham { 4528e2b36eaSArnd Bergmann const struct dw_mci_drv_data *drv_data; 453c3665006SThomas Abraham const struct of_device_id *match; 454c3665006SThomas Abraham 455c3665006SThomas Abraham match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node); 456c3665006SThomas Abraham drv_data = match->data; 457c3665006SThomas Abraham return dw_mci_pltfm_register(pdev, drv_data); 458c3665006SThomas Abraham } 459c3665006SThomas Abraham 46015a2e2abSSachin Kamat static const struct dev_pm_ops dw_mci_exynos_pmops = { 461e2c63599SDoug Anderson SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume) 462e2c63599SDoug Anderson .resume_noirq = dw_mci_exynos_resume_noirq, 463e2c63599SDoug Anderson .thaw_noirq = dw_mci_exynos_resume_noirq, 464e2c63599SDoug Anderson .restore_noirq = dw_mci_exynos_resume_noirq, 465e2c63599SDoug Anderson }; 466e2c63599SDoug Anderson 467c3665006SThomas Abraham static struct platform_driver dw_mci_exynos_pltfm_driver = { 468c3665006SThomas Abraham .probe = dw_mci_exynos_probe, 469c3665006SThomas Abraham .remove = __exit_p(dw_mci_pltfm_remove), 470c3665006SThomas Abraham .driver = { 471c3665006SThomas Abraham .name = "dwmmc_exynos", 47220183d50SSachin Kamat .of_match_table = dw_mci_exynos_match, 473e2c63599SDoug Anderson .pm = &dw_mci_exynos_pmops, 474c3665006SThomas Abraham }, 475c3665006SThomas Abraham }; 476c3665006SThomas Abraham 477c3665006SThomas Abraham module_platform_driver(dw_mci_exynos_pltfm_driver); 478c3665006SThomas Abraham 479c3665006SThomas Abraham MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension"); 480c3665006SThomas Abraham MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com"); 481c3665006SThomas Abraham MODULE_LICENSE("GPL v2"); 482c3665006SThomas Abraham MODULE_ALIAS("platform:dwmmc-exynos"); 483