1 /* 2 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Original author: Purushotam Kumar 6 * Copyright (C) 2009 David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/ioport.h> 25 #include <linux/platform_device.h> 26 #include <linux/clk.h> 27 #include <linux/err.h> 28 #include <linux/cpufreq.h> 29 #include <linux/mmc/host.h> 30 #include <linux/io.h> 31 #include <linux/irq.h> 32 #include <linux/delay.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/mmc/mmc.h> 35 36 #include <mach/mmc.h> 37 #include <mach/edma.h> 38 39 /* 40 * Register Definitions 41 */ 42 #define DAVINCI_MMCCTL 0x00 /* Control Register */ 43 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 44 #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 45 #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 46 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 47 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 48 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 49 #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 50 #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 51 #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 52 #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 53 #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 54 #define DAVINCI_MMCCMD 0x30 /* Command Register */ 55 #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 56 #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 57 #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 58 #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 59 #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 60 #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 61 #define DAVINCI_MMCETOK 0x4C 62 #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 63 #define DAVINCI_MMCCKC 0x54 64 #define DAVINCI_MMCTORC 0x58 65 #define DAVINCI_MMCTODC 0x5C 66 #define DAVINCI_MMCBLNC 0x60 67 #define DAVINCI_SDIOCTL 0x64 68 #define DAVINCI_SDIOST0 0x68 69 #define DAVINCI_SDIOEN 0x6C 70 #define DAVINCI_SDIOST 0x70 71 #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 72 73 /* DAVINCI_MMCCTL definitions */ 74 #define MMCCTL_DATRST (1 << 0) 75 #define MMCCTL_CMDRST (1 << 1) 76 #define MMCCTL_WIDTH_8_BIT (1 << 8) 77 #define MMCCTL_WIDTH_4_BIT (1 << 2) 78 #define MMCCTL_DATEG_DISABLED (0 << 6) 79 #define MMCCTL_DATEG_RISING (1 << 6) 80 #define MMCCTL_DATEG_FALLING (2 << 6) 81 #define MMCCTL_DATEG_BOTH (3 << 6) 82 #define MMCCTL_PERMDR_LE (0 << 9) 83 #define MMCCTL_PERMDR_BE (1 << 9) 84 #define MMCCTL_PERMDX_LE (0 << 10) 85 #define MMCCTL_PERMDX_BE (1 << 10) 86 87 /* DAVINCI_MMCCLK definitions */ 88 #define MMCCLK_CLKEN (1 << 8) 89 #define MMCCLK_CLKRT_MASK (0xFF << 0) 90 91 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 92 #define MMCST0_DATDNE BIT(0) /* data done */ 93 #define MMCST0_BSYDNE BIT(1) /* busy done */ 94 #define MMCST0_RSPDNE BIT(2) /* command done */ 95 #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 96 #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 97 #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 98 #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 99 #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 100 #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 101 #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 102 #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 103 #define MMCST0_TRNDNE BIT(12) /* transfer done */ 104 105 /* DAVINCI_MMCST1 definitions */ 106 #define MMCST1_BUSY (1 << 0) 107 108 /* DAVINCI_MMCCMD definitions */ 109 #define MMCCMD_CMD_MASK (0x3F << 0) 110 #define MMCCMD_PPLEN (1 << 7) 111 #define MMCCMD_BSYEXP (1 << 8) 112 #define MMCCMD_RSPFMT_MASK (3 << 9) 113 #define MMCCMD_RSPFMT_NONE (0 << 9) 114 #define MMCCMD_RSPFMT_R1456 (1 << 9) 115 #define MMCCMD_RSPFMT_R2 (2 << 9) 116 #define MMCCMD_RSPFMT_R3 (3 << 9) 117 #define MMCCMD_DTRW (1 << 11) 118 #define MMCCMD_STRMTP (1 << 12) 119 #define MMCCMD_WDATX (1 << 13) 120 #define MMCCMD_INITCK (1 << 14) 121 #define MMCCMD_DCLR (1 << 15) 122 #define MMCCMD_DMATRIG (1 << 16) 123 124 /* DAVINCI_MMCFIFOCTL definitions */ 125 #define MMCFIFOCTL_FIFORST (1 << 0) 126 #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 127 #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 128 #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 129 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 130 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 131 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 132 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 133 134 135 /* MMCSD Init clock in Hz in opendrain mode */ 136 #define MMCSD_INIT_CLOCK 200000 137 138 /* 139 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 140 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 141 * for drivers with max_hw_segs == 1, making the segments bigger (64KB) 142 * than the page or two that's otherwise typical. nr_sg (passed from 143 * platform data) == 16 gives at least the same throughput boost, using 144 * EDMA transfer linkage instead of spending CPU time copying pages. 145 */ 146 #define MAX_CCNT ((1 << 16) - 1) 147 148 #define MAX_NR_SG 16 149 150 static unsigned rw_threshold = 32; 151 module_param(rw_threshold, uint, S_IRUGO); 152 MODULE_PARM_DESC(rw_threshold, 153 "Read/Write threshold. Default = 32"); 154 155 static unsigned __initdata use_dma = 1; 156 module_param(use_dma, uint, 0); 157 MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 158 159 struct mmc_davinci_host { 160 struct mmc_command *cmd; 161 struct mmc_data *data; 162 struct mmc_host *mmc; 163 struct clk *clk; 164 unsigned int mmc_input_clk; 165 void __iomem *base; 166 struct resource *mem_res; 167 int irq; 168 unsigned char bus_mode; 169 170 #define DAVINCI_MMC_DATADIR_NONE 0 171 #define DAVINCI_MMC_DATADIR_READ 1 172 #define DAVINCI_MMC_DATADIR_WRITE 2 173 unsigned char data_dir; 174 175 /* buffer is used during PIO of one scatterlist segment, and 176 * is updated along with buffer_bytes_left. bytes_left applies 177 * to all N blocks of the PIO transfer. 178 */ 179 u8 *buffer; 180 u32 buffer_bytes_left; 181 u32 bytes_left; 182 183 u32 rxdma, txdma; 184 bool use_dma; 185 bool do_dma; 186 187 /* Scatterlist DMA uses one or more parameter RAM entries: 188 * the main one (associated with rxdma or txdma) plus zero or 189 * more links. The entries for a given transfer differ only 190 * by memory buffer (address, length) and link field. 191 */ 192 struct edmacc_param tx_template; 193 struct edmacc_param rx_template; 194 unsigned n_link; 195 u32 links[MAX_NR_SG - 1]; 196 197 /* For PIO we walk scatterlists one segment at a time. */ 198 unsigned int sg_len; 199 struct scatterlist *sg; 200 201 /* Version of the MMC/SD controller */ 202 u8 version; 203 /* for ns in one cycle calculation */ 204 unsigned ns_in_one_cycle; 205 /* Number of sg segments */ 206 u8 nr_sg; 207 #ifdef CONFIG_CPU_FREQ 208 struct notifier_block freq_transition; 209 #endif 210 }; 211 212 213 /* PIO only */ 214 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 215 { 216 host->buffer_bytes_left = sg_dma_len(host->sg); 217 host->buffer = sg_virt(host->sg); 218 if (host->buffer_bytes_left > host->bytes_left) 219 host->buffer_bytes_left = host->bytes_left; 220 } 221 222 static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 223 unsigned int n) 224 { 225 u8 *p; 226 unsigned int i; 227 228 if (host->buffer_bytes_left == 0) { 229 host->sg = sg_next(host->data->sg); 230 mmc_davinci_sg_to_buf(host); 231 } 232 233 p = host->buffer; 234 if (n > host->buffer_bytes_left) 235 n = host->buffer_bytes_left; 236 host->buffer_bytes_left -= n; 237 host->bytes_left -= n; 238 239 /* NOTE: we never transfer more than rw_threshold bytes 240 * to/from the fifo here; there's no I/O overlap. 241 * This also assumes that access width( i.e. ACCWD) is 4 bytes 242 */ 243 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 244 for (i = 0; i < (n >> 2); i++) { 245 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 246 p = p + 4; 247 } 248 if (n & 3) { 249 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 250 p = p + (n & 3); 251 } 252 } else { 253 for (i = 0; i < (n >> 2); i++) { 254 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 255 p = p + 4; 256 } 257 if (n & 3) { 258 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 259 p = p + (n & 3); 260 } 261 } 262 host->buffer = p; 263 } 264 265 static void mmc_davinci_start_command(struct mmc_davinci_host *host, 266 struct mmc_command *cmd) 267 { 268 u32 cmd_reg = 0; 269 u32 im_val; 270 271 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 272 cmd->opcode, cmd->arg, 273 ({ char *s; 274 switch (mmc_resp_type(cmd)) { 275 case MMC_RSP_R1: 276 s = ", R1/R5/R6/R7 response"; 277 break; 278 case MMC_RSP_R1B: 279 s = ", R1b response"; 280 break; 281 case MMC_RSP_R2: 282 s = ", R2 response"; 283 break; 284 case MMC_RSP_R3: 285 s = ", R3/R4 response"; 286 break; 287 default: 288 s = ", (R? response)"; 289 break; 290 }; s; })); 291 host->cmd = cmd; 292 293 switch (mmc_resp_type(cmd)) { 294 case MMC_RSP_R1B: 295 /* There's some spec confusion about when R1B is 296 * allowed, but if the card doesn't issue a BUSY 297 * then it's harmless for us to allow it. 298 */ 299 cmd_reg |= MMCCMD_BSYEXP; 300 /* FALLTHROUGH */ 301 case MMC_RSP_R1: /* 48 bits, CRC */ 302 cmd_reg |= MMCCMD_RSPFMT_R1456; 303 break; 304 case MMC_RSP_R2: /* 136 bits, CRC */ 305 cmd_reg |= MMCCMD_RSPFMT_R2; 306 break; 307 case MMC_RSP_R3: /* 48 bits, no CRC */ 308 cmd_reg |= MMCCMD_RSPFMT_R3; 309 break; 310 default: 311 cmd_reg |= MMCCMD_RSPFMT_NONE; 312 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 313 mmc_resp_type(cmd)); 314 break; 315 } 316 317 /* Set command index */ 318 cmd_reg |= cmd->opcode; 319 320 /* Enable EDMA transfer triggers */ 321 if (host->do_dma) 322 cmd_reg |= MMCCMD_DMATRIG; 323 324 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 325 host->data_dir == DAVINCI_MMC_DATADIR_READ) 326 cmd_reg |= MMCCMD_DMATRIG; 327 328 /* Setting whether command involves data transfer or not */ 329 if (cmd->data) 330 cmd_reg |= MMCCMD_WDATX; 331 332 /* Setting whether stream or block transfer */ 333 if (cmd->flags & MMC_DATA_STREAM) 334 cmd_reg |= MMCCMD_STRMTP; 335 336 /* Setting whether data read or write */ 337 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 338 cmd_reg |= MMCCMD_DTRW; 339 340 if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 341 cmd_reg |= MMCCMD_PPLEN; 342 343 /* set Command timeout */ 344 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 345 346 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 347 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 348 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 349 im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 350 351 if (!host->do_dma) 352 im_val |= MMCST0_DXRDY; 353 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 354 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 355 356 if (!host->do_dma) 357 im_val |= MMCST0_DRRDY; 358 } 359 360 /* 361 * Before non-DMA WRITE commands the controller needs priming: 362 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 363 */ 364 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 365 davinci_fifo_data_trans(host, rw_threshold); 366 367 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 368 writel(cmd_reg, host->base + DAVINCI_MMCCMD); 369 writel(im_val, host->base + DAVINCI_MMCIM); 370 } 371 372 /*----------------------------------------------------------------------*/ 373 374 /* DMA infrastructure */ 375 376 static void davinci_abort_dma(struct mmc_davinci_host *host) 377 { 378 int sync_dev; 379 380 if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 381 sync_dev = host->rxdma; 382 else 383 sync_dev = host->txdma; 384 385 edma_stop(sync_dev); 386 edma_clean_channel(sync_dev); 387 } 388 389 static void 390 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data); 391 392 static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data) 393 { 394 if (DMA_COMPLETE != ch_status) { 395 struct mmc_davinci_host *host = data; 396 397 /* Currently means: DMA Event Missed, or "null" transfer 398 * request was seen. In the future, TC errors (like bad 399 * addresses) might be presented too. 400 */ 401 dev_warn(mmc_dev(host->mmc), "DMA %s error\n", 402 (host->data->flags & MMC_DATA_WRITE) 403 ? "write" : "read"); 404 host->data->error = -EIO; 405 mmc_davinci_xfer_done(host, host->data); 406 } 407 } 408 409 /* Set up tx or rx template, to be modified and updated later */ 410 static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host, 411 bool tx, struct edmacc_param *template) 412 { 413 unsigned sync_dev; 414 const u16 acnt = 4; 415 const u16 bcnt = rw_threshold >> 2; 416 const u16 ccnt = 0; 417 u32 src_port = 0; 418 u32 dst_port = 0; 419 s16 src_bidx, dst_bidx; 420 s16 src_cidx, dst_cidx; 421 422 /* 423 * A-B Sync transfer: each DMA request is for one "frame" of 424 * rw_threshold bytes, broken into "acnt"-size chunks repeated 425 * "bcnt" times. Each segment needs "ccnt" such frames; since 426 * we tell the block layer our mmc->max_seg_size limit, we can 427 * trust (later) that it's within bounds. 428 * 429 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and 430 * EDMA will optimize memory operations to use larger bursts. 431 */ 432 if (tx) { 433 sync_dev = host->txdma; 434 435 /* src_prt, ccnt, and link to be set up later */ 436 src_bidx = acnt; 437 src_cidx = acnt * bcnt; 438 439 dst_port = host->mem_res->start + DAVINCI_MMCDXR; 440 dst_bidx = 0; 441 dst_cidx = 0; 442 } else { 443 sync_dev = host->rxdma; 444 445 src_port = host->mem_res->start + DAVINCI_MMCDRR; 446 src_bidx = 0; 447 src_cidx = 0; 448 449 /* dst_prt, ccnt, and link to be set up later */ 450 dst_bidx = acnt; 451 dst_cidx = acnt * bcnt; 452 } 453 454 /* 455 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses 456 * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT 457 * parameter is ignored. 458 */ 459 edma_set_src(sync_dev, src_port, INCR, W8BIT); 460 edma_set_dest(sync_dev, dst_port, INCR, W8BIT); 461 462 edma_set_src_index(sync_dev, src_bidx, src_cidx); 463 edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); 464 465 edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); 466 467 edma_read_slot(sync_dev, template); 468 469 /* don't bother with irqs or chaining */ 470 template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; 471 } 472 473 static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 474 struct mmc_data *data) 475 { 476 struct edmacc_param *template; 477 int channel, slot; 478 unsigned link; 479 struct scatterlist *sg; 480 unsigned sg_len; 481 unsigned bytes_left = host->bytes_left; 482 const unsigned shift = ffs(rw_threshold) - 1;; 483 484 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 485 template = &host->tx_template; 486 channel = host->txdma; 487 } else { 488 template = &host->rx_template; 489 channel = host->rxdma; 490 } 491 492 /* We know sg_len and ccnt will never be out of range because 493 * we told the mmc layer which in turn tells the block layer 494 * to ensure that it only hands us one scatterlist segment 495 * per EDMA PARAM entry. Update the PARAM 496 * entries needed for each segment of this scatterlist. 497 */ 498 for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len; 499 sg_len-- != 0 && bytes_left; 500 sg = sg_next(sg), slot = host->links[link++]) { 501 u32 buf = sg_dma_address(sg); 502 unsigned count = sg_dma_len(sg); 503 504 template->link_bcntrld = sg_len 505 ? (EDMA_CHAN_SLOT(host->links[link]) << 5) 506 : 0xffff; 507 508 if (count > bytes_left) 509 count = bytes_left; 510 bytes_left -= count; 511 512 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 513 template->src = buf; 514 else 515 template->dst = buf; 516 template->ccnt = count >> shift; 517 518 edma_write_slot(slot, template); 519 } 520 521 if (host->version == MMC_CTLR_VERSION_2) 522 edma_clear_event(channel); 523 524 edma_start(channel); 525 } 526 527 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 528 struct mmc_data *data) 529 { 530 int i; 531 int mask = rw_threshold - 1; 532 533 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 534 ((data->flags & MMC_DATA_WRITE) 535 ? DMA_TO_DEVICE 536 : DMA_FROM_DEVICE)); 537 538 /* no individual DMA segment should need a partial FIFO */ 539 for (i = 0; i < host->sg_len; i++) { 540 if (sg_dma_len(data->sg + i) & mask) { 541 dma_unmap_sg(mmc_dev(host->mmc), 542 data->sg, data->sg_len, 543 (data->flags & MMC_DATA_WRITE) 544 ? DMA_TO_DEVICE 545 : DMA_FROM_DEVICE); 546 return -1; 547 } 548 } 549 550 host->do_dma = 1; 551 mmc_davinci_send_dma_request(host, data); 552 553 return 0; 554 } 555 556 static void __init_or_module 557 davinci_release_dma_channels(struct mmc_davinci_host *host) 558 { 559 unsigned i; 560 561 if (!host->use_dma) 562 return; 563 564 for (i = 0; i < host->n_link; i++) 565 edma_free_slot(host->links[i]); 566 567 edma_free_channel(host->txdma); 568 edma_free_channel(host->rxdma); 569 } 570 571 static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 572 { 573 u32 link_size; 574 int r, i; 575 576 /* Acquire master DMA write channel */ 577 r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host, 578 EVENTQ_DEFAULT); 579 if (r < 0) { 580 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 581 "tx", r); 582 return r; 583 } 584 mmc_davinci_dma_setup(host, true, &host->tx_template); 585 586 /* Acquire master DMA read channel */ 587 r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host, 588 EVENTQ_DEFAULT); 589 if (r < 0) { 590 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 591 "rx", r); 592 goto free_master_write; 593 } 594 mmc_davinci_dma_setup(host, false, &host->rx_template); 595 596 /* Allocate parameter RAM slots, which will later be bound to a 597 * channel as needed to handle a scatterlist. 598 */ 599 link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); 600 for (i = 0; i < link_size; i++) { 601 r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); 602 if (r < 0) { 603 dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n", 604 r); 605 break; 606 } 607 host->links[i] = r; 608 } 609 host->n_link = i; 610 611 return 0; 612 613 free_master_write: 614 edma_free_channel(host->txdma); 615 616 return r; 617 } 618 619 /*----------------------------------------------------------------------*/ 620 621 static void 622 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 623 { 624 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 625 int timeout; 626 struct mmc_data *data = req->data; 627 628 if (host->version == MMC_CTLR_VERSION_2) 629 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 630 631 host->data = data; 632 if (data == NULL) { 633 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 634 writel(0, host->base + DAVINCI_MMCBLEN); 635 writel(0, host->base + DAVINCI_MMCNBLK); 636 return; 637 } 638 639 dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n", 640 (data->flags & MMC_DATA_STREAM) ? "stream" : "block", 641 (data->flags & MMC_DATA_WRITE) ? "write" : "read", 642 data->blocks, data->blksz); 643 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 644 data->timeout_clks, data->timeout_ns); 645 timeout = data->timeout_clks + 646 (data->timeout_ns / host->ns_in_one_cycle); 647 if (timeout > 0xffff) 648 timeout = 0xffff; 649 650 writel(timeout, host->base + DAVINCI_MMCTOD); 651 writel(data->blocks, host->base + DAVINCI_MMCNBLK); 652 writel(data->blksz, host->base + DAVINCI_MMCBLEN); 653 654 /* Configure the FIFO */ 655 switch (data->flags & MMC_DATA_WRITE) { 656 case MMC_DATA_WRITE: 657 host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 658 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 659 host->base + DAVINCI_MMCFIFOCTL); 660 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 661 host->base + DAVINCI_MMCFIFOCTL); 662 break; 663 664 default: 665 host->data_dir = DAVINCI_MMC_DATADIR_READ; 666 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 667 host->base + DAVINCI_MMCFIFOCTL); 668 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 669 host->base + DAVINCI_MMCFIFOCTL); 670 break; 671 } 672 673 host->buffer = NULL; 674 host->bytes_left = data->blocks * data->blksz; 675 676 /* For now we try to use DMA whenever we won't need partial FIFO 677 * reads or writes, either for the whole transfer (as tested here) 678 * or for any individual scatterlist segment (tested when we call 679 * start_dma_transfer). 680 * 681 * While we *could* change that, unusual block sizes are rarely 682 * used. The occasional fallback to PIO should't hurt. 683 */ 684 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 685 && mmc_davinci_start_dma_transfer(host, data) == 0) { 686 /* zero this to ensure we take no PIO paths */ 687 host->bytes_left = 0; 688 } else { 689 /* Revert to CPU Copy */ 690 host->sg_len = data->sg_len; 691 host->sg = host->data->sg; 692 mmc_davinci_sg_to_buf(host); 693 } 694 } 695 696 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 697 { 698 struct mmc_davinci_host *host = mmc_priv(mmc); 699 unsigned long timeout = jiffies + msecs_to_jiffies(900); 700 u32 mmcst1 = 0; 701 702 /* Card may still be sending BUSY after a previous operation, 703 * typically some kind of write. If so, we can't proceed yet. 704 */ 705 while (time_before(jiffies, timeout)) { 706 mmcst1 = readl(host->base + DAVINCI_MMCST1); 707 if (!(mmcst1 & MMCST1_BUSY)) 708 break; 709 cpu_relax(); 710 } 711 if (mmcst1 & MMCST1_BUSY) { 712 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 713 req->cmd->error = -ETIMEDOUT; 714 mmc_request_done(mmc, req); 715 return; 716 } 717 718 host->do_dma = 0; 719 mmc_davinci_prepare_data(host, req); 720 mmc_davinci_start_command(host, req->cmd); 721 } 722 723 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 724 unsigned int mmc_req_freq) 725 { 726 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 727 728 mmc_pclk = host->mmc_input_clk; 729 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 730 mmc_push_pull_divisor = ((unsigned int)mmc_pclk 731 / (2 * mmc_req_freq)) - 1; 732 else 733 mmc_push_pull_divisor = 0; 734 735 mmc_freq = (unsigned int)mmc_pclk 736 / (2 * (mmc_push_pull_divisor + 1)); 737 738 if (mmc_freq > mmc_req_freq) 739 mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 740 /* Convert ns to clock cycles */ 741 if (mmc_req_freq <= 400000) 742 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 743 / (2 * (mmc_push_pull_divisor + 1)))/1000)); 744 else 745 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 746 / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 747 748 return mmc_push_pull_divisor; 749 } 750 751 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 752 { 753 unsigned int open_drain_freq = 0, mmc_pclk = 0; 754 unsigned int mmc_push_pull_freq = 0; 755 struct mmc_davinci_host *host = mmc_priv(mmc); 756 757 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 758 u32 temp; 759 760 /* Ignoring the init clock value passed for fixing the inter 761 * operability with different cards. 762 */ 763 open_drain_freq = ((unsigned int)mmc_pclk 764 / (2 * MMCSD_INIT_CLOCK)) - 1; 765 766 if (open_drain_freq > 0xFF) 767 open_drain_freq = 0xFF; 768 769 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 770 temp |= open_drain_freq; 771 writel(temp, host->base + DAVINCI_MMCCLK); 772 773 /* Convert ns to clock cycles */ 774 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 775 } else { 776 u32 temp; 777 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 778 779 if (mmc_push_pull_freq > 0xFF) 780 mmc_push_pull_freq = 0xFF; 781 782 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 783 writel(temp, host->base + DAVINCI_MMCCLK); 784 785 udelay(10); 786 787 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 788 temp |= mmc_push_pull_freq; 789 writel(temp, host->base + DAVINCI_MMCCLK); 790 791 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 792 793 udelay(10); 794 } 795 } 796 797 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 798 { 799 struct mmc_davinci_host *host = mmc_priv(mmc); 800 801 dev_dbg(mmc_dev(host->mmc), 802 "clock %dHz busmode %d powermode %d Vdd %04x\n", 803 ios->clock, ios->bus_mode, ios->power_mode, 804 ios->vdd); 805 806 switch (ios->bus_width) { 807 case MMC_BUS_WIDTH_8: 808 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 809 writel((readl(host->base + DAVINCI_MMCCTL) & 810 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 811 host->base + DAVINCI_MMCCTL); 812 break; 813 case MMC_BUS_WIDTH_4: 814 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 815 if (host->version == MMC_CTLR_VERSION_2) 816 writel((readl(host->base + DAVINCI_MMCCTL) & 817 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 818 host->base + DAVINCI_MMCCTL); 819 else 820 writel(readl(host->base + DAVINCI_MMCCTL) | 821 MMCCTL_WIDTH_4_BIT, 822 host->base + DAVINCI_MMCCTL); 823 break; 824 case MMC_BUS_WIDTH_1: 825 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 826 if (host->version == MMC_CTLR_VERSION_2) 827 writel(readl(host->base + DAVINCI_MMCCTL) & 828 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 829 host->base + DAVINCI_MMCCTL); 830 else 831 writel(readl(host->base + DAVINCI_MMCCTL) & 832 ~MMCCTL_WIDTH_4_BIT, 833 host->base + DAVINCI_MMCCTL); 834 break; 835 } 836 837 calculate_clk_divider(mmc, ios); 838 839 host->bus_mode = ios->bus_mode; 840 if (ios->power_mode == MMC_POWER_UP) { 841 unsigned long timeout = jiffies + msecs_to_jiffies(50); 842 bool lose = true; 843 844 /* Send clock cycles, poll completion */ 845 writel(0, host->base + DAVINCI_MMCARGHL); 846 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 847 while (time_before(jiffies, timeout)) { 848 u32 tmp = readl(host->base + DAVINCI_MMCST0); 849 850 if (tmp & MMCST0_RSPDNE) { 851 lose = false; 852 break; 853 } 854 cpu_relax(); 855 } 856 if (lose) 857 dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 858 } 859 860 /* FIXME on power OFF, reset things ... */ 861 } 862 863 static void 864 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 865 { 866 host->data = NULL; 867 868 if (host->do_dma) { 869 davinci_abort_dma(host); 870 871 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 872 (data->flags & MMC_DATA_WRITE) 873 ? DMA_TO_DEVICE 874 : DMA_FROM_DEVICE); 875 host->do_dma = false; 876 } 877 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 878 879 if (!data->stop || (host->cmd && host->cmd->error)) { 880 mmc_request_done(host->mmc, data->mrq); 881 writel(0, host->base + DAVINCI_MMCIM); 882 } else 883 mmc_davinci_start_command(host, data->stop); 884 } 885 886 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 887 struct mmc_command *cmd) 888 { 889 host->cmd = NULL; 890 891 if (cmd->flags & MMC_RSP_PRESENT) { 892 if (cmd->flags & MMC_RSP_136) { 893 /* response type 2 */ 894 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 895 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 896 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 897 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 898 } else { 899 /* response types 1, 1b, 3, 4, 5, 6 */ 900 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 901 } 902 } 903 904 if (host->data == NULL || cmd->error) { 905 if (cmd->error == -ETIMEDOUT) 906 cmd->mrq->cmd->retries = 0; 907 mmc_request_done(host->mmc, cmd->mrq); 908 writel(0, host->base + DAVINCI_MMCIM); 909 } 910 } 911 912 static void 913 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 914 { 915 u32 temp; 916 917 /* reset command and data state machines */ 918 temp = readl(host->base + DAVINCI_MMCCTL); 919 writel(temp | MMCCTL_CMDRST | MMCCTL_DATRST, 920 host->base + DAVINCI_MMCCTL); 921 922 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 923 udelay(10); 924 writel(temp, host->base + DAVINCI_MMCCTL); 925 } 926 927 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 928 { 929 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 930 unsigned int status, qstatus; 931 int end_command = 0; 932 int end_transfer = 0; 933 struct mmc_data *data = host->data; 934 935 if (host->cmd == NULL && host->data == NULL) { 936 status = readl(host->base + DAVINCI_MMCST0); 937 dev_dbg(mmc_dev(host->mmc), 938 "Spurious interrupt 0x%04x\n", status); 939 /* Disable the interrupt from mmcsd */ 940 writel(0, host->base + DAVINCI_MMCIM); 941 return IRQ_NONE; 942 } 943 944 status = readl(host->base + DAVINCI_MMCST0); 945 qstatus = status; 946 947 /* handle FIFO first when using PIO for data. 948 * bytes_left will decrease to zero as I/O progress and status will 949 * read zero over iteration because this controller status 950 * register(MMCST0) reports any status only once and it is cleared 951 * by read. So, it is not unbouned loop even in the case of 952 * non-dma. 953 */ 954 while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 955 davinci_fifo_data_trans(host, rw_threshold); 956 status = readl(host->base + DAVINCI_MMCST0); 957 if (!status) 958 break; 959 qstatus |= status; 960 } 961 962 if (qstatus & MMCST0_DATDNE) { 963 /* All blocks sent/received, and CRC checks passed */ 964 if (data != NULL) { 965 if ((host->do_dma == 0) && (host->bytes_left > 0)) { 966 /* if datasize < rw_threshold 967 * no RX ints are generated 968 */ 969 davinci_fifo_data_trans(host, host->bytes_left); 970 } 971 end_transfer = 1; 972 data->bytes_xfered = data->blocks * data->blksz; 973 } else { 974 dev_err(mmc_dev(host->mmc), 975 "DATDNE with no host->data\n"); 976 } 977 } 978 979 if (qstatus & MMCST0_TOUTRD) { 980 /* Read data timeout */ 981 data->error = -ETIMEDOUT; 982 end_transfer = 1; 983 984 dev_dbg(mmc_dev(host->mmc), 985 "read data timeout, status %x\n", 986 qstatus); 987 988 davinci_abort_data(host, data); 989 } 990 991 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 992 /* Data CRC error */ 993 data->error = -EILSEQ; 994 end_transfer = 1; 995 996 /* NOTE: this controller uses CRCWR to report both CRC 997 * errors and timeouts (on writes). MMCDRSP values are 998 * only weakly documented, but 0x9f was clearly a timeout 999 * case and the two three-bit patterns in various SD specs 1000 * (101, 010) aren't part of it ... 1001 */ 1002 if (qstatus & MMCST0_CRCWR) { 1003 u32 temp = readb(host->base + DAVINCI_MMCDRSP); 1004 1005 if (temp == 0x9f) 1006 data->error = -ETIMEDOUT; 1007 } 1008 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 1009 (qstatus & MMCST0_CRCWR) ? "write" : "read", 1010 (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 1011 1012 davinci_abort_data(host, data); 1013 } 1014 1015 if (qstatus & MMCST0_TOUTRS) { 1016 /* Command timeout */ 1017 if (host->cmd) { 1018 dev_dbg(mmc_dev(host->mmc), 1019 "CMD%d timeout, status %x\n", 1020 host->cmd->opcode, qstatus); 1021 host->cmd->error = -ETIMEDOUT; 1022 if (data) { 1023 end_transfer = 1; 1024 davinci_abort_data(host, data); 1025 } else 1026 end_command = 1; 1027 } 1028 } 1029 1030 if (qstatus & MMCST0_CRCRS) { 1031 /* Command CRC error */ 1032 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1033 if (host->cmd) { 1034 host->cmd->error = -EILSEQ; 1035 end_command = 1; 1036 } 1037 } 1038 1039 if (qstatus & MMCST0_RSPDNE) { 1040 /* End of command phase */ 1041 end_command = (int) host->cmd; 1042 } 1043 1044 if (end_command) 1045 mmc_davinci_cmd_done(host, host->cmd); 1046 if (end_transfer) 1047 mmc_davinci_xfer_done(host, data); 1048 return IRQ_HANDLED; 1049 } 1050 1051 static int mmc_davinci_get_cd(struct mmc_host *mmc) 1052 { 1053 struct platform_device *pdev = to_platform_device(mmc->parent); 1054 struct davinci_mmc_config *config = pdev->dev.platform_data; 1055 1056 if (!config || !config->get_cd) 1057 return -ENOSYS; 1058 return config->get_cd(pdev->id); 1059 } 1060 1061 static int mmc_davinci_get_ro(struct mmc_host *mmc) 1062 { 1063 struct platform_device *pdev = to_platform_device(mmc->parent); 1064 struct davinci_mmc_config *config = pdev->dev.platform_data; 1065 1066 if (!config || !config->get_ro) 1067 return -ENOSYS; 1068 return config->get_ro(pdev->id); 1069 } 1070 1071 static struct mmc_host_ops mmc_davinci_ops = { 1072 .request = mmc_davinci_request, 1073 .set_ios = mmc_davinci_set_ios, 1074 .get_cd = mmc_davinci_get_cd, 1075 .get_ro = mmc_davinci_get_ro, 1076 }; 1077 1078 /*----------------------------------------------------------------------*/ 1079 1080 #ifdef CONFIG_CPU_FREQ 1081 static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 1082 unsigned long val, void *data) 1083 { 1084 struct mmc_davinci_host *host; 1085 unsigned int mmc_pclk; 1086 struct mmc_host *mmc; 1087 unsigned long flags; 1088 1089 host = container_of(nb, struct mmc_davinci_host, freq_transition); 1090 mmc = host->mmc; 1091 mmc_pclk = clk_get_rate(host->clk); 1092 1093 if (val == CPUFREQ_POSTCHANGE) { 1094 spin_lock_irqsave(&mmc->lock, flags); 1095 host->mmc_input_clk = mmc_pclk; 1096 calculate_clk_divider(mmc, &mmc->ios); 1097 spin_unlock_irqrestore(&mmc->lock, flags); 1098 } 1099 1100 return 0; 1101 } 1102 1103 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1104 { 1105 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 1106 1107 return cpufreq_register_notifier(&host->freq_transition, 1108 CPUFREQ_TRANSITION_NOTIFIER); 1109 } 1110 1111 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1112 { 1113 cpufreq_unregister_notifier(&host->freq_transition, 1114 CPUFREQ_TRANSITION_NOTIFIER); 1115 } 1116 #else 1117 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1118 { 1119 return 0; 1120 } 1121 1122 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1123 { 1124 } 1125 #endif 1126 static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1127 { 1128 /* DAT line portion is diabled and in reset state */ 1129 writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_DATRST, 1130 host->base + DAVINCI_MMCCTL); 1131 1132 /* CMD line portion is diabled and in reset state */ 1133 writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_CMDRST, 1134 host->base + DAVINCI_MMCCTL); 1135 1136 udelay(10); 1137 1138 writel(0, host->base + DAVINCI_MMCCLK); 1139 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1140 1141 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1142 writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1143 1144 writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_DATRST, 1145 host->base + DAVINCI_MMCCTL); 1146 writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_CMDRST, 1147 host->base + DAVINCI_MMCCTL); 1148 1149 udelay(10); 1150 } 1151 1152 static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1153 { 1154 struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1155 struct mmc_davinci_host *host = NULL; 1156 struct mmc_host *mmc = NULL; 1157 struct resource *r, *mem = NULL; 1158 int ret = 0, irq = 0; 1159 size_t mem_size; 1160 1161 /* REVISIT: when we're fully converted, fail if pdata is NULL */ 1162 1163 ret = -ENODEV; 1164 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1165 irq = platform_get_irq(pdev, 0); 1166 if (!r || irq == NO_IRQ) 1167 goto out; 1168 1169 ret = -EBUSY; 1170 mem_size = resource_size(r); 1171 mem = request_mem_region(r->start, mem_size, pdev->name); 1172 if (!mem) 1173 goto out; 1174 1175 ret = -ENOMEM; 1176 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1177 if (!mmc) 1178 goto out; 1179 1180 host = mmc_priv(mmc); 1181 host->mmc = mmc; /* Important */ 1182 1183 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1184 if (!r) 1185 goto out; 1186 host->rxdma = r->start; 1187 1188 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1189 if (!r) 1190 goto out; 1191 host->txdma = r->start; 1192 1193 host->mem_res = mem; 1194 host->base = ioremap(mem->start, mem_size); 1195 if (!host->base) 1196 goto out; 1197 1198 ret = -ENXIO; 1199 host->clk = clk_get(&pdev->dev, "MMCSDCLK"); 1200 if (IS_ERR(host->clk)) { 1201 ret = PTR_ERR(host->clk); 1202 goto out; 1203 } 1204 clk_enable(host->clk); 1205 host->mmc_input_clk = clk_get_rate(host->clk); 1206 1207 init_mmcsd_host(host); 1208 1209 if (pdata->nr_sg) 1210 host->nr_sg = pdata->nr_sg - 1; 1211 1212 if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1213 host->nr_sg = MAX_NR_SG; 1214 1215 host->use_dma = use_dma; 1216 host->irq = irq; 1217 1218 if (host->use_dma && davinci_acquire_dma_channels(host) != 0) 1219 host->use_dma = 0; 1220 1221 /* REVISIT: someday, support IRQ-driven card detection. */ 1222 mmc->caps |= MMC_CAP_NEEDS_POLL; 1223 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1224 1225 if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1226 mmc->caps |= MMC_CAP_4_BIT_DATA; 1227 1228 if (pdata && (pdata->wires == 8)) 1229 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1230 1231 host->version = pdata->version; 1232 1233 mmc->ops = &mmc_davinci_ops; 1234 mmc->f_min = 312500; 1235 mmc->f_max = 25000000; 1236 if (pdata && pdata->max_freq) 1237 mmc->f_max = pdata->max_freq; 1238 if (pdata && pdata->caps) 1239 mmc->caps |= pdata->caps; 1240 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1241 1242 /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1243 * Each hw_seg uses one EDMA parameter RAM slot, always one 1244 * channel and then usually some linked slots. 1245 */ 1246 mmc->max_hw_segs = 1 + host->n_link; 1247 mmc->max_phys_segs = mmc->max_hw_segs; 1248 1249 /* EDMA limit per hw segment (one or two MBytes) */ 1250 mmc->max_seg_size = MAX_CCNT * rw_threshold; 1251 1252 /* MMC/SD controller limits for multiblock requests */ 1253 mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1254 mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1255 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1256 1257 dev_dbg(mmc_dev(host->mmc), "max_phys_segs=%d\n", mmc->max_phys_segs); 1258 dev_dbg(mmc_dev(host->mmc), "max_hw_segs=%d\n", mmc->max_hw_segs); 1259 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1260 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1261 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1262 1263 platform_set_drvdata(pdev, host); 1264 1265 ret = mmc_davinci_cpufreq_register(host); 1266 if (ret) { 1267 dev_err(&pdev->dev, "failed to register cpufreq\n"); 1268 goto cpu_freq_fail; 1269 } 1270 1271 ret = mmc_add_host(mmc); 1272 if (ret < 0) 1273 goto out; 1274 1275 ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host); 1276 if (ret) 1277 goto out; 1278 1279 rename_region(mem, mmc_hostname(mmc)); 1280 1281 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1282 host->use_dma ? "DMA" : "PIO", 1283 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1284 1285 return 0; 1286 1287 out: 1288 mmc_davinci_cpufreq_deregister(host); 1289 cpu_freq_fail: 1290 if (host) { 1291 davinci_release_dma_channels(host); 1292 1293 if (host->clk) { 1294 clk_disable(host->clk); 1295 clk_put(host->clk); 1296 } 1297 1298 if (host->base) 1299 iounmap(host->base); 1300 } 1301 1302 if (mmc) 1303 mmc_free_host(mmc); 1304 1305 if (mem) 1306 release_resource(mem); 1307 1308 dev_dbg(&pdev->dev, "probe err %d\n", ret); 1309 1310 return ret; 1311 } 1312 1313 static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1314 { 1315 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1316 1317 platform_set_drvdata(pdev, NULL); 1318 if (host) { 1319 mmc_davinci_cpufreq_deregister(host); 1320 1321 mmc_remove_host(host->mmc); 1322 free_irq(host->irq, host); 1323 1324 davinci_release_dma_channels(host); 1325 1326 clk_disable(host->clk); 1327 clk_put(host->clk); 1328 1329 iounmap(host->base); 1330 1331 release_resource(host->mem_res); 1332 1333 mmc_free_host(host->mmc); 1334 } 1335 1336 return 0; 1337 } 1338 1339 #ifdef CONFIG_PM 1340 static int davinci_mmcsd_suspend(struct platform_device *pdev, pm_message_t msg) 1341 { 1342 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1343 1344 return mmc_suspend_host(host->mmc, msg); 1345 } 1346 1347 static int davinci_mmcsd_resume(struct platform_device *pdev) 1348 { 1349 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1350 1351 return mmc_resume_host(host->mmc); 1352 } 1353 #else 1354 #define davinci_mmcsd_suspend NULL 1355 #define davinci_mmcsd_resume NULL 1356 #endif 1357 1358 static struct platform_driver davinci_mmcsd_driver = { 1359 .driver = { 1360 .name = "davinci_mmc", 1361 .owner = THIS_MODULE, 1362 }, 1363 .remove = __exit_p(davinci_mmcsd_remove), 1364 .suspend = davinci_mmcsd_suspend, 1365 .resume = davinci_mmcsd_resume, 1366 }; 1367 1368 static int __init davinci_mmcsd_init(void) 1369 { 1370 return platform_driver_probe(&davinci_mmcsd_driver, 1371 davinci_mmcsd_probe); 1372 } 1373 module_init(davinci_mmcsd_init); 1374 1375 static void __exit davinci_mmcsd_exit(void) 1376 { 1377 platform_driver_unregister(&davinci_mmcsd_driver); 1378 } 1379 module_exit(davinci_mmcsd_exit); 1380 1381 MODULE_AUTHOR("Texas Instruments India"); 1382 MODULE_LICENSE("GPL"); 1383 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 1384 1385