1 /* 2 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Original author: Purushotam Kumar 6 * Copyright (C) 2009 David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/ioport.h> 25 #include <linux/platform_device.h> 26 #include <linux/clk.h> 27 #include <linux/err.h> 28 #include <linux/cpufreq.h> 29 #include <linux/mmc/host.h> 30 #include <linux/io.h> 31 #include <linux/irq.h> 32 #include <linux/delay.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/mmc/mmc.h> 35 36 #include <mach/mmc.h> 37 #include <mach/edma.h> 38 39 /* 40 * Register Definitions 41 */ 42 #define DAVINCI_MMCCTL 0x00 /* Control Register */ 43 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 44 #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 45 #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 46 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 47 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 48 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 49 #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 50 #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 51 #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 52 #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 53 #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 54 #define DAVINCI_MMCCMD 0x30 /* Command Register */ 55 #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 56 #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 57 #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 58 #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 59 #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 60 #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 61 #define DAVINCI_MMCETOK 0x4C 62 #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 63 #define DAVINCI_MMCCKC 0x54 64 #define DAVINCI_MMCTORC 0x58 65 #define DAVINCI_MMCTODC 0x5C 66 #define DAVINCI_MMCBLNC 0x60 67 #define DAVINCI_SDIOCTL 0x64 68 #define DAVINCI_SDIOST0 0x68 69 #define DAVINCI_SDIOEN 0x6C 70 #define DAVINCI_SDIOST 0x70 71 #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 72 73 /* DAVINCI_MMCCTL definitions */ 74 #define MMCCTL_DATRST (1 << 0) 75 #define MMCCTL_CMDRST (1 << 1) 76 #define MMCCTL_WIDTH_8_BIT (1 << 8) 77 #define MMCCTL_WIDTH_4_BIT (1 << 2) 78 #define MMCCTL_DATEG_DISABLED (0 << 6) 79 #define MMCCTL_DATEG_RISING (1 << 6) 80 #define MMCCTL_DATEG_FALLING (2 << 6) 81 #define MMCCTL_DATEG_BOTH (3 << 6) 82 #define MMCCTL_PERMDR_LE (0 << 9) 83 #define MMCCTL_PERMDR_BE (1 << 9) 84 #define MMCCTL_PERMDX_LE (0 << 10) 85 #define MMCCTL_PERMDX_BE (1 << 10) 86 87 /* DAVINCI_MMCCLK definitions */ 88 #define MMCCLK_CLKEN (1 << 8) 89 #define MMCCLK_CLKRT_MASK (0xFF << 0) 90 91 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 92 #define MMCST0_DATDNE BIT(0) /* data done */ 93 #define MMCST0_BSYDNE BIT(1) /* busy done */ 94 #define MMCST0_RSPDNE BIT(2) /* command done */ 95 #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 96 #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 97 #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 98 #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 99 #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 100 #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 101 #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 102 #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 103 #define MMCST0_TRNDNE BIT(12) /* transfer done */ 104 105 /* DAVINCI_MMCST1 definitions */ 106 #define MMCST1_BUSY (1 << 0) 107 108 /* DAVINCI_MMCCMD definitions */ 109 #define MMCCMD_CMD_MASK (0x3F << 0) 110 #define MMCCMD_PPLEN (1 << 7) 111 #define MMCCMD_BSYEXP (1 << 8) 112 #define MMCCMD_RSPFMT_MASK (3 << 9) 113 #define MMCCMD_RSPFMT_NONE (0 << 9) 114 #define MMCCMD_RSPFMT_R1456 (1 << 9) 115 #define MMCCMD_RSPFMT_R2 (2 << 9) 116 #define MMCCMD_RSPFMT_R3 (3 << 9) 117 #define MMCCMD_DTRW (1 << 11) 118 #define MMCCMD_STRMTP (1 << 12) 119 #define MMCCMD_WDATX (1 << 13) 120 #define MMCCMD_INITCK (1 << 14) 121 #define MMCCMD_DCLR (1 << 15) 122 #define MMCCMD_DMATRIG (1 << 16) 123 124 /* DAVINCI_MMCFIFOCTL definitions */ 125 #define MMCFIFOCTL_FIFORST (1 << 0) 126 #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 127 #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 128 #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 129 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 130 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 131 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 132 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 133 134 135 /* MMCSD Init clock in Hz in opendrain mode */ 136 #define MMCSD_INIT_CLOCK 200000 137 138 /* 139 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 140 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 141 * for drivers with max_segs == 1, making the segments bigger (64KB) 142 * than the page or two that's otherwise typical. nr_sg (passed from 143 * platform data) == 16 gives at least the same throughput boost, using 144 * EDMA transfer linkage instead of spending CPU time copying pages. 145 */ 146 #define MAX_CCNT ((1 << 16) - 1) 147 148 #define MAX_NR_SG 16 149 150 static unsigned rw_threshold = 32; 151 module_param(rw_threshold, uint, S_IRUGO); 152 MODULE_PARM_DESC(rw_threshold, 153 "Read/Write threshold. Default = 32"); 154 155 static unsigned __initdata use_dma = 1; 156 module_param(use_dma, uint, 0); 157 MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 158 159 struct mmc_davinci_host { 160 struct mmc_command *cmd; 161 struct mmc_data *data; 162 struct mmc_host *mmc; 163 struct clk *clk; 164 unsigned int mmc_input_clk; 165 void __iomem *base; 166 struct resource *mem_res; 167 int irq; 168 unsigned char bus_mode; 169 170 #define DAVINCI_MMC_DATADIR_NONE 0 171 #define DAVINCI_MMC_DATADIR_READ 1 172 #define DAVINCI_MMC_DATADIR_WRITE 2 173 unsigned char data_dir; 174 unsigned char suspended; 175 176 /* buffer is used during PIO of one scatterlist segment, and 177 * is updated along with buffer_bytes_left. bytes_left applies 178 * to all N blocks of the PIO transfer. 179 */ 180 u8 *buffer; 181 u32 buffer_bytes_left; 182 u32 bytes_left; 183 184 u32 rxdma, txdma; 185 bool use_dma; 186 bool do_dma; 187 188 /* Scatterlist DMA uses one or more parameter RAM entries: 189 * the main one (associated with rxdma or txdma) plus zero or 190 * more links. The entries for a given transfer differ only 191 * by memory buffer (address, length) and link field. 192 */ 193 struct edmacc_param tx_template; 194 struct edmacc_param rx_template; 195 unsigned n_link; 196 u32 links[MAX_NR_SG - 1]; 197 198 /* For PIO we walk scatterlists one segment at a time. */ 199 unsigned int sg_len; 200 struct scatterlist *sg; 201 202 /* Version of the MMC/SD controller */ 203 u8 version; 204 /* for ns in one cycle calculation */ 205 unsigned ns_in_one_cycle; 206 /* Number of sg segments */ 207 u8 nr_sg; 208 #ifdef CONFIG_CPU_FREQ 209 struct notifier_block freq_transition; 210 #endif 211 }; 212 213 214 /* PIO only */ 215 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 216 { 217 host->buffer_bytes_left = sg_dma_len(host->sg); 218 host->buffer = sg_virt(host->sg); 219 if (host->buffer_bytes_left > host->bytes_left) 220 host->buffer_bytes_left = host->bytes_left; 221 } 222 223 static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 224 unsigned int n) 225 { 226 u8 *p; 227 unsigned int i; 228 229 if (host->buffer_bytes_left == 0) { 230 host->sg = sg_next(host->data->sg); 231 mmc_davinci_sg_to_buf(host); 232 } 233 234 p = host->buffer; 235 if (n > host->buffer_bytes_left) 236 n = host->buffer_bytes_left; 237 host->buffer_bytes_left -= n; 238 host->bytes_left -= n; 239 240 /* NOTE: we never transfer more than rw_threshold bytes 241 * to/from the fifo here; there's no I/O overlap. 242 * This also assumes that access width( i.e. ACCWD) is 4 bytes 243 */ 244 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 245 for (i = 0; i < (n >> 2); i++) { 246 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 247 p = p + 4; 248 } 249 if (n & 3) { 250 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 251 p = p + (n & 3); 252 } 253 } else { 254 for (i = 0; i < (n >> 2); i++) { 255 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 256 p = p + 4; 257 } 258 if (n & 3) { 259 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 260 p = p + (n & 3); 261 } 262 } 263 host->buffer = p; 264 } 265 266 static void mmc_davinci_start_command(struct mmc_davinci_host *host, 267 struct mmc_command *cmd) 268 { 269 u32 cmd_reg = 0; 270 u32 im_val; 271 272 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 273 cmd->opcode, cmd->arg, 274 ({ char *s; 275 switch (mmc_resp_type(cmd)) { 276 case MMC_RSP_R1: 277 s = ", R1/R5/R6/R7 response"; 278 break; 279 case MMC_RSP_R1B: 280 s = ", R1b response"; 281 break; 282 case MMC_RSP_R2: 283 s = ", R2 response"; 284 break; 285 case MMC_RSP_R3: 286 s = ", R3/R4 response"; 287 break; 288 default: 289 s = ", (R? response)"; 290 break; 291 }; s; })); 292 host->cmd = cmd; 293 294 switch (mmc_resp_type(cmd)) { 295 case MMC_RSP_R1B: 296 /* There's some spec confusion about when R1B is 297 * allowed, but if the card doesn't issue a BUSY 298 * then it's harmless for us to allow it. 299 */ 300 cmd_reg |= MMCCMD_BSYEXP; 301 /* FALLTHROUGH */ 302 case MMC_RSP_R1: /* 48 bits, CRC */ 303 cmd_reg |= MMCCMD_RSPFMT_R1456; 304 break; 305 case MMC_RSP_R2: /* 136 bits, CRC */ 306 cmd_reg |= MMCCMD_RSPFMT_R2; 307 break; 308 case MMC_RSP_R3: /* 48 bits, no CRC */ 309 cmd_reg |= MMCCMD_RSPFMT_R3; 310 break; 311 default: 312 cmd_reg |= MMCCMD_RSPFMT_NONE; 313 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 314 mmc_resp_type(cmd)); 315 break; 316 } 317 318 /* Set command index */ 319 cmd_reg |= cmd->opcode; 320 321 /* Enable EDMA transfer triggers */ 322 if (host->do_dma) 323 cmd_reg |= MMCCMD_DMATRIG; 324 325 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 326 host->data_dir == DAVINCI_MMC_DATADIR_READ) 327 cmd_reg |= MMCCMD_DMATRIG; 328 329 /* Setting whether command involves data transfer or not */ 330 if (cmd->data) 331 cmd_reg |= MMCCMD_WDATX; 332 333 /* Setting whether stream or block transfer */ 334 if (cmd->flags & MMC_DATA_STREAM) 335 cmd_reg |= MMCCMD_STRMTP; 336 337 /* Setting whether data read or write */ 338 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 339 cmd_reg |= MMCCMD_DTRW; 340 341 if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 342 cmd_reg |= MMCCMD_PPLEN; 343 344 /* set Command timeout */ 345 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 346 347 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 348 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 349 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 350 im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 351 352 if (!host->do_dma) 353 im_val |= MMCST0_DXRDY; 354 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 355 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 356 357 if (!host->do_dma) 358 im_val |= MMCST0_DRRDY; 359 } 360 361 /* 362 * Before non-DMA WRITE commands the controller needs priming: 363 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 364 */ 365 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 366 davinci_fifo_data_trans(host, rw_threshold); 367 368 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 369 writel(cmd_reg, host->base + DAVINCI_MMCCMD); 370 writel(im_val, host->base + DAVINCI_MMCIM); 371 } 372 373 /*----------------------------------------------------------------------*/ 374 375 /* DMA infrastructure */ 376 377 static void davinci_abort_dma(struct mmc_davinci_host *host) 378 { 379 int sync_dev; 380 381 if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 382 sync_dev = host->rxdma; 383 else 384 sync_dev = host->txdma; 385 386 edma_stop(sync_dev); 387 edma_clean_channel(sync_dev); 388 } 389 390 static void 391 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data); 392 393 static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data) 394 { 395 if (DMA_COMPLETE != ch_status) { 396 struct mmc_davinci_host *host = data; 397 398 /* Currently means: DMA Event Missed, or "null" transfer 399 * request was seen. In the future, TC errors (like bad 400 * addresses) might be presented too. 401 */ 402 dev_warn(mmc_dev(host->mmc), "DMA %s error\n", 403 (host->data->flags & MMC_DATA_WRITE) 404 ? "write" : "read"); 405 host->data->error = -EIO; 406 mmc_davinci_xfer_done(host, host->data); 407 } 408 } 409 410 /* Set up tx or rx template, to be modified and updated later */ 411 static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host, 412 bool tx, struct edmacc_param *template) 413 { 414 unsigned sync_dev; 415 const u16 acnt = 4; 416 const u16 bcnt = rw_threshold >> 2; 417 const u16 ccnt = 0; 418 u32 src_port = 0; 419 u32 dst_port = 0; 420 s16 src_bidx, dst_bidx; 421 s16 src_cidx, dst_cidx; 422 423 /* 424 * A-B Sync transfer: each DMA request is for one "frame" of 425 * rw_threshold bytes, broken into "acnt"-size chunks repeated 426 * "bcnt" times. Each segment needs "ccnt" such frames; since 427 * we tell the block layer our mmc->max_seg_size limit, we can 428 * trust (later) that it's within bounds. 429 * 430 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and 431 * EDMA will optimize memory operations to use larger bursts. 432 */ 433 if (tx) { 434 sync_dev = host->txdma; 435 436 /* src_prt, ccnt, and link to be set up later */ 437 src_bidx = acnt; 438 src_cidx = acnt * bcnt; 439 440 dst_port = host->mem_res->start + DAVINCI_MMCDXR; 441 dst_bidx = 0; 442 dst_cidx = 0; 443 } else { 444 sync_dev = host->rxdma; 445 446 src_port = host->mem_res->start + DAVINCI_MMCDRR; 447 src_bidx = 0; 448 src_cidx = 0; 449 450 /* dst_prt, ccnt, and link to be set up later */ 451 dst_bidx = acnt; 452 dst_cidx = acnt * bcnt; 453 } 454 455 /* 456 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses 457 * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT 458 * parameter is ignored. 459 */ 460 edma_set_src(sync_dev, src_port, INCR, W8BIT); 461 edma_set_dest(sync_dev, dst_port, INCR, W8BIT); 462 463 edma_set_src_index(sync_dev, src_bidx, src_cidx); 464 edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); 465 466 edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); 467 468 edma_read_slot(sync_dev, template); 469 470 /* don't bother with irqs or chaining */ 471 template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; 472 } 473 474 static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 475 struct mmc_data *data) 476 { 477 struct edmacc_param *template; 478 int channel, slot; 479 unsigned link; 480 struct scatterlist *sg; 481 unsigned sg_len; 482 unsigned bytes_left = host->bytes_left; 483 const unsigned shift = ffs(rw_threshold) - 1;; 484 485 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 486 template = &host->tx_template; 487 channel = host->txdma; 488 } else { 489 template = &host->rx_template; 490 channel = host->rxdma; 491 } 492 493 /* We know sg_len and ccnt will never be out of range because 494 * we told the mmc layer which in turn tells the block layer 495 * to ensure that it only hands us one scatterlist segment 496 * per EDMA PARAM entry. Update the PARAM 497 * entries needed for each segment of this scatterlist. 498 */ 499 for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len; 500 sg_len-- != 0 && bytes_left; 501 sg = sg_next(sg), slot = host->links[link++]) { 502 u32 buf = sg_dma_address(sg); 503 unsigned count = sg_dma_len(sg); 504 505 template->link_bcntrld = sg_len 506 ? (EDMA_CHAN_SLOT(host->links[link]) << 5) 507 : 0xffff; 508 509 if (count > bytes_left) 510 count = bytes_left; 511 bytes_left -= count; 512 513 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 514 template->src = buf; 515 else 516 template->dst = buf; 517 template->ccnt = count >> shift; 518 519 edma_write_slot(slot, template); 520 } 521 522 if (host->version == MMC_CTLR_VERSION_2) 523 edma_clear_event(channel); 524 525 edma_start(channel); 526 } 527 528 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 529 struct mmc_data *data) 530 { 531 int i; 532 int mask = rw_threshold - 1; 533 534 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 535 ((data->flags & MMC_DATA_WRITE) 536 ? DMA_TO_DEVICE 537 : DMA_FROM_DEVICE)); 538 539 /* no individual DMA segment should need a partial FIFO */ 540 for (i = 0; i < host->sg_len; i++) { 541 if (sg_dma_len(data->sg + i) & mask) { 542 dma_unmap_sg(mmc_dev(host->mmc), 543 data->sg, data->sg_len, 544 (data->flags & MMC_DATA_WRITE) 545 ? DMA_TO_DEVICE 546 : DMA_FROM_DEVICE); 547 return -1; 548 } 549 } 550 551 host->do_dma = 1; 552 mmc_davinci_send_dma_request(host, data); 553 554 return 0; 555 } 556 557 static void __init_or_module 558 davinci_release_dma_channels(struct mmc_davinci_host *host) 559 { 560 unsigned i; 561 562 if (!host->use_dma) 563 return; 564 565 for (i = 0; i < host->n_link; i++) 566 edma_free_slot(host->links[i]); 567 568 edma_free_channel(host->txdma); 569 edma_free_channel(host->rxdma); 570 } 571 572 static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 573 { 574 u32 link_size; 575 int r, i; 576 577 /* Acquire master DMA write channel */ 578 r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host, 579 EVENTQ_DEFAULT); 580 if (r < 0) { 581 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 582 "tx", r); 583 return r; 584 } 585 mmc_davinci_dma_setup(host, true, &host->tx_template); 586 587 /* Acquire master DMA read channel */ 588 r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host, 589 EVENTQ_DEFAULT); 590 if (r < 0) { 591 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 592 "rx", r); 593 goto free_master_write; 594 } 595 mmc_davinci_dma_setup(host, false, &host->rx_template); 596 597 /* Allocate parameter RAM slots, which will later be bound to a 598 * channel as needed to handle a scatterlist. 599 */ 600 link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); 601 for (i = 0; i < link_size; i++) { 602 r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); 603 if (r < 0) { 604 dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n", 605 r); 606 break; 607 } 608 host->links[i] = r; 609 } 610 host->n_link = i; 611 612 return 0; 613 614 free_master_write: 615 edma_free_channel(host->txdma); 616 617 return r; 618 } 619 620 /*----------------------------------------------------------------------*/ 621 622 static void 623 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 624 { 625 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 626 int timeout; 627 struct mmc_data *data = req->data; 628 629 if (host->version == MMC_CTLR_VERSION_2) 630 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 631 632 host->data = data; 633 if (data == NULL) { 634 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 635 writel(0, host->base + DAVINCI_MMCBLEN); 636 writel(0, host->base + DAVINCI_MMCNBLK); 637 return; 638 } 639 640 dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n", 641 (data->flags & MMC_DATA_STREAM) ? "stream" : "block", 642 (data->flags & MMC_DATA_WRITE) ? "write" : "read", 643 data->blocks, data->blksz); 644 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 645 data->timeout_clks, data->timeout_ns); 646 timeout = data->timeout_clks + 647 (data->timeout_ns / host->ns_in_one_cycle); 648 if (timeout > 0xffff) 649 timeout = 0xffff; 650 651 writel(timeout, host->base + DAVINCI_MMCTOD); 652 writel(data->blocks, host->base + DAVINCI_MMCNBLK); 653 writel(data->blksz, host->base + DAVINCI_MMCBLEN); 654 655 /* Configure the FIFO */ 656 switch (data->flags & MMC_DATA_WRITE) { 657 case MMC_DATA_WRITE: 658 host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 659 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 660 host->base + DAVINCI_MMCFIFOCTL); 661 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 662 host->base + DAVINCI_MMCFIFOCTL); 663 break; 664 665 default: 666 host->data_dir = DAVINCI_MMC_DATADIR_READ; 667 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 668 host->base + DAVINCI_MMCFIFOCTL); 669 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 670 host->base + DAVINCI_MMCFIFOCTL); 671 break; 672 } 673 674 host->buffer = NULL; 675 host->bytes_left = data->blocks * data->blksz; 676 677 /* For now we try to use DMA whenever we won't need partial FIFO 678 * reads or writes, either for the whole transfer (as tested here) 679 * or for any individual scatterlist segment (tested when we call 680 * start_dma_transfer). 681 * 682 * While we *could* change that, unusual block sizes are rarely 683 * used. The occasional fallback to PIO should't hurt. 684 */ 685 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 686 && mmc_davinci_start_dma_transfer(host, data) == 0) { 687 /* zero this to ensure we take no PIO paths */ 688 host->bytes_left = 0; 689 } else { 690 /* Revert to CPU Copy */ 691 host->sg_len = data->sg_len; 692 host->sg = host->data->sg; 693 mmc_davinci_sg_to_buf(host); 694 } 695 } 696 697 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 698 { 699 struct mmc_davinci_host *host = mmc_priv(mmc); 700 unsigned long timeout = jiffies + msecs_to_jiffies(900); 701 u32 mmcst1 = 0; 702 703 /* Card may still be sending BUSY after a previous operation, 704 * typically some kind of write. If so, we can't proceed yet. 705 */ 706 while (time_before(jiffies, timeout)) { 707 mmcst1 = readl(host->base + DAVINCI_MMCST1); 708 if (!(mmcst1 & MMCST1_BUSY)) 709 break; 710 cpu_relax(); 711 } 712 if (mmcst1 & MMCST1_BUSY) { 713 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 714 req->cmd->error = -ETIMEDOUT; 715 mmc_request_done(mmc, req); 716 return; 717 } 718 719 host->do_dma = 0; 720 mmc_davinci_prepare_data(host, req); 721 mmc_davinci_start_command(host, req->cmd); 722 } 723 724 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 725 unsigned int mmc_req_freq) 726 { 727 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 728 729 mmc_pclk = host->mmc_input_clk; 730 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 731 mmc_push_pull_divisor = ((unsigned int)mmc_pclk 732 / (2 * mmc_req_freq)) - 1; 733 else 734 mmc_push_pull_divisor = 0; 735 736 mmc_freq = (unsigned int)mmc_pclk 737 / (2 * (mmc_push_pull_divisor + 1)); 738 739 if (mmc_freq > mmc_req_freq) 740 mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 741 /* Convert ns to clock cycles */ 742 if (mmc_req_freq <= 400000) 743 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 744 / (2 * (mmc_push_pull_divisor + 1)))/1000)); 745 else 746 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 747 / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 748 749 return mmc_push_pull_divisor; 750 } 751 752 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 753 { 754 unsigned int open_drain_freq = 0, mmc_pclk = 0; 755 unsigned int mmc_push_pull_freq = 0; 756 struct mmc_davinci_host *host = mmc_priv(mmc); 757 758 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 759 u32 temp; 760 761 /* Ignoring the init clock value passed for fixing the inter 762 * operability with different cards. 763 */ 764 open_drain_freq = ((unsigned int)mmc_pclk 765 / (2 * MMCSD_INIT_CLOCK)) - 1; 766 767 if (open_drain_freq > 0xFF) 768 open_drain_freq = 0xFF; 769 770 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 771 temp |= open_drain_freq; 772 writel(temp, host->base + DAVINCI_MMCCLK); 773 774 /* Convert ns to clock cycles */ 775 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 776 } else { 777 u32 temp; 778 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 779 780 if (mmc_push_pull_freq > 0xFF) 781 mmc_push_pull_freq = 0xFF; 782 783 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 784 writel(temp, host->base + DAVINCI_MMCCLK); 785 786 udelay(10); 787 788 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 789 temp |= mmc_push_pull_freq; 790 writel(temp, host->base + DAVINCI_MMCCLK); 791 792 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 793 794 udelay(10); 795 } 796 } 797 798 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 799 { 800 struct mmc_davinci_host *host = mmc_priv(mmc); 801 802 dev_dbg(mmc_dev(host->mmc), 803 "clock %dHz busmode %d powermode %d Vdd %04x\n", 804 ios->clock, ios->bus_mode, ios->power_mode, 805 ios->vdd); 806 807 switch (ios->bus_width) { 808 case MMC_BUS_WIDTH_8: 809 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 810 writel((readl(host->base + DAVINCI_MMCCTL) & 811 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 812 host->base + DAVINCI_MMCCTL); 813 break; 814 case MMC_BUS_WIDTH_4: 815 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 816 if (host->version == MMC_CTLR_VERSION_2) 817 writel((readl(host->base + DAVINCI_MMCCTL) & 818 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 819 host->base + DAVINCI_MMCCTL); 820 else 821 writel(readl(host->base + DAVINCI_MMCCTL) | 822 MMCCTL_WIDTH_4_BIT, 823 host->base + DAVINCI_MMCCTL); 824 break; 825 case MMC_BUS_WIDTH_1: 826 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 827 if (host->version == MMC_CTLR_VERSION_2) 828 writel(readl(host->base + DAVINCI_MMCCTL) & 829 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 830 host->base + DAVINCI_MMCCTL); 831 else 832 writel(readl(host->base + DAVINCI_MMCCTL) & 833 ~MMCCTL_WIDTH_4_BIT, 834 host->base + DAVINCI_MMCCTL); 835 break; 836 } 837 838 calculate_clk_divider(mmc, ios); 839 840 host->bus_mode = ios->bus_mode; 841 if (ios->power_mode == MMC_POWER_UP) { 842 unsigned long timeout = jiffies + msecs_to_jiffies(50); 843 bool lose = true; 844 845 /* Send clock cycles, poll completion */ 846 writel(0, host->base + DAVINCI_MMCARGHL); 847 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 848 while (time_before(jiffies, timeout)) { 849 u32 tmp = readl(host->base + DAVINCI_MMCST0); 850 851 if (tmp & MMCST0_RSPDNE) { 852 lose = false; 853 break; 854 } 855 cpu_relax(); 856 } 857 if (lose) 858 dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 859 } 860 861 /* FIXME on power OFF, reset things ... */ 862 } 863 864 static void 865 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 866 { 867 host->data = NULL; 868 869 if (host->do_dma) { 870 davinci_abort_dma(host); 871 872 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 873 (data->flags & MMC_DATA_WRITE) 874 ? DMA_TO_DEVICE 875 : DMA_FROM_DEVICE); 876 host->do_dma = false; 877 } 878 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 879 880 if (!data->stop || (host->cmd && host->cmd->error)) { 881 mmc_request_done(host->mmc, data->mrq); 882 writel(0, host->base + DAVINCI_MMCIM); 883 } else 884 mmc_davinci_start_command(host, data->stop); 885 } 886 887 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 888 struct mmc_command *cmd) 889 { 890 host->cmd = NULL; 891 892 if (cmd->flags & MMC_RSP_PRESENT) { 893 if (cmd->flags & MMC_RSP_136) { 894 /* response type 2 */ 895 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 896 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 897 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 898 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 899 } else { 900 /* response types 1, 1b, 3, 4, 5, 6 */ 901 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 902 } 903 } 904 905 if (host->data == NULL || cmd->error) { 906 if (cmd->error == -ETIMEDOUT) 907 cmd->mrq->cmd->retries = 0; 908 mmc_request_done(host->mmc, cmd->mrq); 909 writel(0, host->base + DAVINCI_MMCIM); 910 } 911 } 912 913 static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 914 int val) 915 { 916 u32 temp; 917 918 temp = readl(host->base + DAVINCI_MMCCTL); 919 if (val) /* reset */ 920 temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 921 else /* enable */ 922 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 923 924 writel(temp, host->base + DAVINCI_MMCCTL); 925 udelay(10); 926 } 927 928 static void 929 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 930 { 931 mmc_davinci_reset_ctrl(host, 1); 932 mmc_davinci_reset_ctrl(host, 0); 933 } 934 935 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 936 { 937 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 938 unsigned int status, qstatus; 939 int end_command = 0; 940 int end_transfer = 0; 941 struct mmc_data *data = host->data; 942 943 if (host->cmd == NULL && host->data == NULL) { 944 status = readl(host->base + DAVINCI_MMCST0); 945 dev_dbg(mmc_dev(host->mmc), 946 "Spurious interrupt 0x%04x\n", status); 947 /* Disable the interrupt from mmcsd */ 948 writel(0, host->base + DAVINCI_MMCIM); 949 return IRQ_NONE; 950 } 951 952 status = readl(host->base + DAVINCI_MMCST0); 953 qstatus = status; 954 955 /* handle FIFO first when using PIO for data. 956 * bytes_left will decrease to zero as I/O progress and status will 957 * read zero over iteration because this controller status 958 * register(MMCST0) reports any status only once and it is cleared 959 * by read. So, it is not unbouned loop even in the case of 960 * non-dma. 961 */ 962 while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 963 davinci_fifo_data_trans(host, rw_threshold); 964 status = readl(host->base + DAVINCI_MMCST0); 965 if (!status) 966 break; 967 qstatus |= status; 968 } 969 970 if (qstatus & MMCST0_DATDNE) { 971 /* All blocks sent/received, and CRC checks passed */ 972 if (data != NULL) { 973 if ((host->do_dma == 0) && (host->bytes_left > 0)) { 974 /* if datasize < rw_threshold 975 * no RX ints are generated 976 */ 977 davinci_fifo_data_trans(host, host->bytes_left); 978 } 979 end_transfer = 1; 980 data->bytes_xfered = data->blocks * data->blksz; 981 } else { 982 dev_err(mmc_dev(host->mmc), 983 "DATDNE with no host->data\n"); 984 } 985 } 986 987 if (qstatus & MMCST0_TOUTRD) { 988 /* Read data timeout */ 989 data->error = -ETIMEDOUT; 990 end_transfer = 1; 991 992 dev_dbg(mmc_dev(host->mmc), 993 "read data timeout, status %x\n", 994 qstatus); 995 996 davinci_abort_data(host, data); 997 } 998 999 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 1000 /* Data CRC error */ 1001 data->error = -EILSEQ; 1002 end_transfer = 1; 1003 1004 /* NOTE: this controller uses CRCWR to report both CRC 1005 * errors and timeouts (on writes). MMCDRSP values are 1006 * only weakly documented, but 0x9f was clearly a timeout 1007 * case and the two three-bit patterns in various SD specs 1008 * (101, 010) aren't part of it ... 1009 */ 1010 if (qstatus & MMCST0_CRCWR) { 1011 u32 temp = readb(host->base + DAVINCI_MMCDRSP); 1012 1013 if (temp == 0x9f) 1014 data->error = -ETIMEDOUT; 1015 } 1016 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 1017 (qstatus & MMCST0_CRCWR) ? "write" : "read", 1018 (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 1019 1020 davinci_abort_data(host, data); 1021 } 1022 1023 if (qstatus & MMCST0_TOUTRS) { 1024 /* Command timeout */ 1025 if (host->cmd) { 1026 dev_dbg(mmc_dev(host->mmc), 1027 "CMD%d timeout, status %x\n", 1028 host->cmd->opcode, qstatus); 1029 host->cmd->error = -ETIMEDOUT; 1030 if (data) { 1031 end_transfer = 1; 1032 davinci_abort_data(host, data); 1033 } else 1034 end_command = 1; 1035 } 1036 } 1037 1038 if (qstatus & MMCST0_CRCRS) { 1039 /* Command CRC error */ 1040 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1041 if (host->cmd) { 1042 host->cmd->error = -EILSEQ; 1043 end_command = 1; 1044 } 1045 } 1046 1047 if (qstatus & MMCST0_RSPDNE) { 1048 /* End of command phase */ 1049 end_command = (int) host->cmd; 1050 } 1051 1052 if (end_command) 1053 mmc_davinci_cmd_done(host, host->cmd); 1054 if (end_transfer) 1055 mmc_davinci_xfer_done(host, data); 1056 return IRQ_HANDLED; 1057 } 1058 1059 static int mmc_davinci_get_cd(struct mmc_host *mmc) 1060 { 1061 struct platform_device *pdev = to_platform_device(mmc->parent); 1062 struct davinci_mmc_config *config = pdev->dev.platform_data; 1063 1064 if (!config || !config->get_cd) 1065 return -ENOSYS; 1066 return config->get_cd(pdev->id); 1067 } 1068 1069 static int mmc_davinci_get_ro(struct mmc_host *mmc) 1070 { 1071 struct platform_device *pdev = to_platform_device(mmc->parent); 1072 struct davinci_mmc_config *config = pdev->dev.platform_data; 1073 1074 if (!config || !config->get_ro) 1075 return -ENOSYS; 1076 return config->get_ro(pdev->id); 1077 } 1078 1079 static struct mmc_host_ops mmc_davinci_ops = { 1080 .request = mmc_davinci_request, 1081 .set_ios = mmc_davinci_set_ios, 1082 .get_cd = mmc_davinci_get_cd, 1083 .get_ro = mmc_davinci_get_ro, 1084 }; 1085 1086 /*----------------------------------------------------------------------*/ 1087 1088 #ifdef CONFIG_CPU_FREQ 1089 static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 1090 unsigned long val, void *data) 1091 { 1092 struct mmc_davinci_host *host; 1093 unsigned int mmc_pclk; 1094 struct mmc_host *mmc; 1095 unsigned long flags; 1096 1097 host = container_of(nb, struct mmc_davinci_host, freq_transition); 1098 mmc = host->mmc; 1099 mmc_pclk = clk_get_rate(host->clk); 1100 1101 if (val == CPUFREQ_POSTCHANGE) { 1102 spin_lock_irqsave(&mmc->lock, flags); 1103 host->mmc_input_clk = mmc_pclk; 1104 calculate_clk_divider(mmc, &mmc->ios); 1105 spin_unlock_irqrestore(&mmc->lock, flags); 1106 } 1107 1108 return 0; 1109 } 1110 1111 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1112 { 1113 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 1114 1115 return cpufreq_register_notifier(&host->freq_transition, 1116 CPUFREQ_TRANSITION_NOTIFIER); 1117 } 1118 1119 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1120 { 1121 cpufreq_unregister_notifier(&host->freq_transition, 1122 CPUFREQ_TRANSITION_NOTIFIER); 1123 } 1124 #else 1125 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1126 { 1127 return 0; 1128 } 1129 1130 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1131 { 1132 } 1133 #endif 1134 static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1135 { 1136 1137 mmc_davinci_reset_ctrl(host, 1); 1138 1139 writel(0, host->base + DAVINCI_MMCCLK); 1140 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1141 1142 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1143 writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1144 1145 mmc_davinci_reset_ctrl(host, 0); 1146 } 1147 1148 static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1149 { 1150 struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1151 struct mmc_davinci_host *host = NULL; 1152 struct mmc_host *mmc = NULL; 1153 struct resource *r, *mem = NULL; 1154 int ret = 0, irq = 0; 1155 size_t mem_size; 1156 1157 /* REVISIT: when we're fully converted, fail if pdata is NULL */ 1158 1159 ret = -ENODEV; 1160 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1161 irq = platform_get_irq(pdev, 0); 1162 if (!r || irq == NO_IRQ) 1163 goto out; 1164 1165 ret = -EBUSY; 1166 mem_size = resource_size(r); 1167 mem = request_mem_region(r->start, mem_size, pdev->name); 1168 if (!mem) 1169 goto out; 1170 1171 ret = -ENOMEM; 1172 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1173 if (!mmc) 1174 goto out; 1175 1176 host = mmc_priv(mmc); 1177 host->mmc = mmc; /* Important */ 1178 1179 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1180 if (!r) 1181 goto out; 1182 host->rxdma = r->start; 1183 1184 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1185 if (!r) 1186 goto out; 1187 host->txdma = r->start; 1188 1189 host->mem_res = mem; 1190 host->base = ioremap(mem->start, mem_size); 1191 if (!host->base) 1192 goto out; 1193 1194 ret = -ENXIO; 1195 host->clk = clk_get(&pdev->dev, "MMCSDCLK"); 1196 if (IS_ERR(host->clk)) { 1197 ret = PTR_ERR(host->clk); 1198 goto out; 1199 } 1200 clk_enable(host->clk); 1201 host->mmc_input_clk = clk_get_rate(host->clk); 1202 1203 init_mmcsd_host(host); 1204 1205 if (pdata->nr_sg) 1206 host->nr_sg = pdata->nr_sg - 1; 1207 1208 if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1209 host->nr_sg = MAX_NR_SG; 1210 1211 host->use_dma = use_dma; 1212 host->irq = irq; 1213 1214 if (host->use_dma && davinci_acquire_dma_channels(host) != 0) 1215 host->use_dma = 0; 1216 1217 /* REVISIT: someday, support IRQ-driven card detection. */ 1218 mmc->caps |= MMC_CAP_NEEDS_POLL; 1219 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1220 1221 if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1222 mmc->caps |= MMC_CAP_4_BIT_DATA; 1223 1224 if (pdata && (pdata->wires == 8)) 1225 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1226 1227 host->version = pdata->version; 1228 1229 mmc->ops = &mmc_davinci_ops; 1230 mmc->f_min = 312500; 1231 mmc->f_max = 25000000; 1232 if (pdata && pdata->max_freq) 1233 mmc->f_max = pdata->max_freq; 1234 if (pdata && pdata->caps) 1235 mmc->caps |= pdata->caps; 1236 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1237 1238 /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1239 * Each hw_seg uses one EDMA parameter RAM slot, always one 1240 * channel and then usually some linked slots. 1241 */ 1242 mmc->max_segs = 1 + host->n_link; 1243 1244 /* EDMA limit per hw segment (one or two MBytes) */ 1245 mmc->max_seg_size = MAX_CCNT * rw_threshold; 1246 1247 /* MMC/SD controller limits for multiblock requests */ 1248 mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1249 mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1250 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1251 1252 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1253 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1254 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1255 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1256 1257 platform_set_drvdata(pdev, host); 1258 1259 ret = mmc_davinci_cpufreq_register(host); 1260 if (ret) { 1261 dev_err(&pdev->dev, "failed to register cpufreq\n"); 1262 goto cpu_freq_fail; 1263 } 1264 1265 ret = mmc_add_host(mmc); 1266 if (ret < 0) 1267 goto out; 1268 1269 ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host); 1270 if (ret) 1271 goto out; 1272 1273 rename_region(mem, mmc_hostname(mmc)); 1274 1275 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1276 host->use_dma ? "DMA" : "PIO", 1277 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1278 1279 return 0; 1280 1281 out: 1282 mmc_davinci_cpufreq_deregister(host); 1283 cpu_freq_fail: 1284 if (host) { 1285 davinci_release_dma_channels(host); 1286 1287 if (host->clk) { 1288 clk_disable(host->clk); 1289 clk_put(host->clk); 1290 } 1291 1292 if (host->base) 1293 iounmap(host->base); 1294 } 1295 1296 if (mmc) 1297 mmc_free_host(mmc); 1298 1299 if (mem) 1300 release_resource(mem); 1301 1302 dev_dbg(&pdev->dev, "probe err %d\n", ret); 1303 1304 return ret; 1305 } 1306 1307 static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1308 { 1309 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1310 1311 platform_set_drvdata(pdev, NULL); 1312 if (host) { 1313 mmc_davinci_cpufreq_deregister(host); 1314 1315 mmc_remove_host(host->mmc); 1316 free_irq(host->irq, host); 1317 1318 davinci_release_dma_channels(host); 1319 1320 clk_disable(host->clk); 1321 clk_put(host->clk); 1322 1323 iounmap(host->base); 1324 1325 release_resource(host->mem_res); 1326 1327 mmc_free_host(host->mmc); 1328 } 1329 1330 return 0; 1331 } 1332 1333 #ifdef CONFIG_PM 1334 static int davinci_mmcsd_suspend(struct device *dev) 1335 { 1336 struct platform_device *pdev = to_platform_device(dev); 1337 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1338 int ret; 1339 1340 mmc_host_enable(host->mmc); 1341 ret = mmc_suspend_host(host->mmc); 1342 if (!ret) { 1343 writel(0, host->base + DAVINCI_MMCIM); 1344 mmc_davinci_reset_ctrl(host, 1); 1345 mmc_host_disable(host->mmc); 1346 clk_disable(host->clk); 1347 host->suspended = 1; 1348 } else { 1349 host->suspended = 0; 1350 mmc_host_disable(host->mmc); 1351 } 1352 1353 return ret; 1354 } 1355 1356 static int davinci_mmcsd_resume(struct device *dev) 1357 { 1358 struct platform_device *pdev = to_platform_device(dev); 1359 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1360 int ret; 1361 1362 if (!host->suspended) 1363 return 0; 1364 1365 clk_enable(host->clk); 1366 mmc_host_enable(host->mmc); 1367 1368 mmc_davinci_reset_ctrl(host, 0); 1369 ret = mmc_resume_host(host->mmc); 1370 if (!ret) 1371 host->suspended = 0; 1372 1373 return ret; 1374 } 1375 1376 static const struct dev_pm_ops davinci_mmcsd_pm = { 1377 .suspend = davinci_mmcsd_suspend, 1378 .resume = davinci_mmcsd_resume, 1379 }; 1380 1381 #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1382 #else 1383 #define davinci_mmcsd_pm_ops NULL 1384 #endif 1385 1386 static struct platform_driver davinci_mmcsd_driver = { 1387 .driver = { 1388 .name = "davinci_mmc", 1389 .owner = THIS_MODULE, 1390 .pm = davinci_mmcsd_pm_ops, 1391 }, 1392 .remove = __exit_p(davinci_mmcsd_remove), 1393 }; 1394 1395 static int __init davinci_mmcsd_init(void) 1396 { 1397 return platform_driver_probe(&davinci_mmcsd_driver, 1398 davinci_mmcsd_probe); 1399 } 1400 module_init(davinci_mmcsd_init); 1401 1402 static void __exit davinci_mmcsd_exit(void) 1403 { 1404 platform_driver_unregister(&davinci_mmcsd_driver); 1405 } 1406 module_exit(davinci_mmcsd_exit); 1407 1408 MODULE_AUTHOR("Texas Instruments India"); 1409 MODULE_LICENSE("GPL"); 1410 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 1411 1412