1b4cff454SVipin Bhandari /* 2b4cff454SVipin Bhandari * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3b4cff454SVipin Bhandari * 4b4cff454SVipin Bhandari * Copyright (C) 2006 Texas Instruments. 5b4cff454SVipin Bhandari * Original author: Purushotam Kumar 6b4cff454SVipin Bhandari * Copyright (C) 2009 David Brownell 7b4cff454SVipin Bhandari * 8b4cff454SVipin Bhandari * This program is free software; you can redistribute it and/or modify 9b4cff454SVipin Bhandari * it under the terms of the GNU General Public License as published by 10b4cff454SVipin Bhandari * the Free Software Foundation; either version 2 of the License, or 11b4cff454SVipin Bhandari * (at your option) any later version. 12b4cff454SVipin Bhandari * 13b4cff454SVipin Bhandari * This program is distributed in the hope that it will be useful, 14b4cff454SVipin Bhandari * but WITHOUT ANY WARRANTY; without even the implied warranty of 15b4cff454SVipin Bhandari * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16b4cff454SVipin Bhandari * GNU General Public License for more details. 17b4cff454SVipin Bhandari * 18b4cff454SVipin Bhandari * You should have received a copy of the GNU General Public License 19b4cff454SVipin Bhandari * along with this program; if not, write to the Free Software 20b4cff454SVipin Bhandari * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21b4cff454SVipin Bhandari */ 22b4cff454SVipin Bhandari 23b4cff454SVipin Bhandari #include <linux/module.h> 24b4cff454SVipin Bhandari #include <linux/ioport.h> 25b4cff454SVipin Bhandari #include <linux/platform_device.h> 26b4cff454SVipin Bhandari #include <linux/clk.h> 27b4cff454SVipin Bhandari #include <linux/err.h> 287e30b8deSChaithrika U S #include <linux/cpufreq.h> 29b4cff454SVipin Bhandari #include <linux/mmc/host.h> 30b4cff454SVipin Bhandari #include <linux/io.h> 31b4cff454SVipin Bhandari #include <linux/irq.h> 32b4cff454SVipin Bhandari #include <linux/delay.h> 335413da81SMatt Porter #include <linux/dmaengine.h> 34b4cff454SVipin Bhandari #include <linux/dma-mapping.h> 35b4cff454SVipin Bhandari #include <linux/mmc/mmc.h> 367b43da4cSManjunathappa, Prakash #include <linux/of.h> 377b43da4cSManjunathappa, Prakash #include <linux/of_device.h> 38c8301e79Sahaslam@baylibre.com #include <linux/mmc/slot-gpio.h> 39b8789ec4SUlf Hansson #include <linux/interrupt.h> 40b4cff454SVipin Bhandari 41ec2a0833SArnd Bergmann #include <linux/platform_data/mmc-davinci.h> 42b4cff454SVipin Bhandari 43b4cff454SVipin Bhandari /* 44b4cff454SVipin Bhandari * Register Definitions 45b4cff454SVipin Bhandari */ 46b4cff454SVipin Bhandari #define DAVINCI_MMCCTL 0x00 /* Control Register */ 47b4cff454SVipin Bhandari #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 48b4cff454SVipin Bhandari #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 49b4cff454SVipin Bhandari #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 50b4cff454SVipin Bhandari #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 51b4cff454SVipin Bhandari #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 52b4cff454SVipin Bhandari #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 53b4cff454SVipin Bhandari #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 54b4cff454SVipin Bhandari #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 55b4cff454SVipin Bhandari #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 56b4cff454SVipin Bhandari #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 57b4cff454SVipin Bhandari #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 58b4cff454SVipin Bhandari #define DAVINCI_MMCCMD 0x30 /* Command Register */ 59b4cff454SVipin Bhandari #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 60b4cff454SVipin Bhandari #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 61b4cff454SVipin Bhandari #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 62b4cff454SVipin Bhandari #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 63b4cff454SVipin Bhandari #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 64b4cff454SVipin Bhandari #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 65b4cff454SVipin Bhandari #define DAVINCI_MMCETOK 0x4C 66b4cff454SVipin Bhandari #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 67b4cff454SVipin Bhandari #define DAVINCI_MMCCKC 0x54 68b4cff454SVipin Bhandari #define DAVINCI_MMCTORC 0x58 69b4cff454SVipin Bhandari #define DAVINCI_MMCTODC 0x5C 70b4cff454SVipin Bhandari #define DAVINCI_MMCBLNC 0x60 71b4cff454SVipin Bhandari #define DAVINCI_SDIOCTL 0x64 72b4cff454SVipin Bhandari #define DAVINCI_SDIOST0 0x68 73f9db92cbSAlagu Sankar #define DAVINCI_SDIOIEN 0x6C 74f9db92cbSAlagu Sankar #define DAVINCI_SDIOIST 0x70 75b4cff454SVipin Bhandari #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 76b4cff454SVipin Bhandari 77b4cff454SVipin Bhandari /* DAVINCI_MMCCTL definitions */ 78b4cff454SVipin Bhandari #define MMCCTL_DATRST (1 << 0) 79b4cff454SVipin Bhandari #define MMCCTL_CMDRST (1 << 1) 80132f1074SVipin Bhandari #define MMCCTL_WIDTH_8_BIT (1 << 8) 81b4cff454SVipin Bhandari #define MMCCTL_WIDTH_4_BIT (1 << 2) 82b4cff454SVipin Bhandari #define MMCCTL_DATEG_DISABLED (0 << 6) 83b4cff454SVipin Bhandari #define MMCCTL_DATEG_RISING (1 << 6) 84b4cff454SVipin Bhandari #define MMCCTL_DATEG_FALLING (2 << 6) 85b4cff454SVipin Bhandari #define MMCCTL_DATEG_BOTH (3 << 6) 86b4cff454SVipin Bhandari #define MMCCTL_PERMDR_LE (0 << 9) 87b4cff454SVipin Bhandari #define MMCCTL_PERMDR_BE (1 << 9) 88b4cff454SVipin Bhandari #define MMCCTL_PERMDX_LE (0 << 10) 89b4cff454SVipin Bhandari #define MMCCTL_PERMDX_BE (1 << 10) 90b4cff454SVipin Bhandari 91b4cff454SVipin Bhandari /* DAVINCI_MMCCLK definitions */ 92b4cff454SVipin Bhandari #define MMCCLK_CLKEN (1 << 8) 93b4cff454SVipin Bhandari #define MMCCLK_CLKRT_MASK (0xFF << 0) 94b4cff454SVipin Bhandari 95b4cff454SVipin Bhandari /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 96b4cff454SVipin Bhandari #define MMCST0_DATDNE BIT(0) /* data done */ 97b4cff454SVipin Bhandari #define MMCST0_BSYDNE BIT(1) /* busy done */ 98b4cff454SVipin Bhandari #define MMCST0_RSPDNE BIT(2) /* command done */ 99b4cff454SVipin Bhandari #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 100b4cff454SVipin Bhandari #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 101b4cff454SVipin Bhandari #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 102b4cff454SVipin Bhandari #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 103b4cff454SVipin Bhandari #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 104b4cff454SVipin Bhandari #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 105b4cff454SVipin Bhandari #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 106b4cff454SVipin Bhandari #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 107b4cff454SVipin Bhandari #define MMCST0_TRNDNE BIT(12) /* transfer done */ 108b4cff454SVipin Bhandari 109b4cff454SVipin Bhandari /* DAVINCI_MMCST1 definitions */ 110b4cff454SVipin Bhandari #define MMCST1_BUSY (1 << 0) 111b4cff454SVipin Bhandari 112b4cff454SVipin Bhandari /* DAVINCI_MMCCMD definitions */ 113b4cff454SVipin Bhandari #define MMCCMD_CMD_MASK (0x3F << 0) 114b4cff454SVipin Bhandari #define MMCCMD_PPLEN (1 << 7) 115b4cff454SVipin Bhandari #define MMCCMD_BSYEXP (1 << 8) 116b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_MASK (3 << 9) 117b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_NONE (0 << 9) 118b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R1456 (1 << 9) 119b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R2 (2 << 9) 120b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R3 (3 << 9) 121b4cff454SVipin Bhandari #define MMCCMD_DTRW (1 << 11) 122b4cff454SVipin Bhandari #define MMCCMD_STRMTP (1 << 12) 123b4cff454SVipin Bhandari #define MMCCMD_WDATX (1 << 13) 124b4cff454SVipin Bhandari #define MMCCMD_INITCK (1 << 14) 125b4cff454SVipin Bhandari #define MMCCMD_DCLR (1 << 15) 126b4cff454SVipin Bhandari #define MMCCMD_DMATRIG (1 << 16) 127b4cff454SVipin Bhandari 128b4cff454SVipin Bhandari /* DAVINCI_MMCFIFOCTL definitions */ 129b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFORST (1 << 0) 130b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 131b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 132b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 133b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 134b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 135b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 136b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 137b4cff454SVipin Bhandari 138f9db92cbSAlagu Sankar /* DAVINCI_SDIOST0 definitions */ 139f9db92cbSAlagu Sankar #define SDIOST0_DAT1_HI BIT(0) 140f9db92cbSAlagu Sankar 141f9db92cbSAlagu Sankar /* DAVINCI_SDIOIEN definitions */ 142f9db92cbSAlagu Sankar #define SDIOIEN_IOINTEN BIT(0) 143f9db92cbSAlagu Sankar 144f9db92cbSAlagu Sankar /* DAVINCI_SDIOIST definitions */ 145f9db92cbSAlagu Sankar #define SDIOIST_IOINT BIT(0) 146b4cff454SVipin Bhandari 147b4cff454SVipin Bhandari /* MMCSD Init clock in Hz in opendrain mode */ 148b4cff454SVipin Bhandari #define MMCSD_INIT_CLOCK 200000 149b4cff454SVipin Bhandari 150b4cff454SVipin Bhandari /* 151b4cff454SVipin Bhandari * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 152ca2afb6dSSudhakar Rajashekhara * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 153a36274e0SMartin K. Petersen * for drivers with max_segs == 1, making the segments bigger (64KB) 154ca2afb6dSSudhakar Rajashekhara * than the page or two that's otherwise typical. nr_sg (passed from 155ca2afb6dSSudhakar Rajashekhara * platform data) == 16 gives at least the same throughput boost, using 156ca2afb6dSSudhakar Rajashekhara * EDMA transfer linkage instead of spending CPU time copying pages. 157b4cff454SVipin Bhandari */ 158b4cff454SVipin Bhandari #define MAX_CCNT ((1 << 16) - 1) 159b4cff454SVipin Bhandari 160ca2afb6dSSudhakar Rajashekhara #define MAX_NR_SG 16 161b4cff454SVipin Bhandari 162b4cff454SVipin Bhandari static unsigned rw_threshold = 32; 163b4cff454SVipin Bhandari module_param(rw_threshold, uint, S_IRUGO); 164b4cff454SVipin Bhandari MODULE_PARM_DESC(rw_threshold, 165b4cff454SVipin Bhandari "Read/Write threshold. Default = 32"); 166b4cff454SVipin Bhandari 167ee698f50SIdo Yariv static unsigned poll_threshold = 128; 168ee698f50SIdo Yariv module_param(poll_threshold, uint, S_IRUGO); 169ee698f50SIdo Yariv MODULE_PARM_DESC(poll_threshold, 170ee698f50SIdo Yariv "Polling transaction size threshold. Default = 128"); 171ee698f50SIdo Yariv 172ee698f50SIdo Yariv static unsigned poll_loopcount = 32; 173ee698f50SIdo Yariv module_param(poll_loopcount, uint, S_IRUGO); 174ee698f50SIdo Yariv MODULE_PARM_DESC(poll_loopcount, 175ee698f50SIdo Yariv "Maximum polling loop count. Default = 32"); 176ee698f50SIdo Yariv 177b4cff454SVipin Bhandari static unsigned __initdata use_dma = 1; 178b4cff454SVipin Bhandari module_param(use_dma, uint, 0); 179b4cff454SVipin Bhandari MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 180b4cff454SVipin Bhandari 181b4cff454SVipin Bhandari struct mmc_davinci_host { 182b4cff454SVipin Bhandari struct mmc_command *cmd; 183b4cff454SVipin Bhandari struct mmc_data *data; 184b4cff454SVipin Bhandari struct mmc_host *mmc; 185b4cff454SVipin Bhandari struct clk *clk; 186b4cff454SVipin Bhandari unsigned int mmc_input_clk; 187b4cff454SVipin Bhandari void __iomem *base; 188b4cff454SVipin Bhandari struct resource *mem_res; 189f9db92cbSAlagu Sankar int mmc_irq, sdio_irq; 190b4cff454SVipin Bhandari unsigned char bus_mode; 191b4cff454SVipin Bhandari 192b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_NONE 0 193b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_READ 1 194b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_WRITE 2 195b4cff454SVipin Bhandari unsigned char data_dir; 196b4cff454SVipin Bhandari 197b4cff454SVipin Bhandari /* buffer is used during PIO of one scatterlist segment, and 198b4cff454SVipin Bhandari * is updated along with buffer_bytes_left. bytes_left applies 199b4cff454SVipin Bhandari * to all N blocks of the PIO transfer. 200b4cff454SVipin Bhandari */ 201b4cff454SVipin Bhandari u8 *buffer; 202b4cff454SVipin Bhandari u32 buffer_bytes_left; 203b4cff454SVipin Bhandari u32 bytes_left; 204b4cff454SVipin Bhandari 2055413da81SMatt Porter struct dma_chan *dma_tx; 2065413da81SMatt Porter struct dma_chan *dma_rx; 207b4cff454SVipin Bhandari bool use_dma; 208b4cff454SVipin Bhandari bool do_dma; 209f9db92cbSAlagu Sankar bool sdio_int; 210ee698f50SIdo Yariv bool active_request; 211b4cff454SVipin Bhandari 212b4cff454SVipin Bhandari /* For PIO we walk scatterlists one segment at a time. */ 213b4cff454SVipin Bhandari unsigned int sg_len; 214b4cff454SVipin Bhandari struct scatterlist *sg; 215b4cff454SVipin Bhandari 216b4cff454SVipin Bhandari /* Version of the MMC/SD controller */ 217b4cff454SVipin Bhandari u8 version; 218b4cff454SVipin Bhandari /* for ns in one cycle calculation */ 219b4cff454SVipin Bhandari unsigned ns_in_one_cycle; 220ca2afb6dSSudhakar Rajashekhara /* Number of sg segments */ 221ca2afb6dSSudhakar Rajashekhara u8 nr_sg; 2227e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 2237e30b8deSChaithrika U S struct notifier_block freq_transition; 2247e30b8deSChaithrika U S #endif 225b4cff454SVipin Bhandari }; 226b4cff454SVipin Bhandari 227ee698f50SIdo Yariv static irqreturn_t mmc_davinci_irq(int irq, void *dev_id); 228b4cff454SVipin Bhandari 229b4cff454SVipin Bhandari /* PIO only */ 230b4cff454SVipin Bhandari static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 231b4cff454SVipin Bhandari { 232b4cff454SVipin Bhandari host->buffer_bytes_left = sg_dma_len(host->sg); 233b4cff454SVipin Bhandari host->buffer = sg_virt(host->sg); 234b4cff454SVipin Bhandari if (host->buffer_bytes_left > host->bytes_left) 235b4cff454SVipin Bhandari host->buffer_bytes_left = host->bytes_left; 236b4cff454SVipin Bhandari } 237b4cff454SVipin Bhandari 238b4cff454SVipin Bhandari static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 239b4cff454SVipin Bhandari unsigned int n) 240b4cff454SVipin Bhandari { 241b4cff454SVipin Bhandari u8 *p; 242b4cff454SVipin Bhandari unsigned int i; 243b4cff454SVipin Bhandari 244b4cff454SVipin Bhandari if (host->buffer_bytes_left == 0) { 245b4cff454SVipin Bhandari host->sg = sg_next(host->data->sg); 246b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 247b4cff454SVipin Bhandari } 248b4cff454SVipin Bhandari 249b4cff454SVipin Bhandari p = host->buffer; 250b4cff454SVipin Bhandari if (n > host->buffer_bytes_left) 251b4cff454SVipin Bhandari n = host->buffer_bytes_left; 252b4cff454SVipin Bhandari host->buffer_bytes_left -= n; 253b4cff454SVipin Bhandari host->bytes_left -= n; 254b4cff454SVipin Bhandari 255b4cff454SVipin Bhandari /* NOTE: we never transfer more than rw_threshold bytes 256b4cff454SVipin Bhandari * to/from the fifo here; there's no I/O overlap. 257b4cff454SVipin Bhandari * This also assumes that access width( i.e. ACCWD) is 4 bytes 258b4cff454SVipin Bhandari */ 259b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 260b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 261b4cff454SVipin Bhandari writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 262b4cff454SVipin Bhandari p = p + 4; 263b4cff454SVipin Bhandari } 264b4cff454SVipin Bhandari if (n & 3) { 265b4cff454SVipin Bhandari iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 266b4cff454SVipin Bhandari p = p + (n & 3); 267b4cff454SVipin Bhandari } 268b4cff454SVipin Bhandari } else { 269b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 270b4cff454SVipin Bhandari *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 271b4cff454SVipin Bhandari p = p + 4; 272b4cff454SVipin Bhandari } 273b4cff454SVipin Bhandari if (n & 3) { 274b4cff454SVipin Bhandari ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 275b4cff454SVipin Bhandari p = p + (n & 3); 276b4cff454SVipin Bhandari } 277b4cff454SVipin Bhandari } 278b4cff454SVipin Bhandari host->buffer = p; 279b4cff454SVipin Bhandari } 280b4cff454SVipin Bhandari 281b4cff454SVipin Bhandari static void mmc_davinci_start_command(struct mmc_davinci_host *host, 282b4cff454SVipin Bhandari struct mmc_command *cmd) 283b4cff454SVipin Bhandari { 284b4cff454SVipin Bhandari u32 cmd_reg = 0; 285b4cff454SVipin Bhandari u32 im_val; 286b4cff454SVipin Bhandari 287b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 288b4cff454SVipin Bhandari cmd->opcode, cmd->arg, 289b4cff454SVipin Bhandari ({ char *s; 290b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 291b4cff454SVipin Bhandari case MMC_RSP_R1: 292b4cff454SVipin Bhandari s = ", R1/R5/R6/R7 response"; 293b4cff454SVipin Bhandari break; 294b4cff454SVipin Bhandari case MMC_RSP_R1B: 295b4cff454SVipin Bhandari s = ", R1b response"; 296b4cff454SVipin Bhandari break; 297b4cff454SVipin Bhandari case MMC_RSP_R2: 298b4cff454SVipin Bhandari s = ", R2 response"; 299b4cff454SVipin Bhandari break; 300b4cff454SVipin Bhandari case MMC_RSP_R3: 301b4cff454SVipin Bhandari s = ", R3/R4 response"; 302b4cff454SVipin Bhandari break; 303b4cff454SVipin Bhandari default: 304b4cff454SVipin Bhandari s = ", (R? response)"; 305b4cff454SVipin Bhandari break; 306b4cff454SVipin Bhandari }; s; })); 307b4cff454SVipin Bhandari host->cmd = cmd; 308b4cff454SVipin Bhandari 309b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 310b4cff454SVipin Bhandari case MMC_RSP_R1B: 311b4cff454SVipin Bhandari /* There's some spec confusion about when R1B is 312b4cff454SVipin Bhandari * allowed, but if the card doesn't issue a BUSY 313b4cff454SVipin Bhandari * then it's harmless for us to allow it. 314b4cff454SVipin Bhandari */ 315b4cff454SVipin Bhandari cmd_reg |= MMCCMD_BSYEXP; 316b4cff454SVipin Bhandari /* FALLTHROUGH */ 317b4cff454SVipin Bhandari case MMC_RSP_R1: /* 48 bits, CRC */ 318b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R1456; 319b4cff454SVipin Bhandari break; 320b4cff454SVipin Bhandari case MMC_RSP_R2: /* 136 bits, CRC */ 321b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R2; 322b4cff454SVipin Bhandari break; 323b4cff454SVipin Bhandari case MMC_RSP_R3: /* 48 bits, no CRC */ 324b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R3; 325b4cff454SVipin Bhandari break; 326b4cff454SVipin Bhandari default: 327b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_NONE; 328b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 329b4cff454SVipin Bhandari mmc_resp_type(cmd)); 330b4cff454SVipin Bhandari break; 331b4cff454SVipin Bhandari } 332b4cff454SVipin Bhandari 333b4cff454SVipin Bhandari /* Set command index */ 334b4cff454SVipin Bhandari cmd_reg |= cmd->opcode; 335b4cff454SVipin Bhandari 336b4cff454SVipin Bhandari /* Enable EDMA transfer triggers */ 337b4cff454SVipin Bhandari if (host->do_dma) 338b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 339b4cff454SVipin Bhandari 340b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 341b4cff454SVipin Bhandari host->data_dir == DAVINCI_MMC_DATADIR_READ) 342b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 343b4cff454SVipin Bhandari 344b4cff454SVipin Bhandari /* Setting whether command involves data transfer or not */ 345b4cff454SVipin Bhandari if (cmd->data) 346b4cff454SVipin Bhandari cmd_reg |= MMCCMD_WDATX; 347b4cff454SVipin Bhandari 348b4cff454SVipin Bhandari /* Setting whether data read or write */ 349b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 350b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DTRW; 351b4cff454SVipin Bhandari 352b4cff454SVipin Bhandari if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 353b4cff454SVipin Bhandari cmd_reg |= MMCCMD_PPLEN; 354b4cff454SVipin Bhandari 355b4cff454SVipin Bhandari /* set Command timeout */ 356b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 357b4cff454SVipin Bhandari 358b4cff454SVipin Bhandari /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 359b4cff454SVipin Bhandari im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 360b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 361b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 362b4cff454SVipin Bhandari 363b4cff454SVipin Bhandari if (!host->do_dma) 364b4cff454SVipin Bhandari im_val |= MMCST0_DXRDY; 365b4cff454SVipin Bhandari } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 366b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 367b4cff454SVipin Bhandari 368b4cff454SVipin Bhandari if (!host->do_dma) 369b4cff454SVipin Bhandari im_val |= MMCST0_DRRDY; 370b4cff454SVipin Bhandari } 371b4cff454SVipin Bhandari 372b4cff454SVipin Bhandari /* 373b4cff454SVipin Bhandari * Before non-DMA WRITE commands the controller needs priming: 374b4cff454SVipin Bhandari * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 375b4cff454SVipin Bhandari */ 376b4cff454SVipin Bhandari if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 377b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 378b4cff454SVipin Bhandari 379b4cff454SVipin Bhandari writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 380b4cff454SVipin Bhandari writel(cmd_reg, host->base + DAVINCI_MMCCMD); 381ee698f50SIdo Yariv 382ee698f50SIdo Yariv host->active_request = true; 383ee698f50SIdo Yariv 384ee698f50SIdo Yariv if (!host->do_dma && host->bytes_left <= poll_threshold) { 385ee698f50SIdo Yariv u32 count = poll_loopcount; 386ee698f50SIdo Yariv 387ee698f50SIdo Yariv while (host->active_request && count--) { 388ee698f50SIdo Yariv mmc_davinci_irq(0, host); 389ee698f50SIdo Yariv cpu_relax(); 390ee698f50SIdo Yariv } 391ee698f50SIdo Yariv } 392ee698f50SIdo Yariv 393ee698f50SIdo Yariv if (host->active_request) 394b4cff454SVipin Bhandari writel(im_val, host->base + DAVINCI_MMCIM); 395b4cff454SVipin Bhandari } 396b4cff454SVipin Bhandari 397b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 398b4cff454SVipin Bhandari 399b4cff454SVipin Bhandari /* DMA infrastructure */ 400b4cff454SVipin Bhandari 401b4cff454SVipin Bhandari static void davinci_abort_dma(struct mmc_davinci_host *host) 402b4cff454SVipin Bhandari { 4035413da81SMatt Porter struct dma_chan *sync_dev; 404b4cff454SVipin Bhandari 405b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 4065413da81SMatt Porter sync_dev = host->dma_rx; 407b4cff454SVipin Bhandari else 4085413da81SMatt Porter sync_dev = host->dma_tx; 409b4cff454SVipin Bhandari 4105413da81SMatt Porter dmaengine_terminate_all(sync_dev); 411b4cff454SVipin Bhandari } 412b4cff454SVipin Bhandari 4135413da81SMatt Porter static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 414b4cff454SVipin Bhandari struct mmc_data *data) 415b4cff454SVipin Bhandari { 4165413da81SMatt Porter struct dma_chan *chan; 4175413da81SMatt Porter struct dma_async_tx_descriptor *desc; 4185413da81SMatt Porter int ret = 0; 419b4cff454SVipin Bhandari 420b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 4215413da81SMatt Porter struct dma_slave_config dma_tx_conf = { 4225413da81SMatt Porter .direction = DMA_MEM_TO_DEV, 4235413da81SMatt Porter .dst_addr = host->mem_res->start + DAVINCI_MMCDXR, 4245413da81SMatt Porter .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 4255413da81SMatt Porter .dst_maxburst = 4265413da81SMatt Porter rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 4275413da81SMatt Porter }; 4285413da81SMatt Porter chan = host->dma_tx; 4295413da81SMatt Porter dmaengine_slave_config(host->dma_tx, &dma_tx_conf); 4305413da81SMatt Porter 4315413da81SMatt Porter desc = dmaengine_prep_slave_sg(host->dma_tx, 4325413da81SMatt Porter data->sg, 4335413da81SMatt Porter host->sg_len, 4345413da81SMatt Porter DMA_MEM_TO_DEV, 4355413da81SMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 4365413da81SMatt Porter if (!desc) { 4375413da81SMatt Porter dev_dbg(mmc_dev(host->mmc), 4385413da81SMatt Porter "failed to allocate DMA TX descriptor"); 4395413da81SMatt Porter ret = -1; 4405413da81SMatt Porter goto out; 4415413da81SMatt Porter } 442b4cff454SVipin Bhandari } else { 4435413da81SMatt Porter struct dma_slave_config dma_rx_conf = { 4445413da81SMatt Porter .direction = DMA_DEV_TO_MEM, 4455413da81SMatt Porter .src_addr = host->mem_res->start + DAVINCI_MMCDRR, 4465413da81SMatt Porter .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 4475413da81SMatt Porter .src_maxburst = 4485413da81SMatt Porter rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 4495413da81SMatt Porter }; 4505413da81SMatt Porter chan = host->dma_rx; 4515413da81SMatt Porter dmaengine_slave_config(host->dma_rx, &dma_rx_conf); 4525413da81SMatt Porter 4535413da81SMatt Porter desc = dmaengine_prep_slave_sg(host->dma_rx, 4545413da81SMatt Porter data->sg, 4555413da81SMatt Porter host->sg_len, 4565413da81SMatt Porter DMA_DEV_TO_MEM, 4575413da81SMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 4585413da81SMatt Porter if (!desc) { 4595413da81SMatt Porter dev_dbg(mmc_dev(host->mmc), 4605413da81SMatt Porter "failed to allocate DMA RX descriptor"); 4615413da81SMatt Porter ret = -1; 4625413da81SMatt Porter goto out; 4635413da81SMatt Porter } 464b4cff454SVipin Bhandari } 465b4cff454SVipin Bhandari 4665413da81SMatt Porter dmaengine_submit(desc); 4675413da81SMatt Porter dma_async_issue_pending(chan); 468b4cff454SVipin Bhandari 4695413da81SMatt Porter out: 4705413da81SMatt Porter return ret; 471b4cff454SVipin Bhandari } 472b4cff454SVipin Bhandari 473b4cff454SVipin Bhandari static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 474b4cff454SVipin Bhandari struct mmc_data *data) 475b4cff454SVipin Bhandari { 476b4cff454SVipin Bhandari int i; 477b4cff454SVipin Bhandari int mask = rw_threshold - 1; 4785413da81SMatt Porter int ret = 0; 479b4cff454SVipin Bhandari 480b4cff454SVipin Bhandari host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 481b4cff454SVipin Bhandari ((data->flags & MMC_DATA_WRITE) 482b4cff454SVipin Bhandari ? DMA_TO_DEVICE 483b4cff454SVipin Bhandari : DMA_FROM_DEVICE)); 484b4cff454SVipin Bhandari 485b4cff454SVipin Bhandari /* no individual DMA segment should need a partial FIFO */ 486b4cff454SVipin Bhandari for (i = 0; i < host->sg_len; i++) { 487b4cff454SVipin Bhandari if (sg_dma_len(data->sg + i) & mask) { 488b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), 489b4cff454SVipin Bhandari data->sg, data->sg_len, 490b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 491b4cff454SVipin Bhandari ? DMA_TO_DEVICE 492b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 493b4cff454SVipin Bhandari return -1; 494b4cff454SVipin Bhandari } 495b4cff454SVipin Bhandari } 496b4cff454SVipin Bhandari 497b4cff454SVipin Bhandari host->do_dma = 1; 4985413da81SMatt Porter ret = mmc_davinci_send_dma_request(host, data); 499b4cff454SVipin Bhandari 5005413da81SMatt Porter return ret; 501b4cff454SVipin Bhandari } 502b4cff454SVipin Bhandari 503b4cff454SVipin Bhandari static void __init_or_module 504b4cff454SVipin Bhandari davinci_release_dma_channels(struct mmc_davinci_host *host) 505b4cff454SVipin Bhandari { 506b4cff454SVipin Bhandari if (!host->use_dma) 507b4cff454SVipin Bhandari return; 508b4cff454SVipin Bhandari 5095413da81SMatt Porter dma_release_channel(host->dma_tx); 5105413da81SMatt Porter dma_release_channel(host->dma_rx); 511b4cff454SVipin Bhandari } 512b4cff454SVipin Bhandari 513b4cff454SVipin Bhandari static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 514b4cff454SVipin Bhandari { 5150a4d7236SPeter Ujfalusi host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); 5160a4d7236SPeter Ujfalusi if (IS_ERR(host->dma_tx)) { 5175413da81SMatt Porter dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); 5180a4d7236SPeter Ujfalusi return PTR_ERR(host->dma_tx); 519b4cff454SVipin Bhandari } 520b4cff454SVipin Bhandari 5210a4d7236SPeter Ujfalusi host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); 5220a4d7236SPeter Ujfalusi if (IS_ERR(host->dma_rx)) { 5235413da81SMatt Porter dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); 5240a4d7236SPeter Ujfalusi dma_release_channel(host->dma_tx); 5250a4d7236SPeter Ujfalusi return PTR_ERR(host->dma_rx); 526b4cff454SVipin Bhandari } 527b4cff454SVipin Bhandari 528b4cff454SVipin Bhandari return 0; 529b4cff454SVipin Bhandari } 530b4cff454SVipin Bhandari 531b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 532b4cff454SVipin Bhandari 533b4cff454SVipin Bhandari static void 534b4cff454SVipin Bhandari mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 535b4cff454SVipin Bhandari { 536b4cff454SVipin Bhandari int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 537b4cff454SVipin Bhandari int timeout; 538b4cff454SVipin Bhandari struct mmc_data *data = req->data; 539b4cff454SVipin Bhandari 540b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 541b4cff454SVipin Bhandari fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 542b4cff454SVipin Bhandari 543b4cff454SVipin Bhandari host->data = data; 544b4cff454SVipin Bhandari if (data == NULL) { 545b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 546b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCBLEN); 547b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCNBLK); 548b4cff454SVipin Bhandari return; 549b4cff454SVipin Bhandari } 550b4cff454SVipin Bhandari 551bbb66fcbSJaehoon Chung dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n", 552b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) ? "write" : "read", 553b4cff454SVipin Bhandari data->blocks, data->blksz); 554b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 555b4cff454SVipin Bhandari data->timeout_clks, data->timeout_ns); 556b4cff454SVipin Bhandari timeout = data->timeout_clks + 557b4cff454SVipin Bhandari (data->timeout_ns / host->ns_in_one_cycle); 558b4cff454SVipin Bhandari if (timeout > 0xffff) 559b4cff454SVipin Bhandari timeout = 0xffff; 560b4cff454SVipin Bhandari 561b4cff454SVipin Bhandari writel(timeout, host->base + DAVINCI_MMCTOD); 562b4cff454SVipin Bhandari writel(data->blocks, host->base + DAVINCI_MMCNBLK); 563b4cff454SVipin Bhandari writel(data->blksz, host->base + DAVINCI_MMCBLEN); 564b4cff454SVipin Bhandari 565b4cff454SVipin Bhandari /* Configure the FIFO */ 566bbb66fcbSJaehoon Chung if (data->flags & MMC_DATA_WRITE) { 567b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 568b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 569b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 570b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 571b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 572bbb66fcbSJaehoon Chung } else { 573b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_READ; 574b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 575b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 576b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 577b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 578b4cff454SVipin Bhandari } 579b4cff454SVipin Bhandari 580b4cff454SVipin Bhandari host->buffer = NULL; 581b4cff454SVipin Bhandari host->bytes_left = data->blocks * data->blksz; 582b4cff454SVipin Bhandari 583b4cff454SVipin Bhandari /* For now we try to use DMA whenever we won't need partial FIFO 584b4cff454SVipin Bhandari * reads or writes, either for the whole transfer (as tested here) 585b4cff454SVipin Bhandari * or for any individual scatterlist segment (tested when we call 586b4cff454SVipin Bhandari * start_dma_transfer). 587b4cff454SVipin Bhandari * 588b4cff454SVipin Bhandari * While we *could* change that, unusual block sizes are rarely 589b4cff454SVipin Bhandari * used. The occasional fallback to PIO should't hurt. 590b4cff454SVipin Bhandari */ 591b4cff454SVipin Bhandari if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 592b4cff454SVipin Bhandari && mmc_davinci_start_dma_transfer(host, data) == 0) { 593b4cff454SVipin Bhandari /* zero this to ensure we take no PIO paths */ 594b4cff454SVipin Bhandari host->bytes_left = 0; 595b4cff454SVipin Bhandari } else { 596b4cff454SVipin Bhandari /* Revert to CPU Copy */ 597b4cff454SVipin Bhandari host->sg_len = data->sg_len; 598b4cff454SVipin Bhandari host->sg = host->data->sg; 599b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 600b4cff454SVipin Bhandari } 601b4cff454SVipin Bhandari } 602b4cff454SVipin Bhandari 603b4cff454SVipin Bhandari static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 604b4cff454SVipin Bhandari { 605b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 606b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(900); 607b4cff454SVipin Bhandari u32 mmcst1 = 0; 608b4cff454SVipin Bhandari 609b4cff454SVipin Bhandari /* Card may still be sending BUSY after a previous operation, 610b4cff454SVipin Bhandari * typically some kind of write. If so, we can't proceed yet. 611b4cff454SVipin Bhandari */ 612b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 613b4cff454SVipin Bhandari mmcst1 = readl(host->base + DAVINCI_MMCST1); 614b4cff454SVipin Bhandari if (!(mmcst1 & MMCST1_BUSY)) 615b4cff454SVipin Bhandari break; 616b4cff454SVipin Bhandari cpu_relax(); 617b4cff454SVipin Bhandari } 618b4cff454SVipin Bhandari if (mmcst1 & MMCST1_BUSY) { 619b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 620b4cff454SVipin Bhandari req->cmd->error = -ETIMEDOUT; 621b4cff454SVipin Bhandari mmc_request_done(mmc, req); 622b4cff454SVipin Bhandari return; 623b4cff454SVipin Bhandari } 624b4cff454SVipin Bhandari 625b4cff454SVipin Bhandari host->do_dma = 0; 626b4cff454SVipin Bhandari mmc_davinci_prepare_data(host, req); 627b4cff454SVipin Bhandari mmc_davinci_start_command(host, req->cmd); 628b4cff454SVipin Bhandari } 629b4cff454SVipin Bhandari 630b4cff454SVipin Bhandari static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 631b4cff454SVipin Bhandari unsigned int mmc_req_freq) 632b4cff454SVipin Bhandari { 633b4cff454SVipin Bhandari unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 634b4cff454SVipin Bhandari 635b4cff454SVipin Bhandari mmc_pclk = host->mmc_input_clk; 636b4cff454SVipin Bhandari if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 637b4cff454SVipin Bhandari mmc_push_pull_divisor = ((unsigned int)mmc_pclk 638b4cff454SVipin Bhandari / (2 * mmc_req_freq)) - 1; 639b4cff454SVipin Bhandari else 640b4cff454SVipin Bhandari mmc_push_pull_divisor = 0; 641b4cff454SVipin Bhandari 642b4cff454SVipin Bhandari mmc_freq = (unsigned int)mmc_pclk 643b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)); 644b4cff454SVipin Bhandari 645b4cff454SVipin Bhandari if (mmc_freq > mmc_req_freq) 646b4cff454SVipin Bhandari mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 647b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 648b4cff454SVipin Bhandari if (mmc_req_freq <= 400000) 649b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 650b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000)); 651b4cff454SVipin Bhandari else 652b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 653b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 654b4cff454SVipin Bhandari 655b4cff454SVipin Bhandari return mmc_push_pull_divisor; 656b4cff454SVipin Bhandari } 657b4cff454SVipin Bhandari 6587e30b8deSChaithrika U S static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 659b4cff454SVipin Bhandari { 660b4cff454SVipin Bhandari unsigned int open_drain_freq = 0, mmc_pclk = 0; 661b4cff454SVipin Bhandari unsigned int mmc_push_pull_freq = 0; 662b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 663b4cff454SVipin Bhandari 664b4cff454SVipin Bhandari if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 665b4cff454SVipin Bhandari u32 temp; 666b4cff454SVipin Bhandari 667b4cff454SVipin Bhandari /* Ignoring the init clock value passed for fixing the inter 668b4cff454SVipin Bhandari * operability with different cards. 669b4cff454SVipin Bhandari */ 670b4cff454SVipin Bhandari open_drain_freq = ((unsigned int)mmc_pclk 671b4cff454SVipin Bhandari / (2 * MMCSD_INIT_CLOCK)) - 1; 672b4cff454SVipin Bhandari 673b4cff454SVipin Bhandari if (open_drain_freq > 0xFF) 674b4cff454SVipin Bhandari open_drain_freq = 0xFF; 675b4cff454SVipin Bhandari 676b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 677b4cff454SVipin Bhandari temp |= open_drain_freq; 678b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 679b4cff454SVipin Bhandari 680b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 681b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 682b4cff454SVipin Bhandari } else { 683b4cff454SVipin Bhandari u32 temp; 684b4cff454SVipin Bhandari mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 685b4cff454SVipin Bhandari 686b4cff454SVipin Bhandari if (mmc_push_pull_freq > 0xFF) 687b4cff454SVipin Bhandari mmc_push_pull_freq = 0xFF; 688b4cff454SVipin Bhandari 689b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 690b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 691b4cff454SVipin Bhandari 692b4cff454SVipin Bhandari udelay(10); 693b4cff454SVipin Bhandari 694b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 695b4cff454SVipin Bhandari temp |= mmc_push_pull_freq; 696b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 697b4cff454SVipin Bhandari 698b4cff454SVipin Bhandari writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 699b4cff454SVipin Bhandari 700b4cff454SVipin Bhandari udelay(10); 701b4cff454SVipin Bhandari } 7027e30b8deSChaithrika U S } 7037e30b8deSChaithrika U S 7047e30b8deSChaithrika U S static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 7057e30b8deSChaithrika U S { 7067e30b8deSChaithrika U S struct mmc_davinci_host *host = mmc_priv(mmc); 7074a9de8adSIdo Yariv struct platform_device *pdev = to_platform_device(mmc->parent); 7084a9de8adSIdo Yariv struct davinci_mmc_config *config = pdev->dev.platform_data; 7097e30b8deSChaithrika U S 7107e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), 7117e30b8deSChaithrika U S "clock %dHz busmode %d powermode %d Vdd %04x\n", 7127e30b8deSChaithrika U S ios->clock, ios->bus_mode, ios->power_mode, 7137e30b8deSChaithrika U S ios->vdd); 714132f1074SVipin Bhandari 7154a9de8adSIdo Yariv switch (ios->power_mode) { 7164a9de8adSIdo Yariv case MMC_POWER_OFF: 7174a9de8adSIdo Yariv if (config && config->set_power) 7184a9de8adSIdo Yariv config->set_power(pdev->id, false); 7194a9de8adSIdo Yariv break; 7204a9de8adSIdo Yariv case MMC_POWER_UP: 7214a9de8adSIdo Yariv if (config && config->set_power) 7224a9de8adSIdo Yariv config->set_power(pdev->id, true); 7234a9de8adSIdo Yariv break; 7244a9de8adSIdo Yariv } 7254a9de8adSIdo Yariv 726132f1074SVipin Bhandari switch (ios->bus_width) { 727132f1074SVipin Bhandari case MMC_BUS_WIDTH_8: 728132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 729132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 730132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 731132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 732132f1074SVipin Bhandari break; 733132f1074SVipin Bhandari case MMC_BUS_WIDTH_4: 7347e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 735132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 736132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 737132f1074SVipin Bhandari ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 7387e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 739132f1074SVipin Bhandari else 740132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) | 741132f1074SVipin Bhandari MMCCTL_WIDTH_4_BIT, 7427e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 743132f1074SVipin Bhandari break; 744132f1074SVipin Bhandari case MMC_BUS_WIDTH_1: 745132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 746132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 747132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 748132f1074SVipin Bhandari ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 749132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 750132f1074SVipin Bhandari else 751132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 752132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT, 753132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 754132f1074SVipin Bhandari break; 7557e30b8deSChaithrika U S } 7567e30b8deSChaithrika U S 7577e30b8deSChaithrika U S calculate_clk_divider(mmc, ios); 758b4cff454SVipin Bhandari 759b4cff454SVipin Bhandari host->bus_mode = ios->bus_mode; 760b4cff454SVipin Bhandari if (ios->power_mode == MMC_POWER_UP) { 761b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(50); 762b4cff454SVipin Bhandari bool lose = true; 763b4cff454SVipin Bhandari 764b4cff454SVipin Bhandari /* Send clock cycles, poll completion */ 765b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCARGHL); 766b4cff454SVipin Bhandari writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 767b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 768b4cff454SVipin Bhandari u32 tmp = readl(host->base + DAVINCI_MMCST0); 769b4cff454SVipin Bhandari 770b4cff454SVipin Bhandari if (tmp & MMCST0_RSPDNE) { 771b4cff454SVipin Bhandari lose = false; 772b4cff454SVipin Bhandari break; 773b4cff454SVipin Bhandari } 774b4cff454SVipin Bhandari cpu_relax(); 775b4cff454SVipin Bhandari } 776b4cff454SVipin Bhandari if (lose) 777b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 778b4cff454SVipin Bhandari } 779b4cff454SVipin Bhandari 780b4cff454SVipin Bhandari /* FIXME on power OFF, reset things ... */ 781b4cff454SVipin Bhandari } 782b4cff454SVipin Bhandari 783b4cff454SVipin Bhandari static void 784b4cff454SVipin Bhandari mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 785b4cff454SVipin Bhandari { 786b4cff454SVipin Bhandari host->data = NULL; 787b4cff454SVipin Bhandari 788f9db92cbSAlagu Sankar if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 789f9db92cbSAlagu Sankar /* 790f9db92cbSAlagu Sankar * SDIO Interrupt Detection work-around as suggested by 791f9db92cbSAlagu Sankar * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata 792f9db92cbSAlagu Sankar * 2.1.6): Signal SDIO interrupt only if it is enabled by core 793f9db92cbSAlagu Sankar */ 794f9db92cbSAlagu Sankar if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & 795f9db92cbSAlagu Sankar SDIOST0_DAT1_HI)) { 796f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 797f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 798f9db92cbSAlagu Sankar } 799f9db92cbSAlagu Sankar } 800f9db92cbSAlagu Sankar 801b4cff454SVipin Bhandari if (host->do_dma) { 802b4cff454SVipin Bhandari davinci_abort_dma(host); 803b4cff454SVipin Bhandari 804b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 805b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 806b4cff454SVipin Bhandari ? DMA_TO_DEVICE 807b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 808b4cff454SVipin Bhandari host->do_dma = false; 809b4cff454SVipin Bhandari } 810b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 811b4cff454SVipin Bhandari 812b4cff454SVipin Bhandari if (!data->stop || (host->cmd && host->cmd->error)) { 813b4cff454SVipin Bhandari mmc_request_done(host->mmc, data->mrq); 814b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 815ee698f50SIdo Yariv host->active_request = false; 816b4cff454SVipin Bhandari } else 817b4cff454SVipin Bhandari mmc_davinci_start_command(host, data->stop); 818b4cff454SVipin Bhandari } 819b4cff454SVipin Bhandari 820b4cff454SVipin Bhandari static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 821b4cff454SVipin Bhandari struct mmc_command *cmd) 822b4cff454SVipin Bhandari { 823b4cff454SVipin Bhandari host->cmd = NULL; 824b4cff454SVipin Bhandari 825b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_PRESENT) { 826b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_136) { 827b4cff454SVipin Bhandari /* response type 2 */ 828b4cff454SVipin Bhandari cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 829b4cff454SVipin Bhandari cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 830b4cff454SVipin Bhandari cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 831b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 832b4cff454SVipin Bhandari } else { 833b4cff454SVipin Bhandari /* response types 1, 1b, 3, 4, 5, 6 */ 834b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 835b4cff454SVipin Bhandari } 836b4cff454SVipin Bhandari } 837b4cff454SVipin Bhandari 838b4cff454SVipin Bhandari if (host->data == NULL || cmd->error) { 839b4cff454SVipin Bhandari if (cmd->error == -ETIMEDOUT) 840b4cff454SVipin Bhandari cmd->mrq->cmd->retries = 0; 841b4cff454SVipin Bhandari mmc_request_done(host->mmc, cmd->mrq); 842b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 843ee698f50SIdo Yariv host->active_request = false; 844b4cff454SVipin Bhandari } 845b4cff454SVipin Bhandari } 846b4cff454SVipin Bhandari 84706de845fSChaithrika U S static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 84806de845fSChaithrika U S int val) 849b4cff454SVipin Bhandari { 850b4cff454SVipin Bhandari u32 temp; 851b4cff454SVipin Bhandari 852b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCTL); 85306de845fSChaithrika U S if (val) /* reset */ 85406de845fSChaithrika U S temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 85506de845fSChaithrika U S else /* enable */ 856b4cff454SVipin Bhandari temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 85706de845fSChaithrika U S 858b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCTL); 85906de845fSChaithrika U S udelay(10); 86006de845fSChaithrika U S } 86106de845fSChaithrika U S 86206de845fSChaithrika U S static void 86306de845fSChaithrika U S davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 86406de845fSChaithrika U S { 86506de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 86606de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 867b4cff454SVipin Bhandari } 868b4cff454SVipin Bhandari 869f9db92cbSAlagu Sankar static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) 870f9db92cbSAlagu Sankar { 871f9db92cbSAlagu Sankar struct mmc_davinci_host *host = dev_id; 872f9db92cbSAlagu Sankar unsigned int status; 873f9db92cbSAlagu Sankar 874f9db92cbSAlagu Sankar status = readl(host->base + DAVINCI_SDIOIST); 875f9db92cbSAlagu Sankar if (status & SDIOIST_IOINT) { 876f9db92cbSAlagu Sankar dev_dbg(mmc_dev(host->mmc), 877f9db92cbSAlagu Sankar "SDIO interrupt status %x\n", status); 878f9db92cbSAlagu Sankar writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 879f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 880f9db92cbSAlagu Sankar } 881f9db92cbSAlagu Sankar return IRQ_HANDLED; 882f9db92cbSAlagu Sankar } 883f9db92cbSAlagu Sankar 884b4cff454SVipin Bhandari static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 885b4cff454SVipin Bhandari { 886b4cff454SVipin Bhandari struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 887b4cff454SVipin Bhandari unsigned int status, qstatus; 888b4cff454SVipin Bhandari int end_command = 0; 889b4cff454SVipin Bhandari int end_transfer = 0; 890b4cff454SVipin Bhandari struct mmc_data *data = host->data; 891b4cff454SVipin Bhandari 892b4cff454SVipin Bhandari if (host->cmd == NULL && host->data == NULL) { 893b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 894b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 895b4cff454SVipin Bhandari "Spurious interrupt 0x%04x\n", status); 896b4cff454SVipin Bhandari /* Disable the interrupt from mmcsd */ 897b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 898b4cff454SVipin Bhandari return IRQ_NONE; 899b4cff454SVipin Bhandari } 900b4cff454SVipin Bhandari 901b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 902b4cff454SVipin Bhandari qstatus = status; 903b4cff454SVipin Bhandari 904b4cff454SVipin Bhandari /* handle FIFO first when using PIO for data. 905b4cff454SVipin Bhandari * bytes_left will decrease to zero as I/O progress and status will 906b4cff454SVipin Bhandari * read zero over iteration because this controller status 907b4cff454SVipin Bhandari * register(MMCST0) reports any status only once and it is cleared 908b4cff454SVipin Bhandari * by read. So, it is not unbouned loop even in the case of 909b4cff454SVipin Bhandari * non-dma. 910b4cff454SVipin Bhandari */ 911be7b5622SIdo Yariv if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 912be7b5622SIdo Yariv unsigned long im_val; 913be7b5622SIdo Yariv 914be7b5622SIdo Yariv /* 915be7b5622SIdo Yariv * If interrupts fire during the following loop, they will be 916be7b5622SIdo Yariv * handled by the handler, but the PIC will still buffer these. 917be7b5622SIdo Yariv * As a result, the handler will be called again to serve these 918be7b5622SIdo Yariv * needlessly. In order to avoid these spurious interrupts, 919be7b5622SIdo Yariv * keep interrupts masked during the loop. 920be7b5622SIdo Yariv */ 921be7b5622SIdo Yariv im_val = readl(host->base + DAVINCI_MMCIM); 922be7b5622SIdo Yariv writel(0, host->base + DAVINCI_MMCIM); 923be7b5622SIdo Yariv 924be7b5622SIdo Yariv do { 925b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 926b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 927b4cff454SVipin Bhandari qstatus |= status; 928be7b5622SIdo Yariv } while (host->bytes_left && 929be7b5622SIdo Yariv (status & (MMCST0_DXRDY | MMCST0_DRRDY))); 930be7b5622SIdo Yariv 931be7b5622SIdo Yariv /* 932be7b5622SIdo Yariv * If an interrupt is pending, it is assumed it will fire when 933be7b5622SIdo Yariv * it is unmasked. This assumption is also taken when the MMCIM 934be7b5622SIdo Yariv * is first set. Otherwise, writing to MMCIM after reading the 935be7b5622SIdo Yariv * status is race-prone. 936be7b5622SIdo Yariv */ 937be7b5622SIdo Yariv writel(im_val, host->base + DAVINCI_MMCIM); 938b4cff454SVipin Bhandari } 939b4cff454SVipin Bhandari 940b4cff454SVipin Bhandari if (qstatus & MMCST0_DATDNE) { 941b4cff454SVipin Bhandari /* All blocks sent/received, and CRC checks passed */ 942b4cff454SVipin Bhandari if (data != NULL) { 943b4cff454SVipin Bhandari if ((host->do_dma == 0) && (host->bytes_left > 0)) { 944b4cff454SVipin Bhandari /* if datasize < rw_threshold 945b4cff454SVipin Bhandari * no RX ints are generated 946b4cff454SVipin Bhandari */ 947b4cff454SVipin Bhandari davinci_fifo_data_trans(host, host->bytes_left); 948b4cff454SVipin Bhandari } 949b4cff454SVipin Bhandari end_transfer = 1; 950b4cff454SVipin Bhandari data->bytes_xfered = data->blocks * data->blksz; 951b4cff454SVipin Bhandari } else { 952b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), 953b4cff454SVipin Bhandari "DATDNE with no host->data\n"); 954b4cff454SVipin Bhandari } 955b4cff454SVipin Bhandari } 956b4cff454SVipin Bhandari 957b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRD) { 958b4cff454SVipin Bhandari /* Read data timeout */ 959b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 960b4cff454SVipin Bhandari end_transfer = 1; 961b4cff454SVipin Bhandari 962b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 963b4cff454SVipin Bhandari "read data timeout, status %x\n", 964b4cff454SVipin Bhandari qstatus); 965b4cff454SVipin Bhandari 966b4cff454SVipin Bhandari davinci_abort_data(host, data); 967b4cff454SVipin Bhandari } 968b4cff454SVipin Bhandari 969b4cff454SVipin Bhandari if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 970b4cff454SVipin Bhandari /* Data CRC error */ 971b4cff454SVipin Bhandari data->error = -EILSEQ; 972b4cff454SVipin Bhandari end_transfer = 1; 973b4cff454SVipin Bhandari 974b4cff454SVipin Bhandari /* NOTE: this controller uses CRCWR to report both CRC 975b4cff454SVipin Bhandari * errors and timeouts (on writes). MMCDRSP values are 976b4cff454SVipin Bhandari * only weakly documented, but 0x9f was clearly a timeout 977b4cff454SVipin Bhandari * case and the two three-bit patterns in various SD specs 978b4cff454SVipin Bhandari * (101, 010) aren't part of it ... 979b4cff454SVipin Bhandari */ 980b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCWR) { 981b4cff454SVipin Bhandari u32 temp = readb(host->base + DAVINCI_MMCDRSP); 982b4cff454SVipin Bhandari 983b4cff454SVipin Bhandari if (temp == 0x9f) 984b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 985b4cff454SVipin Bhandari } 986b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 987b4cff454SVipin Bhandari (qstatus & MMCST0_CRCWR) ? "write" : "read", 988b4cff454SVipin Bhandari (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 989b4cff454SVipin Bhandari 990b4cff454SVipin Bhandari davinci_abort_data(host, data); 991b4cff454SVipin Bhandari } 992b4cff454SVipin Bhandari 993b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRS) { 994b4cff454SVipin Bhandari /* Command timeout */ 995b4cff454SVipin Bhandari if (host->cmd) { 996b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 997b4cff454SVipin Bhandari "CMD%d timeout, status %x\n", 998b4cff454SVipin Bhandari host->cmd->opcode, qstatus); 999b4cff454SVipin Bhandari host->cmd->error = -ETIMEDOUT; 1000b4cff454SVipin Bhandari if (data) { 1001b4cff454SVipin Bhandari end_transfer = 1; 1002b4cff454SVipin Bhandari davinci_abort_data(host, data); 1003b4cff454SVipin Bhandari } else 1004b4cff454SVipin Bhandari end_command = 1; 1005b4cff454SVipin Bhandari } 1006b4cff454SVipin Bhandari } 1007b4cff454SVipin Bhandari 1008b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCRS) { 1009b4cff454SVipin Bhandari /* Command CRC error */ 1010b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1011b4cff454SVipin Bhandari if (host->cmd) { 1012b4cff454SVipin Bhandari host->cmd->error = -EILSEQ; 1013b4cff454SVipin Bhandari end_command = 1; 1014b4cff454SVipin Bhandari } 1015b4cff454SVipin Bhandari } 1016b4cff454SVipin Bhandari 1017b4cff454SVipin Bhandari if (qstatus & MMCST0_RSPDNE) { 1018b4cff454SVipin Bhandari /* End of command phase */ 1019b4cff454SVipin Bhandari end_command = (int) host->cmd; 1020b4cff454SVipin Bhandari } 1021b4cff454SVipin Bhandari 1022b4cff454SVipin Bhandari if (end_command) 1023b4cff454SVipin Bhandari mmc_davinci_cmd_done(host, host->cmd); 1024b4cff454SVipin Bhandari if (end_transfer) 1025b4cff454SVipin Bhandari mmc_davinci_xfer_done(host, data); 1026b4cff454SVipin Bhandari return IRQ_HANDLED; 1027b4cff454SVipin Bhandari } 1028b4cff454SVipin Bhandari 1029b4cff454SVipin Bhandari static int mmc_davinci_get_cd(struct mmc_host *mmc) 1030b4cff454SVipin Bhandari { 1031b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1032b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1033b4cff454SVipin Bhandari 1034c8301e79Sahaslam@baylibre.com if (config && config->get_cd) 1035b4cff454SVipin Bhandari return config->get_cd(pdev->id); 1036c8301e79Sahaslam@baylibre.com 1037c8301e79Sahaslam@baylibre.com return mmc_gpio_get_cd(mmc); 1038b4cff454SVipin Bhandari } 1039b4cff454SVipin Bhandari 1040b4cff454SVipin Bhandari static int mmc_davinci_get_ro(struct mmc_host *mmc) 1041b4cff454SVipin Bhandari { 1042b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1043b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1044b4cff454SVipin Bhandari 1045c8301e79Sahaslam@baylibre.com if (config && config->get_ro) 1046b4cff454SVipin Bhandari return config->get_ro(pdev->id); 1047c8301e79Sahaslam@baylibre.com 1048c8301e79Sahaslam@baylibre.com return mmc_gpio_get_ro(mmc); 1049b4cff454SVipin Bhandari } 1050b4cff454SVipin Bhandari 1051f9db92cbSAlagu Sankar static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1052f9db92cbSAlagu Sankar { 1053f9db92cbSAlagu Sankar struct mmc_davinci_host *host = mmc_priv(mmc); 1054f9db92cbSAlagu Sankar 1055f9db92cbSAlagu Sankar if (enable) { 1056f9db92cbSAlagu Sankar if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { 1057f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1058f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 1059f9db92cbSAlagu Sankar } else { 1060f9db92cbSAlagu Sankar host->sdio_int = true; 1061f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) | 1062f9db92cbSAlagu Sankar SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); 1063f9db92cbSAlagu Sankar } 1064f9db92cbSAlagu Sankar } else { 1065f9db92cbSAlagu Sankar host->sdio_int = false; 1066f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, 1067f9db92cbSAlagu Sankar host->base + DAVINCI_SDIOIEN); 1068f9db92cbSAlagu Sankar } 1069f9db92cbSAlagu Sankar } 1070f9db92cbSAlagu Sankar 1071b4cff454SVipin Bhandari static struct mmc_host_ops mmc_davinci_ops = { 1072b4cff454SVipin Bhandari .request = mmc_davinci_request, 1073b4cff454SVipin Bhandari .set_ios = mmc_davinci_set_ios, 1074b4cff454SVipin Bhandari .get_cd = mmc_davinci_get_cd, 1075b4cff454SVipin Bhandari .get_ro = mmc_davinci_get_ro, 1076f9db92cbSAlagu Sankar .enable_sdio_irq = mmc_davinci_enable_sdio_irq, 1077b4cff454SVipin Bhandari }; 1078b4cff454SVipin Bhandari 1079b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 1080b4cff454SVipin Bhandari 10817e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 10827e30b8deSChaithrika U S static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 10837e30b8deSChaithrika U S unsigned long val, void *data) 10847e30b8deSChaithrika U S { 10857e30b8deSChaithrika U S struct mmc_davinci_host *host; 10867e30b8deSChaithrika U S unsigned int mmc_pclk; 10877e30b8deSChaithrika U S struct mmc_host *mmc; 10887e30b8deSChaithrika U S unsigned long flags; 10897e30b8deSChaithrika U S 10907e30b8deSChaithrika U S host = container_of(nb, struct mmc_davinci_host, freq_transition); 10917e30b8deSChaithrika U S mmc = host->mmc; 10927e30b8deSChaithrika U S mmc_pclk = clk_get_rate(host->clk); 10937e30b8deSChaithrika U S 10947e30b8deSChaithrika U S if (val == CPUFREQ_POSTCHANGE) { 10957e30b8deSChaithrika U S spin_lock_irqsave(&mmc->lock, flags); 10967e30b8deSChaithrika U S host->mmc_input_clk = mmc_pclk; 10977e30b8deSChaithrika U S calculate_clk_divider(mmc, &mmc->ios); 10987e30b8deSChaithrika U S spin_unlock_irqrestore(&mmc->lock, flags); 10997e30b8deSChaithrika U S } 11007e30b8deSChaithrika U S 11017e30b8deSChaithrika U S return 0; 11027e30b8deSChaithrika U S } 11037e30b8deSChaithrika U S 11047e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 11057e30b8deSChaithrika U S { 11067e30b8deSChaithrika U S host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 11077e30b8deSChaithrika U S 11087e30b8deSChaithrika U S return cpufreq_register_notifier(&host->freq_transition, 11097e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 11107e30b8deSChaithrika U S } 11117e30b8deSChaithrika U S 11127e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11137e30b8deSChaithrika U S { 11147e30b8deSChaithrika U S cpufreq_unregister_notifier(&host->freq_transition, 11157e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 11167e30b8deSChaithrika U S } 11177e30b8deSChaithrika U S #else 11187e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 11197e30b8deSChaithrika U S { 11207e30b8deSChaithrika U S return 0; 11217e30b8deSChaithrika U S } 11227e30b8deSChaithrika U S 11237e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11247e30b8deSChaithrika U S { 11257e30b8deSChaithrika U S } 11267e30b8deSChaithrika U S #endif 1127b4cff454SVipin Bhandari static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1128b4cff454SVipin Bhandari { 1129b4cff454SVipin Bhandari 113006de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1131b4cff454SVipin Bhandari 1132b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCCLK); 1133b4cff454SVipin Bhandari writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1134b4cff454SVipin Bhandari 1135b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1136b4cff454SVipin Bhandari writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1137b4cff454SVipin Bhandari 113806de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1139b4cff454SVipin Bhandari } 1140b4cff454SVipin Bhandari 1141ed425fc4SKrzysztof Kozlowski static const struct platform_device_id davinci_mmc_devtype[] = { 1142d7ca4c75SManjunathappa, Prakash { 1143d7ca4c75SManjunathappa, Prakash .name = "dm6441-mmc", 1144d7ca4c75SManjunathappa, Prakash .driver_data = MMC_CTLR_VERSION_1, 1145d7ca4c75SManjunathappa, Prakash }, { 1146d7ca4c75SManjunathappa, Prakash .name = "da830-mmc", 1147d7ca4c75SManjunathappa, Prakash .driver_data = MMC_CTLR_VERSION_2, 1148d7ca4c75SManjunathappa, Prakash }, 1149d7ca4c75SManjunathappa, Prakash {}, 1150d7ca4c75SManjunathappa, Prakash }; 1151d7ca4c75SManjunathappa, Prakash MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype); 1152d7ca4c75SManjunathappa, Prakash 11537b43da4cSManjunathappa, Prakash static const struct of_device_id davinci_mmc_dt_ids[] = { 11547b43da4cSManjunathappa, Prakash { 11557b43da4cSManjunathappa, Prakash .compatible = "ti,dm6441-mmc", 11567b43da4cSManjunathappa, Prakash .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1], 11577b43da4cSManjunathappa, Prakash }, 11587b43da4cSManjunathappa, Prakash { 11597b43da4cSManjunathappa, Prakash .compatible = "ti,da830-mmc", 11607b43da4cSManjunathappa, Prakash .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2], 11617b43da4cSManjunathappa, Prakash }, 11627b43da4cSManjunathappa, Prakash {}, 11637b43da4cSManjunathappa, Prakash }; 11647b43da4cSManjunathappa, Prakash MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids); 11657b43da4cSManjunathappa, Prakash 1166c8301e79Sahaslam@baylibre.com static int mmc_davinci_parse_pdata(struct mmc_host *mmc) 11677b43da4cSManjunathappa, Prakash { 1168c8301e79Sahaslam@baylibre.com struct platform_device *pdev = to_platform_device(mmc->parent); 11697b43da4cSManjunathappa, Prakash struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1170c8301e79Sahaslam@baylibre.com struct mmc_davinci_host *host; 11716e628dadSahaslam@baylibre.com int ret; 11727b43da4cSManjunathappa, Prakash 1173c8301e79Sahaslam@baylibre.com if (!pdata) 1174c8301e79Sahaslam@baylibre.com return -EINVAL; 11757b43da4cSManjunathappa, Prakash 1176c8301e79Sahaslam@baylibre.com host = mmc_priv(mmc); 1177c8301e79Sahaslam@baylibre.com if (!host) 1178c8301e79Sahaslam@baylibre.com return -EINVAL; 11797b43da4cSManjunathappa, Prakash 1180c8301e79Sahaslam@baylibre.com if (pdata && pdata->nr_sg) 1181c8301e79Sahaslam@baylibre.com host->nr_sg = pdata->nr_sg - 1; 11827b43da4cSManjunathappa, Prakash 1183c8301e79Sahaslam@baylibre.com if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1184c8301e79Sahaslam@baylibre.com mmc->caps |= MMC_CAP_4_BIT_DATA; 11857b43da4cSManjunathappa, Prakash 1186c8301e79Sahaslam@baylibre.com if (pdata && (pdata->wires == 8)) 1187c8301e79Sahaslam@baylibre.com mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1188c8301e79Sahaslam@baylibre.com 1189c8301e79Sahaslam@baylibre.com mmc->f_min = 312500; 1190c8301e79Sahaslam@baylibre.com mmc->f_max = 25000000; 1191c8301e79Sahaslam@baylibre.com if (pdata && pdata->max_freq) 1192c8301e79Sahaslam@baylibre.com mmc->f_max = pdata->max_freq; 1193c8301e79Sahaslam@baylibre.com if (pdata && pdata->caps) 1194c8301e79Sahaslam@baylibre.com mmc->caps |= pdata->caps; 1195c8301e79Sahaslam@baylibre.com 11966e628dadSahaslam@baylibre.com /* Register a cd gpio, if there is not one, enable polling */ 11976e628dadSahaslam@baylibre.com ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 11986e628dadSahaslam@baylibre.com if (ret == -EPROBE_DEFER) 11996e628dadSahaslam@baylibre.com return ret; 12006e628dadSahaslam@baylibre.com else if (ret) 12016e628dadSahaslam@baylibre.com mmc->caps |= MMC_CAP_NEEDS_POLL; 12026e628dadSahaslam@baylibre.com 12036e628dadSahaslam@baylibre.com ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 12046e628dadSahaslam@baylibre.com if (ret == -EPROBE_DEFER) 12056e628dadSahaslam@baylibre.com return ret; 12066e628dadSahaslam@baylibre.com 1207c8301e79Sahaslam@baylibre.com return 0; 12087b43da4cSManjunathappa, Prakash } 12097b43da4cSManjunathappa, Prakash 1210b4cff454SVipin Bhandari static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1211b4cff454SVipin Bhandari { 1212c8301e79Sahaslam@baylibre.com const struct of_device_id *match; 1213b4cff454SVipin Bhandari struct mmc_davinci_host *host = NULL; 1214b4cff454SVipin Bhandari struct mmc_host *mmc = NULL; 1215b4cff454SVipin Bhandari struct resource *r, *mem = NULL; 121662ac52b2SDavid Lechner int ret, irq; 1217b4cff454SVipin Bhandari size_t mem_size; 1218d7ca4c75SManjunathappa, Prakash const struct platform_device_id *id_entry; 1219b4cff454SVipin Bhandari 1220b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1221902a8a0bSArnd Bergmann if (!r) 122262ac52b2SDavid Lechner return -ENODEV; 1223902a8a0bSArnd Bergmann irq = platform_get_irq(pdev, 0); 1224902a8a0bSArnd Bergmann if (irq < 0) 1225902a8a0bSArnd Bergmann return irq; 1226b4cff454SVipin Bhandari 1227b4cff454SVipin Bhandari mem_size = resource_size(r); 122862ac52b2SDavid Lechner mem = devm_request_mem_region(&pdev->dev, r->start, mem_size, 122962ac52b2SDavid Lechner pdev->name); 1230b4cff454SVipin Bhandari if (!mem) 123162ac52b2SDavid Lechner return -EBUSY; 1232b4cff454SVipin Bhandari 1233b4cff454SVipin Bhandari mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1234b4cff454SVipin Bhandari if (!mmc) 123562ac52b2SDavid Lechner return -ENOMEM; 1236b4cff454SVipin Bhandari 1237b4cff454SVipin Bhandari host = mmc_priv(mmc); 1238b4cff454SVipin Bhandari host->mmc = mmc; /* Important */ 1239b4cff454SVipin Bhandari 1240b4cff454SVipin Bhandari host->mem_res = mem; 124162ac52b2SDavid Lechner host->base = devm_ioremap(&pdev->dev, mem->start, mem_size); 124262ac52b2SDavid Lechner if (!host->base) { 124362ac52b2SDavid Lechner ret = -ENOMEM; 124462ac52b2SDavid Lechner goto ioremap_fail; 124562ac52b2SDavid Lechner } 1246b4cff454SVipin Bhandari 124762ac52b2SDavid Lechner host->clk = devm_clk_get(&pdev->dev, NULL); 1248b4cff454SVipin Bhandari if (IS_ERR(host->clk)) { 1249b4cff454SVipin Bhandari ret = PTR_ERR(host->clk); 125062ac52b2SDavid Lechner goto clk_get_fail; 1251b4cff454SVipin Bhandari } 1252e2f3bfbdSDavid Lechner ret = clk_prepare_enable(host->clk); 125362ac52b2SDavid Lechner if (ret) 1254e2f3bfbdSDavid Lechner goto clk_prepare_enable_fail; 125562ac52b2SDavid Lechner 1256b4cff454SVipin Bhandari host->mmc_input_clk = clk_get_rate(host->clk); 1257b4cff454SVipin Bhandari 1258c8301e79Sahaslam@baylibre.com match = of_match_device(davinci_mmc_dt_ids, &pdev->dev); 1259c8301e79Sahaslam@baylibre.com if (match) { 1260c8301e79Sahaslam@baylibre.com pdev->id_entry = match->data; 1261c8301e79Sahaslam@baylibre.com ret = mmc_of_parse(mmc); 1262c8301e79Sahaslam@baylibre.com if (ret) { 1263c8301e79Sahaslam@baylibre.com dev_err(&pdev->dev, 1264c8301e79Sahaslam@baylibre.com "could not parse of data: %d\n", ret); 1265c8301e79Sahaslam@baylibre.com goto parse_fail; 1266c8301e79Sahaslam@baylibre.com } 1267c8301e79Sahaslam@baylibre.com } else { 1268c8301e79Sahaslam@baylibre.com ret = mmc_davinci_parse_pdata(mmc); 1269c8301e79Sahaslam@baylibre.com if (ret) { 1270c8301e79Sahaslam@baylibre.com dev_err(&pdev->dev, 1271c8301e79Sahaslam@baylibre.com "could not parse platform data: %d\n", ret); 1272c8301e79Sahaslam@baylibre.com goto parse_fail; 1273c8301e79Sahaslam@baylibre.com } } 1274ca2afb6dSSudhakar Rajashekhara 1275ca2afb6dSSudhakar Rajashekhara if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1276ca2afb6dSSudhakar Rajashekhara host->nr_sg = MAX_NR_SG; 1277ca2afb6dSSudhakar Rajashekhara 1278c8301e79Sahaslam@baylibre.com init_mmcsd_host(host); 1279c8301e79Sahaslam@baylibre.com 1280b4cff454SVipin Bhandari host->use_dma = use_dma; 1281f9db92cbSAlagu Sankar host->mmc_irq = irq; 1282f9db92cbSAlagu Sankar host->sdio_irq = platform_get_irq(pdev, 1); 1283b4cff454SVipin Bhandari 12840a4d7236SPeter Ujfalusi if (host->use_dma) { 12850a4d7236SPeter Ujfalusi ret = davinci_acquire_dma_channels(host); 12860a4d7236SPeter Ujfalusi if (ret == -EPROBE_DEFER) 128762ac52b2SDavid Lechner goto dma_probe_defer; 12880a4d7236SPeter Ujfalusi else if (ret) 1289b4cff454SVipin Bhandari host->use_dma = 0; 12900a4d7236SPeter Ujfalusi } 1291b4cff454SVipin Bhandari 1292132f1074SVipin Bhandari mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1293b4cff454SVipin Bhandari 1294d7ca4c75SManjunathappa, Prakash id_entry = platform_get_device_id(pdev); 1295d7ca4c75SManjunathappa, Prakash if (id_entry) 1296d7ca4c75SManjunathappa, Prakash host->version = id_entry->driver_data; 1297b4cff454SVipin Bhandari 1298b4cff454SVipin Bhandari mmc->ops = &mmc_davinci_ops; 1299b4cff454SVipin Bhandari mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1300b4cff454SVipin Bhandari 1301b4cff454SVipin Bhandari /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1302b4cff454SVipin Bhandari * Each hw_seg uses one EDMA parameter RAM slot, always one 1303b4cff454SVipin Bhandari * channel and then usually some linked slots. 1304b4cff454SVipin Bhandari */ 13055413da81SMatt Porter mmc->max_segs = MAX_NR_SG; 1306b4cff454SVipin Bhandari 1307b4cff454SVipin Bhandari /* EDMA limit per hw segment (one or two MBytes) */ 1308b4cff454SVipin Bhandari mmc->max_seg_size = MAX_CCNT * rw_threshold; 1309b4cff454SVipin Bhandari 1310b4cff454SVipin Bhandari /* MMC/SD controller limits for multiblock requests */ 1311b4cff454SVipin Bhandari mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1312b4cff454SVipin Bhandari mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1313b4cff454SVipin Bhandari mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1314b4cff454SVipin Bhandari 1315a36274e0SMartin K. Petersen dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1316b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1317b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1318b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1319b4cff454SVipin Bhandari 1320b4cff454SVipin Bhandari platform_set_drvdata(pdev, host); 1321b4cff454SVipin Bhandari 13227e30b8deSChaithrika U S ret = mmc_davinci_cpufreq_register(host); 13237e30b8deSChaithrika U S if (ret) { 13247e30b8deSChaithrika U S dev_err(&pdev->dev, "failed to register cpufreq\n"); 13257e30b8deSChaithrika U S goto cpu_freq_fail; 13267e30b8deSChaithrika U S } 13277e30b8deSChaithrika U S 1328b4cff454SVipin Bhandari ret = mmc_add_host(mmc); 1329b4cff454SVipin Bhandari if (ret < 0) 133062ac52b2SDavid Lechner goto mmc_add_host_fail; 1331b4cff454SVipin Bhandari 133262ac52b2SDavid Lechner ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0, 133362ac52b2SDavid Lechner mmc_hostname(mmc), host); 1334b4cff454SVipin Bhandari if (ret) 133562ac52b2SDavid Lechner goto request_irq_fail; 1336b4cff454SVipin Bhandari 1337f9db92cbSAlagu Sankar if (host->sdio_irq >= 0) { 133862ac52b2SDavid Lechner ret = devm_request_irq(&pdev->dev, host->sdio_irq, 133962ac52b2SDavid Lechner mmc_davinci_sdio_irq, 0, 1340f9db92cbSAlagu Sankar mmc_hostname(mmc), host); 1341f9db92cbSAlagu Sankar if (!ret) 1342f9db92cbSAlagu Sankar mmc->caps |= MMC_CAP_SDIO_IRQ; 1343f9db92cbSAlagu Sankar } 1344f9db92cbSAlagu Sankar 1345b4cff454SVipin Bhandari rename_region(mem, mmc_hostname(mmc)); 1346b4cff454SVipin Bhandari 1347b4cff454SVipin Bhandari dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1348b4cff454SVipin Bhandari host->use_dma ? "DMA" : "PIO", 1349b4cff454SVipin Bhandari (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1350b4cff454SVipin Bhandari 1351b4cff454SVipin Bhandari return 0; 1352b4cff454SVipin Bhandari 135362ac52b2SDavid Lechner request_irq_fail: 135462ac52b2SDavid Lechner mmc_remove_host(mmc); 135562ac52b2SDavid Lechner mmc_add_host_fail: 13567e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 13577e30b8deSChaithrika U S cpu_freq_fail: 1358b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1359c8301e79Sahaslam@baylibre.com parse_fail: 136062ac52b2SDavid Lechner dma_probe_defer: 1361e2f3bfbdSDavid Lechner clk_disable_unprepare(host->clk); 1362e2f3bfbdSDavid Lechner clk_prepare_enable_fail: 136362ac52b2SDavid Lechner clk_get_fail: 136462ac52b2SDavid Lechner ioremap_fail: 1365b4cff454SVipin Bhandari mmc_free_host(mmc); 1366b4cff454SVipin Bhandari 1367b4cff454SVipin Bhandari return ret; 1368b4cff454SVipin Bhandari } 1369b4cff454SVipin Bhandari 1370b4cff454SVipin Bhandari static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1371b4cff454SVipin Bhandari { 1372b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1373b4cff454SVipin Bhandari 1374b4cff454SVipin Bhandari mmc_remove_host(host->mmc); 137562ac52b2SDavid Lechner mmc_davinci_cpufreq_deregister(host); 1376b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1377e2f3bfbdSDavid Lechner clk_disable_unprepare(host->clk); 1378b4cff454SVipin Bhandari mmc_free_host(host->mmc); 1379b4cff454SVipin Bhandari 1380b4cff454SVipin Bhandari return 0; 1381b4cff454SVipin Bhandari } 1382b4cff454SVipin Bhandari 1383b4cff454SVipin Bhandari #ifdef CONFIG_PM 1384bbce5802SChaithrika U S static int davinci_mmcsd_suspend(struct device *dev) 1385b4cff454SVipin Bhandari { 1386bbce5802SChaithrika U S struct platform_device *pdev = to_platform_device(dev); 1387b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1388b4cff454SVipin Bhandari 1389bbce5802SChaithrika U S writel(0, host->base + DAVINCI_MMCIM); 1390bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1391bbce5802SChaithrika U S clk_disable(host->clk); 1392b4cff454SVipin Bhandari 13935ffdeea5SUlf Hansson return 0; 1394b4cff454SVipin Bhandari } 1395bbce5802SChaithrika U S 1396bbce5802SChaithrika U S static int davinci_mmcsd_resume(struct device *dev) 1397bbce5802SChaithrika U S { 1398bbce5802SChaithrika U S struct platform_device *pdev = to_platform_device(dev); 1399bbce5802SChaithrika U S struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1400bbce5802SChaithrika U S 1401bbce5802SChaithrika U S clk_enable(host->clk); 1402bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1403bbce5802SChaithrika U S 14045ffdeea5SUlf Hansson return 0; 1405bbce5802SChaithrika U S } 1406bbce5802SChaithrika U S 1407bbce5802SChaithrika U S static const struct dev_pm_ops davinci_mmcsd_pm = { 1408bbce5802SChaithrika U S .suspend = davinci_mmcsd_suspend, 1409bbce5802SChaithrika U S .resume = davinci_mmcsd_resume, 1410bbce5802SChaithrika U S }; 1411bbce5802SChaithrika U S 1412bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1413b4cff454SVipin Bhandari #else 1414bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops NULL 1415b4cff454SVipin Bhandari #endif 1416b4cff454SVipin Bhandari 1417b4cff454SVipin Bhandari static struct platform_driver davinci_mmcsd_driver = { 1418b4cff454SVipin Bhandari .driver = { 1419b4cff454SVipin Bhandari .name = "davinci_mmc", 1420bbce5802SChaithrika U S .pm = davinci_mmcsd_pm_ops, 14216fad5128SSachin Kamat .of_match_table = davinci_mmc_dt_ids, 1422b4cff454SVipin Bhandari }, 1423b4cff454SVipin Bhandari .remove = __exit_p(davinci_mmcsd_remove), 1424d7ca4c75SManjunathappa, Prakash .id_table = davinci_mmc_devtype, 1425b4cff454SVipin Bhandari }; 1426b4cff454SVipin Bhandari 1427d4bf6325SJingoo Han module_platform_driver_probe(davinci_mmcsd_driver, davinci_mmcsd_probe); 1428b4cff454SVipin Bhandari 1429b4cff454SVipin Bhandari MODULE_AUTHOR("Texas Instruments India"); 1430b4cff454SVipin Bhandari MODULE_LICENSE("GPL"); 1431b4cff454SVipin Bhandari MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 14327f8bea7fSJan Luebbe MODULE_ALIAS("platform:davinci_mmc"); 1433b4cff454SVipin Bhandari 1434