174ba9207SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2b4cff454SVipin Bhandari /* 3b4cff454SVipin Bhandari * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 4b4cff454SVipin Bhandari * 5b4cff454SVipin Bhandari * Copyright (C) 2006 Texas Instruments. 6b4cff454SVipin Bhandari * Original author: Purushotam Kumar 7b4cff454SVipin Bhandari * Copyright (C) 2009 David Brownell 8b4cff454SVipin Bhandari */ 9b4cff454SVipin Bhandari 10b4cff454SVipin Bhandari #include <linux/module.h> 11b4cff454SVipin Bhandari #include <linux/ioport.h> 12b4cff454SVipin Bhandari #include <linux/platform_device.h> 13b4cff454SVipin Bhandari #include <linux/clk.h> 14b4cff454SVipin Bhandari #include <linux/err.h> 157e30b8deSChaithrika U S #include <linux/cpufreq.h> 16b4cff454SVipin Bhandari #include <linux/mmc/host.h> 17b4cff454SVipin Bhandari #include <linux/io.h> 18b4cff454SVipin Bhandari #include <linux/irq.h> 19b4cff454SVipin Bhandari #include <linux/delay.h> 205413da81SMatt Porter #include <linux/dmaengine.h> 21b4cff454SVipin Bhandari #include <linux/dma-mapping.h> 22b4cff454SVipin Bhandari #include <linux/mmc/mmc.h> 237b43da4cSManjunathappa, Prakash #include <linux/of.h> 247b43da4cSManjunathappa, Prakash #include <linux/of_device.h> 25c8301e79Sahaslam@baylibre.com #include <linux/mmc/slot-gpio.h> 26b8789ec4SUlf Hansson #include <linux/interrupt.h> 27b4cff454SVipin Bhandari 28ec2a0833SArnd Bergmann #include <linux/platform_data/mmc-davinci.h> 29b4cff454SVipin Bhandari 30b4cff454SVipin Bhandari /* 31b4cff454SVipin Bhandari * Register Definitions 32b4cff454SVipin Bhandari */ 33b4cff454SVipin Bhandari #define DAVINCI_MMCCTL 0x00 /* Control Register */ 34b4cff454SVipin Bhandari #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 35b4cff454SVipin Bhandari #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 36b4cff454SVipin Bhandari #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 37b4cff454SVipin Bhandari #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 38b4cff454SVipin Bhandari #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 39b4cff454SVipin Bhandari #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 40b4cff454SVipin Bhandari #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 41b4cff454SVipin Bhandari #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 42b4cff454SVipin Bhandari #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 43b4cff454SVipin Bhandari #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 44b4cff454SVipin Bhandari #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 45b4cff454SVipin Bhandari #define DAVINCI_MMCCMD 0x30 /* Command Register */ 46b4cff454SVipin Bhandari #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 47b4cff454SVipin Bhandari #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 48b4cff454SVipin Bhandari #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 49b4cff454SVipin Bhandari #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 50b4cff454SVipin Bhandari #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 51b4cff454SVipin Bhandari #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 52b4cff454SVipin Bhandari #define DAVINCI_MMCETOK 0x4C 53b4cff454SVipin Bhandari #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 54b4cff454SVipin Bhandari #define DAVINCI_MMCCKC 0x54 55b4cff454SVipin Bhandari #define DAVINCI_MMCTORC 0x58 56b4cff454SVipin Bhandari #define DAVINCI_MMCTODC 0x5C 57b4cff454SVipin Bhandari #define DAVINCI_MMCBLNC 0x60 58b4cff454SVipin Bhandari #define DAVINCI_SDIOCTL 0x64 59b4cff454SVipin Bhandari #define DAVINCI_SDIOST0 0x68 60f9db92cbSAlagu Sankar #define DAVINCI_SDIOIEN 0x6C 61f9db92cbSAlagu Sankar #define DAVINCI_SDIOIST 0x70 62b4cff454SVipin Bhandari #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 63b4cff454SVipin Bhandari 64b4cff454SVipin Bhandari /* DAVINCI_MMCCTL definitions */ 65b4cff454SVipin Bhandari #define MMCCTL_DATRST (1 << 0) 66b4cff454SVipin Bhandari #define MMCCTL_CMDRST (1 << 1) 67132f1074SVipin Bhandari #define MMCCTL_WIDTH_8_BIT (1 << 8) 68b4cff454SVipin Bhandari #define MMCCTL_WIDTH_4_BIT (1 << 2) 69b4cff454SVipin Bhandari #define MMCCTL_DATEG_DISABLED (0 << 6) 70b4cff454SVipin Bhandari #define MMCCTL_DATEG_RISING (1 << 6) 71b4cff454SVipin Bhandari #define MMCCTL_DATEG_FALLING (2 << 6) 72b4cff454SVipin Bhandari #define MMCCTL_DATEG_BOTH (3 << 6) 73b4cff454SVipin Bhandari #define MMCCTL_PERMDR_LE (0 << 9) 74b4cff454SVipin Bhandari #define MMCCTL_PERMDR_BE (1 << 9) 75b4cff454SVipin Bhandari #define MMCCTL_PERMDX_LE (0 << 10) 76b4cff454SVipin Bhandari #define MMCCTL_PERMDX_BE (1 << 10) 77b4cff454SVipin Bhandari 78b4cff454SVipin Bhandari /* DAVINCI_MMCCLK definitions */ 79b4cff454SVipin Bhandari #define MMCCLK_CLKEN (1 << 8) 80b4cff454SVipin Bhandari #define MMCCLK_CLKRT_MASK (0xFF << 0) 81b4cff454SVipin Bhandari 82b4cff454SVipin Bhandari /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 83b4cff454SVipin Bhandari #define MMCST0_DATDNE BIT(0) /* data done */ 84b4cff454SVipin Bhandari #define MMCST0_BSYDNE BIT(1) /* busy done */ 85b4cff454SVipin Bhandari #define MMCST0_RSPDNE BIT(2) /* command done */ 86b4cff454SVipin Bhandari #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 87b4cff454SVipin Bhandari #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 88b4cff454SVipin Bhandari #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 89b4cff454SVipin Bhandari #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 90b4cff454SVipin Bhandari #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 91b4cff454SVipin Bhandari #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 92b4cff454SVipin Bhandari #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 93b4cff454SVipin Bhandari #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 94b4cff454SVipin Bhandari #define MMCST0_TRNDNE BIT(12) /* transfer done */ 95b4cff454SVipin Bhandari 96b4cff454SVipin Bhandari /* DAVINCI_MMCST1 definitions */ 97b4cff454SVipin Bhandari #define MMCST1_BUSY (1 << 0) 98b4cff454SVipin Bhandari 99b4cff454SVipin Bhandari /* DAVINCI_MMCCMD definitions */ 100b4cff454SVipin Bhandari #define MMCCMD_CMD_MASK (0x3F << 0) 101b4cff454SVipin Bhandari #define MMCCMD_PPLEN (1 << 7) 102b4cff454SVipin Bhandari #define MMCCMD_BSYEXP (1 << 8) 103b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_MASK (3 << 9) 104b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_NONE (0 << 9) 105b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R1456 (1 << 9) 106b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R2 (2 << 9) 107b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R3 (3 << 9) 108b4cff454SVipin Bhandari #define MMCCMD_DTRW (1 << 11) 109b4cff454SVipin Bhandari #define MMCCMD_STRMTP (1 << 12) 110b4cff454SVipin Bhandari #define MMCCMD_WDATX (1 << 13) 111b4cff454SVipin Bhandari #define MMCCMD_INITCK (1 << 14) 112b4cff454SVipin Bhandari #define MMCCMD_DCLR (1 << 15) 113b4cff454SVipin Bhandari #define MMCCMD_DMATRIG (1 << 16) 114b4cff454SVipin Bhandari 115b4cff454SVipin Bhandari /* DAVINCI_MMCFIFOCTL definitions */ 116b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFORST (1 << 0) 117b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 118b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 119b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 120b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 121b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 122b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 123b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 124b4cff454SVipin Bhandari 125f9db92cbSAlagu Sankar /* DAVINCI_SDIOST0 definitions */ 126f9db92cbSAlagu Sankar #define SDIOST0_DAT1_HI BIT(0) 127f9db92cbSAlagu Sankar 128f9db92cbSAlagu Sankar /* DAVINCI_SDIOIEN definitions */ 129f9db92cbSAlagu Sankar #define SDIOIEN_IOINTEN BIT(0) 130f9db92cbSAlagu Sankar 131f9db92cbSAlagu Sankar /* DAVINCI_SDIOIST definitions */ 132f9db92cbSAlagu Sankar #define SDIOIST_IOINT BIT(0) 133b4cff454SVipin Bhandari 134b4cff454SVipin Bhandari /* MMCSD Init clock in Hz in opendrain mode */ 135b4cff454SVipin Bhandari #define MMCSD_INIT_CLOCK 200000 136b4cff454SVipin Bhandari 137b4cff454SVipin Bhandari /* 138b4cff454SVipin Bhandari * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 139ca2afb6dSSudhakar Rajashekhara * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 140a36274e0SMartin K. Petersen * for drivers with max_segs == 1, making the segments bigger (64KB) 141ca2afb6dSSudhakar Rajashekhara * than the page or two that's otherwise typical. nr_sg (passed from 142ca2afb6dSSudhakar Rajashekhara * platform data) == 16 gives at least the same throughput boost, using 143ca2afb6dSSudhakar Rajashekhara * EDMA transfer linkage instead of spending CPU time copying pages. 144b4cff454SVipin Bhandari */ 145b4cff454SVipin Bhandari #define MAX_CCNT ((1 << 16) - 1) 146b4cff454SVipin Bhandari 147ca2afb6dSSudhakar Rajashekhara #define MAX_NR_SG 16 148b4cff454SVipin Bhandari 149b4cff454SVipin Bhandari static unsigned rw_threshold = 32; 150b4cff454SVipin Bhandari module_param(rw_threshold, uint, S_IRUGO); 151b4cff454SVipin Bhandari MODULE_PARM_DESC(rw_threshold, 152b4cff454SVipin Bhandari "Read/Write threshold. Default = 32"); 153b4cff454SVipin Bhandari 154ee698f50SIdo Yariv static unsigned poll_threshold = 128; 155ee698f50SIdo Yariv module_param(poll_threshold, uint, S_IRUGO); 156ee698f50SIdo Yariv MODULE_PARM_DESC(poll_threshold, 157ee698f50SIdo Yariv "Polling transaction size threshold. Default = 128"); 158ee698f50SIdo Yariv 159ee698f50SIdo Yariv static unsigned poll_loopcount = 32; 160ee698f50SIdo Yariv module_param(poll_loopcount, uint, S_IRUGO); 161ee698f50SIdo Yariv MODULE_PARM_DESC(poll_loopcount, 162ee698f50SIdo Yariv "Maximum polling loop count. Default = 32"); 163ee698f50SIdo Yariv 1646478f4e1SDavid Lechner static unsigned use_dma = 1; 165b4cff454SVipin Bhandari module_param(use_dma, uint, 0); 166b4cff454SVipin Bhandari MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 167b4cff454SVipin Bhandari 168b4cff454SVipin Bhandari struct mmc_davinci_host { 169b4cff454SVipin Bhandari struct mmc_command *cmd; 170b4cff454SVipin Bhandari struct mmc_data *data; 171b4cff454SVipin Bhandari struct mmc_host *mmc; 172b4cff454SVipin Bhandari struct clk *clk; 173b4cff454SVipin Bhandari unsigned int mmc_input_clk; 174b4cff454SVipin Bhandari void __iomem *base; 175b4cff454SVipin Bhandari struct resource *mem_res; 176f9db92cbSAlagu Sankar int mmc_irq, sdio_irq; 177b4cff454SVipin Bhandari unsigned char bus_mode; 178b4cff454SVipin Bhandari 179b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_NONE 0 180b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_READ 1 181b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_WRITE 2 182b4cff454SVipin Bhandari unsigned char data_dir; 183b4cff454SVipin Bhandari 184b4cff454SVipin Bhandari /* buffer is used during PIO of one scatterlist segment, and 185b4cff454SVipin Bhandari * is updated along with buffer_bytes_left. bytes_left applies 186b4cff454SVipin Bhandari * to all N blocks of the PIO transfer. 187b4cff454SVipin Bhandari */ 188b4cff454SVipin Bhandari u8 *buffer; 189b4cff454SVipin Bhandari u32 buffer_bytes_left; 190b4cff454SVipin Bhandari u32 bytes_left; 191b4cff454SVipin Bhandari 1925413da81SMatt Porter struct dma_chan *dma_tx; 1935413da81SMatt Porter struct dma_chan *dma_rx; 194b4cff454SVipin Bhandari bool use_dma; 195b4cff454SVipin Bhandari bool do_dma; 196f9db92cbSAlagu Sankar bool sdio_int; 197ee698f50SIdo Yariv bool active_request; 198b4cff454SVipin Bhandari 199b4cff454SVipin Bhandari /* For PIO we walk scatterlists one segment at a time. */ 200b4cff454SVipin Bhandari unsigned int sg_len; 201b4cff454SVipin Bhandari struct scatterlist *sg; 202b4cff454SVipin Bhandari 203b4cff454SVipin Bhandari /* Version of the MMC/SD controller */ 204b4cff454SVipin Bhandari u8 version; 205b4cff454SVipin Bhandari /* for ns in one cycle calculation */ 206b4cff454SVipin Bhandari unsigned ns_in_one_cycle; 207ca2afb6dSSudhakar Rajashekhara /* Number of sg segments */ 208ca2afb6dSSudhakar Rajashekhara u8 nr_sg; 2097e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 2107e30b8deSChaithrika U S struct notifier_block freq_transition; 2117e30b8deSChaithrika U S #endif 212b4cff454SVipin Bhandari }; 213b4cff454SVipin Bhandari 214ee698f50SIdo Yariv static irqreturn_t mmc_davinci_irq(int irq, void *dev_id); 215b4cff454SVipin Bhandari 216b4cff454SVipin Bhandari /* PIO only */ 217b4cff454SVipin Bhandari static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 218b4cff454SVipin Bhandari { 219b4cff454SVipin Bhandari host->buffer_bytes_left = sg_dma_len(host->sg); 220b4cff454SVipin Bhandari host->buffer = sg_virt(host->sg); 221b4cff454SVipin Bhandari if (host->buffer_bytes_left > host->bytes_left) 222b4cff454SVipin Bhandari host->buffer_bytes_left = host->bytes_left; 223b4cff454SVipin Bhandari } 224b4cff454SVipin Bhandari 225b4cff454SVipin Bhandari static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 226b4cff454SVipin Bhandari unsigned int n) 227b4cff454SVipin Bhandari { 228b4cff454SVipin Bhandari u8 *p; 229b4cff454SVipin Bhandari unsigned int i; 230b4cff454SVipin Bhandari 231b4cff454SVipin Bhandari if (host->buffer_bytes_left == 0) { 232b4cff454SVipin Bhandari host->sg = sg_next(host->data->sg); 233b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 234b4cff454SVipin Bhandari } 235b4cff454SVipin Bhandari 236b4cff454SVipin Bhandari p = host->buffer; 237b4cff454SVipin Bhandari if (n > host->buffer_bytes_left) 238b4cff454SVipin Bhandari n = host->buffer_bytes_left; 239b4cff454SVipin Bhandari host->buffer_bytes_left -= n; 240b4cff454SVipin Bhandari host->bytes_left -= n; 241b4cff454SVipin Bhandari 242b4cff454SVipin Bhandari /* NOTE: we never transfer more than rw_threshold bytes 243b4cff454SVipin Bhandari * to/from the fifo here; there's no I/O overlap. 244b4cff454SVipin Bhandari * This also assumes that access width( i.e. ACCWD) is 4 bytes 245b4cff454SVipin Bhandari */ 246b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 247b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 248b4cff454SVipin Bhandari writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 249b4cff454SVipin Bhandari p = p + 4; 250b4cff454SVipin Bhandari } 251b4cff454SVipin Bhandari if (n & 3) { 252b4cff454SVipin Bhandari iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 253b4cff454SVipin Bhandari p = p + (n & 3); 254b4cff454SVipin Bhandari } 255b4cff454SVipin Bhandari } else { 256b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 257b4cff454SVipin Bhandari *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 258b4cff454SVipin Bhandari p = p + 4; 259b4cff454SVipin Bhandari } 260b4cff454SVipin Bhandari if (n & 3) { 261b4cff454SVipin Bhandari ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 262b4cff454SVipin Bhandari p = p + (n & 3); 263b4cff454SVipin Bhandari } 264b4cff454SVipin Bhandari } 265b4cff454SVipin Bhandari host->buffer = p; 266b4cff454SVipin Bhandari } 267b4cff454SVipin Bhandari 268b4cff454SVipin Bhandari static void mmc_davinci_start_command(struct mmc_davinci_host *host, 269b4cff454SVipin Bhandari struct mmc_command *cmd) 270b4cff454SVipin Bhandari { 271b4cff454SVipin Bhandari u32 cmd_reg = 0; 272b4cff454SVipin Bhandari u32 im_val; 273b4cff454SVipin Bhandari 274b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 275b4cff454SVipin Bhandari cmd->opcode, cmd->arg, 276b4cff454SVipin Bhandari ({ char *s; 277b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 278b4cff454SVipin Bhandari case MMC_RSP_R1: 279b4cff454SVipin Bhandari s = ", R1/R5/R6/R7 response"; 280b4cff454SVipin Bhandari break; 281b4cff454SVipin Bhandari case MMC_RSP_R1B: 282b4cff454SVipin Bhandari s = ", R1b response"; 283b4cff454SVipin Bhandari break; 284b4cff454SVipin Bhandari case MMC_RSP_R2: 285b4cff454SVipin Bhandari s = ", R2 response"; 286b4cff454SVipin Bhandari break; 287b4cff454SVipin Bhandari case MMC_RSP_R3: 288b4cff454SVipin Bhandari s = ", R3/R4 response"; 289b4cff454SVipin Bhandari break; 290b4cff454SVipin Bhandari default: 291b4cff454SVipin Bhandari s = ", (R? response)"; 292b4cff454SVipin Bhandari break; 293b4cff454SVipin Bhandari }; s; })); 294b4cff454SVipin Bhandari host->cmd = cmd; 295b4cff454SVipin Bhandari 296b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 297b4cff454SVipin Bhandari case MMC_RSP_R1B: 298b4cff454SVipin Bhandari /* There's some spec confusion about when R1B is 299b4cff454SVipin Bhandari * allowed, but if the card doesn't issue a BUSY 300b4cff454SVipin Bhandari * then it's harmless for us to allow it. 301b4cff454SVipin Bhandari */ 302b4cff454SVipin Bhandari cmd_reg |= MMCCMD_BSYEXP; 303df561f66SGustavo A. R. Silva fallthrough; 304b4cff454SVipin Bhandari case MMC_RSP_R1: /* 48 bits, CRC */ 305b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R1456; 306b4cff454SVipin Bhandari break; 307b4cff454SVipin Bhandari case MMC_RSP_R2: /* 136 bits, CRC */ 308b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R2; 309b4cff454SVipin Bhandari break; 310b4cff454SVipin Bhandari case MMC_RSP_R3: /* 48 bits, no CRC */ 311b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R3; 312b4cff454SVipin Bhandari break; 313b4cff454SVipin Bhandari default: 314b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_NONE; 315b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 316b4cff454SVipin Bhandari mmc_resp_type(cmd)); 317b4cff454SVipin Bhandari break; 318b4cff454SVipin Bhandari } 319b4cff454SVipin Bhandari 320b4cff454SVipin Bhandari /* Set command index */ 321b4cff454SVipin Bhandari cmd_reg |= cmd->opcode; 322b4cff454SVipin Bhandari 323b4cff454SVipin Bhandari /* Enable EDMA transfer triggers */ 324b4cff454SVipin Bhandari if (host->do_dma) 325b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 326b4cff454SVipin Bhandari 327b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 328b4cff454SVipin Bhandari host->data_dir == DAVINCI_MMC_DATADIR_READ) 329b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 330b4cff454SVipin Bhandari 331b4cff454SVipin Bhandari /* Setting whether command involves data transfer or not */ 332b4cff454SVipin Bhandari if (cmd->data) 333b4cff454SVipin Bhandari cmd_reg |= MMCCMD_WDATX; 334b4cff454SVipin Bhandari 335b4cff454SVipin Bhandari /* Setting whether data read or write */ 336b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 337b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DTRW; 338b4cff454SVipin Bhandari 339b4cff454SVipin Bhandari if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 340b4cff454SVipin Bhandari cmd_reg |= MMCCMD_PPLEN; 341b4cff454SVipin Bhandari 342b4cff454SVipin Bhandari /* set Command timeout */ 343b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 344b4cff454SVipin Bhandari 345b4cff454SVipin Bhandari /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 346b4cff454SVipin Bhandari im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 347b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 348b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 349b4cff454SVipin Bhandari 350b4cff454SVipin Bhandari if (!host->do_dma) 351b4cff454SVipin Bhandari im_val |= MMCST0_DXRDY; 352b4cff454SVipin Bhandari } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 353b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 354b4cff454SVipin Bhandari 355b4cff454SVipin Bhandari if (!host->do_dma) 356b4cff454SVipin Bhandari im_val |= MMCST0_DRRDY; 357b4cff454SVipin Bhandari } 358b4cff454SVipin Bhandari 359b4cff454SVipin Bhandari /* 360b4cff454SVipin Bhandari * Before non-DMA WRITE commands the controller needs priming: 361b4cff454SVipin Bhandari * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 362b4cff454SVipin Bhandari */ 363b4cff454SVipin Bhandari if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 364b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 365b4cff454SVipin Bhandari 366b4cff454SVipin Bhandari writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 367b4cff454SVipin Bhandari writel(cmd_reg, host->base + DAVINCI_MMCCMD); 368ee698f50SIdo Yariv 369ee698f50SIdo Yariv host->active_request = true; 370ee698f50SIdo Yariv 371ee698f50SIdo Yariv if (!host->do_dma && host->bytes_left <= poll_threshold) { 372ee698f50SIdo Yariv u32 count = poll_loopcount; 373ee698f50SIdo Yariv 374ee698f50SIdo Yariv while (host->active_request && count--) { 375ee698f50SIdo Yariv mmc_davinci_irq(0, host); 376ee698f50SIdo Yariv cpu_relax(); 377ee698f50SIdo Yariv } 378ee698f50SIdo Yariv } 379ee698f50SIdo Yariv 380ee698f50SIdo Yariv if (host->active_request) 381b4cff454SVipin Bhandari writel(im_val, host->base + DAVINCI_MMCIM); 382b4cff454SVipin Bhandari } 383b4cff454SVipin Bhandari 384b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 385b4cff454SVipin Bhandari 386b4cff454SVipin Bhandari /* DMA infrastructure */ 387b4cff454SVipin Bhandari 388b4cff454SVipin Bhandari static void davinci_abort_dma(struct mmc_davinci_host *host) 389b4cff454SVipin Bhandari { 3905413da81SMatt Porter struct dma_chan *sync_dev; 391b4cff454SVipin Bhandari 392b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 3935413da81SMatt Porter sync_dev = host->dma_rx; 394b4cff454SVipin Bhandari else 3955413da81SMatt Porter sync_dev = host->dma_tx; 396b4cff454SVipin Bhandari 3975413da81SMatt Porter dmaengine_terminate_all(sync_dev); 398b4cff454SVipin Bhandari } 399b4cff454SVipin Bhandari 4005413da81SMatt Porter static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 401b4cff454SVipin Bhandari struct mmc_data *data) 402b4cff454SVipin Bhandari { 4035413da81SMatt Porter struct dma_chan *chan; 4045413da81SMatt Porter struct dma_async_tx_descriptor *desc; 4055413da81SMatt Porter int ret = 0; 406b4cff454SVipin Bhandari 407b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 4085413da81SMatt Porter struct dma_slave_config dma_tx_conf = { 4095413da81SMatt Porter .direction = DMA_MEM_TO_DEV, 4105413da81SMatt Porter .dst_addr = host->mem_res->start + DAVINCI_MMCDXR, 4115413da81SMatt Porter .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 4125413da81SMatt Porter .dst_maxburst = 4135413da81SMatt Porter rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 4145413da81SMatt Porter }; 4155413da81SMatt Porter chan = host->dma_tx; 4165413da81SMatt Porter dmaengine_slave_config(host->dma_tx, &dma_tx_conf); 4175413da81SMatt Porter 4185413da81SMatt Porter desc = dmaengine_prep_slave_sg(host->dma_tx, 4195413da81SMatt Porter data->sg, 4205413da81SMatt Porter host->sg_len, 4215413da81SMatt Porter DMA_MEM_TO_DEV, 4225413da81SMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 4235413da81SMatt Porter if (!desc) { 4245413da81SMatt Porter dev_dbg(mmc_dev(host->mmc), 4255413da81SMatt Porter "failed to allocate DMA TX descriptor"); 4265413da81SMatt Porter ret = -1; 4275413da81SMatt Porter goto out; 4285413da81SMatt Porter } 429b4cff454SVipin Bhandari } else { 4305413da81SMatt Porter struct dma_slave_config dma_rx_conf = { 4315413da81SMatt Porter .direction = DMA_DEV_TO_MEM, 4325413da81SMatt Porter .src_addr = host->mem_res->start + DAVINCI_MMCDRR, 4335413da81SMatt Porter .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 4345413da81SMatt Porter .src_maxburst = 4355413da81SMatt Porter rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 4365413da81SMatt Porter }; 4375413da81SMatt Porter chan = host->dma_rx; 4385413da81SMatt Porter dmaengine_slave_config(host->dma_rx, &dma_rx_conf); 4395413da81SMatt Porter 4405413da81SMatt Porter desc = dmaengine_prep_slave_sg(host->dma_rx, 4415413da81SMatt Porter data->sg, 4425413da81SMatt Porter host->sg_len, 4435413da81SMatt Porter DMA_DEV_TO_MEM, 4445413da81SMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 4455413da81SMatt Porter if (!desc) { 4465413da81SMatt Porter dev_dbg(mmc_dev(host->mmc), 4475413da81SMatt Porter "failed to allocate DMA RX descriptor"); 4485413da81SMatt Porter ret = -1; 4495413da81SMatt Porter goto out; 4505413da81SMatt Porter } 451b4cff454SVipin Bhandari } 452b4cff454SVipin Bhandari 4535413da81SMatt Porter dmaengine_submit(desc); 4545413da81SMatt Porter dma_async_issue_pending(chan); 455b4cff454SVipin Bhandari 4565413da81SMatt Porter out: 4575413da81SMatt Porter return ret; 458b4cff454SVipin Bhandari } 459b4cff454SVipin Bhandari 460b4cff454SVipin Bhandari static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 461b4cff454SVipin Bhandari struct mmc_data *data) 462b4cff454SVipin Bhandari { 463b4cff454SVipin Bhandari int i; 464b4cff454SVipin Bhandari int mask = rw_threshold - 1; 4655413da81SMatt Porter int ret = 0; 466b4cff454SVipin Bhandari 467b4cff454SVipin Bhandari host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 468feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 469b4cff454SVipin Bhandari 470b4cff454SVipin Bhandari /* no individual DMA segment should need a partial FIFO */ 471b4cff454SVipin Bhandari for (i = 0; i < host->sg_len; i++) { 472b4cff454SVipin Bhandari if (sg_dma_len(data->sg + i) & mask) { 473b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), 474b4cff454SVipin Bhandari data->sg, data->sg_len, 475feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 476b4cff454SVipin Bhandari return -1; 477b4cff454SVipin Bhandari } 478b4cff454SVipin Bhandari } 479b4cff454SVipin Bhandari 480b4cff454SVipin Bhandari host->do_dma = 1; 4815413da81SMatt Porter ret = mmc_davinci_send_dma_request(host, data); 482b4cff454SVipin Bhandari 4835413da81SMatt Porter return ret; 484b4cff454SVipin Bhandari } 485b4cff454SVipin Bhandari 4866478f4e1SDavid Lechner static void davinci_release_dma_channels(struct mmc_davinci_host *host) 487b4cff454SVipin Bhandari { 488b4cff454SVipin Bhandari if (!host->use_dma) 489b4cff454SVipin Bhandari return; 490b4cff454SVipin Bhandari 4915413da81SMatt Porter dma_release_channel(host->dma_tx); 4925413da81SMatt Porter dma_release_channel(host->dma_rx); 493b4cff454SVipin Bhandari } 494b4cff454SVipin Bhandari 4956478f4e1SDavid Lechner static int davinci_acquire_dma_channels(struct mmc_davinci_host *host) 496b4cff454SVipin Bhandari { 4970a4d7236SPeter Ujfalusi host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); 4980a4d7236SPeter Ujfalusi if (IS_ERR(host->dma_tx)) { 4995413da81SMatt Porter dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); 5000a4d7236SPeter Ujfalusi return PTR_ERR(host->dma_tx); 501b4cff454SVipin Bhandari } 502b4cff454SVipin Bhandari 5030a4d7236SPeter Ujfalusi host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); 5040a4d7236SPeter Ujfalusi if (IS_ERR(host->dma_rx)) { 5055413da81SMatt Porter dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); 5060a4d7236SPeter Ujfalusi dma_release_channel(host->dma_tx); 5070a4d7236SPeter Ujfalusi return PTR_ERR(host->dma_rx); 508b4cff454SVipin Bhandari } 509b4cff454SVipin Bhandari 510b4cff454SVipin Bhandari return 0; 511b4cff454SVipin Bhandari } 512b4cff454SVipin Bhandari 513b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 514b4cff454SVipin Bhandari 515b4cff454SVipin Bhandari static void 516b4cff454SVipin Bhandari mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 517b4cff454SVipin Bhandari { 518b4cff454SVipin Bhandari int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 519b4cff454SVipin Bhandari int timeout; 520b4cff454SVipin Bhandari struct mmc_data *data = req->data; 521b4cff454SVipin Bhandari 522b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 523b4cff454SVipin Bhandari fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 524b4cff454SVipin Bhandari 525b4cff454SVipin Bhandari host->data = data; 526b4cff454SVipin Bhandari if (data == NULL) { 527b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 528b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCBLEN); 529b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCNBLK); 530b4cff454SVipin Bhandari return; 531b4cff454SVipin Bhandari } 532b4cff454SVipin Bhandari 533bbb66fcbSJaehoon Chung dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n", 534b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) ? "write" : "read", 535b4cff454SVipin Bhandari data->blocks, data->blksz); 536b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 537b4cff454SVipin Bhandari data->timeout_clks, data->timeout_ns); 538b4cff454SVipin Bhandari timeout = data->timeout_clks + 539b4cff454SVipin Bhandari (data->timeout_ns / host->ns_in_one_cycle); 540b4cff454SVipin Bhandari if (timeout > 0xffff) 541b4cff454SVipin Bhandari timeout = 0xffff; 542b4cff454SVipin Bhandari 543b4cff454SVipin Bhandari writel(timeout, host->base + DAVINCI_MMCTOD); 544b4cff454SVipin Bhandari writel(data->blocks, host->base + DAVINCI_MMCNBLK); 545b4cff454SVipin Bhandari writel(data->blksz, host->base + DAVINCI_MMCBLEN); 546b4cff454SVipin Bhandari 547b4cff454SVipin Bhandari /* Configure the FIFO */ 548bbb66fcbSJaehoon Chung if (data->flags & MMC_DATA_WRITE) { 549b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 550b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 551b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 552b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 553b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 554bbb66fcbSJaehoon Chung } else { 555b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_READ; 556b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 557b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 558b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 559b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 560b4cff454SVipin Bhandari } 561b4cff454SVipin Bhandari 562b4cff454SVipin Bhandari host->buffer = NULL; 563b4cff454SVipin Bhandari host->bytes_left = data->blocks * data->blksz; 564b4cff454SVipin Bhandari 565b4cff454SVipin Bhandari /* For now we try to use DMA whenever we won't need partial FIFO 566b4cff454SVipin Bhandari * reads or writes, either for the whole transfer (as tested here) 567b4cff454SVipin Bhandari * or for any individual scatterlist segment (tested when we call 568b4cff454SVipin Bhandari * start_dma_transfer). 569b4cff454SVipin Bhandari * 570b4cff454SVipin Bhandari * While we *could* change that, unusual block sizes are rarely 571b4cff454SVipin Bhandari * used. The occasional fallback to PIO should't hurt. 572b4cff454SVipin Bhandari */ 573b4cff454SVipin Bhandari if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 574b4cff454SVipin Bhandari && mmc_davinci_start_dma_transfer(host, data) == 0) { 575b4cff454SVipin Bhandari /* zero this to ensure we take no PIO paths */ 576b4cff454SVipin Bhandari host->bytes_left = 0; 577b4cff454SVipin Bhandari } else { 578b4cff454SVipin Bhandari /* Revert to CPU Copy */ 579b4cff454SVipin Bhandari host->sg_len = data->sg_len; 580b4cff454SVipin Bhandari host->sg = host->data->sg; 581b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 582b4cff454SVipin Bhandari } 583b4cff454SVipin Bhandari } 584b4cff454SVipin Bhandari 585b4cff454SVipin Bhandari static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 586b4cff454SVipin Bhandari { 587b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 588b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(900); 589b4cff454SVipin Bhandari u32 mmcst1 = 0; 590b4cff454SVipin Bhandari 591b4cff454SVipin Bhandari /* Card may still be sending BUSY after a previous operation, 592b4cff454SVipin Bhandari * typically some kind of write. If so, we can't proceed yet. 593b4cff454SVipin Bhandari */ 594b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 595b4cff454SVipin Bhandari mmcst1 = readl(host->base + DAVINCI_MMCST1); 596b4cff454SVipin Bhandari if (!(mmcst1 & MMCST1_BUSY)) 597b4cff454SVipin Bhandari break; 598b4cff454SVipin Bhandari cpu_relax(); 599b4cff454SVipin Bhandari } 600b4cff454SVipin Bhandari if (mmcst1 & MMCST1_BUSY) { 601b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 602b4cff454SVipin Bhandari req->cmd->error = -ETIMEDOUT; 603b4cff454SVipin Bhandari mmc_request_done(mmc, req); 604b4cff454SVipin Bhandari return; 605b4cff454SVipin Bhandari } 606b4cff454SVipin Bhandari 607b4cff454SVipin Bhandari host->do_dma = 0; 608b4cff454SVipin Bhandari mmc_davinci_prepare_data(host, req); 609b4cff454SVipin Bhandari mmc_davinci_start_command(host, req->cmd); 610b4cff454SVipin Bhandari } 611b4cff454SVipin Bhandari 612b4cff454SVipin Bhandari static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 613b4cff454SVipin Bhandari unsigned int mmc_req_freq) 614b4cff454SVipin Bhandari { 615b4cff454SVipin Bhandari unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 616b4cff454SVipin Bhandari 617b4cff454SVipin Bhandari mmc_pclk = host->mmc_input_clk; 618b4cff454SVipin Bhandari if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 619b4cff454SVipin Bhandari mmc_push_pull_divisor = ((unsigned int)mmc_pclk 620b4cff454SVipin Bhandari / (2 * mmc_req_freq)) - 1; 621b4cff454SVipin Bhandari else 622b4cff454SVipin Bhandari mmc_push_pull_divisor = 0; 623b4cff454SVipin Bhandari 624b4cff454SVipin Bhandari mmc_freq = (unsigned int)mmc_pclk 625b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)); 626b4cff454SVipin Bhandari 627b4cff454SVipin Bhandari if (mmc_freq > mmc_req_freq) 628b4cff454SVipin Bhandari mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 629b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 630b4cff454SVipin Bhandari if (mmc_req_freq <= 400000) 631b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 632b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000)); 633b4cff454SVipin Bhandari else 634b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 635b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 636b4cff454SVipin Bhandari 637b4cff454SVipin Bhandari return mmc_push_pull_divisor; 638b4cff454SVipin Bhandari } 639b4cff454SVipin Bhandari 6407e30b8deSChaithrika U S static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 641b4cff454SVipin Bhandari { 642b4cff454SVipin Bhandari unsigned int open_drain_freq = 0, mmc_pclk = 0; 643b4cff454SVipin Bhandari unsigned int mmc_push_pull_freq = 0; 644b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 645b4cff454SVipin Bhandari 646b4cff454SVipin Bhandari if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 647b4cff454SVipin Bhandari u32 temp; 648b4cff454SVipin Bhandari 649b4cff454SVipin Bhandari /* Ignoring the init clock value passed for fixing the inter 650b4cff454SVipin Bhandari * operability with different cards. 651b4cff454SVipin Bhandari */ 652b4cff454SVipin Bhandari open_drain_freq = ((unsigned int)mmc_pclk 653b4cff454SVipin Bhandari / (2 * MMCSD_INIT_CLOCK)) - 1; 654b4cff454SVipin Bhandari 655b4cff454SVipin Bhandari if (open_drain_freq > 0xFF) 656b4cff454SVipin Bhandari open_drain_freq = 0xFF; 657b4cff454SVipin Bhandari 658b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 659b4cff454SVipin Bhandari temp |= open_drain_freq; 660b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 661b4cff454SVipin Bhandari 662b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 663b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 664b4cff454SVipin Bhandari } else { 665b4cff454SVipin Bhandari u32 temp; 666b4cff454SVipin Bhandari mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 667b4cff454SVipin Bhandari 668b4cff454SVipin Bhandari if (mmc_push_pull_freq > 0xFF) 669b4cff454SVipin Bhandari mmc_push_pull_freq = 0xFF; 670b4cff454SVipin Bhandari 671b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 672b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 673b4cff454SVipin Bhandari 674b4cff454SVipin Bhandari udelay(10); 675b4cff454SVipin Bhandari 676b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 677b4cff454SVipin Bhandari temp |= mmc_push_pull_freq; 678b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 679b4cff454SVipin Bhandari 680b4cff454SVipin Bhandari writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 681b4cff454SVipin Bhandari 682b4cff454SVipin Bhandari udelay(10); 683b4cff454SVipin Bhandari } 6847e30b8deSChaithrika U S } 6857e30b8deSChaithrika U S 6867e30b8deSChaithrika U S static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 6877e30b8deSChaithrika U S { 6887e30b8deSChaithrika U S struct mmc_davinci_host *host = mmc_priv(mmc); 6894a9de8adSIdo Yariv struct platform_device *pdev = to_platform_device(mmc->parent); 6904a9de8adSIdo Yariv struct davinci_mmc_config *config = pdev->dev.platform_data; 6917e30b8deSChaithrika U S 6927e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), 6937e30b8deSChaithrika U S "clock %dHz busmode %d powermode %d Vdd %04x\n", 6947e30b8deSChaithrika U S ios->clock, ios->bus_mode, ios->power_mode, 6957e30b8deSChaithrika U S ios->vdd); 696132f1074SVipin Bhandari 6974a9de8adSIdo Yariv switch (ios->power_mode) { 6984a9de8adSIdo Yariv case MMC_POWER_OFF: 6994a9de8adSIdo Yariv if (config && config->set_power) 7004a9de8adSIdo Yariv config->set_power(pdev->id, false); 7014a9de8adSIdo Yariv break; 7024a9de8adSIdo Yariv case MMC_POWER_UP: 7034a9de8adSIdo Yariv if (config && config->set_power) 7044a9de8adSIdo Yariv config->set_power(pdev->id, true); 7054a9de8adSIdo Yariv break; 7064a9de8adSIdo Yariv } 7074a9de8adSIdo Yariv 708132f1074SVipin Bhandari switch (ios->bus_width) { 709132f1074SVipin Bhandari case MMC_BUS_WIDTH_8: 710132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 711132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 712132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 713132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 714132f1074SVipin Bhandari break; 715132f1074SVipin Bhandari case MMC_BUS_WIDTH_4: 7167e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 717132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 718132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 719132f1074SVipin Bhandari ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 7207e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 721132f1074SVipin Bhandari else 722132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) | 723132f1074SVipin Bhandari MMCCTL_WIDTH_4_BIT, 7247e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 725132f1074SVipin Bhandari break; 726132f1074SVipin Bhandari case MMC_BUS_WIDTH_1: 727132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 728132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 729132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 730132f1074SVipin Bhandari ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 731132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 732132f1074SVipin Bhandari else 733132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 734132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT, 735132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 736132f1074SVipin Bhandari break; 7377e30b8deSChaithrika U S } 7387e30b8deSChaithrika U S 7397e30b8deSChaithrika U S calculate_clk_divider(mmc, ios); 740b4cff454SVipin Bhandari 741b4cff454SVipin Bhandari host->bus_mode = ios->bus_mode; 742b4cff454SVipin Bhandari if (ios->power_mode == MMC_POWER_UP) { 743b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(50); 744b4cff454SVipin Bhandari bool lose = true; 745b4cff454SVipin Bhandari 746b4cff454SVipin Bhandari /* Send clock cycles, poll completion */ 747b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCARGHL); 748b4cff454SVipin Bhandari writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 749b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 750b4cff454SVipin Bhandari u32 tmp = readl(host->base + DAVINCI_MMCST0); 751b4cff454SVipin Bhandari 752b4cff454SVipin Bhandari if (tmp & MMCST0_RSPDNE) { 753b4cff454SVipin Bhandari lose = false; 754b4cff454SVipin Bhandari break; 755b4cff454SVipin Bhandari } 756b4cff454SVipin Bhandari cpu_relax(); 757b4cff454SVipin Bhandari } 758b4cff454SVipin Bhandari if (lose) 759b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 760b4cff454SVipin Bhandari } 761b4cff454SVipin Bhandari 762b4cff454SVipin Bhandari /* FIXME on power OFF, reset things ... */ 763b4cff454SVipin Bhandari } 764b4cff454SVipin Bhandari 765b4cff454SVipin Bhandari static void 766b4cff454SVipin Bhandari mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 767b4cff454SVipin Bhandari { 768b4cff454SVipin Bhandari host->data = NULL; 769b4cff454SVipin Bhandari 770f9db92cbSAlagu Sankar if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 771f9db92cbSAlagu Sankar /* 772f9db92cbSAlagu Sankar * SDIO Interrupt Detection work-around as suggested by 773f9db92cbSAlagu Sankar * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata 774f9db92cbSAlagu Sankar * 2.1.6): Signal SDIO interrupt only if it is enabled by core 775f9db92cbSAlagu Sankar */ 776f9db92cbSAlagu Sankar if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & 777f9db92cbSAlagu Sankar SDIOST0_DAT1_HI)) { 778f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 779f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 780f9db92cbSAlagu Sankar } 781f9db92cbSAlagu Sankar } 782f9db92cbSAlagu Sankar 783b4cff454SVipin Bhandari if (host->do_dma) { 784b4cff454SVipin Bhandari davinci_abort_dma(host); 785b4cff454SVipin Bhandari 786b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 787feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 788b4cff454SVipin Bhandari host->do_dma = false; 789b4cff454SVipin Bhandari } 790b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 791b4cff454SVipin Bhandari 792b4cff454SVipin Bhandari if (!data->stop || (host->cmd && host->cmd->error)) { 793b4cff454SVipin Bhandari mmc_request_done(host->mmc, data->mrq); 794b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 795ee698f50SIdo Yariv host->active_request = false; 796b4cff454SVipin Bhandari } else 797b4cff454SVipin Bhandari mmc_davinci_start_command(host, data->stop); 798b4cff454SVipin Bhandari } 799b4cff454SVipin Bhandari 800b4cff454SVipin Bhandari static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 801b4cff454SVipin Bhandari struct mmc_command *cmd) 802b4cff454SVipin Bhandari { 803b4cff454SVipin Bhandari host->cmd = NULL; 804b4cff454SVipin Bhandari 805b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_PRESENT) { 806b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_136) { 807b4cff454SVipin Bhandari /* response type 2 */ 808b4cff454SVipin Bhandari cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 809b4cff454SVipin Bhandari cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 810b4cff454SVipin Bhandari cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 811b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 812b4cff454SVipin Bhandari } else { 813b4cff454SVipin Bhandari /* response types 1, 1b, 3, 4, 5, 6 */ 814b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 815b4cff454SVipin Bhandari } 816b4cff454SVipin Bhandari } 817b4cff454SVipin Bhandari 818b4cff454SVipin Bhandari if (host->data == NULL || cmd->error) { 819b4cff454SVipin Bhandari if (cmd->error == -ETIMEDOUT) 820b4cff454SVipin Bhandari cmd->mrq->cmd->retries = 0; 821b4cff454SVipin Bhandari mmc_request_done(host->mmc, cmd->mrq); 822b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 823ee698f50SIdo Yariv host->active_request = false; 824b4cff454SVipin Bhandari } 825b4cff454SVipin Bhandari } 826b4cff454SVipin Bhandari 82706de845fSChaithrika U S static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 82806de845fSChaithrika U S int val) 829b4cff454SVipin Bhandari { 830b4cff454SVipin Bhandari u32 temp; 831b4cff454SVipin Bhandari 832b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCTL); 83306de845fSChaithrika U S if (val) /* reset */ 83406de845fSChaithrika U S temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 83506de845fSChaithrika U S else /* enable */ 836b4cff454SVipin Bhandari temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 83706de845fSChaithrika U S 838b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCTL); 83906de845fSChaithrika U S udelay(10); 84006de845fSChaithrika U S } 84106de845fSChaithrika U S 84206de845fSChaithrika U S static void 84306de845fSChaithrika U S davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 84406de845fSChaithrika U S { 84506de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 84606de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 847b4cff454SVipin Bhandari } 848b4cff454SVipin Bhandari 849f9db92cbSAlagu Sankar static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) 850f9db92cbSAlagu Sankar { 851f9db92cbSAlagu Sankar struct mmc_davinci_host *host = dev_id; 852f9db92cbSAlagu Sankar unsigned int status; 853f9db92cbSAlagu Sankar 854f9db92cbSAlagu Sankar status = readl(host->base + DAVINCI_SDIOIST); 855f9db92cbSAlagu Sankar if (status & SDIOIST_IOINT) { 856f9db92cbSAlagu Sankar dev_dbg(mmc_dev(host->mmc), 857f9db92cbSAlagu Sankar "SDIO interrupt status %x\n", status); 858f9db92cbSAlagu Sankar writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 859f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 860f9db92cbSAlagu Sankar } 861f9db92cbSAlagu Sankar return IRQ_HANDLED; 862f9db92cbSAlagu Sankar } 863f9db92cbSAlagu Sankar 864b4cff454SVipin Bhandari static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 865b4cff454SVipin Bhandari { 866b4cff454SVipin Bhandari struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 867b4cff454SVipin Bhandari unsigned int status, qstatus; 868b4cff454SVipin Bhandari int end_command = 0; 869b4cff454SVipin Bhandari int end_transfer = 0; 870b4cff454SVipin Bhandari struct mmc_data *data = host->data; 871b4cff454SVipin Bhandari 872b4cff454SVipin Bhandari if (host->cmd == NULL && host->data == NULL) { 873b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 874b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 875b4cff454SVipin Bhandari "Spurious interrupt 0x%04x\n", status); 876b4cff454SVipin Bhandari /* Disable the interrupt from mmcsd */ 877b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 878b4cff454SVipin Bhandari return IRQ_NONE; 879b4cff454SVipin Bhandari } 880b4cff454SVipin Bhandari 881b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 882b4cff454SVipin Bhandari qstatus = status; 883b4cff454SVipin Bhandari 884b4cff454SVipin Bhandari /* handle FIFO first when using PIO for data. 885b4cff454SVipin Bhandari * bytes_left will decrease to zero as I/O progress and status will 886b4cff454SVipin Bhandari * read zero over iteration because this controller status 887b4cff454SVipin Bhandari * register(MMCST0) reports any status only once and it is cleared 888b4cff454SVipin Bhandari * by read. So, it is not unbouned loop even in the case of 889b4cff454SVipin Bhandari * non-dma. 890b4cff454SVipin Bhandari */ 891be7b5622SIdo Yariv if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 892be7b5622SIdo Yariv unsigned long im_val; 893be7b5622SIdo Yariv 894be7b5622SIdo Yariv /* 895be7b5622SIdo Yariv * If interrupts fire during the following loop, they will be 896be7b5622SIdo Yariv * handled by the handler, but the PIC will still buffer these. 897be7b5622SIdo Yariv * As a result, the handler will be called again to serve these 898be7b5622SIdo Yariv * needlessly. In order to avoid these spurious interrupts, 899be7b5622SIdo Yariv * keep interrupts masked during the loop. 900be7b5622SIdo Yariv */ 901be7b5622SIdo Yariv im_val = readl(host->base + DAVINCI_MMCIM); 902be7b5622SIdo Yariv writel(0, host->base + DAVINCI_MMCIM); 903be7b5622SIdo Yariv 904be7b5622SIdo Yariv do { 905b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 906b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 907b4cff454SVipin Bhandari qstatus |= status; 908be7b5622SIdo Yariv } while (host->bytes_left && 909be7b5622SIdo Yariv (status & (MMCST0_DXRDY | MMCST0_DRRDY))); 910be7b5622SIdo Yariv 911be7b5622SIdo Yariv /* 912be7b5622SIdo Yariv * If an interrupt is pending, it is assumed it will fire when 913be7b5622SIdo Yariv * it is unmasked. This assumption is also taken when the MMCIM 914be7b5622SIdo Yariv * is first set. Otherwise, writing to MMCIM after reading the 915be7b5622SIdo Yariv * status is race-prone. 916be7b5622SIdo Yariv */ 917be7b5622SIdo Yariv writel(im_val, host->base + DAVINCI_MMCIM); 918b4cff454SVipin Bhandari } 919b4cff454SVipin Bhandari 920b4cff454SVipin Bhandari if (qstatus & MMCST0_DATDNE) { 921b4cff454SVipin Bhandari /* All blocks sent/received, and CRC checks passed */ 922b4cff454SVipin Bhandari if (data != NULL) { 923b4cff454SVipin Bhandari if ((host->do_dma == 0) && (host->bytes_left > 0)) { 924b4cff454SVipin Bhandari /* if datasize < rw_threshold 925b4cff454SVipin Bhandari * no RX ints are generated 926b4cff454SVipin Bhandari */ 927b4cff454SVipin Bhandari davinci_fifo_data_trans(host, host->bytes_left); 928b4cff454SVipin Bhandari } 929b4cff454SVipin Bhandari end_transfer = 1; 930b4cff454SVipin Bhandari data->bytes_xfered = data->blocks * data->blksz; 931b4cff454SVipin Bhandari } else { 932b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), 933b4cff454SVipin Bhandari "DATDNE with no host->data\n"); 934b4cff454SVipin Bhandari } 935b4cff454SVipin Bhandari } 936b4cff454SVipin Bhandari 937b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRD) { 938b4cff454SVipin Bhandari /* Read data timeout */ 939b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 940b4cff454SVipin Bhandari end_transfer = 1; 941b4cff454SVipin Bhandari 942b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 943b4cff454SVipin Bhandari "read data timeout, status %x\n", 944b4cff454SVipin Bhandari qstatus); 945b4cff454SVipin Bhandari 946b4cff454SVipin Bhandari davinci_abort_data(host, data); 947b4cff454SVipin Bhandari } 948b4cff454SVipin Bhandari 949b4cff454SVipin Bhandari if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 950b4cff454SVipin Bhandari /* Data CRC error */ 951b4cff454SVipin Bhandari data->error = -EILSEQ; 952b4cff454SVipin Bhandari end_transfer = 1; 953b4cff454SVipin Bhandari 954b4cff454SVipin Bhandari /* NOTE: this controller uses CRCWR to report both CRC 955b4cff454SVipin Bhandari * errors and timeouts (on writes). MMCDRSP values are 956b4cff454SVipin Bhandari * only weakly documented, but 0x9f was clearly a timeout 957b4cff454SVipin Bhandari * case and the two three-bit patterns in various SD specs 958b4cff454SVipin Bhandari * (101, 010) aren't part of it ... 959b4cff454SVipin Bhandari */ 960b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCWR) { 961b4cff454SVipin Bhandari u32 temp = readb(host->base + DAVINCI_MMCDRSP); 962b4cff454SVipin Bhandari 963b4cff454SVipin Bhandari if (temp == 0x9f) 964b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 965b4cff454SVipin Bhandari } 966b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 967b4cff454SVipin Bhandari (qstatus & MMCST0_CRCWR) ? "write" : "read", 968b4cff454SVipin Bhandari (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 969b4cff454SVipin Bhandari 970b4cff454SVipin Bhandari davinci_abort_data(host, data); 971b4cff454SVipin Bhandari } 972b4cff454SVipin Bhandari 973b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRS) { 974b4cff454SVipin Bhandari /* Command timeout */ 975b4cff454SVipin Bhandari if (host->cmd) { 976b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 977b4cff454SVipin Bhandari "CMD%d timeout, status %x\n", 978b4cff454SVipin Bhandari host->cmd->opcode, qstatus); 979b4cff454SVipin Bhandari host->cmd->error = -ETIMEDOUT; 980b4cff454SVipin Bhandari if (data) { 981b4cff454SVipin Bhandari end_transfer = 1; 982b4cff454SVipin Bhandari davinci_abort_data(host, data); 983b4cff454SVipin Bhandari } else 984b4cff454SVipin Bhandari end_command = 1; 985b4cff454SVipin Bhandari } 986b4cff454SVipin Bhandari } 987b4cff454SVipin Bhandari 988b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCRS) { 989b4cff454SVipin Bhandari /* Command CRC error */ 990b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 991b4cff454SVipin Bhandari if (host->cmd) { 992b4cff454SVipin Bhandari host->cmd->error = -EILSEQ; 993b4cff454SVipin Bhandari end_command = 1; 994b4cff454SVipin Bhandari } 995b4cff454SVipin Bhandari } 996b4cff454SVipin Bhandari 997b4cff454SVipin Bhandari if (qstatus & MMCST0_RSPDNE) { 998b4cff454SVipin Bhandari /* End of command phase */ 9998c7f51efSKrzysztof Kozlowski end_command = host->cmd ? 1 : 0; 1000b4cff454SVipin Bhandari } 1001b4cff454SVipin Bhandari 1002b4cff454SVipin Bhandari if (end_command) 1003b4cff454SVipin Bhandari mmc_davinci_cmd_done(host, host->cmd); 1004b4cff454SVipin Bhandari if (end_transfer) 1005b4cff454SVipin Bhandari mmc_davinci_xfer_done(host, data); 1006b4cff454SVipin Bhandari return IRQ_HANDLED; 1007b4cff454SVipin Bhandari } 1008b4cff454SVipin Bhandari 1009b4cff454SVipin Bhandari static int mmc_davinci_get_cd(struct mmc_host *mmc) 1010b4cff454SVipin Bhandari { 1011b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1012b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1013b4cff454SVipin Bhandari 1014c8301e79Sahaslam@baylibre.com if (config && config->get_cd) 1015b4cff454SVipin Bhandari return config->get_cd(pdev->id); 1016c8301e79Sahaslam@baylibre.com 1017c8301e79Sahaslam@baylibre.com return mmc_gpio_get_cd(mmc); 1018b4cff454SVipin Bhandari } 1019b4cff454SVipin Bhandari 1020b4cff454SVipin Bhandari static int mmc_davinci_get_ro(struct mmc_host *mmc) 1021b4cff454SVipin Bhandari { 1022b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1023b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1024b4cff454SVipin Bhandari 1025c8301e79Sahaslam@baylibre.com if (config && config->get_ro) 1026b4cff454SVipin Bhandari return config->get_ro(pdev->id); 1027c8301e79Sahaslam@baylibre.com 1028c8301e79Sahaslam@baylibre.com return mmc_gpio_get_ro(mmc); 1029b4cff454SVipin Bhandari } 1030b4cff454SVipin Bhandari 1031f9db92cbSAlagu Sankar static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1032f9db92cbSAlagu Sankar { 1033f9db92cbSAlagu Sankar struct mmc_davinci_host *host = mmc_priv(mmc); 1034f9db92cbSAlagu Sankar 1035f9db92cbSAlagu Sankar if (enable) { 1036f9db92cbSAlagu Sankar if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { 1037f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1038f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 1039f9db92cbSAlagu Sankar } else { 1040f9db92cbSAlagu Sankar host->sdio_int = true; 1041f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) | 1042f9db92cbSAlagu Sankar SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); 1043f9db92cbSAlagu Sankar } 1044f9db92cbSAlagu Sankar } else { 1045f9db92cbSAlagu Sankar host->sdio_int = false; 1046f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, 1047f9db92cbSAlagu Sankar host->base + DAVINCI_SDIOIEN); 1048f9db92cbSAlagu Sankar } 1049f9db92cbSAlagu Sankar } 1050f9db92cbSAlagu Sankar 10512463941fSJulia Lawall static const struct mmc_host_ops mmc_davinci_ops = { 1052b4cff454SVipin Bhandari .request = mmc_davinci_request, 1053b4cff454SVipin Bhandari .set_ios = mmc_davinci_set_ios, 1054b4cff454SVipin Bhandari .get_cd = mmc_davinci_get_cd, 1055b4cff454SVipin Bhandari .get_ro = mmc_davinci_get_ro, 1056f9db92cbSAlagu Sankar .enable_sdio_irq = mmc_davinci_enable_sdio_irq, 1057b4cff454SVipin Bhandari }; 1058b4cff454SVipin Bhandari 1059b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 1060b4cff454SVipin Bhandari 10617e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 10627e30b8deSChaithrika U S static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 10637e30b8deSChaithrika U S unsigned long val, void *data) 10647e30b8deSChaithrika U S { 10657e30b8deSChaithrika U S struct mmc_davinci_host *host; 10667e30b8deSChaithrika U S unsigned int mmc_pclk; 10677e30b8deSChaithrika U S struct mmc_host *mmc; 10687e30b8deSChaithrika U S unsigned long flags; 10697e30b8deSChaithrika U S 10707e30b8deSChaithrika U S host = container_of(nb, struct mmc_davinci_host, freq_transition); 10717e30b8deSChaithrika U S mmc = host->mmc; 10727e30b8deSChaithrika U S mmc_pclk = clk_get_rate(host->clk); 10737e30b8deSChaithrika U S 10747e30b8deSChaithrika U S if (val == CPUFREQ_POSTCHANGE) { 10757e30b8deSChaithrika U S spin_lock_irqsave(&mmc->lock, flags); 10767e30b8deSChaithrika U S host->mmc_input_clk = mmc_pclk; 10777e30b8deSChaithrika U S calculate_clk_divider(mmc, &mmc->ios); 10787e30b8deSChaithrika U S spin_unlock_irqrestore(&mmc->lock, flags); 10797e30b8deSChaithrika U S } 10807e30b8deSChaithrika U S 10817e30b8deSChaithrika U S return 0; 10827e30b8deSChaithrika U S } 10837e30b8deSChaithrika U S 10847e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 10857e30b8deSChaithrika U S { 10867e30b8deSChaithrika U S host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 10877e30b8deSChaithrika U S 10887e30b8deSChaithrika U S return cpufreq_register_notifier(&host->freq_transition, 10897e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 10907e30b8deSChaithrika U S } 10917e30b8deSChaithrika U S 10927e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 10937e30b8deSChaithrika U S { 10947e30b8deSChaithrika U S cpufreq_unregister_notifier(&host->freq_transition, 10957e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 10967e30b8deSChaithrika U S } 10977e30b8deSChaithrika U S #else 10987e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 10997e30b8deSChaithrika U S { 11007e30b8deSChaithrika U S return 0; 11017e30b8deSChaithrika U S } 11027e30b8deSChaithrika U S 11037e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11047e30b8deSChaithrika U S { 11057e30b8deSChaithrika U S } 11067e30b8deSChaithrika U S #endif 11079ce58dd7SArnd Bergmann static void init_mmcsd_host(struct mmc_davinci_host *host) 1108b4cff454SVipin Bhandari { 1109b4cff454SVipin Bhandari 111006de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1111b4cff454SVipin Bhandari 1112b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCCLK); 1113b4cff454SVipin Bhandari writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1114b4cff454SVipin Bhandari 1115b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1116b4cff454SVipin Bhandari writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1117b4cff454SVipin Bhandari 111806de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1119b4cff454SVipin Bhandari } 1120b4cff454SVipin Bhandari 1121ed425fc4SKrzysztof Kozlowski static const struct platform_device_id davinci_mmc_devtype[] = { 1122d7ca4c75SManjunathappa, Prakash { 1123d7ca4c75SManjunathappa, Prakash .name = "dm6441-mmc", 1124d7ca4c75SManjunathappa, Prakash .driver_data = MMC_CTLR_VERSION_1, 1125d7ca4c75SManjunathappa, Prakash }, { 1126d7ca4c75SManjunathappa, Prakash .name = "da830-mmc", 1127d7ca4c75SManjunathappa, Prakash .driver_data = MMC_CTLR_VERSION_2, 1128d7ca4c75SManjunathappa, Prakash }, 1129d7ca4c75SManjunathappa, Prakash {}, 1130d7ca4c75SManjunathappa, Prakash }; 1131d7ca4c75SManjunathappa, Prakash MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype); 1132d7ca4c75SManjunathappa, Prakash 11337b43da4cSManjunathappa, Prakash static const struct of_device_id davinci_mmc_dt_ids[] = { 11347b43da4cSManjunathappa, Prakash { 11357b43da4cSManjunathappa, Prakash .compatible = "ti,dm6441-mmc", 11367b43da4cSManjunathappa, Prakash .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1], 11377b43da4cSManjunathappa, Prakash }, 11387b43da4cSManjunathappa, Prakash { 11397b43da4cSManjunathappa, Prakash .compatible = "ti,da830-mmc", 11407b43da4cSManjunathappa, Prakash .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2], 11417b43da4cSManjunathappa, Prakash }, 11427b43da4cSManjunathappa, Prakash {}, 11437b43da4cSManjunathappa, Prakash }; 11447b43da4cSManjunathappa, Prakash MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids); 11457b43da4cSManjunathappa, Prakash 1146c8301e79Sahaslam@baylibre.com static int mmc_davinci_parse_pdata(struct mmc_host *mmc) 11477b43da4cSManjunathappa, Prakash { 1148c8301e79Sahaslam@baylibre.com struct platform_device *pdev = to_platform_device(mmc->parent); 11497b43da4cSManjunathappa, Prakash struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1150c8301e79Sahaslam@baylibre.com struct mmc_davinci_host *host; 11516e628dadSahaslam@baylibre.com int ret; 11527b43da4cSManjunathappa, Prakash 1153c8301e79Sahaslam@baylibre.com if (!pdata) 1154c8301e79Sahaslam@baylibre.com return -EINVAL; 11557b43da4cSManjunathappa, Prakash 1156c8301e79Sahaslam@baylibre.com host = mmc_priv(mmc); 1157c8301e79Sahaslam@baylibre.com if (!host) 1158c8301e79Sahaslam@baylibre.com return -EINVAL; 11597b43da4cSManjunathappa, Prakash 1160c8301e79Sahaslam@baylibre.com if (pdata && pdata->nr_sg) 1161c8301e79Sahaslam@baylibre.com host->nr_sg = pdata->nr_sg - 1; 11627b43da4cSManjunathappa, Prakash 1163c8301e79Sahaslam@baylibre.com if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1164c8301e79Sahaslam@baylibre.com mmc->caps |= MMC_CAP_4_BIT_DATA; 11657b43da4cSManjunathappa, Prakash 1166c8301e79Sahaslam@baylibre.com if (pdata && (pdata->wires == 8)) 1167c8301e79Sahaslam@baylibre.com mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1168c8301e79Sahaslam@baylibre.com 1169c8301e79Sahaslam@baylibre.com mmc->f_min = 312500; 1170c8301e79Sahaslam@baylibre.com mmc->f_max = 25000000; 1171c8301e79Sahaslam@baylibre.com if (pdata && pdata->max_freq) 1172c8301e79Sahaslam@baylibre.com mmc->f_max = pdata->max_freq; 1173c8301e79Sahaslam@baylibre.com if (pdata && pdata->caps) 1174c8301e79Sahaslam@baylibre.com mmc->caps |= pdata->caps; 1175c8301e79Sahaslam@baylibre.com 11766e628dadSahaslam@baylibre.com /* Register a cd gpio, if there is not one, enable polling */ 1177d0052ad9SMichał Mirosław ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); 11786e628dadSahaslam@baylibre.com if (ret == -EPROBE_DEFER) 11796e628dadSahaslam@baylibre.com return ret; 11806e628dadSahaslam@baylibre.com else if (ret) 11816e628dadSahaslam@baylibre.com mmc->caps |= MMC_CAP_NEEDS_POLL; 11826e628dadSahaslam@baylibre.com 1183d0052ad9SMichał Mirosław ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); 11846e628dadSahaslam@baylibre.com if (ret == -EPROBE_DEFER) 11856e628dadSahaslam@baylibre.com return ret; 11866e628dadSahaslam@baylibre.com 1187c8301e79Sahaslam@baylibre.com return 0; 11887b43da4cSManjunathappa, Prakash } 11897b43da4cSManjunathappa, Prakash 11906478f4e1SDavid Lechner static int davinci_mmcsd_probe(struct platform_device *pdev) 1191b4cff454SVipin Bhandari { 1192c8301e79Sahaslam@baylibre.com const struct of_device_id *match; 1193b4cff454SVipin Bhandari struct mmc_davinci_host *host = NULL; 1194b4cff454SVipin Bhandari struct mmc_host *mmc = NULL; 1195b4cff454SVipin Bhandari struct resource *r, *mem = NULL; 119662ac52b2SDavid Lechner int ret, irq; 1197b4cff454SVipin Bhandari size_t mem_size; 1198d7ca4c75SManjunathappa, Prakash const struct platform_device_id *id_entry; 1199b4cff454SVipin Bhandari 1200b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1201902a8a0bSArnd Bergmann if (!r) 120262ac52b2SDavid Lechner return -ENODEV; 1203902a8a0bSArnd Bergmann irq = platform_get_irq(pdev, 0); 1204902a8a0bSArnd Bergmann if (irq < 0) 1205902a8a0bSArnd Bergmann return irq; 1206b4cff454SVipin Bhandari 1207b4cff454SVipin Bhandari mem_size = resource_size(r); 120862ac52b2SDavid Lechner mem = devm_request_mem_region(&pdev->dev, r->start, mem_size, 120962ac52b2SDavid Lechner pdev->name); 1210b4cff454SVipin Bhandari if (!mem) 121162ac52b2SDavid Lechner return -EBUSY; 1212b4cff454SVipin Bhandari 1213b4cff454SVipin Bhandari mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1214b4cff454SVipin Bhandari if (!mmc) 121562ac52b2SDavid Lechner return -ENOMEM; 1216b4cff454SVipin Bhandari 1217b4cff454SVipin Bhandari host = mmc_priv(mmc); 1218b4cff454SVipin Bhandari host->mmc = mmc; /* Important */ 1219b4cff454SVipin Bhandari 1220b4cff454SVipin Bhandari host->mem_res = mem; 122162ac52b2SDavid Lechner host->base = devm_ioremap(&pdev->dev, mem->start, mem_size); 122262ac52b2SDavid Lechner if (!host->base) { 122362ac52b2SDavid Lechner ret = -ENOMEM; 122462ac52b2SDavid Lechner goto ioremap_fail; 122562ac52b2SDavid Lechner } 1226b4cff454SVipin Bhandari 122762ac52b2SDavid Lechner host->clk = devm_clk_get(&pdev->dev, NULL); 1228b4cff454SVipin Bhandari if (IS_ERR(host->clk)) { 1229b4cff454SVipin Bhandari ret = PTR_ERR(host->clk); 123062ac52b2SDavid Lechner goto clk_get_fail; 1231b4cff454SVipin Bhandari } 1232e2f3bfbdSDavid Lechner ret = clk_prepare_enable(host->clk); 123362ac52b2SDavid Lechner if (ret) 1234e2f3bfbdSDavid Lechner goto clk_prepare_enable_fail; 123562ac52b2SDavid Lechner 1236b4cff454SVipin Bhandari host->mmc_input_clk = clk_get_rate(host->clk); 1237b4cff454SVipin Bhandari 1238c8301e79Sahaslam@baylibre.com match = of_match_device(davinci_mmc_dt_ids, &pdev->dev); 1239c8301e79Sahaslam@baylibre.com if (match) { 1240c8301e79Sahaslam@baylibre.com pdev->id_entry = match->data; 1241c8301e79Sahaslam@baylibre.com ret = mmc_of_parse(mmc); 1242c8301e79Sahaslam@baylibre.com if (ret) { 12433a35e7e1SKrzysztof Kozlowski dev_err_probe(&pdev->dev, ret, 12443a35e7e1SKrzysztof Kozlowski "could not parse of data\n"); 1245c8301e79Sahaslam@baylibre.com goto parse_fail; 1246c8301e79Sahaslam@baylibre.com } 1247c8301e79Sahaslam@baylibre.com } else { 1248c8301e79Sahaslam@baylibre.com ret = mmc_davinci_parse_pdata(mmc); 1249c8301e79Sahaslam@baylibre.com if (ret) { 1250c8301e79Sahaslam@baylibre.com dev_err(&pdev->dev, 1251c8301e79Sahaslam@baylibre.com "could not parse platform data: %d\n", ret); 1252c8301e79Sahaslam@baylibre.com goto parse_fail; 1253c8301e79Sahaslam@baylibre.com } } 1254ca2afb6dSSudhakar Rajashekhara 1255ca2afb6dSSudhakar Rajashekhara if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1256ca2afb6dSSudhakar Rajashekhara host->nr_sg = MAX_NR_SG; 1257ca2afb6dSSudhakar Rajashekhara 1258c8301e79Sahaslam@baylibre.com init_mmcsd_host(host); 1259c8301e79Sahaslam@baylibre.com 1260b4cff454SVipin Bhandari host->use_dma = use_dma; 1261f9db92cbSAlagu Sankar host->mmc_irq = irq; 1262f9db92cbSAlagu Sankar host->sdio_irq = platform_get_irq(pdev, 1); 1263b4cff454SVipin Bhandari 12640a4d7236SPeter Ujfalusi if (host->use_dma) { 12650a4d7236SPeter Ujfalusi ret = davinci_acquire_dma_channels(host); 12660a4d7236SPeter Ujfalusi if (ret == -EPROBE_DEFER) 126762ac52b2SDavid Lechner goto dma_probe_defer; 12680a4d7236SPeter Ujfalusi else if (ret) 1269b4cff454SVipin Bhandari host->use_dma = 0; 12700a4d7236SPeter Ujfalusi } 1271b4cff454SVipin Bhandari 1272132f1074SVipin Bhandari mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1273b4cff454SVipin Bhandari 1274d7ca4c75SManjunathappa, Prakash id_entry = platform_get_device_id(pdev); 1275d7ca4c75SManjunathappa, Prakash if (id_entry) 1276d7ca4c75SManjunathappa, Prakash host->version = id_entry->driver_data; 1277b4cff454SVipin Bhandari 1278b4cff454SVipin Bhandari mmc->ops = &mmc_davinci_ops; 1279b4cff454SVipin Bhandari mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1280b4cff454SVipin Bhandari 1281b4cff454SVipin Bhandari /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1282b4cff454SVipin Bhandari * Each hw_seg uses one EDMA parameter RAM slot, always one 1283b4cff454SVipin Bhandari * channel and then usually some linked slots. 1284b4cff454SVipin Bhandari */ 12855413da81SMatt Porter mmc->max_segs = MAX_NR_SG; 1286b4cff454SVipin Bhandari 1287b4cff454SVipin Bhandari /* EDMA limit per hw segment (one or two MBytes) */ 1288b4cff454SVipin Bhandari mmc->max_seg_size = MAX_CCNT * rw_threshold; 1289b4cff454SVipin Bhandari 1290b4cff454SVipin Bhandari /* MMC/SD controller limits for multiblock requests */ 1291b4cff454SVipin Bhandari mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1292b4cff454SVipin Bhandari mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1293b4cff454SVipin Bhandari mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1294b4cff454SVipin Bhandari 1295a36274e0SMartin K. Petersen dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1296b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1297b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1298b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1299b4cff454SVipin Bhandari 1300b4cff454SVipin Bhandari platform_set_drvdata(pdev, host); 1301b4cff454SVipin Bhandari 13027e30b8deSChaithrika U S ret = mmc_davinci_cpufreq_register(host); 13037e30b8deSChaithrika U S if (ret) { 13047e30b8deSChaithrika U S dev_err(&pdev->dev, "failed to register cpufreq\n"); 13057e30b8deSChaithrika U S goto cpu_freq_fail; 13067e30b8deSChaithrika U S } 13077e30b8deSChaithrika U S 1308b4cff454SVipin Bhandari ret = mmc_add_host(mmc); 1309b4cff454SVipin Bhandari if (ret < 0) 131062ac52b2SDavid Lechner goto mmc_add_host_fail; 1311b4cff454SVipin Bhandari 131262ac52b2SDavid Lechner ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0, 131362ac52b2SDavid Lechner mmc_hostname(mmc), host); 1314b4cff454SVipin Bhandari if (ret) 131562ac52b2SDavid Lechner goto request_irq_fail; 1316b4cff454SVipin Bhandari 1317f9db92cbSAlagu Sankar if (host->sdio_irq >= 0) { 131862ac52b2SDavid Lechner ret = devm_request_irq(&pdev->dev, host->sdio_irq, 131962ac52b2SDavid Lechner mmc_davinci_sdio_irq, 0, 1320f9db92cbSAlagu Sankar mmc_hostname(mmc), host); 1321f9db92cbSAlagu Sankar if (!ret) 1322f9db92cbSAlagu Sankar mmc->caps |= MMC_CAP_SDIO_IRQ; 1323f9db92cbSAlagu Sankar } 1324f9db92cbSAlagu Sankar 1325b4cff454SVipin Bhandari rename_region(mem, mmc_hostname(mmc)); 1326b4cff454SVipin Bhandari 1327b4cff454SVipin Bhandari dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1328b4cff454SVipin Bhandari host->use_dma ? "DMA" : "PIO", 1329b4cff454SVipin Bhandari (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1330b4cff454SVipin Bhandari 1331b4cff454SVipin Bhandari return 0; 1332b4cff454SVipin Bhandari 133362ac52b2SDavid Lechner request_irq_fail: 133462ac52b2SDavid Lechner mmc_remove_host(mmc); 133562ac52b2SDavid Lechner mmc_add_host_fail: 13367e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 13377e30b8deSChaithrika U S cpu_freq_fail: 1338b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1339c8301e79Sahaslam@baylibre.com parse_fail: 134062ac52b2SDavid Lechner dma_probe_defer: 1341e2f3bfbdSDavid Lechner clk_disable_unprepare(host->clk); 1342e2f3bfbdSDavid Lechner clk_prepare_enable_fail: 134362ac52b2SDavid Lechner clk_get_fail: 134462ac52b2SDavid Lechner ioremap_fail: 1345b4cff454SVipin Bhandari mmc_free_host(mmc); 1346b4cff454SVipin Bhandari 1347b4cff454SVipin Bhandari return ret; 1348b4cff454SVipin Bhandari } 1349b4cff454SVipin Bhandari 1350b4cff454SVipin Bhandari static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1351b4cff454SVipin Bhandari { 1352b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1353b4cff454SVipin Bhandari 1354b4cff454SVipin Bhandari mmc_remove_host(host->mmc); 135562ac52b2SDavid Lechner mmc_davinci_cpufreq_deregister(host); 1356b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1357e2f3bfbdSDavid Lechner clk_disable_unprepare(host->clk); 1358b4cff454SVipin Bhandari mmc_free_host(host->mmc); 1359b4cff454SVipin Bhandari 1360b4cff454SVipin Bhandari return 0; 1361b4cff454SVipin Bhandari } 1362b4cff454SVipin Bhandari 1363b4cff454SVipin Bhandari #ifdef CONFIG_PM 1364bbce5802SChaithrika U S static int davinci_mmcsd_suspend(struct device *dev) 1365b4cff454SVipin Bhandari { 1366970f2d90SWolfram Sang struct mmc_davinci_host *host = dev_get_drvdata(dev); 1367b4cff454SVipin Bhandari 1368bbce5802SChaithrika U S writel(0, host->base + DAVINCI_MMCIM); 1369bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1370bbce5802SChaithrika U S clk_disable(host->clk); 1371b4cff454SVipin Bhandari 13725ffdeea5SUlf Hansson return 0; 1373b4cff454SVipin Bhandari } 1374bbce5802SChaithrika U S 1375bbce5802SChaithrika U S static int davinci_mmcsd_resume(struct device *dev) 1376bbce5802SChaithrika U S { 1377970f2d90SWolfram Sang struct mmc_davinci_host *host = dev_get_drvdata(dev); 1378bbce5802SChaithrika U S 1379bbce5802SChaithrika U S clk_enable(host->clk); 1380bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1381bbce5802SChaithrika U S 13825ffdeea5SUlf Hansson return 0; 1383bbce5802SChaithrika U S } 1384bbce5802SChaithrika U S 1385bbce5802SChaithrika U S static const struct dev_pm_ops davinci_mmcsd_pm = { 1386bbce5802SChaithrika U S .suspend = davinci_mmcsd_suspend, 1387bbce5802SChaithrika U S .resume = davinci_mmcsd_resume, 1388bbce5802SChaithrika U S }; 1389bbce5802SChaithrika U S 1390bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1391b4cff454SVipin Bhandari #else 1392bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops NULL 1393b4cff454SVipin Bhandari #endif 1394b4cff454SVipin Bhandari 1395b4cff454SVipin Bhandari static struct platform_driver davinci_mmcsd_driver = { 1396b4cff454SVipin Bhandari .driver = { 1397b4cff454SVipin Bhandari .name = "davinci_mmc", 1398bbce5802SChaithrika U S .pm = davinci_mmcsd_pm_ops, 13996fad5128SSachin Kamat .of_match_table = davinci_mmc_dt_ids, 1400b4cff454SVipin Bhandari }, 14016478f4e1SDavid Lechner .probe = davinci_mmcsd_probe, 1402b4cff454SVipin Bhandari .remove = __exit_p(davinci_mmcsd_remove), 1403d7ca4c75SManjunathappa, Prakash .id_table = davinci_mmc_devtype, 1404b4cff454SVipin Bhandari }; 1405b4cff454SVipin Bhandari 14066478f4e1SDavid Lechner module_platform_driver(davinci_mmcsd_driver); 1407b4cff454SVipin Bhandari 1408b4cff454SVipin Bhandari MODULE_AUTHOR("Texas Instruments India"); 1409b4cff454SVipin Bhandari MODULE_LICENSE("GPL"); 1410b4cff454SVipin Bhandari MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 14117f8bea7fSJan Luebbe MODULE_ALIAS("platform:davinci_mmc"); 1412b4cff454SVipin Bhandari 1413