1b4cff454SVipin Bhandari /* 2b4cff454SVipin Bhandari * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3b4cff454SVipin Bhandari * 4b4cff454SVipin Bhandari * Copyright (C) 2006 Texas Instruments. 5b4cff454SVipin Bhandari * Original author: Purushotam Kumar 6b4cff454SVipin Bhandari * Copyright (C) 2009 David Brownell 7b4cff454SVipin Bhandari * 8b4cff454SVipin Bhandari * This program is free software; you can redistribute it and/or modify 9b4cff454SVipin Bhandari * it under the terms of the GNU General Public License as published by 10b4cff454SVipin Bhandari * the Free Software Foundation; either version 2 of the License, or 11b4cff454SVipin Bhandari * (at your option) any later version. 12b4cff454SVipin Bhandari * 13b4cff454SVipin Bhandari * This program is distributed in the hope that it will be useful, 14b4cff454SVipin Bhandari * but WITHOUT ANY WARRANTY; without even the implied warranty of 15b4cff454SVipin Bhandari * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16b4cff454SVipin Bhandari * GNU General Public License for more details. 17b4cff454SVipin Bhandari * 18b4cff454SVipin Bhandari * You should have received a copy of the GNU General Public License 19b4cff454SVipin Bhandari * along with this program; if not, write to the Free Software 20b4cff454SVipin Bhandari * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21b4cff454SVipin Bhandari */ 22b4cff454SVipin Bhandari 23b4cff454SVipin Bhandari #include <linux/module.h> 24b4cff454SVipin Bhandari #include <linux/ioport.h> 25b4cff454SVipin Bhandari #include <linux/platform_device.h> 26b4cff454SVipin Bhandari #include <linux/clk.h> 27b4cff454SVipin Bhandari #include <linux/err.h> 287e30b8deSChaithrika U S #include <linux/cpufreq.h> 29b4cff454SVipin Bhandari #include <linux/mmc/host.h> 30b4cff454SVipin Bhandari #include <linux/io.h> 31b4cff454SVipin Bhandari #include <linux/irq.h> 32b4cff454SVipin Bhandari #include <linux/delay.h> 33b4cff454SVipin Bhandari #include <linux/dma-mapping.h> 34b4cff454SVipin Bhandari #include <linux/mmc/mmc.h> 35b4cff454SVipin Bhandari 36b4cff454SVipin Bhandari #include <mach/mmc.h> 37b4cff454SVipin Bhandari #include <mach/edma.h> 38b4cff454SVipin Bhandari 39b4cff454SVipin Bhandari /* 40b4cff454SVipin Bhandari * Register Definitions 41b4cff454SVipin Bhandari */ 42b4cff454SVipin Bhandari #define DAVINCI_MMCCTL 0x00 /* Control Register */ 43b4cff454SVipin Bhandari #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 44b4cff454SVipin Bhandari #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 45b4cff454SVipin Bhandari #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 46b4cff454SVipin Bhandari #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 47b4cff454SVipin Bhandari #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 48b4cff454SVipin Bhandari #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 49b4cff454SVipin Bhandari #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 50b4cff454SVipin Bhandari #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 51b4cff454SVipin Bhandari #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 52b4cff454SVipin Bhandari #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 53b4cff454SVipin Bhandari #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 54b4cff454SVipin Bhandari #define DAVINCI_MMCCMD 0x30 /* Command Register */ 55b4cff454SVipin Bhandari #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 56b4cff454SVipin Bhandari #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 57b4cff454SVipin Bhandari #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 58b4cff454SVipin Bhandari #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 59b4cff454SVipin Bhandari #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 60b4cff454SVipin Bhandari #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 61b4cff454SVipin Bhandari #define DAVINCI_MMCETOK 0x4C 62b4cff454SVipin Bhandari #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 63b4cff454SVipin Bhandari #define DAVINCI_MMCCKC 0x54 64b4cff454SVipin Bhandari #define DAVINCI_MMCTORC 0x58 65b4cff454SVipin Bhandari #define DAVINCI_MMCTODC 0x5C 66b4cff454SVipin Bhandari #define DAVINCI_MMCBLNC 0x60 67b4cff454SVipin Bhandari #define DAVINCI_SDIOCTL 0x64 68b4cff454SVipin Bhandari #define DAVINCI_SDIOST0 0x68 69f9db92cbSAlagu Sankar #define DAVINCI_SDIOIEN 0x6C 70f9db92cbSAlagu Sankar #define DAVINCI_SDIOIST 0x70 71b4cff454SVipin Bhandari #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 72b4cff454SVipin Bhandari 73b4cff454SVipin Bhandari /* DAVINCI_MMCCTL definitions */ 74b4cff454SVipin Bhandari #define MMCCTL_DATRST (1 << 0) 75b4cff454SVipin Bhandari #define MMCCTL_CMDRST (1 << 1) 76132f1074SVipin Bhandari #define MMCCTL_WIDTH_8_BIT (1 << 8) 77b4cff454SVipin Bhandari #define MMCCTL_WIDTH_4_BIT (1 << 2) 78b4cff454SVipin Bhandari #define MMCCTL_DATEG_DISABLED (0 << 6) 79b4cff454SVipin Bhandari #define MMCCTL_DATEG_RISING (1 << 6) 80b4cff454SVipin Bhandari #define MMCCTL_DATEG_FALLING (2 << 6) 81b4cff454SVipin Bhandari #define MMCCTL_DATEG_BOTH (3 << 6) 82b4cff454SVipin Bhandari #define MMCCTL_PERMDR_LE (0 << 9) 83b4cff454SVipin Bhandari #define MMCCTL_PERMDR_BE (1 << 9) 84b4cff454SVipin Bhandari #define MMCCTL_PERMDX_LE (0 << 10) 85b4cff454SVipin Bhandari #define MMCCTL_PERMDX_BE (1 << 10) 86b4cff454SVipin Bhandari 87b4cff454SVipin Bhandari /* DAVINCI_MMCCLK definitions */ 88b4cff454SVipin Bhandari #define MMCCLK_CLKEN (1 << 8) 89b4cff454SVipin Bhandari #define MMCCLK_CLKRT_MASK (0xFF << 0) 90b4cff454SVipin Bhandari 91b4cff454SVipin Bhandari /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 92b4cff454SVipin Bhandari #define MMCST0_DATDNE BIT(0) /* data done */ 93b4cff454SVipin Bhandari #define MMCST0_BSYDNE BIT(1) /* busy done */ 94b4cff454SVipin Bhandari #define MMCST0_RSPDNE BIT(2) /* command done */ 95b4cff454SVipin Bhandari #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 96b4cff454SVipin Bhandari #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 97b4cff454SVipin Bhandari #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 98b4cff454SVipin Bhandari #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 99b4cff454SVipin Bhandari #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 100b4cff454SVipin Bhandari #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 101b4cff454SVipin Bhandari #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 102b4cff454SVipin Bhandari #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 103b4cff454SVipin Bhandari #define MMCST0_TRNDNE BIT(12) /* transfer done */ 104b4cff454SVipin Bhandari 105b4cff454SVipin Bhandari /* DAVINCI_MMCST1 definitions */ 106b4cff454SVipin Bhandari #define MMCST1_BUSY (1 << 0) 107b4cff454SVipin Bhandari 108b4cff454SVipin Bhandari /* DAVINCI_MMCCMD definitions */ 109b4cff454SVipin Bhandari #define MMCCMD_CMD_MASK (0x3F << 0) 110b4cff454SVipin Bhandari #define MMCCMD_PPLEN (1 << 7) 111b4cff454SVipin Bhandari #define MMCCMD_BSYEXP (1 << 8) 112b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_MASK (3 << 9) 113b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_NONE (0 << 9) 114b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R1456 (1 << 9) 115b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R2 (2 << 9) 116b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R3 (3 << 9) 117b4cff454SVipin Bhandari #define MMCCMD_DTRW (1 << 11) 118b4cff454SVipin Bhandari #define MMCCMD_STRMTP (1 << 12) 119b4cff454SVipin Bhandari #define MMCCMD_WDATX (1 << 13) 120b4cff454SVipin Bhandari #define MMCCMD_INITCK (1 << 14) 121b4cff454SVipin Bhandari #define MMCCMD_DCLR (1 << 15) 122b4cff454SVipin Bhandari #define MMCCMD_DMATRIG (1 << 16) 123b4cff454SVipin Bhandari 124b4cff454SVipin Bhandari /* DAVINCI_MMCFIFOCTL definitions */ 125b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFORST (1 << 0) 126b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 127b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 128b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 129b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 130b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 131b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 132b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 133b4cff454SVipin Bhandari 134f9db92cbSAlagu Sankar /* DAVINCI_SDIOST0 definitions */ 135f9db92cbSAlagu Sankar #define SDIOST0_DAT1_HI BIT(0) 136f9db92cbSAlagu Sankar 137f9db92cbSAlagu Sankar /* DAVINCI_SDIOIEN definitions */ 138f9db92cbSAlagu Sankar #define SDIOIEN_IOINTEN BIT(0) 139f9db92cbSAlagu Sankar 140f9db92cbSAlagu Sankar /* DAVINCI_SDIOIST definitions */ 141f9db92cbSAlagu Sankar #define SDIOIST_IOINT BIT(0) 142b4cff454SVipin Bhandari 143b4cff454SVipin Bhandari /* MMCSD Init clock in Hz in opendrain mode */ 144b4cff454SVipin Bhandari #define MMCSD_INIT_CLOCK 200000 145b4cff454SVipin Bhandari 146b4cff454SVipin Bhandari /* 147b4cff454SVipin Bhandari * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 148ca2afb6dSSudhakar Rajashekhara * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 149a36274e0SMartin K. Petersen * for drivers with max_segs == 1, making the segments bigger (64KB) 150ca2afb6dSSudhakar Rajashekhara * than the page or two that's otherwise typical. nr_sg (passed from 151ca2afb6dSSudhakar Rajashekhara * platform data) == 16 gives at least the same throughput boost, using 152ca2afb6dSSudhakar Rajashekhara * EDMA transfer linkage instead of spending CPU time copying pages. 153b4cff454SVipin Bhandari */ 154b4cff454SVipin Bhandari #define MAX_CCNT ((1 << 16) - 1) 155b4cff454SVipin Bhandari 156ca2afb6dSSudhakar Rajashekhara #define MAX_NR_SG 16 157b4cff454SVipin Bhandari 158b4cff454SVipin Bhandari static unsigned rw_threshold = 32; 159b4cff454SVipin Bhandari module_param(rw_threshold, uint, S_IRUGO); 160b4cff454SVipin Bhandari MODULE_PARM_DESC(rw_threshold, 161b4cff454SVipin Bhandari "Read/Write threshold. Default = 32"); 162b4cff454SVipin Bhandari 163ee698f50SIdo Yariv static unsigned poll_threshold = 128; 164ee698f50SIdo Yariv module_param(poll_threshold, uint, S_IRUGO); 165ee698f50SIdo Yariv MODULE_PARM_DESC(poll_threshold, 166ee698f50SIdo Yariv "Polling transaction size threshold. Default = 128"); 167ee698f50SIdo Yariv 168ee698f50SIdo Yariv static unsigned poll_loopcount = 32; 169ee698f50SIdo Yariv module_param(poll_loopcount, uint, S_IRUGO); 170ee698f50SIdo Yariv MODULE_PARM_DESC(poll_loopcount, 171ee698f50SIdo Yariv "Maximum polling loop count. Default = 32"); 172ee698f50SIdo Yariv 173b4cff454SVipin Bhandari static unsigned __initdata use_dma = 1; 174b4cff454SVipin Bhandari module_param(use_dma, uint, 0); 175b4cff454SVipin Bhandari MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 176b4cff454SVipin Bhandari 177b4cff454SVipin Bhandari struct mmc_davinci_host { 178b4cff454SVipin Bhandari struct mmc_command *cmd; 179b4cff454SVipin Bhandari struct mmc_data *data; 180b4cff454SVipin Bhandari struct mmc_host *mmc; 181b4cff454SVipin Bhandari struct clk *clk; 182b4cff454SVipin Bhandari unsigned int mmc_input_clk; 183b4cff454SVipin Bhandari void __iomem *base; 184b4cff454SVipin Bhandari struct resource *mem_res; 185f9db92cbSAlagu Sankar int mmc_irq, sdio_irq; 186b4cff454SVipin Bhandari unsigned char bus_mode; 187b4cff454SVipin Bhandari 188b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_NONE 0 189b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_READ 1 190b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_WRITE 2 191b4cff454SVipin Bhandari unsigned char data_dir; 192bbce5802SChaithrika U S unsigned char suspended; 193b4cff454SVipin Bhandari 194b4cff454SVipin Bhandari /* buffer is used during PIO of one scatterlist segment, and 195b4cff454SVipin Bhandari * is updated along with buffer_bytes_left. bytes_left applies 196b4cff454SVipin Bhandari * to all N blocks of the PIO transfer. 197b4cff454SVipin Bhandari */ 198b4cff454SVipin Bhandari u8 *buffer; 199b4cff454SVipin Bhandari u32 buffer_bytes_left; 200b4cff454SVipin Bhandari u32 bytes_left; 201b4cff454SVipin Bhandari 2023d348aafSSudhakar Rajashekhara u32 rxdma, txdma; 203b4cff454SVipin Bhandari bool use_dma; 204b4cff454SVipin Bhandari bool do_dma; 205f9db92cbSAlagu Sankar bool sdio_int; 206ee698f50SIdo Yariv bool active_request; 207b4cff454SVipin Bhandari 208b4cff454SVipin Bhandari /* Scatterlist DMA uses one or more parameter RAM entries: 209b4cff454SVipin Bhandari * the main one (associated with rxdma or txdma) plus zero or 210b4cff454SVipin Bhandari * more links. The entries for a given transfer differ only 211b4cff454SVipin Bhandari * by memory buffer (address, length) and link field. 212b4cff454SVipin Bhandari */ 213b4cff454SVipin Bhandari struct edmacc_param tx_template; 214b4cff454SVipin Bhandari struct edmacc_param rx_template; 215b4cff454SVipin Bhandari unsigned n_link; 216ca2afb6dSSudhakar Rajashekhara u32 links[MAX_NR_SG - 1]; 217b4cff454SVipin Bhandari 218b4cff454SVipin Bhandari /* For PIO we walk scatterlists one segment at a time. */ 219b4cff454SVipin Bhandari unsigned int sg_len; 220b4cff454SVipin Bhandari struct scatterlist *sg; 221b4cff454SVipin Bhandari 222b4cff454SVipin Bhandari /* Version of the MMC/SD controller */ 223b4cff454SVipin Bhandari u8 version; 224b4cff454SVipin Bhandari /* for ns in one cycle calculation */ 225b4cff454SVipin Bhandari unsigned ns_in_one_cycle; 226ca2afb6dSSudhakar Rajashekhara /* Number of sg segments */ 227ca2afb6dSSudhakar Rajashekhara u8 nr_sg; 2287e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 2297e30b8deSChaithrika U S struct notifier_block freq_transition; 2307e30b8deSChaithrika U S #endif 231b4cff454SVipin Bhandari }; 232b4cff454SVipin Bhandari 233ee698f50SIdo Yariv static irqreturn_t mmc_davinci_irq(int irq, void *dev_id); 234b4cff454SVipin Bhandari 235b4cff454SVipin Bhandari /* PIO only */ 236b4cff454SVipin Bhandari static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 237b4cff454SVipin Bhandari { 238b4cff454SVipin Bhandari host->buffer_bytes_left = sg_dma_len(host->sg); 239b4cff454SVipin Bhandari host->buffer = sg_virt(host->sg); 240b4cff454SVipin Bhandari if (host->buffer_bytes_left > host->bytes_left) 241b4cff454SVipin Bhandari host->buffer_bytes_left = host->bytes_left; 242b4cff454SVipin Bhandari } 243b4cff454SVipin Bhandari 244b4cff454SVipin Bhandari static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 245b4cff454SVipin Bhandari unsigned int n) 246b4cff454SVipin Bhandari { 247b4cff454SVipin Bhandari u8 *p; 248b4cff454SVipin Bhandari unsigned int i; 249b4cff454SVipin Bhandari 250b4cff454SVipin Bhandari if (host->buffer_bytes_left == 0) { 251b4cff454SVipin Bhandari host->sg = sg_next(host->data->sg); 252b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 253b4cff454SVipin Bhandari } 254b4cff454SVipin Bhandari 255b4cff454SVipin Bhandari p = host->buffer; 256b4cff454SVipin Bhandari if (n > host->buffer_bytes_left) 257b4cff454SVipin Bhandari n = host->buffer_bytes_left; 258b4cff454SVipin Bhandari host->buffer_bytes_left -= n; 259b4cff454SVipin Bhandari host->bytes_left -= n; 260b4cff454SVipin Bhandari 261b4cff454SVipin Bhandari /* NOTE: we never transfer more than rw_threshold bytes 262b4cff454SVipin Bhandari * to/from the fifo here; there's no I/O overlap. 263b4cff454SVipin Bhandari * This also assumes that access width( i.e. ACCWD) is 4 bytes 264b4cff454SVipin Bhandari */ 265b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 266b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 267b4cff454SVipin Bhandari writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 268b4cff454SVipin Bhandari p = p + 4; 269b4cff454SVipin Bhandari } 270b4cff454SVipin Bhandari if (n & 3) { 271b4cff454SVipin Bhandari iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 272b4cff454SVipin Bhandari p = p + (n & 3); 273b4cff454SVipin Bhandari } 274b4cff454SVipin Bhandari } else { 275b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 276b4cff454SVipin Bhandari *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 277b4cff454SVipin Bhandari p = p + 4; 278b4cff454SVipin Bhandari } 279b4cff454SVipin Bhandari if (n & 3) { 280b4cff454SVipin Bhandari ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 281b4cff454SVipin Bhandari p = p + (n & 3); 282b4cff454SVipin Bhandari } 283b4cff454SVipin Bhandari } 284b4cff454SVipin Bhandari host->buffer = p; 285b4cff454SVipin Bhandari } 286b4cff454SVipin Bhandari 287b4cff454SVipin Bhandari static void mmc_davinci_start_command(struct mmc_davinci_host *host, 288b4cff454SVipin Bhandari struct mmc_command *cmd) 289b4cff454SVipin Bhandari { 290b4cff454SVipin Bhandari u32 cmd_reg = 0; 291b4cff454SVipin Bhandari u32 im_val; 292b4cff454SVipin Bhandari 293b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 294b4cff454SVipin Bhandari cmd->opcode, cmd->arg, 295b4cff454SVipin Bhandari ({ char *s; 296b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 297b4cff454SVipin Bhandari case MMC_RSP_R1: 298b4cff454SVipin Bhandari s = ", R1/R5/R6/R7 response"; 299b4cff454SVipin Bhandari break; 300b4cff454SVipin Bhandari case MMC_RSP_R1B: 301b4cff454SVipin Bhandari s = ", R1b response"; 302b4cff454SVipin Bhandari break; 303b4cff454SVipin Bhandari case MMC_RSP_R2: 304b4cff454SVipin Bhandari s = ", R2 response"; 305b4cff454SVipin Bhandari break; 306b4cff454SVipin Bhandari case MMC_RSP_R3: 307b4cff454SVipin Bhandari s = ", R3/R4 response"; 308b4cff454SVipin Bhandari break; 309b4cff454SVipin Bhandari default: 310b4cff454SVipin Bhandari s = ", (R? response)"; 311b4cff454SVipin Bhandari break; 312b4cff454SVipin Bhandari }; s; })); 313b4cff454SVipin Bhandari host->cmd = cmd; 314b4cff454SVipin Bhandari 315b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 316b4cff454SVipin Bhandari case MMC_RSP_R1B: 317b4cff454SVipin Bhandari /* There's some spec confusion about when R1B is 318b4cff454SVipin Bhandari * allowed, but if the card doesn't issue a BUSY 319b4cff454SVipin Bhandari * then it's harmless for us to allow it. 320b4cff454SVipin Bhandari */ 321b4cff454SVipin Bhandari cmd_reg |= MMCCMD_BSYEXP; 322b4cff454SVipin Bhandari /* FALLTHROUGH */ 323b4cff454SVipin Bhandari case MMC_RSP_R1: /* 48 bits, CRC */ 324b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R1456; 325b4cff454SVipin Bhandari break; 326b4cff454SVipin Bhandari case MMC_RSP_R2: /* 136 bits, CRC */ 327b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R2; 328b4cff454SVipin Bhandari break; 329b4cff454SVipin Bhandari case MMC_RSP_R3: /* 48 bits, no CRC */ 330b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R3; 331b4cff454SVipin Bhandari break; 332b4cff454SVipin Bhandari default: 333b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_NONE; 334b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 335b4cff454SVipin Bhandari mmc_resp_type(cmd)); 336b4cff454SVipin Bhandari break; 337b4cff454SVipin Bhandari } 338b4cff454SVipin Bhandari 339b4cff454SVipin Bhandari /* Set command index */ 340b4cff454SVipin Bhandari cmd_reg |= cmd->opcode; 341b4cff454SVipin Bhandari 342b4cff454SVipin Bhandari /* Enable EDMA transfer triggers */ 343b4cff454SVipin Bhandari if (host->do_dma) 344b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 345b4cff454SVipin Bhandari 346b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 347b4cff454SVipin Bhandari host->data_dir == DAVINCI_MMC_DATADIR_READ) 348b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 349b4cff454SVipin Bhandari 350b4cff454SVipin Bhandari /* Setting whether command involves data transfer or not */ 351b4cff454SVipin Bhandari if (cmd->data) 352b4cff454SVipin Bhandari cmd_reg |= MMCCMD_WDATX; 353b4cff454SVipin Bhandari 354b4cff454SVipin Bhandari /* Setting whether stream or block transfer */ 355b4cff454SVipin Bhandari if (cmd->flags & MMC_DATA_STREAM) 356b4cff454SVipin Bhandari cmd_reg |= MMCCMD_STRMTP; 357b4cff454SVipin Bhandari 358b4cff454SVipin Bhandari /* Setting whether data read or write */ 359b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 360b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DTRW; 361b4cff454SVipin Bhandari 362b4cff454SVipin Bhandari if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 363b4cff454SVipin Bhandari cmd_reg |= MMCCMD_PPLEN; 364b4cff454SVipin Bhandari 365b4cff454SVipin Bhandari /* set Command timeout */ 366b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 367b4cff454SVipin Bhandari 368b4cff454SVipin Bhandari /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 369b4cff454SVipin Bhandari im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 370b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 371b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 372b4cff454SVipin Bhandari 373b4cff454SVipin Bhandari if (!host->do_dma) 374b4cff454SVipin Bhandari im_val |= MMCST0_DXRDY; 375b4cff454SVipin Bhandari } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 376b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 377b4cff454SVipin Bhandari 378b4cff454SVipin Bhandari if (!host->do_dma) 379b4cff454SVipin Bhandari im_val |= MMCST0_DRRDY; 380b4cff454SVipin Bhandari } 381b4cff454SVipin Bhandari 382b4cff454SVipin Bhandari /* 383b4cff454SVipin Bhandari * Before non-DMA WRITE commands the controller needs priming: 384b4cff454SVipin Bhandari * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 385b4cff454SVipin Bhandari */ 386b4cff454SVipin Bhandari if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 387b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 388b4cff454SVipin Bhandari 389b4cff454SVipin Bhandari writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 390b4cff454SVipin Bhandari writel(cmd_reg, host->base + DAVINCI_MMCCMD); 391ee698f50SIdo Yariv 392ee698f50SIdo Yariv host->active_request = true; 393ee698f50SIdo Yariv 394ee698f50SIdo Yariv if (!host->do_dma && host->bytes_left <= poll_threshold) { 395ee698f50SIdo Yariv u32 count = poll_loopcount; 396ee698f50SIdo Yariv 397ee698f50SIdo Yariv while (host->active_request && count--) { 398ee698f50SIdo Yariv mmc_davinci_irq(0, host); 399ee698f50SIdo Yariv cpu_relax(); 400ee698f50SIdo Yariv } 401ee698f50SIdo Yariv } 402ee698f50SIdo Yariv 403ee698f50SIdo Yariv if (host->active_request) 404b4cff454SVipin Bhandari writel(im_val, host->base + DAVINCI_MMCIM); 405b4cff454SVipin Bhandari } 406b4cff454SVipin Bhandari 407b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 408b4cff454SVipin Bhandari 409b4cff454SVipin Bhandari /* DMA infrastructure */ 410b4cff454SVipin Bhandari 411b4cff454SVipin Bhandari static void davinci_abort_dma(struct mmc_davinci_host *host) 412b4cff454SVipin Bhandari { 413b4cff454SVipin Bhandari int sync_dev; 414b4cff454SVipin Bhandari 415b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 416b4cff454SVipin Bhandari sync_dev = host->rxdma; 417b4cff454SVipin Bhandari else 418b4cff454SVipin Bhandari sync_dev = host->txdma; 419b4cff454SVipin Bhandari 420b4cff454SVipin Bhandari edma_stop(sync_dev); 421b4cff454SVipin Bhandari edma_clean_channel(sync_dev); 422b4cff454SVipin Bhandari } 423b4cff454SVipin Bhandari 424b4cff454SVipin Bhandari static void 425b4cff454SVipin Bhandari mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data); 426b4cff454SVipin Bhandari 427b4cff454SVipin Bhandari static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data) 428b4cff454SVipin Bhandari { 429b4cff454SVipin Bhandari if (DMA_COMPLETE != ch_status) { 430b4cff454SVipin Bhandari struct mmc_davinci_host *host = data; 431b4cff454SVipin Bhandari 432b4cff454SVipin Bhandari /* Currently means: DMA Event Missed, or "null" transfer 433b4cff454SVipin Bhandari * request was seen. In the future, TC errors (like bad 434b4cff454SVipin Bhandari * addresses) might be presented too. 435b4cff454SVipin Bhandari */ 436b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "DMA %s error\n", 437b4cff454SVipin Bhandari (host->data->flags & MMC_DATA_WRITE) 438b4cff454SVipin Bhandari ? "write" : "read"); 439b4cff454SVipin Bhandari host->data->error = -EIO; 440b4cff454SVipin Bhandari mmc_davinci_xfer_done(host, host->data); 441b4cff454SVipin Bhandari } 442b4cff454SVipin Bhandari } 443b4cff454SVipin Bhandari 444b4cff454SVipin Bhandari /* Set up tx or rx template, to be modified and updated later */ 445b4cff454SVipin Bhandari static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host, 446b4cff454SVipin Bhandari bool tx, struct edmacc_param *template) 447b4cff454SVipin Bhandari { 448b4cff454SVipin Bhandari unsigned sync_dev; 449b4cff454SVipin Bhandari const u16 acnt = 4; 450b4cff454SVipin Bhandari const u16 bcnt = rw_threshold >> 2; 451b4cff454SVipin Bhandari const u16 ccnt = 0; 452b4cff454SVipin Bhandari u32 src_port = 0; 453b4cff454SVipin Bhandari u32 dst_port = 0; 454b4cff454SVipin Bhandari s16 src_bidx, dst_bidx; 455b4cff454SVipin Bhandari s16 src_cidx, dst_cidx; 456b4cff454SVipin Bhandari 457b4cff454SVipin Bhandari /* 458b4cff454SVipin Bhandari * A-B Sync transfer: each DMA request is for one "frame" of 459b4cff454SVipin Bhandari * rw_threshold bytes, broken into "acnt"-size chunks repeated 460b4cff454SVipin Bhandari * "bcnt" times. Each segment needs "ccnt" such frames; since 461b4cff454SVipin Bhandari * we tell the block layer our mmc->max_seg_size limit, we can 462b4cff454SVipin Bhandari * trust (later) that it's within bounds. 463b4cff454SVipin Bhandari * 464b4cff454SVipin Bhandari * The FIFOs are read/written in 4-byte chunks (acnt == 4) and 465b4cff454SVipin Bhandari * EDMA will optimize memory operations to use larger bursts. 466b4cff454SVipin Bhandari */ 467b4cff454SVipin Bhandari if (tx) { 468b4cff454SVipin Bhandari sync_dev = host->txdma; 469b4cff454SVipin Bhandari 470b4cff454SVipin Bhandari /* src_prt, ccnt, and link to be set up later */ 471b4cff454SVipin Bhandari src_bidx = acnt; 472b4cff454SVipin Bhandari src_cidx = acnt * bcnt; 473b4cff454SVipin Bhandari 474b4cff454SVipin Bhandari dst_port = host->mem_res->start + DAVINCI_MMCDXR; 475b4cff454SVipin Bhandari dst_bidx = 0; 476b4cff454SVipin Bhandari dst_cidx = 0; 477b4cff454SVipin Bhandari } else { 478b4cff454SVipin Bhandari sync_dev = host->rxdma; 479b4cff454SVipin Bhandari 480b4cff454SVipin Bhandari src_port = host->mem_res->start + DAVINCI_MMCDRR; 481b4cff454SVipin Bhandari src_bidx = 0; 482b4cff454SVipin Bhandari src_cidx = 0; 483b4cff454SVipin Bhandari 484b4cff454SVipin Bhandari /* dst_prt, ccnt, and link to be set up later */ 485b4cff454SVipin Bhandari dst_bidx = acnt; 486b4cff454SVipin Bhandari dst_cidx = acnt * bcnt; 487b4cff454SVipin Bhandari } 488b4cff454SVipin Bhandari 489b4cff454SVipin Bhandari /* 490b4cff454SVipin Bhandari * We can't use FIFO mode for the FIFOs because MMC FIFO addresses 491b4cff454SVipin Bhandari * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT 492b4cff454SVipin Bhandari * parameter is ignored. 493b4cff454SVipin Bhandari */ 494b4cff454SVipin Bhandari edma_set_src(sync_dev, src_port, INCR, W8BIT); 495b4cff454SVipin Bhandari edma_set_dest(sync_dev, dst_port, INCR, W8BIT); 496b4cff454SVipin Bhandari 497b4cff454SVipin Bhandari edma_set_src_index(sync_dev, src_bidx, src_cidx); 498b4cff454SVipin Bhandari edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); 499b4cff454SVipin Bhandari 500b4cff454SVipin Bhandari edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); 501b4cff454SVipin Bhandari 502b4cff454SVipin Bhandari edma_read_slot(sync_dev, template); 503b4cff454SVipin Bhandari 504b4cff454SVipin Bhandari /* don't bother with irqs or chaining */ 505b4cff454SVipin Bhandari template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; 506b4cff454SVipin Bhandari } 507b4cff454SVipin Bhandari 508b4cff454SVipin Bhandari static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 509b4cff454SVipin Bhandari struct mmc_data *data) 510b4cff454SVipin Bhandari { 511b4cff454SVipin Bhandari struct edmacc_param *template; 512b4cff454SVipin Bhandari int channel, slot; 513b4cff454SVipin Bhandari unsigned link; 514b4cff454SVipin Bhandari struct scatterlist *sg; 515b4cff454SVipin Bhandari unsigned sg_len; 516b4cff454SVipin Bhandari unsigned bytes_left = host->bytes_left; 517150ee73dSJoe Perches const unsigned shift = ffs(rw_threshold) - 1; 518b4cff454SVipin Bhandari 519b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 520b4cff454SVipin Bhandari template = &host->tx_template; 521b4cff454SVipin Bhandari channel = host->txdma; 522b4cff454SVipin Bhandari } else { 523b4cff454SVipin Bhandari template = &host->rx_template; 524b4cff454SVipin Bhandari channel = host->rxdma; 525b4cff454SVipin Bhandari } 526b4cff454SVipin Bhandari 527b4cff454SVipin Bhandari /* We know sg_len and ccnt will never be out of range because 528b4cff454SVipin Bhandari * we told the mmc layer which in turn tells the block layer 529b4cff454SVipin Bhandari * to ensure that it only hands us one scatterlist segment 530b4cff454SVipin Bhandari * per EDMA PARAM entry. Update the PARAM 531b4cff454SVipin Bhandari * entries needed for each segment of this scatterlist. 532b4cff454SVipin Bhandari */ 533b4cff454SVipin Bhandari for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len; 534b4cff454SVipin Bhandari sg_len-- != 0 && bytes_left; 535b4cff454SVipin Bhandari sg = sg_next(sg), slot = host->links[link++]) { 536b4cff454SVipin Bhandari u32 buf = sg_dma_address(sg); 537b4cff454SVipin Bhandari unsigned count = sg_dma_len(sg); 538b4cff454SVipin Bhandari 539b4cff454SVipin Bhandari template->link_bcntrld = sg_len 540b4cff454SVipin Bhandari ? (EDMA_CHAN_SLOT(host->links[link]) << 5) 541b4cff454SVipin Bhandari : 0xffff; 542b4cff454SVipin Bhandari 543b4cff454SVipin Bhandari if (count > bytes_left) 544b4cff454SVipin Bhandari count = bytes_left; 545b4cff454SVipin Bhandari bytes_left -= count; 546b4cff454SVipin Bhandari 547b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 548b4cff454SVipin Bhandari template->src = buf; 549b4cff454SVipin Bhandari else 550b4cff454SVipin Bhandari template->dst = buf; 551b4cff454SVipin Bhandari template->ccnt = count >> shift; 552b4cff454SVipin Bhandari 553b4cff454SVipin Bhandari edma_write_slot(slot, template); 554b4cff454SVipin Bhandari } 555b4cff454SVipin Bhandari 556b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 557b4cff454SVipin Bhandari edma_clear_event(channel); 558b4cff454SVipin Bhandari 559b4cff454SVipin Bhandari edma_start(channel); 560b4cff454SVipin Bhandari } 561b4cff454SVipin Bhandari 562b4cff454SVipin Bhandari static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 563b4cff454SVipin Bhandari struct mmc_data *data) 564b4cff454SVipin Bhandari { 565b4cff454SVipin Bhandari int i; 566b4cff454SVipin Bhandari int mask = rw_threshold - 1; 567b4cff454SVipin Bhandari 568b4cff454SVipin Bhandari host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 569b4cff454SVipin Bhandari ((data->flags & MMC_DATA_WRITE) 570b4cff454SVipin Bhandari ? DMA_TO_DEVICE 571b4cff454SVipin Bhandari : DMA_FROM_DEVICE)); 572b4cff454SVipin Bhandari 573b4cff454SVipin Bhandari /* no individual DMA segment should need a partial FIFO */ 574b4cff454SVipin Bhandari for (i = 0; i < host->sg_len; i++) { 575b4cff454SVipin Bhandari if (sg_dma_len(data->sg + i) & mask) { 576b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), 577b4cff454SVipin Bhandari data->sg, data->sg_len, 578b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 579b4cff454SVipin Bhandari ? DMA_TO_DEVICE 580b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 581b4cff454SVipin Bhandari return -1; 582b4cff454SVipin Bhandari } 583b4cff454SVipin Bhandari } 584b4cff454SVipin Bhandari 585b4cff454SVipin Bhandari host->do_dma = 1; 586b4cff454SVipin Bhandari mmc_davinci_send_dma_request(host, data); 587b4cff454SVipin Bhandari 588b4cff454SVipin Bhandari return 0; 589b4cff454SVipin Bhandari } 590b4cff454SVipin Bhandari 591b4cff454SVipin Bhandari static void __init_or_module 592b4cff454SVipin Bhandari davinci_release_dma_channels(struct mmc_davinci_host *host) 593b4cff454SVipin Bhandari { 594b4cff454SVipin Bhandari unsigned i; 595b4cff454SVipin Bhandari 596b4cff454SVipin Bhandari if (!host->use_dma) 597b4cff454SVipin Bhandari return; 598b4cff454SVipin Bhandari 599b4cff454SVipin Bhandari for (i = 0; i < host->n_link; i++) 600b4cff454SVipin Bhandari edma_free_slot(host->links[i]); 601b4cff454SVipin Bhandari 602b4cff454SVipin Bhandari edma_free_channel(host->txdma); 603b4cff454SVipin Bhandari edma_free_channel(host->rxdma); 604b4cff454SVipin Bhandari } 605b4cff454SVipin Bhandari 606b4cff454SVipin Bhandari static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 607b4cff454SVipin Bhandari { 608ca2afb6dSSudhakar Rajashekhara u32 link_size; 609b4cff454SVipin Bhandari int r, i; 610b4cff454SVipin Bhandari 611b4cff454SVipin Bhandari /* Acquire master DMA write channel */ 612b4cff454SVipin Bhandari r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host, 613b4cff454SVipin Bhandari EVENTQ_DEFAULT); 614b4cff454SVipin Bhandari if (r < 0) { 615b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 616b4cff454SVipin Bhandari "tx", r); 617b4cff454SVipin Bhandari return r; 618b4cff454SVipin Bhandari } 619b4cff454SVipin Bhandari mmc_davinci_dma_setup(host, true, &host->tx_template); 620b4cff454SVipin Bhandari 621b4cff454SVipin Bhandari /* Acquire master DMA read channel */ 622b4cff454SVipin Bhandari r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host, 623b4cff454SVipin Bhandari EVENTQ_DEFAULT); 624b4cff454SVipin Bhandari if (r < 0) { 625b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 626b4cff454SVipin Bhandari "rx", r); 627b4cff454SVipin Bhandari goto free_master_write; 628b4cff454SVipin Bhandari } 629b4cff454SVipin Bhandari mmc_davinci_dma_setup(host, false, &host->rx_template); 630b4cff454SVipin Bhandari 631b4cff454SVipin Bhandari /* Allocate parameter RAM slots, which will later be bound to a 632b4cff454SVipin Bhandari * channel as needed to handle a scatterlist. 633b4cff454SVipin Bhandari */ 634ca2afb6dSSudhakar Rajashekhara link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); 635ca2afb6dSSudhakar Rajashekhara for (i = 0; i < link_size; i++) { 636b4cff454SVipin Bhandari r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); 637b4cff454SVipin Bhandari if (r < 0) { 638b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n", 639b4cff454SVipin Bhandari r); 640b4cff454SVipin Bhandari break; 641b4cff454SVipin Bhandari } 642b4cff454SVipin Bhandari host->links[i] = r; 643b4cff454SVipin Bhandari } 644b4cff454SVipin Bhandari host->n_link = i; 645b4cff454SVipin Bhandari 646b4cff454SVipin Bhandari return 0; 647b4cff454SVipin Bhandari 648b4cff454SVipin Bhandari free_master_write: 649b4cff454SVipin Bhandari edma_free_channel(host->txdma); 650b4cff454SVipin Bhandari 651b4cff454SVipin Bhandari return r; 652b4cff454SVipin Bhandari } 653b4cff454SVipin Bhandari 654b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 655b4cff454SVipin Bhandari 656b4cff454SVipin Bhandari static void 657b4cff454SVipin Bhandari mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 658b4cff454SVipin Bhandari { 659b4cff454SVipin Bhandari int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 660b4cff454SVipin Bhandari int timeout; 661b4cff454SVipin Bhandari struct mmc_data *data = req->data; 662b4cff454SVipin Bhandari 663b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 664b4cff454SVipin Bhandari fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 665b4cff454SVipin Bhandari 666b4cff454SVipin Bhandari host->data = data; 667b4cff454SVipin Bhandari if (data == NULL) { 668b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 669b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCBLEN); 670b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCNBLK); 671b4cff454SVipin Bhandari return; 672b4cff454SVipin Bhandari } 673b4cff454SVipin Bhandari 674b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n", 675b4cff454SVipin Bhandari (data->flags & MMC_DATA_STREAM) ? "stream" : "block", 676b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) ? "write" : "read", 677b4cff454SVipin Bhandari data->blocks, data->blksz); 678b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 679b4cff454SVipin Bhandari data->timeout_clks, data->timeout_ns); 680b4cff454SVipin Bhandari timeout = data->timeout_clks + 681b4cff454SVipin Bhandari (data->timeout_ns / host->ns_in_one_cycle); 682b4cff454SVipin Bhandari if (timeout > 0xffff) 683b4cff454SVipin Bhandari timeout = 0xffff; 684b4cff454SVipin Bhandari 685b4cff454SVipin Bhandari writel(timeout, host->base + DAVINCI_MMCTOD); 686b4cff454SVipin Bhandari writel(data->blocks, host->base + DAVINCI_MMCNBLK); 687b4cff454SVipin Bhandari writel(data->blksz, host->base + DAVINCI_MMCBLEN); 688b4cff454SVipin Bhandari 689b4cff454SVipin Bhandari /* Configure the FIFO */ 690b4cff454SVipin Bhandari switch (data->flags & MMC_DATA_WRITE) { 691b4cff454SVipin Bhandari case MMC_DATA_WRITE: 692b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 693b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 694b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 695b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 696b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 697b4cff454SVipin Bhandari break; 698b4cff454SVipin Bhandari 699b4cff454SVipin Bhandari default: 700b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_READ; 701b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 702b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 703b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 704b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 705b4cff454SVipin Bhandari break; 706b4cff454SVipin Bhandari } 707b4cff454SVipin Bhandari 708b4cff454SVipin Bhandari host->buffer = NULL; 709b4cff454SVipin Bhandari host->bytes_left = data->blocks * data->blksz; 710b4cff454SVipin Bhandari 711b4cff454SVipin Bhandari /* For now we try to use DMA whenever we won't need partial FIFO 712b4cff454SVipin Bhandari * reads or writes, either for the whole transfer (as tested here) 713b4cff454SVipin Bhandari * or for any individual scatterlist segment (tested when we call 714b4cff454SVipin Bhandari * start_dma_transfer). 715b4cff454SVipin Bhandari * 716b4cff454SVipin Bhandari * While we *could* change that, unusual block sizes are rarely 717b4cff454SVipin Bhandari * used. The occasional fallback to PIO should't hurt. 718b4cff454SVipin Bhandari */ 719b4cff454SVipin Bhandari if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 720b4cff454SVipin Bhandari && mmc_davinci_start_dma_transfer(host, data) == 0) { 721b4cff454SVipin Bhandari /* zero this to ensure we take no PIO paths */ 722b4cff454SVipin Bhandari host->bytes_left = 0; 723b4cff454SVipin Bhandari } else { 724b4cff454SVipin Bhandari /* Revert to CPU Copy */ 725b4cff454SVipin Bhandari host->sg_len = data->sg_len; 726b4cff454SVipin Bhandari host->sg = host->data->sg; 727b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 728b4cff454SVipin Bhandari } 729b4cff454SVipin Bhandari } 730b4cff454SVipin Bhandari 731b4cff454SVipin Bhandari static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 732b4cff454SVipin Bhandari { 733b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 734b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(900); 735b4cff454SVipin Bhandari u32 mmcst1 = 0; 736b4cff454SVipin Bhandari 737b4cff454SVipin Bhandari /* Card may still be sending BUSY after a previous operation, 738b4cff454SVipin Bhandari * typically some kind of write. If so, we can't proceed yet. 739b4cff454SVipin Bhandari */ 740b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 741b4cff454SVipin Bhandari mmcst1 = readl(host->base + DAVINCI_MMCST1); 742b4cff454SVipin Bhandari if (!(mmcst1 & MMCST1_BUSY)) 743b4cff454SVipin Bhandari break; 744b4cff454SVipin Bhandari cpu_relax(); 745b4cff454SVipin Bhandari } 746b4cff454SVipin Bhandari if (mmcst1 & MMCST1_BUSY) { 747b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 748b4cff454SVipin Bhandari req->cmd->error = -ETIMEDOUT; 749b4cff454SVipin Bhandari mmc_request_done(mmc, req); 750b4cff454SVipin Bhandari return; 751b4cff454SVipin Bhandari } 752b4cff454SVipin Bhandari 753b4cff454SVipin Bhandari host->do_dma = 0; 754b4cff454SVipin Bhandari mmc_davinci_prepare_data(host, req); 755b4cff454SVipin Bhandari mmc_davinci_start_command(host, req->cmd); 756b4cff454SVipin Bhandari } 757b4cff454SVipin Bhandari 758b4cff454SVipin Bhandari static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 759b4cff454SVipin Bhandari unsigned int mmc_req_freq) 760b4cff454SVipin Bhandari { 761b4cff454SVipin Bhandari unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 762b4cff454SVipin Bhandari 763b4cff454SVipin Bhandari mmc_pclk = host->mmc_input_clk; 764b4cff454SVipin Bhandari if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 765b4cff454SVipin Bhandari mmc_push_pull_divisor = ((unsigned int)mmc_pclk 766b4cff454SVipin Bhandari / (2 * mmc_req_freq)) - 1; 767b4cff454SVipin Bhandari else 768b4cff454SVipin Bhandari mmc_push_pull_divisor = 0; 769b4cff454SVipin Bhandari 770b4cff454SVipin Bhandari mmc_freq = (unsigned int)mmc_pclk 771b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)); 772b4cff454SVipin Bhandari 773b4cff454SVipin Bhandari if (mmc_freq > mmc_req_freq) 774b4cff454SVipin Bhandari mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 775b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 776b4cff454SVipin Bhandari if (mmc_req_freq <= 400000) 777b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 778b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000)); 779b4cff454SVipin Bhandari else 780b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 781b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 782b4cff454SVipin Bhandari 783b4cff454SVipin Bhandari return mmc_push_pull_divisor; 784b4cff454SVipin Bhandari } 785b4cff454SVipin Bhandari 7867e30b8deSChaithrika U S static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 787b4cff454SVipin Bhandari { 788b4cff454SVipin Bhandari unsigned int open_drain_freq = 0, mmc_pclk = 0; 789b4cff454SVipin Bhandari unsigned int mmc_push_pull_freq = 0; 790b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 791b4cff454SVipin Bhandari 792b4cff454SVipin Bhandari if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 793b4cff454SVipin Bhandari u32 temp; 794b4cff454SVipin Bhandari 795b4cff454SVipin Bhandari /* Ignoring the init clock value passed for fixing the inter 796b4cff454SVipin Bhandari * operability with different cards. 797b4cff454SVipin Bhandari */ 798b4cff454SVipin Bhandari open_drain_freq = ((unsigned int)mmc_pclk 799b4cff454SVipin Bhandari / (2 * MMCSD_INIT_CLOCK)) - 1; 800b4cff454SVipin Bhandari 801b4cff454SVipin Bhandari if (open_drain_freq > 0xFF) 802b4cff454SVipin Bhandari open_drain_freq = 0xFF; 803b4cff454SVipin Bhandari 804b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 805b4cff454SVipin Bhandari temp |= open_drain_freq; 806b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 807b4cff454SVipin Bhandari 808b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 809b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 810b4cff454SVipin Bhandari } else { 811b4cff454SVipin Bhandari u32 temp; 812b4cff454SVipin Bhandari mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 813b4cff454SVipin Bhandari 814b4cff454SVipin Bhandari if (mmc_push_pull_freq > 0xFF) 815b4cff454SVipin Bhandari mmc_push_pull_freq = 0xFF; 816b4cff454SVipin Bhandari 817b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 818b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 819b4cff454SVipin Bhandari 820b4cff454SVipin Bhandari udelay(10); 821b4cff454SVipin Bhandari 822b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 823b4cff454SVipin Bhandari temp |= mmc_push_pull_freq; 824b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 825b4cff454SVipin Bhandari 826b4cff454SVipin Bhandari writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 827b4cff454SVipin Bhandari 828b4cff454SVipin Bhandari udelay(10); 829b4cff454SVipin Bhandari } 8307e30b8deSChaithrika U S } 8317e30b8deSChaithrika U S 8327e30b8deSChaithrika U S static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 8337e30b8deSChaithrika U S { 8347e30b8deSChaithrika U S struct mmc_davinci_host *host = mmc_priv(mmc); 8354a9de8adSIdo Yariv struct platform_device *pdev = to_platform_device(mmc->parent); 8364a9de8adSIdo Yariv struct davinci_mmc_config *config = pdev->dev.platform_data; 8377e30b8deSChaithrika U S 8387e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), 8397e30b8deSChaithrika U S "clock %dHz busmode %d powermode %d Vdd %04x\n", 8407e30b8deSChaithrika U S ios->clock, ios->bus_mode, ios->power_mode, 8417e30b8deSChaithrika U S ios->vdd); 842132f1074SVipin Bhandari 8434a9de8adSIdo Yariv switch (ios->power_mode) { 8444a9de8adSIdo Yariv case MMC_POWER_OFF: 8454a9de8adSIdo Yariv if (config && config->set_power) 8464a9de8adSIdo Yariv config->set_power(pdev->id, false); 8474a9de8adSIdo Yariv break; 8484a9de8adSIdo Yariv case MMC_POWER_UP: 8494a9de8adSIdo Yariv if (config && config->set_power) 8504a9de8adSIdo Yariv config->set_power(pdev->id, true); 8514a9de8adSIdo Yariv break; 8524a9de8adSIdo Yariv } 8534a9de8adSIdo Yariv 854132f1074SVipin Bhandari switch (ios->bus_width) { 855132f1074SVipin Bhandari case MMC_BUS_WIDTH_8: 856132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 857132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 858132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 859132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 860132f1074SVipin Bhandari break; 861132f1074SVipin Bhandari case MMC_BUS_WIDTH_4: 8627e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 863132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 864132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 865132f1074SVipin Bhandari ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 8667e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 867132f1074SVipin Bhandari else 868132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) | 869132f1074SVipin Bhandari MMCCTL_WIDTH_4_BIT, 8707e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 871132f1074SVipin Bhandari break; 872132f1074SVipin Bhandari case MMC_BUS_WIDTH_1: 873132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 874132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 875132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 876132f1074SVipin Bhandari ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 877132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 878132f1074SVipin Bhandari else 879132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 880132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT, 881132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 882132f1074SVipin Bhandari break; 8837e30b8deSChaithrika U S } 8847e30b8deSChaithrika U S 8857e30b8deSChaithrika U S calculate_clk_divider(mmc, ios); 886b4cff454SVipin Bhandari 887b4cff454SVipin Bhandari host->bus_mode = ios->bus_mode; 888b4cff454SVipin Bhandari if (ios->power_mode == MMC_POWER_UP) { 889b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(50); 890b4cff454SVipin Bhandari bool lose = true; 891b4cff454SVipin Bhandari 892b4cff454SVipin Bhandari /* Send clock cycles, poll completion */ 893b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCARGHL); 894b4cff454SVipin Bhandari writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 895b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 896b4cff454SVipin Bhandari u32 tmp = readl(host->base + DAVINCI_MMCST0); 897b4cff454SVipin Bhandari 898b4cff454SVipin Bhandari if (tmp & MMCST0_RSPDNE) { 899b4cff454SVipin Bhandari lose = false; 900b4cff454SVipin Bhandari break; 901b4cff454SVipin Bhandari } 902b4cff454SVipin Bhandari cpu_relax(); 903b4cff454SVipin Bhandari } 904b4cff454SVipin Bhandari if (lose) 905b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 906b4cff454SVipin Bhandari } 907b4cff454SVipin Bhandari 908b4cff454SVipin Bhandari /* FIXME on power OFF, reset things ... */ 909b4cff454SVipin Bhandari } 910b4cff454SVipin Bhandari 911b4cff454SVipin Bhandari static void 912b4cff454SVipin Bhandari mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 913b4cff454SVipin Bhandari { 914b4cff454SVipin Bhandari host->data = NULL; 915b4cff454SVipin Bhandari 916f9db92cbSAlagu Sankar if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 917f9db92cbSAlagu Sankar /* 918f9db92cbSAlagu Sankar * SDIO Interrupt Detection work-around as suggested by 919f9db92cbSAlagu Sankar * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata 920f9db92cbSAlagu Sankar * 2.1.6): Signal SDIO interrupt only if it is enabled by core 921f9db92cbSAlagu Sankar */ 922f9db92cbSAlagu Sankar if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & 923f9db92cbSAlagu Sankar SDIOST0_DAT1_HI)) { 924f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 925f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 926f9db92cbSAlagu Sankar } 927f9db92cbSAlagu Sankar } 928f9db92cbSAlagu Sankar 929b4cff454SVipin Bhandari if (host->do_dma) { 930b4cff454SVipin Bhandari davinci_abort_dma(host); 931b4cff454SVipin Bhandari 932b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 933b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 934b4cff454SVipin Bhandari ? DMA_TO_DEVICE 935b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 936b4cff454SVipin Bhandari host->do_dma = false; 937b4cff454SVipin Bhandari } 938b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 939b4cff454SVipin Bhandari 940b4cff454SVipin Bhandari if (!data->stop || (host->cmd && host->cmd->error)) { 941b4cff454SVipin Bhandari mmc_request_done(host->mmc, data->mrq); 942b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 943ee698f50SIdo Yariv host->active_request = false; 944b4cff454SVipin Bhandari } else 945b4cff454SVipin Bhandari mmc_davinci_start_command(host, data->stop); 946b4cff454SVipin Bhandari } 947b4cff454SVipin Bhandari 948b4cff454SVipin Bhandari static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 949b4cff454SVipin Bhandari struct mmc_command *cmd) 950b4cff454SVipin Bhandari { 951b4cff454SVipin Bhandari host->cmd = NULL; 952b4cff454SVipin Bhandari 953b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_PRESENT) { 954b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_136) { 955b4cff454SVipin Bhandari /* response type 2 */ 956b4cff454SVipin Bhandari cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 957b4cff454SVipin Bhandari cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 958b4cff454SVipin Bhandari cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 959b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 960b4cff454SVipin Bhandari } else { 961b4cff454SVipin Bhandari /* response types 1, 1b, 3, 4, 5, 6 */ 962b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 963b4cff454SVipin Bhandari } 964b4cff454SVipin Bhandari } 965b4cff454SVipin Bhandari 966b4cff454SVipin Bhandari if (host->data == NULL || cmd->error) { 967b4cff454SVipin Bhandari if (cmd->error == -ETIMEDOUT) 968b4cff454SVipin Bhandari cmd->mrq->cmd->retries = 0; 969b4cff454SVipin Bhandari mmc_request_done(host->mmc, cmd->mrq); 970b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 971ee698f50SIdo Yariv host->active_request = false; 972b4cff454SVipin Bhandari } 973b4cff454SVipin Bhandari } 974b4cff454SVipin Bhandari 97506de845fSChaithrika U S static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 97606de845fSChaithrika U S int val) 977b4cff454SVipin Bhandari { 978b4cff454SVipin Bhandari u32 temp; 979b4cff454SVipin Bhandari 980b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCTL); 98106de845fSChaithrika U S if (val) /* reset */ 98206de845fSChaithrika U S temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 98306de845fSChaithrika U S else /* enable */ 984b4cff454SVipin Bhandari temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 98506de845fSChaithrika U S 986b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCTL); 98706de845fSChaithrika U S udelay(10); 98806de845fSChaithrika U S } 98906de845fSChaithrika U S 99006de845fSChaithrika U S static void 99106de845fSChaithrika U S davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 99206de845fSChaithrika U S { 99306de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 99406de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 995b4cff454SVipin Bhandari } 996b4cff454SVipin Bhandari 997f9db92cbSAlagu Sankar static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) 998f9db92cbSAlagu Sankar { 999f9db92cbSAlagu Sankar struct mmc_davinci_host *host = dev_id; 1000f9db92cbSAlagu Sankar unsigned int status; 1001f9db92cbSAlagu Sankar 1002f9db92cbSAlagu Sankar status = readl(host->base + DAVINCI_SDIOIST); 1003f9db92cbSAlagu Sankar if (status & SDIOIST_IOINT) { 1004f9db92cbSAlagu Sankar dev_dbg(mmc_dev(host->mmc), 1005f9db92cbSAlagu Sankar "SDIO interrupt status %x\n", status); 1006f9db92cbSAlagu Sankar writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1007f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 1008f9db92cbSAlagu Sankar } 1009f9db92cbSAlagu Sankar return IRQ_HANDLED; 1010f9db92cbSAlagu Sankar } 1011f9db92cbSAlagu Sankar 1012b4cff454SVipin Bhandari static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 1013b4cff454SVipin Bhandari { 1014b4cff454SVipin Bhandari struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 1015b4cff454SVipin Bhandari unsigned int status, qstatus; 1016b4cff454SVipin Bhandari int end_command = 0; 1017b4cff454SVipin Bhandari int end_transfer = 0; 1018b4cff454SVipin Bhandari struct mmc_data *data = host->data; 1019b4cff454SVipin Bhandari 1020b4cff454SVipin Bhandari if (host->cmd == NULL && host->data == NULL) { 1021b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 1022b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 1023b4cff454SVipin Bhandari "Spurious interrupt 0x%04x\n", status); 1024b4cff454SVipin Bhandari /* Disable the interrupt from mmcsd */ 1025b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 1026b4cff454SVipin Bhandari return IRQ_NONE; 1027b4cff454SVipin Bhandari } 1028b4cff454SVipin Bhandari 1029b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 1030b4cff454SVipin Bhandari qstatus = status; 1031b4cff454SVipin Bhandari 1032b4cff454SVipin Bhandari /* handle FIFO first when using PIO for data. 1033b4cff454SVipin Bhandari * bytes_left will decrease to zero as I/O progress and status will 1034b4cff454SVipin Bhandari * read zero over iteration because this controller status 1035b4cff454SVipin Bhandari * register(MMCST0) reports any status only once and it is cleared 1036b4cff454SVipin Bhandari * by read. So, it is not unbouned loop even in the case of 1037b4cff454SVipin Bhandari * non-dma. 1038b4cff454SVipin Bhandari */ 1039be7b5622SIdo Yariv if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 1040be7b5622SIdo Yariv unsigned long im_val; 1041be7b5622SIdo Yariv 1042be7b5622SIdo Yariv /* 1043be7b5622SIdo Yariv * If interrupts fire during the following loop, they will be 1044be7b5622SIdo Yariv * handled by the handler, but the PIC will still buffer these. 1045be7b5622SIdo Yariv * As a result, the handler will be called again to serve these 1046be7b5622SIdo Yariv * needlessly. In order to avoid these spurious interrupts, 1047be7b5622SIdo Yariv * keep interrupts masked during the loop. 1048be7b5622SIdo Yariv */ 1049be7b5622SIdo Yariv im_val = readl(host->base + DAVINCI_MMCIM); 1050be7b5622SIdo Yariv writel(0, host->base + DAVINCI_MMCIM); 1051be7b5622SIdo Yariv 1052be7b5622SIdo Yariv do { 1053b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 1054b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 1055b4cff454SVipin Bhandari qstatus |= status; 1056be7b5622SIdo Yariv } while (host->bytes_left && 1057be7b5622SIdo Yariv (status & (MMCST0_DXRDY | MMCST0_DRRDY))); 1058be7b5622SIdo Yariv 1059be7b5622SIdo Yariv /* 1060be7b5622SIdo Yariv * If an interrupt is pending, it is assumed it will fire when 1061be7b5622SIdo Yariv * it is unmasked. This assumption is also taken when the MMCIM 1062be7b5622SIdo Yariv * is first set. Otherwise, writing to MMCIM after reading the 1063be7b5622SIdo Yariv * status is race-prone. 1064be7b5622SIdo Yariv */ 1065be7b5622SIdo Yariv writel(im_val, host->base + DAVINCI_MMCIM); 1066b4cff454SVipin Bhandari } 1067b4cff454SVipin Bhandari 1068b4cff454SVipin Bhandari if (qstatus & MMCST0_DATDNE) { 1069b4cff454SVipin Bhandari /* All blocks sent/received, and CRC checks passed */ 1070b4cff454SVipin Bhandari if (data != NULL) { 1071b4cff454SVipin Bhandari if ((host->do_dma == 0) && (host->bytes_left > 0)) { 1072b4cff454SVipin Bhandari /* if datasize < rw_threshold 1073b4cff454SVipin Bhandari * no RX ints are generated 1074b4cff454SVipin Bhandari */ 1075b4cff454SVipin Bhandari davinci_fifo_data_trans(host, host->bytes_left); 1076b4cff454SVipin Bhandari } 1077b4cff454SVipin Bhandari end_transfer = 1; 1078b4cff454SVipin Bhandari data->bytes_xfered = data->blocks * data->blksz; 1079b4cff454SVipin Bhandari } else { 1080b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), 1081b4cff454SVipin Bhandari "DATDNE with no host->data\n"); 1082b4cff454SVipin Bhandari } 1083b4cff454SVipin Bhandari } 1084b4cff454SVipin Bhandari 1085b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRD) { 1086b4cff454SVipin Bhandari /* Read data timeout */ 1087b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 1088b4cff454SVipin Bhandari end_transfer = 1; 1089b4cff454SVipin Bhandari 1090b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 1091b4cff454SVipin Bhandari "read data timeout, status %x\n", 1092b4cff454SVipin Bhandari qstatus); 1093b4cff454SVipin Bhandari 1094b4cff454SVipin Bhandari davinci_abort_data(host, data); 1095b4cff454SVipin Bhandari } 1096b4cff454SVipin Bhandari 1097b4cff454SVipin Bhandari if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 1098b4cff454SVipin Bhandari /* Data CRC error */ 1099b4cff454SVipin Bhandari data->error = -EILSEQ; 1100b4cff454SVipin Bhandari end_transfer = 1; 1101b4cff454SVipin Bhandari 1102b4cff454SVipin Bhandari /* NOTE: this controller uses CRCWR to report both CRC 1103b4cff454SVipin Bhandari * errors and timeouts (on writes). MMCDRSP values are 1104b4cff454SVipin Bhandari * only weakly documented, but 0x9f was clearly a timeout 1105b4cff454SVipin Bhandari * case and the two three-bit patterns in various SD specs 1106b4cff454SVipin Bhandari * (101, 010) aren't part of it ... 1107b4cff454SVipin Bhandari */ 1108b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCWR) { 1109b4cff454SVipin Bhandari u32 temp = readb(host->base + DAVINCI_MMCDRSP); 1110b4cff454SVipin Bhandari 1111b4cff454SVipin Bhandari if (temp == 0x9f) 1112b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 1113b4cff454SVipin Bhandari } 1114b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 1115b4cff454SVipin Bhandari (qstatus & MMCST0_CRCWR) ? "write" : "read", 1116b4cff454SVipin Bhandari (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 1117b4cff454SVipin Bhandari 1118b4cff454SVipin Bhandari davinci_abort_data(host, data); 1119b4cff454SVipin Bhandari } 1120b4cff454SVipin Bhandari 1121b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRS) { 1122b4cff454SVipin Bhandari /* Command timeout */ 1123b4cff454SVipin Bhandari if (host->cmd) { 1124b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 1125b4cff454SVipin Bhandari "CMD%d timeout, status %x\n", 1126b4cff454SVipin Bhandari host->cmd->opcode, qstatus); 1127b4cff454SVipin Bhandari host->cmd->error = -ETIMEDOUT; 1128b4cff454SVipin Bhandari if (data) { 1129b4cff454SVipin Bhandari end_transfer = 1; 1130b4cff454SVipin Bhandari davinci_abort_data(host, data); 1131b4cff454SVipin Bhandari } else 1132b4cff454SVipin Bhandari end_command = 1; 1133b4cff454SVipin Bhandari } 1134b4cff454SVipin Bhandari } 1135b4cff454SVipin Bhandari 1136b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCRS) { 1137b4cff454SVipin Bhandari /* Command CRC error */ 1138b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1139b4cff454SVipin Bhandari if (host->cmd) { 1140b4cff454SVipin Bhandari host->cmd->error = -EILSEQ; 1141b4cff454SVipin Bhandari end_command = 1; 1142b4cff454SVipin Bhandari } 1143b4cff454SVipin Bhandari } 1144b4cff454SVipin Bhandari 1145b4cff454SVipin Bhandari if (qstatus & MMCST0_RSPDNE) { 1146b4cff454SVipin Bhandari /* End of command phase */ 1147b4cff454SVipin Bhandari end_command = (int) host->cmd; 1148b4cff454SVipin Bhandari } 1149b4cff454SVipin Bhandari 1150b4cff454SVipin Bhandari if (end_command) 1151b4cff454SVipin Bhandari mmc_davinci_cmd_done(host, host->cmd); 1152b4cff454SVipin Bhandari if (end_transfer) 1153b4cff454SVipin Bhandari mmc_davinci_xfer_done(host, data); 1154b4cff454SVipin Bhandari return IRQ_HANDLED; 1155b4cff454SVipin Bhandari } 1156b4cff454SVipin Bhandari 1157b4cff454SVipin Bhandari static int mmc_davinci_get_cd(struct mmc_host *mmc) 1158b4cff454SVipin Bhandari { 1159b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1160b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1161b4cff454SVipin Bhandari 1162b4cff454SVipin Bhandari if (!config || !config->get_cd) 1163b4cff454SVipin Bhandari return -ENOSYS; 1164b4cff454SVipin Bhandari return config->get_cd(pdev->id); 1165b4cff454SVipin Bhandari } 1166b4cff454SVipin Bhandari 1167b4cff454SVipin Bhandari static int mmc_davinci_get_ro(struct mmc_host *mmc) 1168b4cff454SVipin Bhandari { 1169b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1170b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1171b4cff454SVipin Bhandari 1172b4cff454SVipin Bhandari if (!config || !config->get_ro) 1173b4cff454SVipin Bhandari return -ENOSYS; 1174b4cff454SVipin Bhandari return config->get_ro(pdev->id); 1175b4cff454SVipin Bhandari } 1176b4cff454SVipin Bhandari 1177f9db92cbSAlagu Sankar static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1178f9db92cbSAlagu Sankar { 1179f9db92cbSAlagu Sankar struct mmc_davinci_host *host = mmc_priv(mmc); 1180f9db92cbSAlagu Sankar 1181f9db92cbSAlagu Sankar if (enable) { 1182f9db92cbSAlagu Sankar if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { 1183f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1184f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 1185f9db92cbSAlagu Sankar } else { 1186f9db92cbSAlagu Sankar host->sdio_int = true; 1187f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) | 1188f9db92cbSAlagu Sankar SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); 1189f9db92cbSAlagu Sankar } 1190f9db92cbSAlagu Sankar } else { 1191f9db92cbSAlagu Sankar host->sdio_int = false; 1192f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, 1193f9db92cbSAlagu Sankar host->base + DAVINCI_SDIOIEN); 1194f9db92cbSAlagu Sankar } 1195f9db92cbSAlagu Sankar } 1196f9db92cbSAlagu Sankar 1197b4cff454SVipin Bhandari static struct mmc_host_ops mmc_davinci_ops = { 1198b4cff454SVipin Bhandari .request = mmc_davinci_request, 1199b4cff454SVipin Bhandari .set_ios = mmc_davinci_set_ios, 1200b4cff454SVipin Bhandari .get_cd = mmc_davinci_get_cd, 1201b4cff454SVipin Bhandari .get_ro = mmc_davinci_get_ro, 1202f9db92cbSAlagu Sankar .enable_sdio_irq = mmc_davinci_enable_sdio_irq, 1203b4cff454SVipin Bhandari }; 1204b4cff454SVipin Bhandari 1205b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 1206b4cff454SVipin Bhandari 12077e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 12087e30b8deSChaithrika U S static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 12097e30b8deSChaithrika U S unsigned long val, void *data) 12107e30b8deSChaithrika U S { 12117e30b8deSChaithrika U S struct mmc_davinci_host *host; 12127e30b8deSChaithrika U S unsigned int mmc_pclk; 12137e30b8deSChaithrika U S struct mmc_host *mmc; 12147e30b8deSChaithrika U S unsigned long flags; 12157e30b8deSChaithrika U S 12167e30b8deSChaithrika U S host = container_of(nb, struct mmc_davinci_host, freq_transition); 12177e30b8deSChaithrika U S mmc = host->mmc; 12187e30b8deSChaithrika U S mmc_pclk = clk_get_rate(host->clk); 12197e30b8deSChaithrika U S 12207e30b8deSChaithrika U S if (val == CPUFREQ_POSTCHANGE) { 12217e30b8deSChaithrika U S spin_lock_irqsave(&mmc->lock, flags); 12227e30b8deSChaithrika U S host->mmc_input_clk = mmc_pclk; 12237e30b8deSChaithrika U S calculate_clk_divider(mmc, &mmc->ios); 12247e30b8deSChaithrika U S spin_unlock_irqrestore(&mmc->lock, flags); 12257e30b8deSChaithrika U S } 12267e30b8deSChaithrika U S 12277e30b8deSChaithrika U S return 0; 12287e30b8deSChaithrika U S } 12297e30b8deSChaithrika U S 12307e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 12317e30b8deSChaithrika U S { 12327e30b8deSChaithrika U S host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 12337e30b8deSChaithrika U S 12347e30b8deSChaithrika U S return cpufreq_register_notifier(&host->freq_transition, 12357e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 12367e30b8deSChaithrika U S } 12377e30b8deSChaithrika U S 12387e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 12397e30b8deSChaithrika U S { 12407e30b8deSChaithrika U S cpufreq_unregister_notifier(&host->freq_transition, 12417e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 12427e30b8deSChaithrika U S } 12437e30b8deSChaithrika U S #else 12447e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 12457e30b8deSChaithrika U S { 12467e30b8deSChaithrika U S return 0; 12477e30b8deSChaithrika U S } 12487e30b8deSChaithrika U S 12497e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 12507e30b8deSChaithrika U S { 12517e30b8deSChaithrika U S } 12527e30b8deSChaithrika U S #endif 1253b4cff454SVipin Bhandari static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1254b4cff454SVipin Bhandari { 1255b4cff454SVipin Bhandari 125606de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1257b4cff454SVipin Bhandari 1258b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCCLK); 1259b4cff454SVipin Bhandari writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1260b4cff454SVipin Bhandari 1261b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1262b4cff454SVipin Bhandari writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1263b4cff454SVipin Bhandari 126406de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1265b4cff454SVipin Bhandari } 1266b4cff454SVipin Bhandari 1267b4cff454SVipin Bhandari static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1268b4cff454SVipin Bhandari { 1269b4cff454SVipin Bhandari struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1270b4cff454SVipin Bhandari struct mmc_davinci_host *host = NULL; 1271b4cff454SVipin Bhandari struct mmc_host *mmc = NULL; 1272b4cff454SVipin Bhandari struct resource *r, *mem = NULL; 1273b4cff454SVipin Bhandari int ret = 0, irq = 0; 1274b4cff454SVipin Bhandari size_t mem_size; 1275b4cff454SVipin Bhandari 1276b4cff454SVipin Bhandari /* REVISIT: when we're fully converted, fail if pdata is NULL */ 1277b4cff454SVipin Bhandari 1278b4cff454SVipin Bhandari ret = -ENODEV; 1279b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1280b4cff454SVipin Bhandari irq = platform_get_irq(pdev, 0); 1281b4cff454SVipin Bhandari if (!r || irq == NO_IRQ) 1282b4cff454SVipin Bhandari goto out; 1283b4cff454SVipin Bhandari 1284b4cff454SVipin Bhandari ret = -EBUSY; 1285b4cff454SVipin Bhandari mem_size = resource_size(r); 1286b4cff454SVipin Bhandari mem = request_mem_region(r->start, mem_size, pdev->name); 1287b4cff454SVipin Bhandari if (!mem) 1288b4cff454SVipin Bhandari goto out; 1289b4cff454SVipin Bhandari 1290b4cff454SVipin Bhandari ret = -ENOMEM; 1291b4cff454SVipin Bhandari mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1292b4cff454SVipin Bhandari if (!mmc) 1293b4cff454SVipin Bhandari goto out; 1294b4cff454SVipin Bhandari 1295b4cff454SVipin Bhandari host = mmc_priv(mmc); 1296b4cff454SVipin Bhandari host->mmc = mmc; /* Important */ 1297b4cff454SVipin Bhandari 1298b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1299b4cff454SVipin Bhandari if (!r) 1300b4cff454SVipin Bhandari goto out; 1301b4cff454SVipin Bhandari host->rxdma = r->start; 1302b4cff454SVipin Bhandari 1303b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1304b4cff454SVipin Bhandari if (!r) 1305b4cff454SVipin Bhandari goto out; 1306b4cff454SVipin Bhandari host->txdma = r->start; 1307b4cff454SVipin Bhandari 1308b4cff454SVipin Bhandari host->mem_res = mem; 1309b4cff454SVipin Bhandari host->base = ioremap(mem->start, mem_size); 1310b4cff454SVipin Bhandari if (!host->base) 1311b4cff454SVipin Bhandari goto out; 1312b4cff454SVipin Bhandari 1313b4cff454SVipin Bhandari ret = -ENXIO; 1314b4cff454SVipin Bhandari host->clk = clk_get(&pdev->dev, "MMCSDCLK"); 1315b4cff454SVipin Bhandari if (IS_ERR(host->clk)) { 1316b4cff454SVipin Bhandari ret = PTR_ERR(host->clk); 1317b4cff454SVipin Bhandari goto out; 1318b4cff454SVipin Bhandari } 1319b4cff454SVipin Bhandari clk_enable(host->clk); 1320b4cff454SVipin Bhandari host->mmc_input_clk = clk_get_rate(host->clk); 1321b4cff454SVipin Bhandari 1322b4cff454SVipin Bhandari init_mmcsd_host(host); 1323b4cff454SVipin Bhandari 1324ca2afb6dSSudhakar Rajashekhara if (pdata->nr_sg) 1325ca2afb6dSSudhakar Rajashekhara host->nr_sg = pdata->nr_sg - 1; 1326ca2afb6dSSudhakar Rajashekhara 1327ca2afb6dSSudhakar Rajashekhara if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1328ca2afb6dSSudhakar Rajashekhara host->nr_sg = MAX_NR_SG; 1329ca2afb6dSSudhakar Rajashekhara 1330b4cff454SVipin Bhandari host->use_dma = use_dma; 1331f9db92cbSAlagu Sankar host->mmc_irq = irq; 1332f9db92cbSAlagu Sankar host->sdio_irq = platform_get_irq(pdev, 1); 1333b4cff454SVipin Bhandari 1334b4cff454SVipin Bhandari if (host->use_dma && davinci_acquire_dma_channels(host) != 0) 1335b4cff454SVipin Bhandari host->use_dma = 0; 1336b4cff454SVipin Bhandari 1337b4cff454SVipin Bhandari /* REVISIT: someday, support IRQ-driven card detection. */ 1338b4cff454SVipin Bhandari mmc->caps |= MMC_CAP_NEEDS_POLL; 1339132f1074SVipin Bhandari mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1340b4cff454SVipin Bhandari 1341132f1074SVipin Bhandari if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1342b4cff454SVipin Bhandari mmc->caps |= MMC_CAP_4_BIT_DATA; 1343b4cff454SVipin Bhandari 1344132f1074SVipin Bhandari if (pdata && (pdata->wires == 8)) 1345132f1074SVipin Bhandari mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1346132f1074SVipin Bhandari 1347b4cff454SVipin Bhandari host->version = pdata->version; 1348b4cff454SVipin Bhandari 1349b4cff454SVipin Bhandari mmc->ops = &mmc_davinci_ops; 1350b4cff454SVipin Bhandari mmc->f_min = 312500; 1351b4cff454SVipin Bhandari mmc->f_max = 25000000; 1352b4cff454SVipin Bhandari if (pdata && pdata->max_freq) 1353b4cff454SVipin Bhandari mmc->f_max = pdata->max_freq; 1354b4cff454SVipin Bhandari if (pdata && pdata->caps) 1355b4cff454SVipin Bhandari mmc->caps |= pdata->caps; 1356b4cff454SVipin Bhandari mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1357b4cff454SVipin Bhandari 1358b4cff454SVipin Bhandari /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1359b4cff454SVipin Bhandari * Each hw_seg uses one EDMA parameter RAM slot, always one 1360b4cff454SVipin Bhandari * channel and then usually some linked slots. 1361b4cff454SVipin Bhandari */ 1362a36274e0SMartin K. Petersen mmc->max_segs = 1 + host->n_link; 1363b4cff454SVipin Bhandari 1364b4cff454SVipin Bhandari /* EDMA limit per hw segment (one or two MBytes) */ 1365b4cff454SVipin Bhandari mmc->max_seg_size = MAX_CCNT * rw_threshold; 1366b4cff454SVipin Bhandari 1367b4cff454SVipin Bhandari /* MMC/SD controller limits for multiblock requests */ 1368b4cff454SVipin Bhandari mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1369b4cff454SVipin Bhandari mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1370b4cff454SVipin Bhandari mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1371b4cff454SVipin Bhandari 1372a36274e0SMartin K. Petersen dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1373b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1374b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1375b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1376b4cff454SVipin Bhandari 1377b4cff454SVipin Bhandari platform_set_drvdata(pdev, host); 1378b4cff454SVipin Bhandari 13797e30b8deSChaithrika U S ret = mmc_davinci_cpufreq_register(host); 13807e30b8deSChaithrika U S if (ret) { 13817e30b8deSChaithrika U S dev_err(&pdev->dev, "failed to register cpufreq\n"); 13827e30b8deSChaithrika U S goto cpu_freq_fail; 13837e30b8deSChaithrika U S } 13847e30b8deSChaithrika U S 1385b4cff454SVipin Bhandari ret = mmc_add_host(mmc); 1386b4cff454SVipin Bhandari if (ret < 0) 1387b4cff454SVipin Bhandari goto out; 1388b4cff454SVipin Bhandari 1389b4cff454SVipin Bhandari ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host); 1390b4cff454SVipin Bhandari if (ret) 1391b4cff454SVipin Bhandari goto out; 1392b4cff454SVipin Bhandari 1393f9db92cbSAlagu Sankar if (host->sdio_irq >= 0) { 1394f9db92cbSAlagu Sankar ret = request_irq(host->sdio_irq, mmc_davinci_sdio_irq, 0, 1395f9db92cbSAlagu Sankar mmc_hostname(mmc), host); 1396f9db92cbSAlagu Sankar if (!ret) 1397f9db92cbSAlagu Sankar mmc->caps |= MMC_CAP_SDIO_IRQ; 1398f9db92cbSAlagu Sankar } 1399f9db92cbSAlagu Sankar 1400b4cff454SVipin Bhandari rename_region(mem, mmc_hostname(mmc)); 1401b4cff454SVipin Bhandari 1402b4cff454SVipin Bhandari dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1403b4cff454SVipin Bhandari host->use_dma ? "DMA" : "PIO", 1404b4cff454SVipin Bhandari (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1405b4cff454SVipin Bhandari 1406b4cff454SVipin Bhandari return 0; 1407b4cff454SVipin Bhandari 1408b4cff454SVipin Bhandari out: 14097e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 14107e30b8deSChaithrika U S cpu_freq_fail: 1411b4cff454SVipin Bhandari if (host) { 1412b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1413b4cff454SVipin Bhandari 1414b4cff454SVipin Bhandari if (host->clk) { 1415b4cff454SVipin Bhandari clk_disable(host->clk); 1416b4cff454SVipin Bhandari clk_put(host->clk); 1417b4cff454SVipin Bhandari } 1418b4cff454SVipin Bhandari 1419b4cff454SVipin Bhandari if (host->base) 1420b4cff454SVipin Bhandari iounmap(host->base); 1421b4cff454SVipin Bhandari } 1422b4cff454SVipin Bhandari 1423b4cff454SVipin Bhandari if (mmc) 1424b4cff454SVipin Bhandari mmc_free_host(mmc); 1425b4cff454SVipin Bhandari 1426b4cff454SVipin Bhandari if (mem) 1427b4cff454SVipin Bhandari release_resource(mem); 1428b4cff454SVipin Bhandari 1429b4cff454SVipin Bhandari dev_dbg(&pdev->dev, "probe err %d\n", ret); 1430b4cff454SVipin Bhandari 1431b4cff454SVipin Bhandari return ret; 1432b4cff454SVipin Bhandari } 1433b4cff454SVipin Bhandari 1434b4cff454SVipin Bhandari static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1435b4cff454SVipin Bhandari { 1436b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1437b4cff454SVipin Bhandari 1438b4cff454SVipin Bhandari platform_set_drvdata(pdev, NULL); 1439b4cff454SVipin Bhandari if (host) { 14407e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 14417e30b8deSChaithrika U S 1442b4cff454SVipin Bhandari mmc_remove_host(host->mmc); 1443f9db92cbSAlagu Sankar free_irq(host->mmc_irq, host); 1444f9db92cbSAlagu Sankar if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 1445f9db92cbSAlagu Sankar free_irq(host->sdio_irq, host); 1446b4cff454SVipin Bhandari 1447b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1448b4cff454SVipin Bhandari 1449b4cff454SVipin Bhandari clk_disable(host->clk); 1450b4cff454SVipin Bhandari clk_put(host->clk); 1451b4cff454SVipin Bhandari 1452b4cff454SVipin Bhandari iounmap(host->base); 1453b4cff454SVipin Bhandari 1454b4cff454SVipin Bhandari release_resource(host->mem_res); 1455b4cff454SVipin Bhandari 1456b4cff454SVipin Bhandari mmc_free_host(host->mmc); 1457b4cff454SVipin Bhandari } 1458b4cff454SVipin Bhandari 1459b4cff454SVipin Bhandari return 0; 1460b4cff454SVipin Bhandari } 1461b4cff454SVipin Bhandari 1462b4cff454SVipin Bhandari #ifdef CONFIG_PM 1463bbce5802SChaithrika U S static int davinci_mmcsd_suspend(struct device *dev) 1464b4cff454SVipin Bhandari { 1465bbce5802SChaithrika U S struct platform_device *pdev = to_platform_device(dev); 1466b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1467bbce5802SChaithrika U S int ret; 1468b4cff454SVipin Bhandari 14691a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 1470bbce5802SChaithrika U S if (!ret) { 1471bbce5802SChaithrika U S writel(0, host->base + DAVINCI_MMCIM); 1472bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1473bbce5802SChaithrika U S clk_disable(host->clk); 1474bbce5802SChaithrika U S host->suspended = 1; 1475bbce5802SChaithrika U S } else { 1476bbce5802SChaithrika U S host->suspended = 0; 1477b4cff454SVipin Bhandari } 1478b4cff454SVipin Bhandari 1479bbce5802SChaithrika U S return ret; 1480b4cff454SVipin Bhandari } 1481bbce5802SChaithrika U S 1482bbce5802SChaithrika U S static int davinci_mmcsd_resume(struct device *dev) 1483bbce5802SChaithrika U S { 1484bbce5802SChaithrika U S struct platform_device *pdev = to_platform_device(dev); 1485bbce5802SChaithrika U S struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1486bbce5802SChaithrika U S int ret; 1487bbce5802SChaithrika U S 1488bbce5802SChaithrika U S if (!host->suspended) 1489bbce5802SChaithrika U S return 0; 1490bbce5802SChaithrika U S 1491bbce5802SChaithrika U S clk_enable(host->clk); 1492bbce5802SChaithrika U S 1493bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1494bbce5802SChaithrika U S ret = mmc_resume_host(host->mmc); 1495bbce5802SChaithrika U S if (!ret) 1496bbce5802SChaithrika U S host->suspended = 0; 1497bbce5802SChaithrika U S 1498bbce5802SChaithrika U S return ret; 1499bbce5802SChaithrika U S } 1500bbce5802SChaithrika U S 1501bbce5802SChaithrika U S static const struct dev_pm_ops davinci_mmcsd_pm = { 1502bbce5802SChaithrika U S .suspend = davinci_mmcsd_suspend, 1503bbce5802SChaithrika U S .resume = davinci_mmcsd_resume, 1504bbce5802SChaithrika U S }; 1505bbce5802SChaithrika U S 1506bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1507b4cff454SVipin Bhandari #else 1508bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops NULL 1509b4cff454SVipin Bhandari #endif 1510b4cff454SVipin Bhandari 1511b4cff454SVipin Bhandari static struct platform_driver davinci_mmcsd_driver = { 1512b4cff454SVipin Bhandari .driver = { 1513b4cff454SVipin Bhandari .name = "davinci_mmc", 1514b4cff454SVipin Bhandari .owner = THIS_MODULE, 1515bbce5802SChaithrika U S .pm = davinci_mmcsd_pm_ops, 1516b4cff454SVipin Bhandari }, 1517b4cff454SVipin Bhandari .remove = __exit_p(davinci_mmcsd_remove), 1518b4cff454SVipin Bhandari }; 1519b4cff454SVipin Bhandari 1520b4cff454SVipin Bhandari static int __init davinci_mmcsd_init(void) 1521b4cff454SVipin Bhandari { 1522b4cff454SVipin Bhandari return platform_driver_probe(&davinci_mmcsd_driver, 1523b4cff454SVipin Bhandari davinci_mmcsd_probe); 1524b4cff454SVipin Bhandari } 1525b4cff454SVipin Bhandari module_init(davinci_mmcsd_init); 1526b4cff454SVipin Bhandari 1527b4cff454SVipin Bhandari static void __exit davinci_mmcsd_exit(void) 1528b4cff454SVipin Bhandari { 1529b4cff454SVipin Bhandari platform_driver_unregister(&davinci_mmcsd_driver); 1530b4cff454SVipin Bhandari } 1531b4cff454SVipin Bhandari module_exit(davinci_mmcsd_exit); 1532b4cff454SVipin Bhandari 1533b4cff454SVipin Bhandari MODULE_AUTHOR("Texas Instruments India"); 1534b4cff454SVipin Bhandari MODULE_LICENSE("GPL"); 1535b4cff454SVipin Bhandari MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 15367f8bea7fSJan Luebbe MODULE_ALIAS("platform:davinci_mmc"); 1537b4cff454SVipin Bhandari 1538