1b4cff454SVipin Bhandari /* 2b4cff454SVipin Bhandari * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3b4cff454SVipin Bhandari * 4b4cff454SVipin Bhandari * Copyright (C) 2006 Texas Instruments. 5b4cff454SVipin Bhandari * Original author: Purushotam Kumar 6b4cff454SVipin Bhandari * Copyright (C) 2009 David Brownell 7b4cff454SVipin Bhandari * 8b4cff454SVipin Bhandari * This program is free software; you can redistribute it and/or modify 9b4cff454SVipin Bhandari * it under the terms of the GNU General Public License as published by 10b4cff454SVipin Bhandari * the Free Software Foundation; either version 2 of the License, or 11b4cff454SVipin Bhandari * (at your option) any later version. 12b4cff454SVipin Bhandari * 13b4cff454SVipin Bhandari * This program is distributed in the hope that it will be useful, 14b4cff454SVipin Bhandari * but WITHOUT ANY WARRANTY; without even the implied warranty of 15b4cff454SVipin Bhandari * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16b4cff454SVipin Bhandari * GNU General Public License for more details. 17b4cff454SVipin Bhandari * 18b4cff454SVipin Bhandari * You should have received a copy of the GNU General Public License 19b4cff454SVipin Bhandari * along with this program; if not, write to the Free Software 20b4cff454SVipin Bhandari * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21b4cff454SVipin Bhandari */ 22b4cff454SVipin Bhandari 23b4cff454SVipin Bhandari #include <linux/module.h> 24b4cff454SVipin Bhandari #include <linux/ioport.h> 25b4cff454SVipin Bhandari #include <linux/platform_device.h> 26b4cff454SVipin Bhandari #include <linux/clk.h> 27b4cff454SVipin Bhandari #include <linux/err.h> 287e30b8deSChaithrika U S #include <linux/cpufreq.h> 29b4cff454SVipin Bhandari #include <linux/mmc/host.h> 30b4cff454SVipin Bhandari #include <linux/io.h> 31b4cff454SVipin Bhandari #include <linux/irq.h> 32b4cff454SVipin Bhandari #include <linux/delay.h> 335413da81SMatt Porter #include <linux/dmaengine.h> 34b4cff454SVipin Bhandari #include <linux/dma-mapping.h> 35b4cff454SVipin Bhandari #include <linux/mmc/mmc.h> 367b43da4cSManjunathappa, Prakash #include <linux/of.h> 377b43da4cSManjunathappa, Prakash #include <linux/of_device.h> 38b4cff454SVipin Bhandari 39ec2a0833SArnd Bergmann #include <linux/platform_data/mmc-davinci.h> 40b4cff454SVipin Bhandari 41b4cff454SVipin Bhandari /* 42b4cff454SVipin Bhandari * Register Definitions 43b4cff454SVipin Bhandari */ 44b4cff454SVipin Bhandari #define DAVINCI_MMCCTL 0x00 /* Control Register */ 45b4cff454SVipin Bhandari #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 46b4cff454SVipin Bhandari #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 47b4cff454SVipin Bhandari #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 48b4cff454SVipin Bhandari #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 49b4cff454SVipin Bhandari #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 50b4cff454SVipin Bhandari #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 51b4cff454SVipin Bhandari #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 52b4cff454SVipin Bhandari #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 53b4cff454SVipin Bhandari #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 54b4cff454SVipin Bhandari #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 55b4cff454SVipin Bhandari #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 56b4cff454SVipin Bhandari #define DAVINCI_MMCCMD 0x30 /* Command Register */ 57b4cff454SVipin Bhandari #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 58b4cff454SVipin Bhandari #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 59b4cff454SVipin Bhandari #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 60b4cff454SVipin Bhandari #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 61b4cff454SVipin Bhandari #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 62b4cff454SVipin Bhandari #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 63b4cff454SVipin Bhandari #define DAVINCI_MMCETOK 0x4C 64b4cff454SVipin Bhandari #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 65b4cff454SVipin Bhandari #define DAVINCI_MMCCKC 0x54 66b4cff454SVipin Bhandari #define DAVINCI_MMCTORC 0x58 67b4cff454SVipin Bhandari #define DAVINCI_MMCTODC 0x5C 68b4cff454SVipin Bhandari #define DAVINCI_MMCBLNC 0x60 69b4cff454SVipin Bhandari #define DAVINCI_SDIOCTL 0x64 70b4cff454SVipin Bhandari #define DAVINCI_SDIOST0 0x68 71f9db92cbSAlagu Sankar #define DAVINCI_SDIOIEN 0x6C 72f9db92cbSAlagu Sankar #define DAVINCI_SDIOIST 0x70 73b4cff454SVipin Bhandari #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 74b4cff454SVipin Bhandari 75b4cff454SVipin Bhandari /* DAVINCI_MMCCTL definitions */ 76b4cff454SVipin Bhandari #define MMCCTL_DATRST (1 << 0) 77b4cff454SVipin Bhandari #define MMCCTL_CMDRST (1 << 1) 78132f1074SVipin Bhandari #define MMCCTL_WIDTH_8_BIT (1 << 8) 79b4cff454SVipin Bhandari #define MMCCTL_WIDTH_4_BIT (1 << 2) 80b4cff454SVipin Bhandari #define MMCCTL_DATEG_DISABLED (0 << 6) 81b4cff454SVipin Bhandari #define MMCCTL_DATEG_RISING (1 << 6) 82b4cff454SVipin Bhandari #define MMCCTL_DATEG_FALLING (2 << 6) 83b4cff454SVipin Bhandari #define MMCCTL_DATEG_BOTH (3 << 6) 84b4cff454SVipin Bhandari #define MMCCTL_PERMDR_LE (0 << 9) 85b4cff454SVipin Bhandari #define MMCCTL_PERMDR_BE (1 << 9) 86b4cff454SVipin Bhandari #define MMCCTL_PERMDX_LE (0 << 10) 87b4cff454SVipin Bhandari #define MMCCTL_PERMDX_BE (1 << 10) 88b4cff454SVipin Bhandari 89b4cff454SVipin Bhandari /* DAVINCI_MMCCLK definitions */ 90b4cff454SVipin Bhandari #define MMCCLK_CLKEN (1 << 8) 91b4cff454SVipin Bhandari #define MMCCLK_CLKRT_MASK (0xFF << 0) 92b4cff454SVipin Bhandari 93b4cff454SVipin Bhandari /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 94b4cff454SVipin Bhandari #define MMCST0_DATDNE BIT(0) /* data done */ 95b4cff454SVipin Bhandari #define MMCST0_BSYDNE BIT(1) /* busy done */ 96b4cff454SVipin Bhandari #define MMCST0_RSPDNE BIT(2) /* command done */ 97b4cff454SVipin Bhandari #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 98b4cff454SVipin Bhandari #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 99b4cff454SVipin Bhandari #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 100b4cff454SVipin Bhandari #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 101b4cff454SVipin Bhandari #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 102b4cff454SVipin Bhandari #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 103b4cff454SVipin Bhandari #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 104b4cff454SVipin Bhandari #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 105b4cff454SVipin Bhandari #define MMCST0_TRNDNE BIT(12) /* transfer done */ 106b4cff454SVipin Bhandari 107b4cff454SVipin Bhandari /* DAVINCI_MMCST1 definitions */ 108b4cff454SVipin Bhandari #define MMCST1_BUSY (1 << 0) 109b4cff454SVipin Bhandari 110b4cff454SVipin Bhandari /* DAVINCI_MMCCMD definitions */ 111b4cff454SVipin Bhandari #define MMCCMD_CMD_MASK (0x3F << 0) 112b4cff454SVipin Bhandari #define MMCCMD_PPLEN (1 << 7) 113b4cff454SVipin Bhandari #define MMCCMD_BSYEXP (1 << 8) 114b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_MASK (3 << 9) 115b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_NONE (0 << 9) 116b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R1456 (1 << 9) 117b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R2 (2 << 9) 118b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R3 (3 << 9) 119b4cff454SVipin Bhandari #define MMCCMD_DTRW (1 << 11) 120b4cff454SVipin Bhandari #define MMCCMD_STRMTP (1 << 12) 121b4cff454SVipin Bhandari #define MMCCMD_WDATX (1 << 13) 122b4cff454SVipin Bhandari #define MMCCMD_INITCK (1 << 14) 123b4cff454SVipin Bhandari #define MMCCMD_DCLR (1 << 15) 124b4cff454SVipin Bhandari #define MMCCMD_DMATRIG (1 << 16) 125b4cff454SVipin Bhandari 126b4cff454SVipin Bhandari /* DAVINCI_MMCFIFOCTL definitions */ 127b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFORST (1 << 0) 128b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 129b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 130b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 131b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 132b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 133b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 134b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 135b4cff454SVipin Bhandari 136f9db92cbSAlagu Sankar /* DAVINCI_SDIOST0 definitions */ 137f9db92cbSAlagu Sankar #define SDIOST0_DAT1_HI BIT(0) 138f9db92cbSAlagu Sankar 139f9db92cbSAlagu Sankar /* DAVINCI_SDIOIEN definitions */ 140f9db92cbSAlagu Sankar #define SDIOIEN_IOINTEN BIT(0) 141f9db92cbSAlagu Sankar 142f9db92cbSAlagu Sankar /* DAVINCI_SDIOIST definitions */ 143f9db92cbSAlagu Sankar #define SDIOIST_IOINT BIT(0) 144b4cff454SVipin Bhandari 145b4cff454SVipin Bhandari /* MMCSD Init clock in Hz in opendrain mode */ 146b4cff454SVipin Bhandari #define MMCSD_INIT_CLOCK 200000 147b4cff454SVipin Bhandari 148b4cff454SVipin Bhandari /* 149b4cff454SVipin Bhandari * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 150ca2afb6dSSudhakar Rajashekhara * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 151a36274e0SMartin K. Petersen * for drivers with max_segs == 1, making the segments bigger (64KB) 152ca2afb6dSSudhakar Rajashekhara * than the page or two that's otherwise typical. nr_sg (passed from 153ca2afb6dSSudhakar Rajashekhara * platform data) == 16 gives at least the same throughput boost, using 154ca2afb6dSSudhakar Rajashekhara * EDMA transfer linkage instead of spending CPU time copying pages. 155b4cff454SVipin Bhandari */ 156b4cff454SVipin Bhandari #define MAX_CCNT ((1 << 16) - 1) 157b4cff454SVipin Bhandari 158ca2afb6dSSudhakar Rajashekhara #define MAX_NR_SG 16 159b4cff454SVipin Bhandari 160b4cff454SVipin Bhandari static unsigned rw_threshold = 32; 161b4cff454SVipin Bhandari module_param(rw_threshold, uint, S_IRUGO); 162b4cff454SVipin Bhandari MODULE_PARM_DESC(rw_threshold, 163b4cff454SVipin Bhandari "Read/Write threshold. Default = 32"); 164b4cff454SVipin Bhandari 165ee698f50SIdo Yariv static unsigned poll_threshold = 128; 166ee698f50SIdo Yariv module_param(poll_threshold, uint, S_IRUGO); 167ee698f50SIdo Yariv MODULE_PARM_DESC(poll_threshold, 168ee698f50SIdo Yariv "Polling transaction size threshold. Default = 128"); 169ee698f50SIdo Yariv 170ee698f50SIdo Yariv static unsigned poll_loopcount = 32; 171ee698f50SIdo Yariv module_param(poll_loopcount, uint, S_IRUGO); 172ee698f50SIdo Yariv MODULE_PARM_DESC(poll_loopcount, 173ee698f50SIdo Yariv "Maximum polling loop count. Default = 32"); 174ee698f50SIdo Yariv 175b4cff454SVipin Bhandari static unsigned __initdata use_dma = 1; 176b4cff454SVipin Bhandari module_param(use_dma, uint, 0); 177b4cff454SVipin Bhandari MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 178b4cff454SVipin Bhandari 179b4cff454SVipin Bhandari struct mmc_davinci_host { 180b4cff454SVipin Bhandari struct mmc_command *cmd; 181b4cff454SVipin Bhandari struct mmc_data *data; 182b4cff454SVipin Bhandari struct mmc_host *mmc; 183b4cff454SVipin Bhandari struct clk *clk; 184b4cff454SVipin Bhandari unsigned int mmc_input_clk; 185b4cff454SVipin Bhandari void __iomem *base; 186b4cff454SVipin Bhandari struct resource *mem_res; 187f9db92cbSAlagu Sankar int mmc_irq, sdio_irq; 188b4cff454SVipin Bhandari unsigned char bus_mode; 189b4cff454SVipin Bhandari 190b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_NONE 0 191b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_READ 1 192b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_WRITE 2 193b4cff454SVipin Bhandari unsigned char data_dir; 194b4cff454SVipin Bhandari 195b4cff454SVipin Bhandari /* buffer is used during PIO of one scatterlist segment, and 196b4cff454SVipin Bhandari * is updated along with buffer_bytes_left. bytes_left applies 197b4cff454SVipin Bhandari * to all N blocks of the PIO transfer. 198b4cff454SVipin Bhandari */ 199b4cff454SVipin Bhandari u8 *buffer; 200b4cff454SVipin Bhandari u32 buffer_bytes_left; 201b4cff454SVipin Bhandari u32 bytes_left; 202b4cff454SVipin Bhandari 2035413da81SMatt Porter struct dma_chan *dma_tx; 2045413da81SMatt Porter struct dma_chan *dma_rx; 205b4cff454SVipin Bhandari bool use_dma; 206b4cff454SVipin Bhandari bool do_dma; 207f9db92cbSAlagu Sankar bool sdio_int; 208ee698f50SIdo Yariv bool active_request; 209b4cff454SVipin Bhandari 210b4cff454SVipin Bhandari /* For PIO we walk scatterlists one segment at a time. */ 211b4cff454SVipin Bhandari unsigned int sg_len; 212b4cff454SVipin Bhandari struct scatterlist *sg; 213b4cff454SVipin Bhandari 214b4cff454SVipin Bhandari /* Version of the MMC/SD controller */ 215b4cff454SVipin Bhandari u8 version; 216b4cff454SVipin Bhandari /* for ns in one cycle calculation */ 217b4cff454SVipin Bhandari unsigned ns_in_one_cycle; 218ca2afb6dSSudhakar Rajashekhara /* Number of sg segments */ 219ca2afb6dSSudhakar Rajashekhara u8 nr_sg; 2207e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 2217e30b8deSChaithrika U S struct notifier_block freq_transition; 2227e30b8deSChaithrika U S #endif 223b4cff454SVipin Bhandari }; 224b4cff454SVipin Bhandari 225ee698f50SIdo Yariv static irqreturn_t mmc_davinci_irq(int irq, void *dev_id); 226b4cff454SVipin Bhandari 227b4cff454SVipin Bhandari /* PIO only */ 228b4cff454SVipin Bhandari static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 229b4cff454SVipin Bhandari { 230b4cff454SVipin Bhandari host->buffer_bytes_left = sg_dma_len(host->sg); 231b4cff454SVipin Bhandari host->buffer = sg_virt(host->sg); 232b4cff454SVipin Bhandari if (host->buffer_bytes_left > host->bytes_left) 233b4cff454SVipin Bhandari host->buffer_bytes_left = host->bytes_left; 234b4cff454SVipin Bhandari } 235b4cff454SVipin Bhandari 236b4cff454SVipin Bhandari static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 237b4cff454SVipin Bhandari unsigned int n) 238b4cff454SVipin Bhandari { 239b4cff454SVipin Bhandari u8 *p; 240b4cff454SVipin Bhandari unsigned int i; 241b4cff454SVipin Bhandari 242b4cff454SVipin Bhandari if (host->buffer_bytes_left == 0) { 243b4cff454SVipin Bhandari host->sg = sg_next(host->data->sg); 244b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 245b4cff454SVipin Bhandari } 246b4cff454SVipin Bhandari 247b4cff454SVipin Bhandari p = host->buffer; 248b4cff454SVipin Bhandari if (n > host->buffer_bytes_left) 249b4cff454SVipin Bhandari n = host->buffer_bytes_left; 250b4cff454SVipin Bhandari host->buffer_bytes_left -= n; 251b4cff454SVipin Bhandari host->bytes_left -= n; 252b4cff454SVipin Bhandari 253b4cff454SVipin Bhandari /* NOTE: we never transfer more than rw_threshold bytes 254b4cff454SVipin Bhandari * to/from the fifo here; there's no I/O overlap. 255b4cff454SVipin Bhandari * This also assumes that access width( i.e. ACCWD) is 4 bytes 256b4cff454SVipin Bhandari */ 257b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 258b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 259b4cff454SVipin Bhandari writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 260b4cff454SVipin Bhandari p = p + 4; 261b4cff454SVipin Bhandari } 262b4cff454SVipin Bhandari if (n & 3) { 263b4cff454SVipin Bhandari iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 264b4cff454SVipin Bhandari p = p + (n & 3); 265b4cff454SVipin Bhandari } 266b4cff454SVipin Bhandari } else { 267b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 268b4cff454SVipin Bhandari *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 269b4cff454SVipin Bhandari p = p + 4; 270b4cff454SVipin Bhandari } 271b4cff454SVipin Bhandari if (n & 3) { 272b4cff454SVipin Bhandari ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 273b4cff454SVipin Bhandari p = p + (n & 3); 274b4cff454SVipin Bhandari } 275b4cff454SVipin Bhandari } 276b4cff454SVipin Bhandari host->buffer = p; 277b4cff454SVipin Bhandari } 278b4cff454SVipin Bhandari 279b4cff454SVipin Bhandari static void mmc_davinci_start_command(struct mmc_davinci_host *host, 280b4cff454SVipin Bhandari struct mmc_command *cmd) 281b4cff454SVipin Bhandari { 282b4cff454SVipin Bhandari u32 cmd_reg = 0; 283b4cff454SVipin Bhandari u32 im_val; 284b4cff454SVipin Bhandari 285b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 286b4cff454SVipin Bhandari cmd->opcode, cmd->arg, 287b4cff454SVipin Bhandari ({ char *s; 288b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 289b4cff454SVipin Bhandari case MMC_RSP_R1: 290b4cff454SVipin Bhandari s = ", R1/R5/R6/R7 response"; 291b4cff454SVipin Bhandari break; 292b4cff454SVipin Bhandari case MMC_RSP_R1B: 293b4cff454SVipin Bhandari s = ", R1b response"; 294b4cff454SVipin Bhandari break; 295b4cff454SVipin Bhandari case MMC_RSP_R2: 296b4cff454SVipin Bhandari s = ", R2 response"; 297b4cff454SVipin Bhandari break; 298b4cff454SVipin Bhandari case MMC_RSP_R3: 299b4cff454SVipin Bhandari s = ", R3/R4 response"; 300b4cff454SVipin Bhandari break; 301b4cff454SVipin Bhandari default: 302b4cff454SVipin Bhandari s = ", (R? response)"; 303b4cff454SVipin Bhandari break; 304b4cff454SVipin Bhandari }; s; })); 305b4cff454SVipin Bhandari host->cmd = cmd; 306b4cff454SVipin Bhandari 307b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 308b4cff454SVipin Bhandari case MMC_RSP_R1B: 309b4cff454SVipin Bhandari /* There's some spec confusion about when R1B is 310b4cff454SVipin Bhandari * allowed, but if the card doesn't issue a BUSY 311b4cff454SVipin Bhandari * then it's harmless for us to allow it. 312b4cff454SVipin Bhandari */ 313b4cff454SVipin Bhandari cmd_reg |= MMCCMD_BSYEXP; 314b4cff454SVipin Bhandari /* FALLTHROUGH */ 315b4cff454SVipin Bhandari case MMC_RSP_R1: /* 48 bits, CRC */ 316b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R1456; 317b4cff454SVipin Bhandari break; 318b4cff454SVipin Bhandari case MMC_RSP_R2: /* 136 bits, CRC */ 319b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R2; 320b4cff454SVipin Bhandari break; 321b4cff454SVipin Bhandari case MMC_RSP_R3: /* 48 bits, no CRC */ 322b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R3; 323b4cff454SVipin Bhandari break; 324b4cff454SVipin Bhandari default: 325b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_NONE; 326b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 327b4cff454SVipin Bhandari mmc_resp_type(cmd)); 328b4cff454SVipin Bhandari break; 329b4cff454SVipin Bhandari } 330b4cff454SVipin Bhandari 331b4cff454SVipin Bhandari /* Set command index */ 332b4cff454SVipin Bhandari cmd_reg |= cmd->opcode; 333b4cff454SVipin Bhandari 334b4cff454SVipin Bhandari /* Enable EDMA transfer triggers */ 335b4cff454SVipin Bhandari if (host->do_dma) 336b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 337b4cff454SVipin Bhandari 338b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 339b4cff454SVipin Bhandari host->data_dir == DAVINCI_MMC_DATADIR_READ) 340b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 341b4cff454SVipin Bhandari 342b4cff454SVipin Bhandari /* Setting whether command involves data transfer or not */ 343b4cff454SVipin Bhandari if (cmd->data) 344b4cff454SVipin Bhandari cmd_reg |= MMCCMD_WDATX; 345b4cff454SVipin Bhandari 346b4cff454SVipin Bhandari /* Setting whether data read or write */ 347b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 348b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DTRW; 349b4cff454SVipin Bhandari 350b4cff454SVipin Bhandari if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 351b4cff454SVipin Bhandari cmd_reg |= MMCCMD_PPLEN; 352b4cff454SVipin Bhandari 353b4cff454SVipin Bhandari /* set Command timeout */ 354b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 355b4cff454SVipin Bhandari 356b4cff454SVipin Bhandari /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 357b4cff454SVipin Bhandari im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 358b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 359b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 360b4cff454SVipin Bhandari 361b4cff454SVipin Bhandari if (!host->do_dma) 362b4cff454SVipin Bhandari im_val |= MMCST0_DXRDY; 363b4cff454SVipin Bhandari } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 364b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 365b4cff454SVipin Bhandari 366b4cff454SVipin Bhandari if (!host->do_dma) 367b4cff454SVipin Bhandari im_val |= MMCST0_DRRDY; 368b4cff454SVipin Bhandari } 369b4cff454SVipin Bhandari 370b4cff454SVipin Bhandari /* 371b4cff454SVipin Bhandari * Before non-DMA WRITE commands the controller needs priming: 372b4cff454SVipin Bhandari * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 373b4cff454SVipin Bhandari */ 374b4cff454SVipin Bhandari if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 375b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 376b4cff454SVipin Bhandari 377b4cff454SVipin Bhandari writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 378b4cff454SVipin Bhandari writel(cmd_reg, host->base + DAVINCI_MMCCMD); 379ee698f50SIdo Yariv 380ee698f50SIdo Yariv host->active_request = true; 381ee698f50SIdo Yariv 382ee698f50SIdo Yariv if (!host->do_dma && host->bytes_left <= poll_threshold) { 383ee698f50SIdo Yariv u32 count = poll_loopcount; 384ee698f50SIdo Yariv 385ee698f50SIdo Yariv while (host->active_request && count--) { 386ee698f50SIdo Yariv mmc_davinci_irq(0, host); 387ee698f50SIdo Yariv cpu_relax(); 388ee698f50SIdo Yariv } 389ee698f50SIdo Yariv } 390ee698f50SIdo Yariv 391ee698f50SIdo Yariv if (host->active_request) 392b4cff454SVipin Bhandari writel(im_val, host->base + DAVINCI_MMCIM); 393b4cff454SVipin Bhandari } 394b4cff454SVipin Bhandari 395b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 396b4cff454SVipin Bhandari 397b4cff454SVipin Bhandari /* DMA infrastructure */ 398b4cff454SVipin Bhandari 399b4cff454SVipin Bhandari static void davinci_abort_dma(struct mmc_davinci_host *host) 400b4cff454SVipin Bhandari { 4015413da81SMatt Porter struct dma_chan *sync_dev; 402b4cff454SVipin Bhandari 403b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 4045413da81SMatt Porter sync_dev = host->dma_rx; 405b4cff454SVipin Bhandari else 4065413da81SMatt Porter sync_dev = host->dma_tx; 407b4cff454SVipin Bhandari 4085413da81SMatt Porter dmaengine_terminate_all(sync_dev); 409b4cff454SVipin Bhandari } 410b4cff454SVipin Bhandari 4115413da81SMatt Porter static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 412b4cff454SVipin Bhandari struct mmc_data *data) 413b4cff454SVipin Bhandari { 4145413da81SMatt Porter struct dma_chan *chan; 4155413da81SMatt Porter struct dma_async_tx_descriptor *desc; 4165413da81SMatt Porter int ret = 0; 417b4cff454SVipin Bhandari 418b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 4195413da81SMatt Porter struct dma_slave_config dma_tx_conf = { 4205413da81SMatt Porter .direction = DMA_MEM_TO_DEV, 4215413da81SMatt Porter .dst_addr = host->mem_res->start + DAVINCI_MMCDXR, 4225413da81SMatt Porter .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 4235413da81SMatt Porter .dst_maxburst = 4245413da81SMatt Porter rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 4255413da81SMatt Porter }; 4265413da81SMatt Porter chan = host->dma_tx; 4275413da81SMatt Porter dmaengine_slave_config(host->dma_tx, &dma_tx_conf); 4285413da81SMatt Porter 4295413da81SMatt Porter desc = dmaengine_prep_slave_sg(host->dma_tx, 4305413da81SMatt Porter data->sg, 4315413da81SMatt Porter host->sg_len, 4325413da81SMatt Porter DMA_MEM_TO_DEV, 4335413da81SMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 4345413da81SMatt Porter if (!desc) { 4355413da81SMatt Porter dev_dbg(mmc_dev(host->mmc), 4365413da81SMatt Porter "failed to allocate DMA TX descriptor"); 4375413da81SMatt Porter ret = -1; 4385413da81SMatt Porter goto out; 4395413da81SMatt Porter } 440b4cff454SVipin Bhandari } else { 4415413da81SMatt Porter struct dma_slave_config dma_rx_conf = { 4425413da81SMatt Porter .direction = DMA_DEV_TO_MEM, 4435413da81SMatt Porter .src_addr = host->mem_res->start + DAVINCI_MMCDRR, 4445413da81SMatt Porter .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 4455413da81SMatt Porter .src_maxburst = 4465413da81SMatt Porter rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 4475413da81SMatt Porter }; 4485413da81SMatt Porter chan = host->dma_rx; 4495413da81SMatt Porter dmaengine_slave_config(host->dma_rx, &dma_rx_conf); 4505413da81SMatt Porter 4515413da81SMatt Porter desc = dmaengine_prep_slave_sg(host->dma_rx, 4525413da81SMatt Porter data->sg, 4535413da81SMatt Porter host->sg_len, 4545413da81SMatt Porter DMA_DEV_TO_MEM, 4555413da81SMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 4565413da81SMatt Porter if (!desc) { 4575413da81SMatt Porter dev_dbg(mmc_dev(host->mmc), 4585413da81SMatt Porter "failed to allocate DMA RX descriptor"); 4595413da81SMatt Porter ret = -1; 4605413da81SMatt Porter goto out; 4615413da81SMatt Porter } 462b4cff454SVipin Bhandari } 463b4cff454SVipin Bhandari 4645413da81SMatt Porter dmaengine_submit(desc); 4655413da81SMatt Porter dma_async_issue_pending(chan); 466b4cff454SVipin Bhandari 4675413da81SMatt Porter out: 4685413da81SMatt Porter return ret; 469b4cff454SVipin Bhandari } 470b4cff454SVipin Bhandari 471b4cff454SVipin Bhandari static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 472b4cff454SVipin Bhandari struct mmc_data *data) 473b4cff454SVipin Bhandari { 474b4cff454SVipin Bhandari int i; 475b4cff454SVipin Bhandari int mask = rw_threshold - 1; 4765413da81SMatt Porter int ret = 0; 477b4cff454SVipin Bhandari 478b4cff454SVipin Bhandari host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 479b4cff454SVipin Bhandari ((data->flags & MMC_DATA_WRITE) 480b4cff454SVipin Bhandari ? DMA_TO_DEVICE 481b4cff454SVipin Bhandari : DMA_FROM_DEVICE)); 482b4cff454SVipin Bhandari 483b4cff454SVipin Bhandari /* no individual DMA segment should need a partial FIFO */ 484b4cff454SVipin Bhandari for (i = 0; i < host->sg_len; i++) { 485b4cff454SVipin Bhandari if (sg_dma_len(data->sg + i) & mask) { 486b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), 487b4cff454SVipin Bhandari data->sg, data->sg_len, 488b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 489b4cff454SVipin Bhandari ? DMA_TO_DEVICE 490b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 491b4cff454SVipin Bhandari return -1; 492b4cff454SVipin Bhandari } 493b4cff454SVipin Bhandari } 494b4cff454SVipin Bhandari 495b4cff454SVipin Bhandari host->do_dma = 1; 4965413da81SMatt Porter ret = mmc_davinci_send_dma_request(host, data); 497b4cff454SVipin Bhandari 4985413da81SMatt Porter return ret; 499b4cff454SVipin Bhandari } 500b4cff454SVipin Bhandari 501b4cff454SVipin Bhandari static void __init_or_module 502b4cff454SVipin Bhandari davinci_release_dma_channels(struct mmc_davinci_host *host) 503b4cff454SVipin Bhandari { 504b4cff454SVipin Bhandari if (!host->use_dma) 505b4cff454SVipin Bhandari return; 506b4cff454SVipin Bhandari 5075413da81SMatt Porter dma_release_channel(host->dma_tx); 5085413da81SMatt Porter dma_release_channel(host->dma_rx); 509b4cff454SVipin Bhandari } 510b4cff454SVipin Bhandari 511b4cff454SVipin Bhandari static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 512b4cff454SVipin Bhandari { 5130a4d7236SPeter Ujfalusi host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); 5140a4d7236SPeter Ujfalusi if (IS_ERR(host->dma_tx)) { 5155413da81SMatt Porter dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); 5160a4d7236SPeter Ujfalusi return PTR_ERR(host->dma_tx); 517b4cff454SVipin Bhandari } 518b4cff454SVipin Bhandari 5190a4d7236SPeter Ujfalusi host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); 5200a4d7236SPeter Ujfalusi if (IS_ERR(host->dma_rx)) { 5215413da81SMatt Porter dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); 5220a4d7236SPeter Ujfalusi dma_release_channel(host->dma_tx); 5230a4d7236SPeter Ujfalusi return PTR_ERR(host->dma_rx); 524b4cff454SVipin Bhandari } 525b4cff454SVipin Bhandari 526b4cff454SVipin Bhandari return 0; 527b4cff454SVipin Bhandari } 528b4cff454SVipin Bhandari 529b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 530b4cff454SVipin Bhandari 531b4cff454SVipin Bhandari static void 532b4cff454SVipin Bhandari mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 533b4cff454SVipin Bhandari { 534b4cff454SVipin Bhandari int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 535b4cff454SVipin Bhandari int timeout; 536b4cff454SVipin Bhandari struct mmc_data *data = req->data; 537b4cff454SVipin Bhandari 538b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 539b4cff454SVipin Bhandari fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 540b4cff454SVipin Bhandari 541b4cff454SVipin Bhandari host->data = data; 542b4cff454SVipin Bhandari if (data == NULL) { 543b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 544b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCBLEN); 545b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCNBLK); 546b4cff454SVipin Bhandari return; 547b4cff454SVipin Bhandari } 548b4cff454SVipin Bhandari 549bbb66fcbSJaehoon Chung dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n", 550b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) ? "write" : "read", 551b4cff454SVipin Bhandari data->blocks, data->blksz); 552b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 553b4cff454SVipin Bhandari data->timeout_clks, data->timeout_ns); 554b4cff454SVipin Bhandari timeout = data->timeout_clks + 555b4cff454SVipin Bhandari (data->timeout_ns / host->ns_in_one_cycle); 556b4cff454SVipin Bhandari if (timeout > 0xffff) 557b4cff454SVipin Bhandari timeout = 0xffff; 558b4cff454SVipin Bhandari 559b4cff454SVipin Bhandari writel(timeout, host->base + DAVINCI_MMCTOD); 560b4cff454SVipin Bhandari writel(data->blocks, host->base + DAVINCI_MMCNBLK); 561b4cff454SVipin Bhandari writel(data->blksz, host->base + DAVINCI_MMCBLEN); 562b4cff454SVipin Bhandari 563b4cff454SVipin Bhandari /* Configure the FIFO */ 564bbb66fcbSJaehoon Chung if (data->flags & MMC_DATA_WRITE) { 565b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 566b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 567b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 568b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 569b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 570bbb66fcbSJaehoon Chung } else { 571b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_READ; 572b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 573b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 574b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 575b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 576b4cff454SVipin Bhandari } 577b4cff454SVipin Bhandari 578b4cff454SVipin Bhandari host->buffer = NULL; 579b4cff454SVipin Bhandari host->bytes_left = data->blocks * data->blksz; 580b4cff454SVipin Bhandari 581b4cff454SVipin Bhandari /* For now we try to use DMA whenever we won't need partial FIFO 582b4cff454SVipin Bhandari * reads or writes, either for the whole transfer (as tested here) 583b4cff454SVipin Bhandari * or for any individual scatterlist segment (tested when we call 584b4cff454SVipin Bhandari * start_dma_transfer). 585b4cff454SVipin Bhandari * 586b4cff454SVipin Bhandari * While we *could* change that, unusual block sizes are rarely 587b4cff454SVipin Bhandari * used. The occasional fallback to PIO should't hurt. 588b4cff454SVipin Bhandari */ 589b4cff454SVipin Bhandari if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 590b4cff454SVipin Bhandari && mmc_davinci_start_dma_transfer(host, data) == 0) { 591b4cff454SVipin Bhandari /* zero this to ensure we take no PIO paths */ 592b4cff454SVipin Bhandari host->bytes_left = 0; 593b4cff454SVipin Bhandari } else { 594b4cff454SVipin Bhandari /* Revert to CPU Copy */ 595b4cff454SVipin Bhandari host->sg_len = data->sg_len; 596b4cff454SVipin Bhandari host->sg = host->data->sg; 597b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 598b4cff454SVipin Bhandari } 599b4cff454SVipin Bhandari } 600b4cff454SVipin Bhandari 601b4cff454SVipin Bhandari static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 602b4cff454SVipin Bhandari { 603b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 604b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(900); 605b4cff454SVipin Bhandari u32 mmcst1 = 0; 606b4cff454SVipin Bhandari 607b4cff454SVipin Bhandari /* Card may still be sending BUSY after a previous operation, 608b4cff454SVipin Bhandari * typically some kind of write. If so, we can't proceed yet. 609b4cff454SVipin Bhandari */ 610b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 611b4cff454SVipin Bhandari mmcst1 = readl(host->base + DAVINCI_MMCST1); 612b4cff454SVipin Bhandari if (!(mmcst1 & MMCST1_BUSY)) 613b4cff454SVipin Bhandari break; 614b4cff454SVipin Bhandari cpu_relax(); 615b4cff454SVipin Bhandari } 616b4cff454SVipin Bhandari if (mmcst1 & MMCST1_BUSY) { 617b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 618b4cff454SVipin Bhandari req->cmd->error = -ETIMEDOUT; 619b4cff454SVipin Bhandari mmc_request_done(mmc, req); 620b4cff454SVipin Bhandari return; 621b4cff454SVipin Bhandari } 622b4cff454SVipin Bhandari 623b4cff454SVipin Bhandari host->do_dma = 0; 624b4cff454SVipin Bhandari mmc_davinci_prepare_data(host, req); 625b4cff454SVipin Bhandari mmc_davinci_start_command(host, req->cmd); 626b4cff454SVipin Bhandari } 627b4cff454SVipin Bhandari 628b4cff454SVipin Bhandari static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 629b4cff454SVipin Bhandari unsigned int mmc_req_freq) 630b4cff454SVipin Bhandari { 631b4cff454SVipin Bhandari unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 632b4cff454SVipin Bhandari 633b4cff454SVipin Bhandari mmc_pclk = host->mmc_input_clk; 634b4cff454SVipin Bhandari if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 635b4cff454SVipin Bhandari mmc_push_pull_divisor = ((unsigned int)mmc_pclk 636b4cff454SVipin Bhandari / (2 * mmc_req_freq)) - 1; 637b4cff454SVipin Bhandari else 638b4cff454SVipin Bhandari mmc_push_pull_divisor = 0; 639b4cff454SVipin Bhandari 640b4cff454SVipin Bhandari mmc_freq = (unsigned int)mmc_pclk 641b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)); 642b4cff454SVipin Bhandari 643b4cff454SVipin Bhandari if (mmc_freq > mmc_req_freq) 644b4cff454SVipin Bhandari mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 645b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 646b4cff454SVipin Bhandari if (mmc_req_freq <= 400000) 647b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 648b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000)); 649b4cff454SVipin Bhandari else 650b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 651b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 652b4cff454SVipin Bhandari 653b4cff454SVipin Bhandari return mmc_push_pull_divisor; 654b4cff454SVipin Bhandari } 655b4cff454SVipin Bhandari 6567e30b8deSChaithrika U S static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 657b4cff454SVipin Bhandari { 658b4cff454SVipin Bhandari unsigned int open_drain_freq = 0, mmc_pclk = 0; 659b4cff454SVipin Bhandari unsigned int mmc_push_pull_freq = 0; 660b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 661b4cff454SVipin Bhandari 662b4cff454SVipin Bhandari if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 663b4cff454SVipin Bhandari u32 temp; 664b4cff454SVipin Bhandari 665b4cff454SVipin Bhandari /* Ignoring the init clock value passed for fixing the inter 666b4cff454SVipin Bhandari * operability with different cards. 667b4cff454SVipin Bhandari */ 668b4cff454SVipin Bhandari open_drain_freq = ((unsigned int)mmc_pclk 669b4cff454SVipin Bhandari / (2 * MMCSD_INIT_CLOCK)) - 1; 670b4cff454SVipin Bhandari 671b4cff454SVipin Bhandari if (open_drain_freq > 0xFF) 672b4cff454SVipin Bhandari open_drain_freq = 0xFF; 673b4cff454SVipin Bhandari 674b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 675b4cff454SVipin Bhandari temp |= open_drain_freq; 676b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 677b4cff454SVipin Bhandari 678b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 679b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 680b4cff454SVipin Bhandari } else { 681b4cff454SVipin Bhandari u32 temp; 682b4cff454SVipin Bhandari mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 683b4cff454SVipin Bhandari 684b4cff454SVipin Bhandari if (mmc_push_pull_freq > 0xFF) 685b4cff454SVipin Bhandari mmc_push_pull_freq = 0xFF; 686b4cff454SVipin Bhandari 687b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 688b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 689b4cff454SVipin Bhandari 690b4cff454SVipin Bhandari udelay(10); 691b4cff454SVipin Bhandari 692b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 693b4cff454SVipin Bhandari temp |= mmc_push_pull_freq; 694b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 695b4cff454SVipin Bhandari 696b4cff454SVipin Bhandari writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 697b4cff454SVipin Bhandari 698b4cff454SVipin Bhandari udelay(10); 699b4cff454SVipin Bhandari } 7007e30b8deSChaithrika U S } 7017e30b8deSChaithrika U S 7027e30b8deSChaithrika U S static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 7037e30b8deSChaithrika U S { 7047e30b8deSChaithrika U S struct mmc_davinci_host *host = mmc_priv(mmc); 7054a9de8adSIdo Yariv struct platform_device *pdev = to_platform_device(mmc->parent); 7064a9de8adSIdo Yariv struct davinci_mmc_config *config = pdev->dev.platform_data; 7077e30b8deSChaithrika U S 7087e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), 7097e30b8deSChaithrika U S "clock %dHz busmode %d powermode %d Vdd %04x\n", 7107e30b8deSChaithrika U S ios->clock, ios->bus_mode, ios->power_mode, 7117e30b8deSChaithrika U S ios->vdd); 712132f1074SVipin Bhandari 7134a9de8adSIdo Yariv switch (ios->power_mode) { 7144a9de8adSIdo Yariv case MMC_POWER_OFF: 7154a9de8adSIdo Yariv if (config && config->set_power) 7164a9de8adSIdo Yariv config->set_power(pdev->id, false); 7174a9de8adSIdo Yariv break; 7184a9de8adSIdo Yariv case MMC_POWER_UP: 7194a9de8adSIdo Yariv if (config && config->set_power) 7204a9de8adSIdo Yariv config->set_power(pdev->id, true); 7214a9de8adSIdo Yariv break; 7224a9de8adSIdo Yariv } 7234a9de8adSIdo Yariv 724132f1074SVipin Bhandari switch (ios->bus_width) { 725132f1074SVipin Bhandari case MMC_BUS_WIDTH_8: 726132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 727132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 728132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 729132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 730132f1074SVipin Bhandari break; 731132f1074SVipin Bhandari case MMC_BUS_WIDTH_4: 7327e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 733132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 734132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 735132f1074SVipin Bhandari ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 7367e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 737132f1074SVipin Bhandari else 738132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) | 739132f1074SVipin Bhandari MMCCTL_WIDTH_4_BIT, 7407e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 741132f1074SVipin Bhandari break; 742132f1074SVipin Bhandari case MMC_BUS_WIDTH_1: 743132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 744132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 745132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 746132f1074SVipin Bhandari ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 747132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 748132f1074SVipin Bhandari else 749132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 750132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT, 751132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 752132f1074SVipin Bhandari break; 7537e30b8deSChaithrika U S } 7547e30b8deSChaithrika U S 7557e30b8deSChaithrika U S calculate_clk_divider(mmc, ios); 756b4cff454SVipin Bhandari 757b4cff454SVipin Bhandari host->bus_mode = ios->bus_mode; 758b4cff454SVipin Bhandari if (ios->power_mode == MMC_POWER_UP) { 759b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(50); 760b4cff454SVipin Bhandari bool lose = true; 761b4cff454SVipin Bhandari 762b4cff454SVipin Bhandari /* Send clock cycles, poll completion */ 763b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCARGHL); 764b4cff454SVipin Bhandari writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 765b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 766b4cff454SVipin Bhandari u32 tmp = readl(host->base + DAVINCI_MMCST0); 767b4cff454SVipin Bhandari 768b4cff454SVipin Bhandari if (tmp & MMCST0_RSPDNE) { 769b4cff454SVipin Bhandari lose = false; 770b4cff454SVipin Bhandari break; 771b4cff454SVipin Bhandari } 772b4cff454SVipin Bhandari cpu_relax(); 773b4cff454SVipin Bhandari } 774b4cff454SVipin Bhandari if (lose) 775b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 776b4cff454SVipin Bhandari } 777b4cff454SVipin Bhandari 778b4cff454SVipin Bhandari /* FIXME on power OFF, reset things ... */ 779b4cff454SVipin Bhandari } 780b4cff454SVipin Bhandari 781b4cff454SVipin Bhandari static void 782b4cff454SVipin Bhandari mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 783b4cff454SVipin Bhandari { 784b4cff454SVipin Bhandari host->data = NULL; 785b4cff454SVipin Bhandari 786f9db92cbSAlagu Sankar if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 787f9db92cbSAlagu Sankar /* 788f9db92cbSAlagu Sankar * SDIO Interrupt Detection work-around as suggested by 789f9db92cbSAlagu Sankar * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata 790f9db92cbSAlagu Sankar * 2.1.6): Signal SDIO interrupt only if it is enabled by core 791f9db92cbSAlagu Sankar */ 792f9db92cbSAlagu Sankar if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & 793f9db92cbSAlagu Sankar SDIOST0_DAT1_HI)) { 794f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 795f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 796f9db92cbSAlagu Sankar } 797f9db92cbSAlagu Sankar } 798f9db92cbSAlagu Sankar 799b4cff454SVipin Bhandari if (host->do_dma) { 800b4cff454SVipin Bhandari davinci_abort_dma(host); 801b4cff454SVipin Bhandari 802b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 803b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 804b4cff454SVipin Bhandari ? DMA_TO_DEVICE 805b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 806b4cff454SVipin Bhandari host->do_dma = false; 807b4cff454SVipin Bhandari } 808b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 809b4cff454SVipin Bhandari 810b4cff454SVipin Bhandari if (!data->stop || (host->cmd && host->cmd->error)) { 811b4cff454SVipin Bhandari mmc_request_done(host->mmc, data->mrq); 812b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 813ee698f50SIdo Yariv host->active_request = false; 814b4cff454SVipin Bhandari } else 815b4cff454SVipin Bhandari mmc_davinci_start_command(host, data->stop); 816b4cff454SVipin Bhandari } 817b4cff454SVipin Bhandari 818b4cff454SVipin Bhandari static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 819b4cff454SVipin Bhandari struct mmc_command *cmd) 820b4cff454SVipin Bhandari { 821b4cff454SVipin Bhandari host->cmd = NULL; 822b4cff454SVipin Bhandari 823b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_PRESENT) { 824b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_136) { 825b4cff454SVipin Bhandari /* response type 2 */ 826b4cff454SVipin Bhandari cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 827b4cff454SVipin Bhandari cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 828b4cff454SVipin Bhandari cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 829b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 830b4cff454SVipin Bhandari } else { 831b4cff454SVipin Bhandari /* response types 1, 1b, 3, 4, 5, 6 */ 832b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 833b4cff454SVipin Bhandari } 834b4cff454SVipin Bhandari } 835b4cff454SVipin Bhandari 836b4cff454SVipin Bhandari if (host->data == NULL || cmd->error) { 837b4cff454SVipin Bhandari if (cmd->error == -ETIMEDOUT) 838b4cff454SVipin Bhandari cmd->mrq->cmd->retries = 0; 839b4cff454SVipin Bhandari mmc_request_done(host->mmc, cmd->mrq); 840b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 841ee698f50SIdo Yariv host->active_request = false; 842b4cff454SVipin Bhandari } 843b4cff454SVipin Bhandari } 844b4cff454SVipin Bhandari 84506de845fSChaithrika U S static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 84606de845fSChaithrika U S int val) 847b4cff454SVipin Bhandari { 848b4cff454SVipin Bhandari u32 temp; 849b4cff454SVipin Bhandari 850b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCTL); 85106de845fSChaithrika U S if (val) /* reset */ 85206de845fSChaithrika U S temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 85306de845fSChaithrika U S else /* enable */ 854b4cff454SVipin Bhandari temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 85506de845fSChaithrika U S 856b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCTL); 85706de845fSChaithrika U S udelay(10); 85806de845fSChaithrika U S } 85906de845fSChaithrika U S 86006de845fSChaithrika U S static void 86106de845fSChaithrika U S davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 86206de845fSChaithrika U S { 86306de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 86406de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 865b4cff454SVipin Bhandari } 866b4cff454SVipin Bhandari 867f9db92cbSAlagu Sankar static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) 868f9db92cbSAlagu Sankar { 869f9db92cbSAlagu Sankar struct mmc_davinci_host *host = dev_id; 870f9db92cbSAlagu Sankar unsigned int status; 871f9db92cbSAlagu Sankar 872f9db92cbSAlagu Sankar status = readl(host->base + DAVINCI_SDIOIST); 873f9db92cbSAlagu Sankar if (status & SDIOIST_IOINT) { 874f9db92cbSAlagu Sankar dev_dbg(mmc_dev(host->mmc), 875f9db92cbSAlagu Sankar "SDIO interrupt status %x\n", status); 876f9db92cbSAlagu Sankar writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 877f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 878f9db92cbSAlagu Sankar } 879f9db92cbSAlagu Sankar return IRQ_HANDLED; 880f9db92cbSAlagu Sankar } 881f9db92cbSAlagu Sankar 882b4cff454SVipin Bhandari static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 883b4cff454SVipin Bhandari { 884b4cff454SVipin Bhandari struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 885b4cff454SVipin Bhandari unsigned int status, qstatus; 886b4cff454SVipin Bhandari int end_command = 0; 887b4cff454SVipin Bhandari int end_transfer = 0; 888b4cff454SVipin Bhandari struct mmc_data *data = host->data; 889b4cff454SVipin Bhandari 890b4cff454SVipin Bhandari if (host->cmd == NULL && host->data == NULL) { 891b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 892b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 893b4cff454SVipin Bhandari "Spurious interrupt 0x%04x\n", status); 894b4cff454SVipin Bhandari /* Disable the interrupt from mmcsd */ 895b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 896b4cff454SVipin Bhandari return IRQ_NONE; 897b4cff454SVipin Bhandari } 898b4cff454SVipin Bhandari 899b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 900b4cff454SVipin Bhandari qstatus = status; 901b4cff454SVipin Bhandari 902b4cff454SVipin Bhandari /* handle FIFO first when using PIO for data. 903b4cff454SVipin Bhandari * bytes_left will decrease to zero as I/O progress and status will 904b4cff454SVipin Bhandari * read zero over iteration because this controller status 905b4cff454SVipin Bhandari * register(MMCST0) reports any status only once and it is cleared 906b4cff454SVipin Bhandari * by read. So, it is not unbouned loop even in the case of 907b4cff454SVipin Bhandari * non-dma. 908b4cff454SVipin Bhandari */ 909be7b5622SIdo Yariv if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 910be7b5622SIdo Yariv unsigned long im_val; 911be7b5622SIdo Yariv 912be7b5622SIdo Yariv /* 913be7b5622SIdo Yariv * If interrupts fire during the following loop, they will be 914be7b5622SIdo Yariv * handled by the handler, but the PIC will still buffer these. 915be7b5622SIdo Yariv * As a result, the handler will be called again to serve these 916be7b5622SIdo Yariv * needlessly. In order to avoid these spurious interrupts, 917be7b5622SIdo Yariv * keep interrupts masked during the loop. 918be7b5622SIdo Yariv */ 919be7b5622SIdo Yariv im_val = readl(host->base + DAVINCI_MMCIM); 920be7b5622SIdo Yariv writel(0, host->base + DAVINCI_MMCIM); 921be7b5622SIdo Yariv 922be7b5622SIdo Yariv do { 923b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 924b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 925b4cff454SVipin Bhandari qstatus |= status; 926be7b5622SIdo Yariv } while (host->bytes_left && 927be7b5622SIdo Yariv (status & (MMCST0_DXRDY | MMCST0_DRRDY))); 928be7b5622SIdo Yariv 929be7b5622SIdo Yariv /* 930be7b5622SIdo Yariv * If an interrupt is pending, it is assumed it will fire when 931be7b5622SIdo Yariv * it is unmasked. This assumption is also taken when the MMCIM 932be7b5622SIdo Yariv * is first set. Otherwise, writing to MMCIM after reading the 933be7b5622SIdo Yariv * status is race-prone. 934be7b5622SIdo Yariv */ 935be7b5622SIdo Yariv writel(im_val, host->base + DAVINCI_MMCIM); 936b4cff454SVipin Bhandari } 937b4cff454SVipin Bhandari 938b4cff454SVipin Bhandari if (qstatus & MMCST0_DATDNE) { 939b4cff454SVipin Bhandari /* All blocks sent/received, and CRC checks passed */ 940b4cff454SVipin Bhandari if (data != NULL) { 941b4cff454SVipin Bhandari if ((host->do_dma == 0) && (host->bytes_left > 0)) { 942b4cff454SVipin Bhandari /* if datasize < rw_threshold 943b4cff454SVipin Bhandari * no RX ints are generated 944b4cff454SVipin Bhandari */ 945b4cff454SVipin Bhandari davinci_fifo_data_trans(host, host->bytes_left); 946b4cff454SVipin Bhandari } 947b4cff454SVipin Bhandari end_transfer = 1; 948b4cff454SVipin Bhandari data->bytes_xfered = data->blocks * data->blksz; 949b4cff454SVipin Bhandari } else { 950b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), 951b4cff454SVipin Bhandari "DATDNE with no host->data\n"); 952b4cff454SVipin Bhandari } 953b4cff454SVipin Bhandari } 954b4cff454SVipin Bhandari 955b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRD) { 956b4cff454SVipin Bhandari /* Read data timeout */ 957b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 958b4cff454SVipin Bhandari end_transfer = 1; 959b4cff454SVipin Bhandari 960b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 961b4cff454SVipin Bhandari "read data timeout, status %x\n", 962b4cff454SVipin Bhandari qstatus); 963b4cff454SVipin Bhandari 964b4cff454SVipin Bhandari davinci_abort_data(host, data); 965b4cff454SVipin Bhandari } 966b4cff454SVipin Bhandari 967b4cff454SVipin Bhandari if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 968b4cff454SVipin Bhandari /* Data CRC error */ 969b4cff454SVipin Bhandari data->error = -EILSEQ; 970b4cff454SVipin Bhandari end_transfer = 1; 971b4cff454SVipin Bhandari 972b4cff454SVipin Bhandari /* NOTE: this controller uses CRCWR to report both CRC 973b4cff454SVipin Bhandari * errors and timeouts (on writes). MMCDRSP values are 974b4cff454SVipin Bhandari * only weakly documented, but 0x9f was clearly a timeout 975b4cff454SVipin Bhandari * case and the two three-bit patterns in various SD specs 976b4cff454SVipin Bhandari * (101, 010) aren't part of it ... 977b4cff454SVipin Bhandari */ 978b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCWR) { 979b4cff454SVipin Bhandari u32 temp = readb(host->base + DAVINCI_MMCDRSP); 980b4cff454SVipin Bhandari 981b4cff454SVipin Bhandari if (temp == 0x9f) 982b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 983b4cff454SVipin Bhandari } 984b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 985b4cff454SVipin Bhandari (qstatus & MMCST0_CRCWR) ? "write" : "read", 986b4cff454SVipin Bhandari (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 987b4cff454SVipin Bhandari 988b4cff454SVipin Bhandari davinci_abort_data(host, data); 989b4cff454SVipin Bhandari } 990b4cff454SVipin Bhandari 991b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRS) { 992b4cff454SVipin Bhandari /* Command timeout */ 993b4cff454SVipin Bhandari if (host->cmd) { 994b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 995b4cff454SVipin Bhandari "CMD%d timeout, status %x\n", 996b4cff454SVipin Bhandari host->cmd->opcode, qstatus); 997b4cff454SVipin Bhandari host->cmd->error = -ETIMEDOUT; 998b4cff454SVipin Bhandari if (data) { 999b4cff454SVipin Bhandari end_transfer = 1; 1000b4cff454SVipin Bhandari davinci_abort_data(host, data); 1001b4cff454SVipin Bhandari } else 1002b4cff454SVipin Bhandari end_command = 1; 1003b4cff454SVipin Bhandari } 1004b4cff454SVipin Bhandari } 1005b4cff454SVipin Bhandari 1006b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCRS) { 1007b4cff454SVipin Bhandari /* Command CRC error */ 1008b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1009b4cff454SVipin Bhandari if (host->cmd) { 1010b4cff454SVipin Bhandari host->cmd->error = -EILSEQ; 1011b4cff454SVipin Bhandari end_command = 1; 1012b4cff454SVipin Bhandari } 1013b4cff454SVipin Bhandari } 1014b4cff454SVipin Bhandari 1015b4cff454SVipin Bhandari if (qstatus & MMCST0_RSPDNE) { 1016b4cff454SVipin Bhandari /* End of command phase */ 1017b4cff454SVipin Bhandari end_command = (int) host->cmd; 1018b4cff454SVipin Bhandari } 1019b4cff454SVipin Bhandari 1020b4cff454SVipin Bhandari if (end_command) 1021b4cff454SVipin Bhandari mmc_davinci_cmd_done(host, host->cmd); 1022b4cff454SVipin Bhandari if (end_transfer) 1023b4cff454SVipin Bhandari mmc_davinci_xfer_done(host, data); 1024b4cff454SVipin Bhandari return IRQ_HANDLED; 1025b4cff454SVipin Bhandari } 1026b4cff454SVipin Bhandari 1027b4cff454SVipin Bhandari static int mmc_davinci_get_cd(struct mmc_host *mmc) 1028b4cff454SVipin Bhandari { 1029b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1030b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1031b4cff454SVipin Bhandari 1032b4cff454SVipin Bhandari if (!config || !config->get_cd) 1033b4cff454SVipin Bhandari return -ENOSYS; 1034b4cff454SVipin Bhandari return config->get_cd(pdev->id); 1035b4cff454SVipin Bhandari } 1036b4cff454SVipin Bhandari 1037b4cff454SVipin Bhandari static int mmc_davinci_get_ro(struct mmc_host *mmc) 1038b4cff454SVipin Bhandari { 1039b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1040b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1041b4cff454SVipin Bhandari 1042b4cff454SVipin Bhandari if (!config || !config->get_ro) 1043b4cff454SVipin Bhandari return -ENOSYS; 1044b4cff454SVipin Bhandari return config->get_ro(pdev->id); 1045b4cff454SVipin Bhandari } 1046b4cff454SVipin Bhandari 1047f9db92cbSAlagu Sankar static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1048f9db92cbSAlagu Sankar { 1049f9db92cbSAlagu Sankar struct mmc_davinci_host *host = mmc_priv(mmc); 1050f9db92cbSAlagu Sankar 1051f9db92cbSAlagu Sankar if (enable) { 1052f9db92cbSAlagu Sankar if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { 1053f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1054f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 1055f9db92cbSAlagu Sankar } else { 1056f9db92cbSAlagu Sankar host->sdio_int = true; 1057f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) | 1058f9db92cbSAlagu Sankar SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); 1059f9db92cbSAlagu Sankar } 1060f9db92cbSAlagu Sankar } else { 1061f9db92cbSAlagu Sankar host->sdio_int = false; 1062f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, 1063f9db92cbSAlagu Sankar host->base + DAVINCI_SDIOIEN); 1064f9db92cbSAlagu Sankar } 1065f9db92cbSAlagu Sankar } 1066f9db92cbSAlagu Sankar 1067b4cff454SVipin Bhandari static struct mmc_host_ops mmc_davinci_ops = { 1068b4cff454SVipin Bhandari .request = mmc_davinci_request, 1069b4cff454SVipin Bhandari .set_ios = mmc_davinci_set_ios, 1070b4cff454SVipin Bhandari .get_cd = mmc_davinci_get_cd, 1071b4cff454SVipin Bhandari .get_ro = mmc_davinci_get_ro, 1072f9db92cbSAlagu Sankar .enable_sdio_irq = mmc_davinci_enable_sdio_irq, 1073b4cff454SVipin Bhandari }; 1074b4cff454SVipin Bhandari 1075b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 1076b4cff454SVipin Bhandari 10777e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 10787e30b8deSChaithrika U S static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 10797e30b8deSChaithrika U S unsigned long val, void *data) 10807e30b8deSChaithrika U S { 10817e30b8deSChaithrika U S struct mmc_davinci_host *host; 10827e30b8deSChaithrika U S unsigned int mmc_pclk; 10837e30b8deSChaithrika U S struct mmc_host *mmc; 10847e30b8deSChaithrika U S unsigned long flags; 10857e30b8deSChaithrika U S 10867e30b8deSChaithrika U S host = container_of(nb, struct mmc_davinci_host, freq_transition); 10877e30b8deSChaithrika U S mmc = host->mmc; 10887e30b8deSChaithrika U S mmc_pclk = clk_get_rate(host->clk); 10897e30b8deSChaithrika U S 10907e30b8deSChaithrika U S if (val == CPUFREQ_POSTCHANGE) { 10917e30b8deSChaithrika U S spin_lock_irqsave(&mmc->lock, flags); 10927e30b8deSChaithrika U S host->mmc_input_clk = mmc_pclk; 10937e30b8deSChaithrika U S calculate_clk_divider(mmc, &mmc->ios); 10947e30b8deSChaithrika U S spin_unlock_irqrestore(&mmc->lock, flags); 10957e30b8deSChaithrika U S } 10967e30b8deSChaithrika U S 10977e30b8deSChaithrika U S return 0; 10987e30b8deSChaithrika U S } 10997e30b8deSChaithrika U S 11007e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 11017e30b8deSChaithrika U S { 11027e30b8deSChaithrika U S host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 11037e30b8deSChaithrika U S 11047e30b8deSChaithrika U S return cpufreq_register_notifier(&host->freq_transition, 11057e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 11067e30b8deSChaithrika U S } 11077e30b8deSChaithrika U S 11087e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11097e30b8deSChaithrika U S { 11107e30b8deSChaithrika U S cpufreq_unregister_notifier(&host->freq_transition, 11117e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 11127e30b8deSChaithrika U S } 11137e30b8deSChaithrika U S #else 11147e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 11157e30b8deSChaithrika U S { 11167e30b8deSChaithrika U S return 0; 11177e30b8deSChaithrika U S } 11187e30b8deSChaithrika U S 11197e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11207e30b8deSChaithrika U S { 11217e30b8deSChaithrika U S } 11227e30b8deSChaithrika U S #endif 1123b4cff454SVipin Bhandari static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1124b4cff454SVipin Bhandari { 1125b4cff454SVipin Bhandari 112606de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1127b4cff454SVipin Bhandari 1128b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCCLK); 1129b4cff454SVipin Bhandari writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1130b4cff454SVipin Bhandari 1131b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1132b4cff454SVipin Bhandari writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1133b4cff454SVipin Bhandari 113406de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1135b4cff454SVipin Bhandari } 1136b4cff454SVipin Bhandari 1137ed425fc4SKrzysztof Kozlowski static const struct platform_device_id davinci_mmc_devtype[] = { 1138d7ca4c75SManjunathappa, Prakash { 1139d7ca4c75SManjunathappa, Prakash .name = "dm6441-mmc", 1140d7ca4c75SManjunathappa, Prakash .driver_data = MMC_CTLR_VERSION_1, 1141d7ca4c75SManjunathappa, Prakash }, { 1142d7ca4c75SManjunathappa, Prakash .name = "da830-mmc", 1143d7ca4c75SManjunathappa, Prakash .driver_data = MMC_CTLR_VERSION_2, 1144d7ca4c75SManjunathappa, Prakash }, 1145d7ca4c75SManjunathappa, Prakash {}, 1146d7ca4c75SManjunathappa, Prakash }; 1147d7ca4c75SManjunathappa, Prakash MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype); 1148d7ca4c75SManjunathappa, Prakash 11497b43da4cSManjunathappa, Prakash static const struct of_device_id davinci_mmc_dt_ids[] = { 11507b43da4cSManjunathappa, Prakash { 11517b43da4cSManjunathappa, Prakash .compatible = "ti,dm6441-mmc", 11527b43da4cSManjunathappa, Prakash .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1], 11537b43da4cSManjunathappa, Prakash }, 11547b43da4cSManjunathappa, Prakash { 11557b43da4cSManjunathappa, Prakash .compatible = "ti,da830-mmc", 11567b43da4cSManjunathappa, Prakash .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2], 11577b43da4cSManjunathappa, Prakash }, 11587b43da4cSManjunathappa, Prakash {}, 11597b43da4cSManjunathappa, Prakash }; 11607b43da4cSManjunathappa, Prakash MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids); 11617b43da4cSManjunathappa, Prakash 11627b43da4cSManjunathappa, Prakash static struct davinci_mmc_config 11637b43da4cSManjunathappa, Prakash *mmc_parse_pdata(struct platform_device *pdev) 11647b43da4cSManjunathappa, Prakash { 11657b43da4cSManjunathappa, Prakash struct device_node *np; 11667b43da4cSManjunathappa, Prakash struct davinci_mmc_config *pdata = pdev->dev.platform_data; 11677b43da4cSManjunathappa, Prakash const struct of_device_id *match = 11686fad5128SSachin Kamat of_match_device(davinci_mmc_dt_ids, &pdev->dev); 11697b43da4cSManjunathappa, Prakash u32 data; 11707b43da4cSManjunathappa, Prakash 11717b43da4cSManjunathappa, Prakash np = pdev->dev.of_node; 11727b43da4cSManjunathappa, Prakash if (!np) 11737b43da4cSManjunathappa, Prakash return pdata; 11747b43da4cSManjunathappa, Prakash 11757b43da4cSManjunathappa, Prakash pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 11767b43da4cSManjunathappa, Prakash if (!pdata) { 11777b43da4cSManjunathappa, Prakash dev_err(&pdev->dev, "Failed to allocate memory for struct davinci_mmc_config\n"); 11787b43da4cSManjunathappa, Prakash goto nodata; 11797b43da4cSManjunathappa, Prakash } 11807b43da4cSManjunathappa, Prakash 11817b43da4cSManjunathappa, Prakash if (match) 11827b43da4cSManjunathappa, Prakash pdev->id_entry = match->data; 11837b43da4cSManjunathappa, Prakash 11847b43da4cSManjunathappa, Prakash if (of_property_read_u32(np, "max-frequency", &pdata->max_freq)) 11857b43da4cSManjunathappa, Prakash dev_info(&pdev->dev, "'max-frequency' property not specified, defaulting to 25MHz\n"); 11867b43da4cSManjunathappa, Prakash 11877b43da4cSManjunathappa, Prakash of_property_read_u32(np, "bus-width", &data); 11887b43da4cSManjunathappa, Prakash switch (data) { 11897b43da4cSManjunathappa, Prakash case 1: 11907b43da4cSManjunathappa, Prakash case 4: 11917b43da4cSManjunathappa, Prakash case 8: 11927b43da4cSManjunathappa, Prakash pdata->wires = data; 11937b43da4cSManjunathappa, Prakash break; 11947b43da4cSManjunathappa, Prakash default: 11957b43da4cSManjunathappa, Prakash pdata->wires = 1; 11967b43da4cSManjunathappa, Prakash dev_info(&pdev->dev, "Unsupported buswidth, defaulting to 1 bit\n"); 11977b43da4cSManjunathappa, Prakash } 11987b43da4cSManjunathappa, Prakash nodata: 11997b43da4cSManjunathappa, Prakash return pdata; 12007b43da4cSManjunathappa, Prakash } 12017b43da4cSManjunathappa, Prakash 1202b4cff454SVipin Bhandari static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1203b4cff454SVipin Bhandari { 12047b43da4cSManjunathappa, Prakash struct davinci_mmc_config *pdata = NULL; 1205b4cff454SVipin Bhandari struct mmc_davinci_host *host = NULL; 1206b4cff454SVipin Bhandari struct mmc_host *mmc = NULL; 1207b4cff454SVipin Bhandari struct resource *r, *mem = NULL; 120862ac52b2SDavid Lechner int ret, irq; 1209b4cff454SVipin Bhandari size_t mem_size; 1210d7ca4c75SManjunathappa, Prakash const struct platform_device_id *id_entry; 1211b4cff454SVipin Bhandari 12127b43da4cSManjunathappa, Prakash pdata = mmc_parse_pdata(pdev); 12137b43da4cSManjunathappa, Prakash if (pdata == NULL) { 12147b43da4cSManjunathappa, Prakash dev_err(&pdev->dev, "Couldn't get platform data\n"); 12157b43da4cSManjunathappa, Prakash return -ENOENT; 12167b43da4cSManjunathappa, Prakash } 1217b4cff454SVipin Bhandari 1218b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1219b4cff454SVipin Bhandari irq = platform_get_irq(pdev, 0); 1220b4cff454SVipin Bhandari if (!r || irq == NO_IRQ) 122162ac52b2SDavid Lechner return -ENODEV; 1222b4cff454SVipin Bhandari 1223b4cff454SVipin Bhandari mem_size = resource_size(r); 122462ac52b2SDavid Lechner mem = devm_request_mem_region(&pdev->dev, r->start, mem_size, 122562ac52b2SDavid Lechner pdev->name); 1226b4cff454SVipin Bhandari if (!mem) 122762ac52b2SDavid Lechner return -EBUSY; 1228b4cff454SVipin Bhandari 1229b4cff454SVipin Bhandari mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1230b4cff454SVipin Bhandari if (!mmc) 123162ac52b2SDavid Lechner return -ENOMEM; 1232b4cff454SVipin Bhandari 1233b4cff454SVipin Bhandari host = mmc_priv(mmc); 1234b4cff454SVipin Bhandari host->mmc = mmc; /* Important */ 1235b4cff454SVipin Bhandari 1236b4cff454SVipin Bhandari host->mem_res = mem; 123762ac52b2SDavid Lechner host->base = devm_ioremap(&pdev->dev, mem->start, mem_size); 123862ac52b2SDavid Lechner if (!host->base) { 123962ac52b2SDavid Lechner ret = -ENOMEM; 124062ac52b2SDavid Lechner goto ioremap_fail; 124162ac52b2SDavid Lechner } 1242b4cff454SVipin Bhandari 124362ac52b2SDavid Lechner host->clk = devm_clk_get(&pdev->dev, NULL); 1244b4cff454SVipin Bhandari if (IS_ERR(host->clk)) { 1245b4cff454SVipin Bhandari ret = PTR_ERR(host->clk); 124662ac52b2SDavid Lechner goto clk_get_fail; 1247b4cff454SVipin Bhandari } 124862ac52b2SDavid Lechner ret = clk_enable(host->clk); 124962ac52b2SDavid Lechner if (ret) 125062ac52b2SDavid Lechner goto clk_enable_fail; 125162ac52b2SDavid Lechner 1252b4cff454SVipin Bhandari host->mmc_input_clk = clk_get_rate(host->clk); 1253b4cff454SVipin Bhandari 1254b4cff454SVipin Bhandari init_mmcsd_host(host); 1255b4cff454SVipin Bhandari 1256ca2afb6dSSudhakar Rajashekhara if (pdata->nr_sg) 1257ca2afb6dSSudhakar Rajashekhara host->nr_sg = pdata->nr_sg - 1; 1258ca2afb6dSSudhakar Rajashekhara 1259ca2afb6dSSudhakar Rajashekhara if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1260ca2afb6dSSudhakar Rajashekhara host->nr_sg = MAX_NR_SG; 1261ca2afb6dSSudhakar Rajashekhara 1262b4cff454SVipin Bhandari host->use_dma = use_dma; 1263f9db92cbSAlagu Sankar host->mmc_irq = irq; 1264f9db92cbSAlagu Sankar host->sdio_irq = platform_get_irq(pdev, 1); 1265b4cff454SVipin Bhandari 12660a4d7236SPeter Ujfalusi if (host->use_dma) { 12670a4d7236SPeter Ujfalusi ret = davinci_acquire_dma_channels(host); 12680a4d7236SPeter Ujfalusi if (ret == -EPROBE_DEFER) 126962ac52b2SDavid Lechner goto dma_probe_defer; 12700a4d7236SPeter Ujfalusi else if (ret) 1271b4cff454SVipin Bhandari host->use_dma = 0; 12720a4d7236SPeter Ujfalusi } 1273b4cff454SVipin Bhandari 1274b4cff454SVipin Bhandari /* REVISIT: someday, support IRQ-driven card detection. */ 1275b4cff454SVipin Bhandari mmc->caps |= MMC_CAP_NEEDS_POLL; 1276132f1074SVipin Bhandari mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1277b4cff454SVipin Bhandari 1278132f1074SVipin Bhandari if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1279b4cff454SVipin Bhandari mmc->caps |= MMC_CAP_4_BIT_DATA; 1280b4cff454SVipin Bhandari 1281132f1074SVipin Bhandari if (pdata && (pdata->wires == 8)) 1282132f1074SVipin Bhandari mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1283132f1074SVipin Bhandari 1284d7ca4c75SManjunathappa, Prakash id_entry = platform_get_device_id(pdev); 1285d7ca4c75SManjunathappa, Prakash if (id_entry) 1286d7ca4c75SManjunathappa, Prakash host->version = id_entry->driver_data; 1287b4cff454SVipin Bhandari 1288b4cff454SVipin Bhandari mmc->ops = &mmc_davinci_ops; 1289b4cff454SVipin Bhandari mmc->f_min = 312500; 1290b4cff454SVipin Bhandari mmc->f_max = 25000000; 1291b4cff454SVipin Bhandari if (pdata && pdata->max_freq) 1292b4cff454SVipin Bhandari mmc->f_max = pdata->max_freq; 1293b4cff454SVipin Bhandari if (pdata && pdata->caps) 1294b4cff454SVipin Bhandari mmc->caps |= pdata->caps; 1295b4cff454SVipin Bhandari mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1296b4cff454SVipin Bhandari 1297b4cff454SVipin Bhandari /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1298b4cff454SVipin Bhandari * Each hw_seg uses one EDMA parameter RAM slot, always one 1299b4cff454SVipin Bhandari * channel and then usually some linked slots. 1300b4cff454SVipin Bhandari */ 13015413da81SMatt Porter mmc->max_segs = MAX_NR_SG; 1302b4cff454SVipin Bhandari 1303b4cff454SVipin Bhandari /* EDMA limit per hw segment (one or two MBytes) */ 1304b4cff454SVipin Bhandari mmc->max_seg_size = MAX_CCNT * rw_threshold; 1305b4cff454SVipin Bhandari 1306b4cff454SVipin Bhandari /* MMC/SD controller limits for multiblock requests */ 1307b4cff454SVipin Bhandari mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1308b4cff454SVipin Bhandari mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1309b4cff454SVipin Bhandari mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1310b4cff454SVipin Bhandari 1311a36274e0SMartin K. Petersen dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1312b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1313b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1314b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1315b4cff454SVipin Bhandari 1316b4cff454SVipin Bhandari platform_set_drvdata(pdev, host); 1317b4cff454SVipin Bhandari 13187e30b8deSChaithrika U S ret = mmc_davinci_cpufreq_register(host); 13197e30b8deSChaithrika U S if (ret) { 13207e30b8deSChaithrika U S dev_err(&pdev->dev, "failed to register cpufreq\n"); 13217e30b8deSChaithrika U S goto cpu_freq_fail; 13227e30b8deSChaithrika U S } 13237e30b8deSChaithrika U S 1324b4cff454SVipin Bhandari ret = mmc_add_host(mmc); 1325b4cff454SVipin Bhandari if (ret < 0) 132662ac52b2SDavid Lechner goto mmc_add_host_fail; 1327b4cff454SVipin Bhandari 132862ac52b2SDavid Lechner ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0, 132962ac52b2SDavid Lechner mmc_hostname(mmc), host); 1330b4cff454SVipin Bhandari if (ret) 133162ac52b2SDavid Lechner goto request_irq_fail; 1332b4cff454SVipin Bhandari 1333f9db92cbSAlagu Sankar if (host->sdio_irq >= 0) { 133462ac52b2SDavid Lechner ret = devm_request_irq(&pdev->dev, host->sdio_irq, 133562ac52b2SDavid Lechner mmc_davinci_sdio_irq, 0, 1336f9db92cbSAlagu Sankar mmc_hostname(mmc), host); 1337f9db92cbSAlagu Sankar if (!ret) 1338f9db92cbSAlagu Sankar mmc->caps |= MMC_CAP_SDIO_IRQ; 1339f9db92cbSAlagu Sankar } 1340f9db92cbSAlagu Sankar 1341b4cff454SVipin Bhandari rename_region(mem, mmc_hostname(mmc)); 1342b4cff454SVipin Bhandari 1343b4cff454SVipin Bhandari dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1344b4cff454SVipin Bhandari host->use_dma ? "DMA" : "PIO", 1345b4cff454SVipin Bhandari (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1346b4cff454SVipin Bhandari 1347b4cff454SVipin Bhandari return 0; 1348b4cff454SVipin Bhandari 134962ac52b2SDavid Lechner request_irq_fail: 135062ac52b2SDavid Lechner mmc_remove_host(mmc); 135162ac52b2SDavid Lechner mmc_add_host_fail: 13527e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 13537e30b8deSChaithrika U S cpu_freq_fail: 1354b4cff454SVipin Bhandari davinci_release_dma_channels(host); 135562ac52b2SDavid Lechner dma_probe_defer: 1356b4cff454SVipin Bhandari clk_disable(host->clk); 135762ac52b2SDavid Lechner clk_enable_fail: 135862ac52b2SDavid Lechner clk_get_fail: 135962ac52b2SDavid Lechner ioremap_fail: 1360b4cff454SVipin Bhandari mmc_free_host(mmc); 1361b4cff454SVipin Bhandari 1362b4cff454SVipin Bhandari return ret; 1363b4cff454SVipin Bhandari } 1364b4cff454SVipin Bhandari 1365b4cff454SVipin Bhandari static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1366b4cff454SVipin Bhandari { 1367b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1368b4cff454SVipin Bhandari 1369b4cff454SVipin Bhandari mmc_remove_host(host->mmc); 137062ac52b2SDavid Lechner mmc_davinci_cpufreq_deregister(host); 1371b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1372b4cff454SVipin Bhandari clk_disable(host->clk); 1373b4cff454SVipin Bhandari mmc_free_host(host->mmc); 1374b4cff454SVipin Bhandari 1375b4cff454SVipin Bhandari return 0; 1376b4cff454SVipin Bhandari } 1377b4cff454SVipin Bhandari 1378b4cff454SVipin Bhandari #ifdef CONFIG_PM 1379bbce5802SChaithrika U S static int davinci_mmcsd_suspend(struct device *dev) 1380b4cff454SVipin Bhandari { 1381bbce5802SChaithrika U S struct platform_device *pdev = to_platform_device(dev); 1382b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1383b4cff454SVipin Bhandari 1384bbce5802SChaithrika U S writel(0, host->base + DAVINCI_MMCIM); 1385bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1386bbce5802SChaithrika U S clk_disable(host->clk); 1387b4cff454SVipin Bhandari 13885ffdeea5SUlf Hansson return 0; 1389b4cff454SVipin Bhandari } 1390bbce5802SChaithrika U S 1391bbce5802SChaithrika U S static int davinci_mmcsd_resume(struct device *dev) 1392bbce5802SChaithrika U S { 1393bbce5802SChaithrika U S struct platform_device *pdev = to_platform_device(dev); 1394bbce5802SChaithrika U S struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1395bbce5802SChaithrika U S 1396bbce5802SChaithrika U S clk_enable(host->clk); 1397bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1398bbce5802SChaithrika U S 13995ffdeea5SUlf Hansson return 0; 1400bbce5802SChaithrika U S } 1401bbce5802SChaithrika U S 1402bbce5802SChaithrika U S static const struct dev_pm_ops davinci_mmcsd_pm = { 1403bbce5802SChaithrika U S .suspend = davinci_mmcsd_suspend, 1404bbce5802SChaithrika U S .resume = davinci_mmcsd_resume, 1405bbce5802SChaithrika U S }; 1406bbce5802SChaithrika U S 1407bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1408b4cff454SVipin Bhandari #else 1409bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops NULL 1410b4cff454SVipin Bhandari #endif 1411b4cff454SVipin Bhandari 1412b4cff454SVipin Bhandari static struct platform_driver davinci_mmcsd_driver = { 1413b4cff454SVipin Bhandari .driver = { 1414b4cff454SVipin Bhandari .name = "davinci_mmc", 1415bbce5802SChaithrika U S .pm = davinci_mmcsd_pm_ops, 14166fad5128SSachin Kamat .of_match_table = davinci_mmc_dt_ids, 1417b4cff454SVipin Bhandari }, 1418b4cff454SVipin Bhandari .remove = __exit_p(davinci_mmcsd_remove), 1419d7ca4c75SManjunathappa, Prakash .id_table = davinci_mmc_devtype, 1420b4cff454SVipin Bhandari }; 1421b4cff454SVipin Bhandari 1422d4bf6325SJingoo Han module_platform_driver_probe(davinci_mmcsd_driver, davinci_mmcsd_probe); 1423b4cff454SVipin Bhandari 1424b4cff454SVipin Bhandari MODULE_AUTHOR("Texas Instruments India"); 1425b4cff454SVipin Bhandari MODULE_LICENSE("GPL"); 1426b4cff454SVipin Bhandari MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 14277f8bea7fSJan Luebbe MODULE_ALIAS("platform:davinci_mmc"); 1428b4cff454SVipin Bhandari 1429