1b4cff454SVipin Bhandari /* 2b4cff454SVipin Bhandari * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3b4cff454SVipin Bhandari * 4b4cff454SVipin Bhandari * Copyright (C) 2006 Texas Instruments. 5b4cff454SVipin Bhandari * Original author: Purushotam Kumar 6b4cff454SVipin Bhandari * Copyright (C) 2009 David Brownell 7b4cff454SVipin Bhandari * 8b4cff454SVipin Bhandari * This program is free software; you can redistribute it and/or modify 9b4cff454SVipin Bhandari * it under the terms of the GNU General Public License as published by 10b4cff454SVipin Bhandari * the Free Software Foundation; either version 2 of the License, or 11b4cff454SVipin Bhandari * (at your option) any later version. 12b4cff454SVipin Bhandari * 13b4cff454SVipin Bhandari * This program is distributed in the hope that it will be useful, 14b4cff454SVipin Bhandari * but WITHOUT ANY WARRANTY; without even the implied warranty of 15b4cff454SVipin Bhandari * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16b4cff454SVipin Bhandari * GNU General Public License for more details. 17b4cff454SVipin Bhandari * 18b4cff454SVipin Bhandari * You should have received a copy of the GNU General Public License 19b4cff454SVipin Bhandari * along with this program; if not, write to the Free Software 20b4cff454SVipin Bhandari * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21b4cff454SVipin Bhandari */ 22b4cff454SVipin Bhandari 23b4cff454SVipin Bhandari #include <linux/module.h> 24b4cff454SVipin Bhandari #include <linux/ioport.h> 25b4cff454SVipin Bhandari #include <linux/platform_device.h> 26b4cff454SVipin Bhandari #include <linux/clk.h> 27b4cff454SVipin Bhandari #include <linux/err.h> 287e30b8deSChaithrika U S #include <linux/cpufreq.h> 29b4cff454SVipin Bhandari #include <linux/mmc/host.h> 30b4cff454SVipin Bhandari #include <linux/io.h> 31b4cff454SVipin Bhandari #include <linux/irq.h> 32b4cff454SVipin Bhandari #include <linux/delay.h> 335413da81SMatt Porter #include <linux/dmaengine.h> 34b4cff454SVipin Bhandari #include <linux/dma-mapping.h> 355413da81SMatt Porter #include <linux/edma.h> 36b4cff454SVipin Bhandari #include <linux/mmc/mmc.h> 37b4cff454SVipin Bhandari 38b4cff454SVipin Bhandari #include <mach/mmc.h> 39b4cff454SVipin Bhandari 40b4cff454SVipin Bhandari /* 41b4cff454SVipin Bhandari * Register Definitions 42b4cff454SVipin Bhandari */ 43b4cff454SVipin Bhandari #define DAVINCI_MMCCTL 0x00 /* Control Register */ 44b4cff454SVipin Bhandari #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 45b4cff454SVipin Bhandari #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 46b4cff454SVipin Bhandari #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 47b4cff454SVipin Bhandari #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 48b4cff454SVipin Bhandari #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 49b4cff454SVipin Bhandari #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 50b4cff454SVipin Bhandari #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 51b4cff454SVipin Bhandari #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 52b4cff454SVipin Bhandari #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 53b4cff454SVipin Bhandari #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 54b4cff454SVipin Bhandari #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 55b4cff454SVipin Bhandari #define DAVINCI_MMCCMD 0x30 /* Command Register */ 56b4cff454SVipin Bhandari #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 57b4cff454SVipin Bhandari #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 58b4cff454SVipin Bhandari #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 59b4cff454SVipin Bhandari #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 60b4cff454SVipin Bhandari #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 61b4cff454SVipin Bhandari #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 62b4cff454SVipin Bhandari #define DAVINCI_MMCETOK 0x4C 63b4cff454SVipin Bhandari #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 64b4cff454SVipin Bhandari #define DAVINCI_MMCCKC 0x54 65b4cff454SVipin Bhandari #define DAVINCI_MMCTORC 0x58 66b4cff454SVipin Bhandari #define DAVINCI_MMCTODC 0x5C 67b4cff454SVipin Bhandari #define DAVINCI_MMCBLNC 0x60 68b4cff454SVipin Bhandari #define DAVINCI_SDIOCTL 0x64 69b4cff454SVipin Bhandari #define DAVINCI_SDIOST0 0x68 70f9db92cbSAlagu Sankar #define DAVINCI_SDIOIEN 0x6C 71f9db92cbSAlagu Sankar #define DAVINCI_SDIOIST 0x70 72b4cff454SVipin Bhandari #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 73b4cff454SVipin Bhandari 74b4cff454SVipin Bhandari /* DAVINCI_MMCCTL definitions */ 75b4cff454SVipin Bhandari #define MMCCTL_DATRST (1 << 0) 76b4cff454SVipin Bhandari #define MMCCTL_CMDRST (1 << 1) 77132f1074SVipin Bhandari #define MMCCTL_WIDTH_8_BIT (1 << 8) 78b4cff454SVipin Bhandari #define MMCCTL_WIDTH_4_BIT (1 << 2) 79b4cff454SVipin Bhandari #define MMCCTL_DATEG_DISABLED (0 << 6) 80b4cff454SVipin Bhandari #define MMCCTL_DATEG_RISING (1 << 6) 81b4cff454SVipin Bhandari #define MMCCTL_DATEG_FALLING (2 << 6) 82b4cff454SVipin Bhandari #define MMCCTL_DATEG_BOTH (3 << 6) 83b4cff454SVipin Bhandari #define MMCCTL_PERMDR_LE (0 << 9) 84b4cff454SVipin Bhandari #define MMCCTL_PERMDR_BE (1 << 9) 85b4cff454SVipin Bhandari #define MMCCTL_PERMDX_LE (0 << 10) 86b4cff454SVipin Bhandari #define MMCCTL_PERMDX_BE (1 << 10) 87b4cff454SVipin Bhandari 88b4cff454SVipin Bhandari /* DAVINCI_MMCCLK definitions */ 89b4cff454SVipin Bhandari #define MMCCLK_CLKEN (1 << 8) 90b4cff454SVipin Bhandari #define MMCCLK_CLKRT_MASK (0xFF << 0) 91b4cff454SVipin Bhandari 92b4cff454SVipin Bhandari /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 93b4cff454SVipin Bhandari #define MMCST0_DATDNE BIT(0) /* data done */ 94b4cff454SVipin Bhandari #define MMCST0_BSYDNE BIT(1) /* busy done */ 95b4cff454SVipin Bhandari #define MMCST0_RSPDNE BIT(2) /* command done */ 96b4cff454SVipin Bhandari #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 97b4cff454SVipin Bhandari #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 98b4cff454SVipin Bhandari #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 99b4cff454SVipin Bhandari #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 100b4cff454SVipin Bhandari #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 101b4cff454SVipin Bhandari #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 102b4cff454SVipin Bhandari #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 103b4cff454SVipin Bhandari #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 104b4cff454SVipin Bhandari #define MMCST0_TRNDNE BIT(12) /* transfer done */ 105b4cff454SVipin Bhandari 106b4cff454SVipin Bhandari /* DAVINCI_MMCST1 definitions */ 107b4cff454SVipin Bhandari #define MMCST1_BUSY (1 << 0) 108b4cff454SVipin Bhandari 109b4cff454SVipin Bhandari /* DAVINCI_MMCCMD definitions */ 110b4cff454SVipin Bhandari #define MMCCMD_CMD_MASK (0x3F << 0) 111b4cff454SVipin Bhandari #define MMCCMD_PPLEN (1 << 7) 112b4cff454SVipin Bhandari #define MMCCMD_BSYEXP (1 << 8) 113b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_MASK (3 << 9) 114b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_NONE (0 << 9) 115b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R1456 (1 << 9) 116b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R2 (2 << 9) 117b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R3 (3 << 9) 118b4cff454SVipin Bhandari #define MMCCMD_DTRW (1 << 11) 119b4cff454SVipin Bhandari #define MMCCMD_STRMTP (1 << 12) 120b4cff454SVipin Bhandari #define MMCCMD_WDATX (1 << 13) 121b4cff454SVipin Bhandari #define MMCCMD_INITCK (1 << 14) 122b4cff454SVipin Bhandari #define MMCCMD_DCLR (1 << 15) 123b4cff454SVipin Bhandari #define MMCCMD_DMATRIG (1 << 16) 124b4cff454SVipin Bhandari 125b4cff454SVipin Bhandari /* DAVINCI_MMCFIFOCTL definitions */ 126b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFORST (1 << 0) 127b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 128b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 129b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 130b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 131b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 132b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 133b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 134b4cff454SVipin Bhandari 135f9db92cbSAlagu Sankar /* DAVINCI_SDIOST0 definitions */ 136f9db92cbSAlagu Sankar #define SDIOST0_DAT1_HI BIT(0) 137f9db92cbSAlagu Sankar 138f9db92cbSAlagu Sankar /* DAVINCI_SDIOIEN definitions */ 139f9db92cbSAlagu Sankar #define SDIOIEN_IOINTEN BIT(0) 140f9db92cbSAlagu Sankar 141f9db92cbSAlagu Sankar /* DAVINCI_SDIOIST definitions */ 142f9db92cbSAlagu Sankar #define SDIOIST_IOINT BIT(0) 143b4cff454SVipin Bhandari 144b4cff454SVipin Bhandari /* MMCSD Init clock in Hz in opendrain mode */ 145b4cff454SVipin Bhandari #define MMCSD_INIT_CLOCK 200000 146b4cff454SVipin Bhandari 147b4cff454SVipin Bhandari /* 148b4cff454SVipin Bhandari * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 149ca2afb6dSSudhakar Rajashekhara * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 150a36274e0SMartin K. Petersen * for drivers with max_segs == 1, making the segments bigger (64KB) 151ca2afb6dSSudhakar Rajashekhara * than the page or two that's otherwise typical. nr_sg (passed from 152ca2afb6dSSudhakar Rajashekhara * platform data) == 16 gives at least the same throughput boost, using 153ca2afb6dSSudhakar Rajashekhara * EDMA transfer linkage instead of spending CPU time copying pages. 154b4cff454SVipin Bhandari */ 155b4cff454SVipin Bhandari #define MAX_CCNT ((1 << 16) - 1) 156b4cff454SVipin Bhandari 157ca2afb6dSSudhakar Rajashekhara #define MAX_NR_SG 16 158b4cff454SVipin Bhandari 159b4cff454SVipin Bhandari static unsigned rw_threshold = 32; 160b4cff454SVipin Bhandari module_param(rw_threshold, uint, S_IRUGO); 161b4cff454SVipin Bhandari MODULE_PARM_DESC(rw_threshold, 162b4cff454SVipin Bhandari "Read/Write threshold. Default = 32"); 163b4cff454SVipin Bhandari 164ee698f50SIdo Yariv static unsigned poll_threshold = 128; 165ee698f50SIdo Yariv module_param(poll_threshold, uint, S_IRUGO); 166ee698f50SIdo Yariv MODULE_PARM_DESC(poll_threshold, 167ee698f50SIdo Yariv "Polling transaction size threshold. Default = 128"); 168ee698f50SIdo Yariv 169ee698f50SIdo Yariv static unsigned poll_loopcount = 32; 170ee698f50SIdo Yariv module_param(poll_loopcount, uint, S_IRUGO); 171ee698f50SIdo Yariv MODULE_PARM_DESC(poll_loopcount, 172ee698f50SIdo Yariv "Maximum polling loop count. Default = 32"); 173ee698f50SIdo Yariv 174b4cff454SVipin Bhandari static unsigned __initdata use_dma = 1; 175b4cff454SVipin Bhandari module_param(use_dma, uint, 0); 176b4cff454SVipin Bhandari MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 177b4cff454SVipin Bhandari 178b4cff454SVipin Bhandari struct mmc_davinci_host { 179b4cff454SVipin Bhandari struct mmc_command *cmd; 180b4cff454SVipin Bhandari struct mmc_data *data; 181b4cff454SVipin Bhandari struct mmc_host *mmc; 182b4cff454SVipin Bhandari struct clk *clk; 183b4cff454SVipin Bhandari unsigned int mmc_input_clk; 184b4cff454SVipin Bhandari void __iomem *base; 185b4cff454SVipin Bhandari struct resource *mem_res; 186f9db92cbSAlagu Sankar int mmc_irq, sdio_irq; 187b4cff454SVipin Bhandari unsigned char bus_mode; 188b4cff454SVipin Bhandari 189b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_NONE 0 190b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_READ 1 191b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_WRITE 2 192b4cff454SVipin Bhandari unsigned char data_dir; 193bbce5802SChaithrika U S unsigned char suspended; 194b4cff454SVipin Bhandari 195b4cff454SVipin Bhandari /* buffer is used during PIO of one scatterlist segment, and 196b4cff454SVipin Bhandari * is updated along with buffer_bytes_left. bytes_left applies 197b4cff454SVipin Bhandari * to all N blocks of the PIO transfer. 198b4cff454SVipin Bhandari */ 199b4cff454SVipin Bhandari u8 *buffer; 200b4cff454SVipin Bhandari u32 buffer_bytes_left; 201b4cff454SVipin Bhandari u32 bytes_left; 202b4cff454SVipin Bhandari 2033d348aafSSudhakar Rajashekhara u32 rxdma, txdma; 2045413da81SMatt Porter struct dma_chan *dma_tx; 2055413da81SMatt Porter struct dma_chan *dma_rx; 206b4cff454SVipin Bhandari bool use_dma; 207b4cff454SVipin Bhandari bool do_dma; 208f9db92cbSAlagu Sankar bool sdio_int; 209ee698f50SIdo Yariv bool active_request; 210b4cff454SVipin Bhandari 211b4cff454SVipin Bhandari /* For PIO we walk scatterlists one segment at a time. */ 212b4cff454SVipin Bhandari unsigned int sg_len; 213b4cff454SVipin Bhandari struct scatterlist *sg; 214b4cff454SVipin Bhandari 215b4cff454SVipin Bhandari /* Version of the MMC/SD controller */ 216b4cff454SVipin Bhandari u8 version; 217b4cff454SVipin Bhandari /* for ns in one cycle calculation */ 218b4cff454SVipin Bhandari unsigned ns_in_one_cycle; 219ca2afb6dSSudhakar Rajashekhara /* Number of sg segments */ 220ca2afb6dSSudhakar Rajashekhara u8 nr_sg; 2217e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 2227e30b8deSChaithrika U S struct notifier_block freq_transition; 2237e30b8deSChaithrika U S #endif 224b4cff454SVipin Bhandari }; 225b4cff454SVipin Bhandari 226ee698f50SIdo Yariv static irqreturn_t mmc_davinci_irq(int irq, void *dev_id); 227b4cff454SVipin Bhandari 228b4cff454SVipin Bhandari /* PIO only */ 229b4cff454SVipin Bhandari static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 230b4cff454SVipin Bhandari { 231b4cff454SVipin Bhandari host->buffer_bytes_left = sg_dma_len(host->sg); 232b4cff454SVipin Bhandari host->buffer = sg_virt(host->sg); 233b4cff454SVipin Bhandari if (host->buffer_bytes_left > host->bytes_left) 234b4cff454SVipin Bhandari host->buffer_bytes_left = host->bytes_left; 235b4cff454SVipin Bhandari } 236b4cff454SVipin Bhandari 237b4cff454SVipin Bhandari static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 238b4cff454SVipin Bhandari unsigned int n) 239b4cff454SVipin Bhandari { 240b4cff454SVipin Bhandari u8 *p; 241b4cff454SVipin Bhandari unsigned int i; 242b4cff454SVipin Bhandari 243b4cff454SVipin Bhandari if (host->buffer_bytes_left == 0) { 244b4cff454SVipin Bhandari host->sg = sg_next(host->data->sg); 245b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 246b4cff454SVipin Bhandari } 247b4cff454SVipin Bhandari 248b4cff454SVipin Bhandari p = host->buffer; 249b4cff454SVipin Bhandari if (n > host->buffer_bytes_left) 250b4cff454SVipin Bhandari n = host->buffer_bytes_left; 251b4cff454SVipin Bhandari host->buffer_bytes_left -= n; 252b4cff454SVipin Bhandari host->bytes_left -= n; 253b4cff454SVipin Bhandari 254b4cff454SVipin Bhandari /* NOTE: we never transfer more than rw_threshold bytes 255b4cff454SVipin Bhandari * to/from the fifo here; there's no I/O overlap. 256b4cff454SVipin Bhandari * This also assumes that access width( i.e. ACCWD) is 4 bytes 257b4cff454SVipin Bhandari */ 258b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 259b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 260b4cff454SVipin Bhandari writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 261b4cff454SVipin Bhandari p = p + 4; 262b4cff454SVipin Bhandari } 263b4cff454SVipin Bhandari if (n & 3) { 264b4cff454SVipin Bhandari iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 265b4cff454SVipin Bhandari p = p + (n & 3); 266b4cff454SVipin Bhandari } 267b4cff454SVipin Bhandari } else { 268b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 269b4cff454SVipin Bhandari *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 270b4cff454SVipin Bhandari p = p + 4; 271b4cff454SVipin Bhandari } 272b4cff454SVipin Bhandari if (n & 3) { 273b4cff454SVipin Bhandari ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 274b4cff454SVipin Bhandari p = p + (n & 3); 275b4cff454SVipin Bhandari } 276b4cff454SVipin Bhandari } 277b4cff454SVipin Bhandari host->buffer = p; 278b4cff454SVipin Bhandari } 279b4cff454SVipin Bhandari 280b4cff454SVipin Bhandari static void mmc_davinci_start_command(struct mmc_davinci_host *host, 281b4cff454SVipin Bhandari struct mmc_command *cmd) 282b4cff454SVipin Bhandari { 283b4cff454SVipin Bhandari u32 cmd_reg = 0; 284b4cff454SVipin Bhandari u32 im_val; 285b4cff454SVipin Bhandari 286b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 287b4cff454SVipin Bhandari cmd->opcode, cmd->arg, 288b4cff454SVipin Bhandari ({ char *s; 289b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 290b4cff454SVipin Bhandari case MMC_RSP_R1: 291b4cff454SVipin Bhandari s = ", R1/R5/R6/R7 response"; 292b4cff454SVipin Bhandari break; 293b4cff454SVipin Bhandari case MMC_RSP_R1B: 294b4cff454SVipin Bhandari s = ", R1b response"; 295b4cff454SVipin Bhandari break; 296b4cff454SVipin Bhandari case MMC_RSP_R2: 297b4cff454SVipin Bhandari s = ", R2 response"; 298b4cff454SVipin Bhandari break; 299b4cff454SVipin Bhandari case MMC_RSP_R3: 300b4cff454SVipin Bhandari s = ", R3/R4 response"; 301b4cff454SVipin Bhandari break; 302b4cff454SVipin Bhandari default: 303b4cff454SVipin Bhandari s = ", (R? response)"; 304b4cff454SVipin Bhandari break; 305b4cff454SVipin Bhandari }; s; })); 306b4cff454SVipin Bhandari host->cmd = cmd; 307b4cff454SVipin Bhandari 308b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 309b4cff454SVipin Bhandari case MMC_RSP_R1B: 310b4cff454SVipin Bhandari /* There's some spec confusion about when R1B is 311b4cff454SVipin Bhandari * allowed, but if the card doesn't issue a BUSY 312b4cff454SVipin Bhandari * then it's harmless for us to allow it. 313b4cff454SVipin Bhandari */ 314b4cff454SVipin Bhandari cmd_reg |= MMCCMD_BSYEXP; 315b4cff454SVipin Bhandari /* FALLTHROUGH */ 316b4cff454SVipin Bhandari case MMC_RSP_R1: /* 48 bits, CRC */ 317b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R1456; 318b4cff454SVipin Bhandari break; 319b4cff454SVipin Bhandari case MMC_RSP_R2: /* 136 bits, CRC */ 320b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R2; 321b4cff454SVipin Bhandari break; 322b4cff454SVipin Bhandari case MMC_RSP_R3: /* 48 bits, no CRC */ 323b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R3; 324b4cff454SVipin Bhandari break; 325b4cff454SVipin Bhandari default: 326b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_NONE; 327b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 328b4cff454SVipin Bhandari mmc_resp_type(cmd)); 329b4cff454SVipin Bhandari break; 330b4cff454SVipin Bhandari } 331b4cff454SVipin Bhandari 332b4cff454SVipin Bhandari /* Set command index */ 333b4cff454SVipin Bhandari cmd_reg |= cmd->opcode; 334b4cff454SVipin Bhandari 335b4cff454SVipin Bhandari /* Enable EDMA transfer triggers */ 336b4cff454SVipin Bhandari if (host->do_dma) 337b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 338b4cff454SVipin Bhandari 339b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 340b4cff454SVipin Bhandari host->data_dir == DAVINCI_MMC_DATADIR_READ) 341b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 342b4cff454SVipin Bhandari 343b4cff454SVipin Bhandari /* Setting whether command involves data transfer or not */ 344b4cff454SVipin Bhandari if (cmd->data) 345b4cff454SVipin Bhandari cmd_reg |= MMCCMD_WDATX; 346b4cff454SVipin Bhandari 347b4cff454SVipin Bhandari /* Setting whether stream or block transfer */ 348b4cff454SVipin Bhandari if (cmd->flags & MMC_DATA_STREAM) 349b4cff454SVipin Bhandari cmd_reg |= MMCCMD_STRMTP; 350b4cff454SVipin Bhandari 351b4cff454SVipin Bhandari /* Setting whether data read or write */ 352b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 353b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DTRW; 354b4cff454SVipin Bhandari 355b4cff454SVipin Bhandari if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 356b4cff454SVipin Bhandari cmd_reg |= MMCCMD_PPLEN; 357b4cff454SVipin Bhandari 358b4cff454SVipin Bhandari /* set Command timeout */ 359b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 360b4cff454SVipin Bhandari 361b4cff454SVipin Bhandari /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 362b4cff454SVipin Bhandari im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 363b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 364b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 365b4cff454SVipin Bhandari 366b4cff454SVipin Bhandari if (!host->do_dma) 367b4cff454SVipin Bhandari im_val |= MMCST0_DXRDY; 368b4cff454SVipin Bhandari } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 369b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 370b4cff454SVipin Bhandari 371b4cff454SVipin Bhandari if (!host->do_dma) 372b4cff454SVipin Bhandari im_val |= MMCST0_DRRDY; 373b4cff454SVipin Bhandari } 374b4cff454SVipin Bhandari 375b4cff454SVipin Bhandari /* 376b4cff454SVipin Bhandari * Before non-DMA WRITE commands the controller needs priming: 377b4cff454SVipin Bhandari * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 378b4cff454SVipin Bhandari */ 379b4cff454SVipin Bhandari if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 380b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 381b4cff454SVipin Bhandari 382b4cff454SVipin Bhandari writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 383b4cff454SVipin Bhandari writel(cmd_reg, host->base + DAVINCI_MMCCMD); 384ee698f50SIdo Yariv 385ee698f50SIdo Yariv host->active_request = true; 386ee698f50SIdo Yariv 387ee698f50SIdo Yariv if (!host->do_dma && host->bytes_left <= poll_threshold) { 388ee698f50SIdo Yariv u32 count = poll_loopcount; 389ee698f50SIdo Yariv 390ee698f50SIdo Yariv while (host->active_request && count--) { 391ee698f50SIdo Yariv mmc_davinci_irq(0, host); 392ee698f50SIdo Yariv cpu_relax(); 393ee698f50SIdo Yariv } 394ee698f50SIdo Yariv } 395ee698f50SIdo Yariv 396ee698f50SIdo Yariv if (host->active_request) 397b4cff454SVipin Bhandari writel(im_val, host->base + DAVINCI_MMCIM); 398b4cff454SVipin Bhandari } 399b4cff454SVipin Bhandari 400b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 401b4cff454SVipin Bhandari 402b4cff454SVipin Bhandari /* DMA infrastructure */ 403b4cff454SVipin Bhandari 404b4cff454SVipin Bhandari static void davinci_abort_dma(struct mmc_davinci_host *host) 405b4cff454SVipin Bhandari { 4065413da81SMatt Porter struct dma_chan *sync_dev; 407b4cff454SVipin Bhandari 408b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 4095413da81SMatt Porter sync_dev = host->dma_rx; 410b4cff454SVipin Bhandari else 4115413da81SMatt Porter sync_dev = host->dma_tx; 412b4cff454SVipin Bhandari 4135413da81SMatt Porter dmaengine_terminate_all(sync_dev); 414b4cff454SVipin Bhandari } 415b4cff454SVipin Bhandari 4165413da81SMatt Porter static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 417b4cff454SVipin Bhandari struct mmc_data *data) 418b4cff454SVipin Bhandari { 4195413da81SMatt Porter struct dma_chan *chan; 4205413da81SMatt Porter struct dma_async_tx_descriptor *desc; 4215413da81SMatt Porter int ret = 0; 422b4cff454SVipin Bhandari 423b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 4245413da81SMatt Porter struct dma_slave_config dma_tx_conf = { 4255413da81SMatt Porter .direction = DMA_MEM_TO_DEV, 4265413da81SMatt Porter .dst_addr = host->mem_res->start + DAVINCI_MMCDXR, 4275413da81SMatt Porter .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 4285413da81SMatt Porter .dst_maxburst = 4295413da81SMatt Porter rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 4305413da81SMatt Porter }; 4315413da81SMatt Porter chan = host->dma_tx; 4325413da81SMatt Porter dmaengine_slave_config(host->dma_tx, &dma_tx_conf); 4335413da81SMatt Porter 4345413da81SMatt Porter desc = dmaengine_prep_slave_sg(host->dma_tx, 4355413da81SMatt Porter data->sg, 4365413da81SMatt Porter host->sg_len, 4375413da81SMatt Porter DMA_MEM_TO_DEV, 4385413da81SMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 4395413da81SMatt Porter if (!desc) { 4405413da81SMatt Porter dev_dbg(mmc_dev(host->mmc), 4415413da81SMatt Porter "failed to allocate DMA TX descriptor"); 4425413da81SMatt Porter ret = -1; 4435413da81SMatt Porter goto out; 4445413da81SMatt Porter } 445b4cff454SVipin Bhandari } else { 4465413da81SMatt Porter struct dma_slave_config dma_rx_conf = { 4475413da81SMatt Porter .direction = DMA_DEV_TO_MEM, 4485413da81SMatt Porter .src_addr = host->mem_res->start + DAVINCI_MMCDRR, 4495413da81SMatt Porter .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 4505413da81SMatt Porter .src_maxburst = 4515413da81SMatt Porter rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 4525413da81SMatt Porter }; 4535413da81SMatt Porter chan = host->dma_rx; 4545413da81SMatt Porter dmaengine_slave_config(host->dma_rx, &dma_rx_conf); 4555413da81SMatt Porter 4565413da81SMatt Porter desc = dmaengine_prep_slave_sg(host->dma_rx, 4575413da81SMatt Porter data->sg, 4585413da81SMatt Porter host->sg_len, 4595413da81SMatt Porter DMA_DEV_TO_MEM, 4605413da81SMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 4615413da81SMatt Porter if (!desc) { 4625413da81SMatt Porter dev_dbg(mmc_dev(host->mmc), 4635413da81SMatt Porter "failed to allocate DMA RX descriptor"); 4645413da81SMatt Porter ret = -1; 4655413da81SMatt Porter goto out; 4665413da81SMatt Porter } 467b4cff454SVipin Bhandari } 468b4cff454SVipin Bhandari 4695413da81SMatt Porter dmaengine_submit(desc); 4705413da81SMatt Porter dma_async_issue_pending(chan); 471b4cff454SVipin Bhandari 4725413da81SMatt Porter out: 4735413da81SMatt Porter return ret; 474b4cff454SVipin Bhandari } 475b4cff454SVipin Bhandari 476b4cff454SVipin Bhandari static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 477b4cff454SVipin Bhandari struct mmc_data *data) 478b4cff454SVipin Bhandari { 479b4cff454SVipin Bhandari int i; 480b4cff454SVipin Bhandari int mask = rw_threshold - 1; 4815413da81SMatt Porter int ret = 0; 482b4cff454SVipin Bhandari 483b4cff454SVipin Bhandari host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 484b4cff454SVipin Bhandari ((data->flags & MMC_DATA_WRITE) 485b4cff454SVipin Bhandari ? DMA_TO_DEVICE 486b4cff454SVipin Bhandari : DMA_FROM_DEVICE)); 487b4cff454SVipin Bhandari 488b4cff454SVipin Bhandari /* no individual DMA segment should need a partial FIFO */ 489b4cff454SVipin Bhandari for (i = 0; i < host->sg_len; i++) { 490b4cff454SVipin Bhandari if (sg_dma_len(data->sg + i) & mask) { 491b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), 492b4cff454SVipin Bhandari data->sg, data->sg_len, 493b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 494b4cff454SVipin Bhandari ? DMA_TO_DEVICE 495b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 496b4cff454SVipin Bhandari return -1; 497b4cff454SVipin Bhandari } 498b4cff454SVipin Bhandari } 499b4cff454SVipin Bhandari 500b4cff454SVipin Bhandari host->do_dma = 1; 5015413da81SMatt Porter ret = mmc_davinci_send_dma_request(host, data); 502b4cff454SVipin Bhandari 5035413da81SMatt Porter return ret; 504b4cff454SVipin Bhandari } 505b4cff454SVipin Bhandari 506b4cff454SVipin Bhandari static void __init_or_module 507b4cff454SVipin Bhandari davinci_release_dma_channels(struct mmc_davinci_host *host) 508b4cff454SVipin Bhandari { 509b4cff454SVipin Bhandari if (!host->use_dma) 510b4cff454SVipin Bhandari return; 511b4cff454SVipin Bhandari 5125413da81SMatt Porter dma_release_channel(host->dma_tx); 5135413da81SMatt Porter dma_release_channel(host->dma_rx); 514b4cff454SVipin Bhandari } 515b4cff454SVipin Bhandari 516b4cff454SVipin Bhandari static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 517b4cff454SVipin Bhandari { 5185413da81SMatt Porter int r; 5195413da81SMatt Porter dma_cap_mask_t mask; 520b4cff454SVipin Bhandari 5215413da81SMatt Porter dma_cap_zero(mask); 5225413da81SMatt Porter dma_cap_set(DMA_SLAVE, mask); 5235413da81SMatt Porter 5245413da81SMatt Porter host->dma_tx = 5255413da81SMatt Porter dma_request_channel(mask, edma_filter_fn, &host->txdma); 5265413da81SMatt Porter if (!host->dma_tx) { 5275413da81SMatt Porter dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); 5285413da81SMatt Porter return -ENODEV; 529b4cff454SVipin Bhandari } 530b4cff454SVipin Bhandari 5315413da81SMatt Porter host->dma_rx = 5325413da81SMatt Porter dma_request_channel(mask, edma_filter_fn, &host->rxdma); 5335413da81SMatt Porter if (!host->dma_rx) { 5345413da81SMatt Porter dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); 5355413da81SMatt Porter r = -ENODEV; 536b4cff454SVipin Bhandari goto free_master_write; 537b4cff454SVipin Bhandari } 538b4cff454SVipin Bhandari 539b4cff454SVipin Bhandari return 0; 540b4cff454SVipin Bhandari 541b4cff454SVipin Bhandari free_master_write: 5425413da81SMatt Porter dma_release_channel(host->dma_tx); 543b4cff454SVipin Bhandari 544b4cff454SVipin Bhandari return r; 545b4cff454SVipin Bhandari } 546b4cff454SVipin Bhandari 547b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 548b4cff454SVipin Bhandari 549b4cff454SVipin Bhandari static void 550b4cff454SVipin Bhandari mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 551b4cff454SVipin Bhandari { 552b4cff454SVipin Bhandari int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 553b4cff454SVipin Bhandari int timeout; 554b4cff454SVipin Bhandari struct mmc_data *data = req->data; 555b4cff454SVipin Bhandari 556b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 557b4cff454SVipin Bhandari fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 558b4cff454SVipin Bhandari 559b4cff454SVipin Bhandari host->data = data; 560b4cff454SVipin Bhandari if (data == NULL) { 561b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 562b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCBLEN); 563b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCNBLK); 564b4cff454SVipin Bhandari return; 565b4cff454SVipin Bhandari } 566b4cff454SVipin Bhandari 567b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n", 568b4cff454SVipin Bhandari (data->flags & MMC_DATA_STREAM) ? "stream" : "block", 569b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) ? "write" : "read", 570b4cff454SVipin Bhandari data->blocks, data->blksz); 571b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 572b4cff454SVipin Bhandari data->timeout_clks, data->timeout_ns); 573b4cff454SVipin Bhandari timeout = data->timeout_clks + 574b4cff454SVipin Bhandari (data->timeout_ns / host->ns_in_one_cycle); 575b4cff454SVipin Bhandari if (timeout > 0xffff) 576b4cff454SVipin Bhandari timeout = 0xffff; 577b4cff454SVipin Bhandari 578b4cff454SVipin Bhandari writel(timeout, host->base + DAVINCI_MMCTOD); 579b4cff454SVipin Bhandari writel(data->blocks, host->base + DAVINCI_MMCNBLK); 580b4cff454SVipin Bhandari writel(data->blksz, host->base + DAVINCI_MMCBLEN); 581b4cff454SVipin Bhandari 582b4cff454SVipin Bhandari /* Configure the FIFO */ 583b4cff454SVipin Bhandari switch (data->flags & MMC_DATA_WRITE) { 584b4cff454SVipin Bhandari case MMC_DATA_WRITE: 585b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 586b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 587b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 588b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 589b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 590b4cff454SVipin Bhandari break; 591b4cff454SVipin Bhandari 592b4cff454SVipin Bhandari default: 593b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_READ; 594b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 595b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 596b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 597b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 598b4cff454SVipin Bhandari break; 599b4cff454SVipin Bhandari } 600b4cff454SVipin Bhandari 601b4cff454SVipin Bhandari host->buffer = NULL; 602b4cff454SVipin Bhandari host->bytes_left = data->blocks * data->blksz; 603b4cff454SVipin Bhandari 604b4cff454SVipin Bhandari /* For now we try to use DMA whenever we won't need partial FIFO 605b4cff454SVipin Bhandari * reads or writes, either for the whole transfer (as tested here) 606b4cff454SVipin Bhandari * or for any individual scatterlist segment (tested when we call 607b4cff454SVipin Bhandari * start_dma_transfer). 608b4cff454SVipin Bhandari * 609b4cff454SVipin Bhandari * While we *could* change that, unusual block sizes are rarely 610b4cff454SVipin Bhandari * used. The occasional fallback to PIO should't hurt. 611b4cff454SVipin Bhandari */ 612b4cff454SVipin Bhandari if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 613b4cff454SVipin Bhandari && mmc_davinci_start_dma_transfer(host, data) == 0) { 614b4cff454SVipin Bhandari /* zero this to ensure we take no PIO paths */ 615b4cff454SVipin Bhandari host->bytes_left = 0; 616b4cff454SVipin Bhandari } else { 617b4cff454SVipin Bhandari /* Revert to CPU Copy */ 618b4cff454SVipin Bhandari host->sg_len = data->sg_len; 619b4cff454SVipin Bhandari host->sg = host->data->sg; 620b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 621b4cff454SVipin Bhandari } 622b4cff454SVipin Bhandari } 623b4cff454SVipin Bhandari 624b4cff454SVipin Bhandari static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 625b4cff454SVipin Bhandari { 626b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 627b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(900); 628b4cff454SVipin Bhandari u32 mmcst1 = 0; 629b4cff454SVipin Bhandari 630b4cff454SVipin Bhandari /* Card may still be sending BUSY after a previous operation, 631b4cff454SVipin Bhandari * typically some kind of write. If so, we can't proceed yet. 632b4cff454SVipin Bhandari */ 633b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 634b4cff454SVipin Bhandari mmcst1 = readl(host->base + DAVINCI_MMCST1); 635b4cff454SVipin Bhandari if (!(mmcst1 & MMCST1_BUSY)) 636b4cff454SVipin Bhandari break; 637b4cff454SVipin Bhandari cpu_relax(); 638b4cff454SVipin Bhandari } 639b4cff454SVipin Bhandari if (mmcst1 & MMCST1_BUSY) { 640b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 641b4cff454SVipin Bhandari req->cmd->error = -ETIMEDOUT; 642b4cff454SVipin Bhandari mmc_request_done(mmc, req); 643b4cff454SVipin Bhandari return; 644b4cff454SVipin Bhandari } 645b4cff454SVipin Bhandari 646b4cff454SVipin Bhandari host->do_dma = 0; 647b4cff454SVipin Bhandari mmc_davinci_prepare_data(host, req); 648b4cff454SVipin Bhandari mmc_davinci_start_command(host, req->cmd); 649b4cff454SVipin Bhandari } 650b4cff454SVipin Bhandari 651b4cff454SVipin Bhandari static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 652b4cff454SVipin Bhandari unsigned int mmc_req_freq) 653b4cff454SVipin Bhandari { 654b4cff454SVipin Bhandari unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 655b4cff454SVipin Bhandari 656b4cff454SVipin Bhandari mmc_pclk = host->mmc_input_clk; 657b4cff454SVipin Bhandari if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 658b4cff454SVipin Bhandari mmc_push_pull_divisor = ((unsigned int)mmc_pclk 659b4cff454SVipin Bhandari / (2 * mmc_req_freq)) - 1; 660b4cff454SVipin Bhandari else 661b4cff454SVipin Bhandari mmc_push_pull_divisor = 0; 662b4cff454SVipin Bhandari 663b4cff454SVipin Bhandari mmc_freq = (unsigned int)mmc_pclk 664b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)); 665b4cff454SVipin Bhandari 666b4cff454SVipin Bhandari if (mmc_freq > mmc_req_freq) 667b4cff454SVipin Bhandari mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 668b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 669b4cff454SVipin Bhandari if (mmc_req_freq <= 400000) 670b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 671b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000)); 672b4cff454SVipin Bhandari else 673b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 674b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 675b4cff454SVipin Bhandari 676b4cff454SVipin Bhandari return mmc_push_pull_divisor; 677b4cff454SVipin Bhandari } 678b4cff454SVipin Bhandari 6797e30b8deSChaithrika U S static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 680b4cff454SVipin Bhandari { 681b4cff454SVipin Bhandari unsigned int open_drain_freq = 0, mmc_pclk = 0; 682b4cff454SVipin Bhandari unsigned int mmc_push_pull_freq = 0; 683b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 684b4cff454SVipin Bhandari 685b4cff454SVipin Bhandari if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 686b4cff454SVipin Bhandari u32 temp; 687b4cff454SVipin Bhandari 688b4cff454SVipin Bhandari /* Ignoring the init clock value passed for fixing the inter 689b4cff454SVipin Bhandari * operability with different cards. 690b4cff454SVipin Bhandari */ 691b4cff454SVipin Bhandari open_drain_freq = ((unsigned int)mmc_pclk 692b4cff454SVipin Bhandari / (2 * MMCSD_INIT_CLOCK)) - 1; 693b4cff454SVipin Bhandari 694b4cff454SVipin Bhandari if (open_drain_freq > 0xFF) 695b4cff454SVipin Bhandari open_drain_freq = 0xFF; 696b4cff454SVipin Bhandari 697b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 698b4cff454SVipin Bhandari temp |= open_drain_freq; 699b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 700b4cff454SVipin Bhandari 701b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 702b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 703b4cff454SVipin Bhandari } else { 704b4cff454SVipin Bhandari u32 temp; 705b4cff454SVipin Bhandari mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 706b4cff454SVipin Bhandari 707b4cff454SVipin Bhandari if (mmc_push_pull_freq > 0xFF) 708b4cff454SVipin Bhandari mmc_push_pull_freq = 0xFF; 709b4cff454SVipin Bhandari 710b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 711b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 712b4cff454SVipin Bhandari 713b4cff454SVipin Bhandari udelay(10); 714b4cff454SVipin Bhandari 715b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 716b4cff454SVipin Bhandari temp |= mmc_push_pull_freq; 717b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 718b4cff454SVipin Bhandari 719b4cff454SVipin Bhandari writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 720b4cff454SVipin Bhandari 721b4cff454SVipin Bhandari udelay(10); 722b4cff454SVipin Bhandari } 7237e30b8deSChaithrika U S } 7247e30b8deSChaithrika U S 7257e30b8deSChaithrika U S static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 7267e30b8deSChaithrika U S { 7277e30b8deSChaithrika U S struct mmc_davinci_host *host = mmc_priv(mmc); 7284a9de8adSIdo Yariv struct platform_device *pdev = to_platform_device(mmc->parent); 7294a9de8adSIdo Yariv struct davinci_mmc_config *config = pdev->dev.platform_data; 7307e30b8deSChaithrika U S 7317e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), 7327e30b8deSChaithrika U S "clock %dHz busmode %d powermode %d Vdd %04x\n", 7337e30b8deSChaithrika U S ios->clock, ios->bus_mode, ios->power_mode, 7347e30b8deSChaithrika U S ios->vdd); 735132f1074SVipin Bhandari 7364a9de8adSIdo Yariv switch (ios->power_mode) { 7374a9de8adSIdo Yariv case MMC_POWER_OFF: 7384a9de8adSIdo Yariv if (config && config->set_power) 7394a9de8adSIdo Yariv config->set_power(pdev->id, false); 7404a9de8adSIdo Yariv break; 7414a9de8adSIdo Yariv case MMC_POWER_UP: 7424a9de8adSIdo Yariv if (config && config->set_power) 7434a9de8adSIdo Yariv config->set_power(pdev->id, true); 7444a9de8adSIdo Yariv break; 7454a9de8adSIdo Yariv } 7464a9de8adSIdo Yariv 747132f1074SVipin Bhandari switch (ios->bus_width) { 748132f1074SVipin Bhandari case MMC_BUS_WIDTH_8: 749132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 750132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 751132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 752132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 753132f1074SVipin Bhandari break; 754132f1074SVipin Bhandari case MMC_BUS_WIDTH_4: 7557e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 756132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 757132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 758132f1074SVipin Bhandari ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 7597e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 760132f1074SVipin Bhandari else 761132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) | 762132f1074SVipin Bhandari MMCCTL_WIDTH_4_BIT, 7637e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 764132f1074SVipin Bhandari break; 765132f1074SVipin Bhandari case MMC_BUS_WIDTH_1: 766132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 767132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 768132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 769132f1074SVipin Bhandari ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 770132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 771132f1074SVipin Bhandari else 772132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 773132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT, 774132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 775132f1074SVipin Bhandari break; 7767e30b8deSChaithrika U S } 7777e30b8deSChaithrika U S 7787e30b8deSChaithrika U S calculate_clk_divider(mmc, ios); 779b4cff454SVipin Bhandari 780b4cff454SVipin Bhandari host->bus_mode = ios->bus_mode; 781b4cff454SVipin Bhandari if (ios->power_mode == MMC_POWER_UP) { 782b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(50); 783b4cff454SVipin Bhandari bool lose = true; 784b4cff454SVipin Bhandari 785b4cff454SVipin Bhandari /* Send clock cycles, poll completion */ 786b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCARGHL); 787b4cff454SVipin Bhandari writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 788b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 789b4cff454SVipin Bhandari u32 tmp = readl(host->base + DAVINCI_MMCST0); 790b4cff454SVipin Bhandari 791b4cff454SVipin Bhandari if (tmp & MMCST0_RSPDNE) { 792b4cff454SVipin Bhandari lose = false; 793b4cff454SVipin Bhandari break; 794b4cff454SVipin Bhandari } 795b4cff454SVipin Bhandari cpu_relax(); 796b4cff454SVipin Bhandari } 797b4cff454SVipin Bhandari if (lose) 798b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 799b4cff454SVipin Bhandari } 800b4cff454SVipin Bhandari 801b4cff454SVipin Bhandari /* FIXME on power OFF, reset things ... */ 802b4cff454SVipin Bhandari } 803b4cff454SVipin Bhandari 804b4cff454SVipin Bhandari static void 805b4cff454SVipin Bhandari mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 806b4cff454SVipin Bhandari { 807b4cff454SVipin Bhandari host->data = NULL; 808b4cff454SVipin Bhandari 809f9db92cbSAlagu Sankar if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 810f9db92cbSAlagu Sankar /* 811f9db92cbSAlagu Sankar * SDIO Interrupt Detection work-around as suggested by 812f9db92cbSAlagu Sankar * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata 813f9db92cbSAlagu Sankar * 2.1.6): Signal SDIO interrupt only if it is enabled by core 814f9db92cbSAlagu Sankar */ 815f9db92cbSAlagu Sankar if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & 816f9db92cbSAlagu Sankar SDIOST0_DAT1_HI)) { 817f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 818f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 819f9db92cbSAlagu Sankar } 820f9db92cbSAlagu Sankar } 821f9db92cbSAlagu Sankar 822b4cff454SVipin Bhandari if (host->do_dma) { 823b4cff454SVipin Bhandari davinci_abort_dma(host); 824b4cff454SVipin Bhandari 825b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 826b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 827b4cff454SVipin Bhandari ? DMA_TO_DEVICE 828b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 829b4cff454SVipin Bhandari host->do_dma = false; 830b4cff454SVipin Bhandari } 831b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 832b4cff454SVipin Bhandari 833b4cff454SVipin Bhandari if (!data->stop || (host->cmd && host->cmd->error)) { 834b4cff454SVipin Bhandari mmc_request_done(host->mmc, data->mrq); 835b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 836ee698f50SIdo Yariv host->active_request = false; 837b4cff454SVipin Bhandari } else 838b4cff454SVipin Bhandari mmc_davinci_start_command(host, data->stop); 839b4cff454SVipin Bhandari } 840b4cff454SVipin Bhandari 841b4cff454SVipin Bhandari static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 842b4cff454SVipin Bhandari struct mmc_command *cmd) 843b4cff454SVipin Bhandari { 844b4cff454SVipin Bhandari host->cmd = NULL; 845b4cff454SVipin Bhandari 846b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_PRESENT) { 847b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_136) { 848b4cff454SVipin Bhandari /* response type 2 */ 849b4cff454SVipin Bhandari cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 850b4cff454SVipin Bhandari cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 851b4cff454SVipin Bhandari cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 852b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 853b4cff454SVipin Bhandari } else { 854b4cff454SVipin Bhandari /* response types 1, 1b, 3, 4, 5, 6 */ 855b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 856b4cff454SVipin Bhandari } 857b4cff454SVipin Bhandari } 858b4cff454SVipin Bhandari 859b4cff454SVipin Bhandari if (host->data == NULL || cmd->error) { 860b4cff454SVipin Bhandari if (cmd->error == -ETIMEDOUT) 861b4cff454SVipin Bhandari cmd->mrq->cmd->retries = 0; 862b4cff454SVipin Bhandari mmc_request_done(host->mmc, cmd->mrq); 863b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 864ee698f50SIdo Yariv host->active_request = false; 865b4cff454SVipin Bhandari } 866b4cff454SVipin Bhandari } 867b4cff454SVipin Bhandari 86806de845fSChaithrika U S static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 86906de845fSChaithrika U S int val) 870b4cff454SVipin Bhandari { 871b4cff454SVipin Bhandari u32 temp; 872b4cff454SVipin Bhandari 873b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCTL); 87406de845fSChaithrika U S if (val) /* reset */ 87506de845fSChaithrika U S temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 87606de845fSChaithrika U S else /* enable */ 877b4cff454SVipin Bhandari temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 87806de845fSChaithrika U S 879b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCTL); 88006de845fSChaithrika U S udelay(10); 88106de845fSChaithrika U S } 88206de845fSChaithrika U S 88306de845fSChaithrika U S static void 88406de845fSChaithrika U S davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 88506de845fSChaithrika U S { 88606de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 88706de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 888b4cff454SVipin Bhandari } 889b4cff454SVipin Bhandari 890f9db92cbSAlagu Sankar static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) 891f9db92cbSAlagu Sankar { 892f9db92cbSAlagu Sankar struct mmc_davinci_host *host = dev_id; 893f9db92cbSAlagu Sankar unsigned int status; 894f9db92cbSAlagu Sankar 895f9db92cbSAlagu Sankar status = readl(host->base + DAVINCI_SDIOIST); 896f9db92cbSAlagu Sankar if (status & SDIOIST_IOINT) { 897f9db92cbSAlagu Sankar dev_dbg(mmc_dev(host->mmc), 898f9db92cbSAlagu Sankar "SDIO interrupt status %x\n", status); 899f9db92cbSAlagu Sankar writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 900f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 901f9db92cbSAlagu Sankar } 902f9db92cbSAlagu Sankar return IRQ_HANDLED; 903f9db92cbSAlagu Sankar } 904f9db92cbSAlagu Sankar 905b4cff454SVipin Bhandari static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 906b4cff454SVipin Bhandari { 907b4cff454SVipin Bhandari struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 908b4cff454SVipin Bhandari unsigned int status, qstatus; 909b4cff454SVipin Bhandari int end_command = 0; 910b4cff454SVipin Bhandari int end_transfer = 0; 911b4cff454SVipin Bhandari struct mmc_data *data = host->data; 912b4cff454SVipin Bhandari 913b4cff454SVipin Bhandari if (host->cmd == NULL && host->data == NULL) { 914b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 915b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 916b4cff454SVipin Bhandari "Spurious interrupt 0x%04x\n", status); 917b4cff454SVipin Bhandari /* Disable the interrupt from mmcsd */ 918b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 919b4cff454SVipin Bhandari return IRQ_NONE; 920b4cff454SVipin Bhandari } 921b4cff454SVipin Bhandari 922b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 923b4cff454SVipin Bhandari qstatus = status; 924b4cff454SVipin Bhandari 925b4cff454SVipin Bhandari /* handle FIFO first when using PIO for data. 926b4cff454SVipin Bhandari * bytes_left will decrease to zero as I/O progress and status will 927b4cff454SVipin Bhandari * read zero over iteration because this controller status 928b4cff454SVipin Bhandari * register(MMCST0) reports any status only once and it is cleared 929b4cff454SVipin Bhandari * by read. So, it is not unbouned loop even in the case of 930b4cff454SVipin Bhandari * non-dma. 931b4cff454SVipin Bhandari */ 932be7b5622SIdo Yariv if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 933be7b5622SIdo Yariv unsigned long im_val; 934be7b5622SIdo Yariv 935be7b5622SIdo Yariv /* 936be7b5622SIdo Yariv * If interrupts fire during the following loop, they will be 937be7b5622SIdo Yariv * handled by the handler, but the PIC will still buffer these. 938be7b5622SIdo Yariv * As a result, the handler will be called again to serve these 939be7b5622SIdo Yariv * needlessly. In order to avoid these spurious interrupts, 940be7b5622SIdo Yariv * keep interrupts masked during the loop. 941be7b5622SIdo Yariv */ 942be7b5622SIdo Yariv im_val = readl(host->base + DAVINCI_MMCIM); 943be7b5622SIdo Yariv writel(0, host->base + DAVINCI_MMCIM); 944be7b5622SIdo Yariv 945be7b5622SIdo Yariv do { 946b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 947b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 948b4cff454SVipin Bhandari qstatus |= status; 949be7b5622SIdo Yariv } while (host->bytes_left && 950be7b5622SIdo Yariv (status & (MMCST0_DXRDY | MMCST0_DRRDY))); 951be7b5622SIdo Yariv 952be7b5622SIdo Yariv /* 953be7b5622SIdo Yariv * If an interrupt is pending, it is assumed it will fire when 954be7b5622SIdo Yariv * it is unmasked. This assumption is also taken when the MMCIM 955be7b5622SIdo Yariv * is first set. Otherwise, writing to MMCIM after reading the 956be7b5622SIdo Yariv * status is race-prone. 957be7b5622SIdo Yariv */ 958be7b5622SIdo Yariv writel(im_val, host->base + DAVINCI_MMCIM); 959b4cff454SVipin Bhandari } 960b4cff454SVipin Bhandari 961b4cff454SVipin Bhandari if (qstatus & MMCST0_DATDNE) { 962b4cff454SVipin Bhandari /* All blocks sent/received, and CRC checks passed */ 963b4cff454SVipin Bhandari if (data != NULL) { 964b4cff454SVipin Bhandari if ((host->do_dma == 0) && (host->bytes_left > 0)) { 965b4cff454SVipin Bhandari /* if datasize < rw_threshold 966b4cff454SVipin Bhandari * no RX ints are generated 967b4cff454SVipin Bhandari */ 968b4cff454SVipin Bhandari davinci_fifo_data_trans(host, host->bytes_left); 969b4cff454SVipin Bhandari } 970b4cff454SVipin Bhandari end_transfer = 1; 971b4cff454SVipin Bhandari data->bytes_xfered = data->blocks * data->blksz; 972b4cff454SVipin Bhandari } else { 973b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), 974b4cff454SVipin Bhandari "DATDNE with no host->data\n"); 975b4cff454SVipin Bhandari } 976b4cff454SVipin Bhandari } 977b4cff454SVipin Bhandari 978b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRD) { 979b4cff454SVipin Bhandari /* Read data timeout */ 980b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 981b4cff454SVipin Bhandari end_transfer = 1; 982b4cff454SVipin Bhandari 983b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 984b4cff454SVipin Bhandari "read data timeout, status %x\n", 985b4cff454SVipin Bhandari qstatus); 986b4cff454SVipin Bhandari 987b4cff454SVipin Bhandari davinci_abort_data(host, data); 988b4cff454SVipin Bhandari } 989b4cff454SVipin Bhandari 990b4cff454SVipin Bhandari if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 991b4cff454SVipin Bhandari /* Data CRC error */ 992b4cff454SVipin Bhandari data->error = -EILSEQ; 993b4cff454SVipin Bhandari end_transfer = 1; 994b4cff454SVipin Bhandari 995b4cff454SVipin Bhandari /* NOTE: this controller uses CRCWR to report both CRC 996b4cff454SVipin Bhandari * errors and timeouts (on writes). MMCDRSP values are 997b4cff454SVipin Bhandari * only weakly documented, but 0x9f was clearly a timeout 998b4cff454SVipin Bhandari * case and the two three-bit patterns in various SD specs 999b4cff454SVipin Bhandari * (101, 010) aren't part of it ... 1000b4cff454SVipin Bhandari */ 1001b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCWR) { 1002b4cff454SVipin Bhandari u32 temp = readb(host->base + DAVINCI_MMCDRSP); 1003b4cff454SVipin Bhandari 1004b4cff454SVipin Bhandari if (temp == 0x9f) 1005b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 1006b4cff454SVipin Bhandari } 1007b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 1008b4cff454SVipin Bhandari (qstatus & MMCST0_CRCWR) ? "write" : "read", 1009b4cff454SVipin Bhandari (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 1010b4cff454SVipin Bhandari 1011b4cff454SVipin Bhandari davinci_abort_data(host, data); 1012b4cff454SVipin Bhandari } 1013b4cff454SVipin Bhandari 1014b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRS) { 1015b4cff454SVipin Bhandari /* Command timeout */ 1016b4cff454SVipin Bhandari if (host->cmd) { 1017b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 1018b4cff454SVipin Bhandari "CMD%d timeout, status %x\n", 1019b4cff454SVipin Bhandari host->cmd->opcode, qstatus); 1020b4cff454SVipin Bhandari host->cmd->error = -ETIMEDOUT; 1021b4cff454SVipin Bhandari if (data) { 1022b4cff454SVipin Bhandari end_transfer = 1; 1023b4cff454SVipin Bhandari davinci_abort_data(host, data); 1024b4cff454SVipin Bhandari } else 1025b4cff454SVipin Bhandari end_command = 1; 1026b4cff454SVipin Bhandari } 1027b4cff454SVipin Bhandari } 1028b4cff454SVipin Bhandari 1029b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCRS) { 1030b4cff454SVipin Bhandari /* Command CRC error */ 1031b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1032b4cff454SVipin Bhandari if (host->cmd) { 1033b4cff454SVipin Bhandari host->cmd->error = -EILSEQ; 1034b4cff454SVipin Bhandari end_command = 1; 1035b4cff454SVipin Bhandari } 1036b4cff454SVipin Bhandari } 1037b4cff454SVipin Bhandari 1038b4cff454SVipin Bhandari if (qstatus & MMCST0_RSPDNE) { 1039b4cff454SVipin Bhandari /* End of command phase */ 1040b4cff454SVipin Bhandari end_command = (int) host->cmd; 1041b4cff454SVipin Bhandari } 1042b4cff454SVipin Bhandari 1043b4cff454SVipin Bhandari if (end_command) 1044b4cff454SVipin Bhandari mmc_davinci_cmd_done(host, host->cmd); 1045b4cff454SVipin Bhandari if (end_transfer) 1046b4cff454SVipin Bhandari mmc_davinci_xfer_done(host, data); 1047b4cff454SVipin Bhandari return IRQ_HANDLED; 1048b4cff454SVipin Bhandari } 1049b4cff454SVipin Bhandari 1050b4cff454SVipin Bhandari static int mmc_davinci_get_cd(struct mmc_host *mmc) 1051b4cff454SVipin Bhandari { 1052b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1053b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1054b4cff454SVipin Bhandari 1055b4cff454SVipin Bhandari if (!config || !config->get_cd) 1056b4cff454SVipin Bhandari return -ENOSYS; 1057b4cff454SVipin Bhandari return config->get_cd(pdev->id); 1058b4cff454SVipin Bhandari } 1059b4cff454SVipin Bhandari 1060b4cff454SVipin Bhandari static int mmc_davinci_get_ro(struct mmc_host *mmc) 1061b4cff454SVipin Bhandari { 1062b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1063b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1064b4cff454SVipin Bhandari 1065b4cff454SVipin Bhandari if (!config || !config->get_ro) 1066b4cff454SVipin Bhandari return -ENOSYS; 1067b4cff454SVipin Bhandari return config->get_ro(pdev->id); 1068b4cff454SVipin Bhandari } 1069b4cff454SVipin Bhandari 1070f9db92cbSAlagu Sankar static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1071f9db92cbSAlagu Sankar { 1072f9db92cbSAlagu Sankar struct mmc_davinci_host *host = mmc_priv(mmc); 1073f9db92cbSAlagu Sankar 1074f9db92cbSAlagu Sankar if (enable) { 1075f9db92cbSAlagu Sankar if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { 1076f9db92cbSAlagu Sankar writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1077f9db92cbSAlagu Sankar mmc_signal_sdio_irq(host->mmc); 1078f9db92cbSAlagu Sankar } else { 1079f9db92cbSAlagu Sankar host->sdio_int = true; 1080f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) | 1081f9db92cbSAlagu Sankar SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); 1082f9db92cbSAlagu Sankar } 1083f9db92cbSAlagu Sankar } else { 1084f9db92cbSAlagu Sankar host->sdio_int = false; 1085f9db92cbSAlagu Sankar writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, 1086f9db92cbSAlagu Sankar host->base + DAVINCI_SDIOIEN); 1087f9db92cbSAlagu Sankar } 1088f9db92cbSAlagu Sankar } 1089f9db92cbSAlagu Sankar 1090b4cff454SVipin Bhandari static struct mmc_host_ops mmc_davinci_ops = { 1091b4cff454SVipin Bhandari .request = mmc_davinci_request, 1092b4cff454SVipin Bhandari .set_ios = mmc_davinci_set_ios, 1093b4cff454SVipin Bhandari .get_cd = mmc_davinci_get_cd, 1094b4cff454SVipin Bhandari .get_ro = mmc_davinci_get_ro, 1095f9db92cbSAlagu Sankar .enable_sdio_irq = mmc_davinci_enable_sdio_irq, 1096b4cff454SVipin Bhandari }; 1097b4cff454SVipin Bhandari 1098b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 1099b4cff454SVipin Bhandari 11007e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 11017e30b8deSChaithrika U S static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 11027e30b8deSChaithrika U S unsigned long val, void *data) 11037e30b8deSChaithrika U S { 11047e30b8deSChaithrika U S struct mmc_davinci_host *host; 11057e30b8deSChaithrika U S unsigned int mmc_pclk; 11067e30b8deSChaithrika U S struct mmc_host *mmc; 11077e30b8deSChaithrika U S unsigned long flags; 11087e30b8deSChaithrika U S 11097e30b8deSChaithrika U S host = container_of(nb, struct mmc_davinci_host, freq_transition); 11107e30b8deSChaithrika U S mmc = host->mmc; 11117e30b8deSChaithrika U S mmc_pclk = clk_get_rate(host->clk); 11127e30b8deSChaithrika U S 11137e30b8deSChaithrika U S if (val == CPUFREQ_POSTCHANGE) { 11147e30b8deSChaithrika U S spin_lock_irqsave(&mmc->lock, flags); 11157e30b8deSChaithrika U S host->mmc_input_clk = mmc_pclk; 11167e30b8deSChaithrika U S calculate_clk_divider(mmc, &mmc->ios); 11177e30b8deSChaithrika U S spin_unlock_irqrestore(&mmc->lock, flags); 11187e30b8deSChaithrika U S } 11197e30b8deSChaithrika U S 11207e30b8deSChaithrika U S return 0; 11217e30b8deSChaithrika U S } 11227e30b8deSChaithrika U S 11237e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 11247e30b8deSChaithrika U S { 11257e30b8deSChaithrika U S host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 11267e30b8deSChaithrika U S 11277e30b8deSChaithrika U S return cpufreq_register_notifier(&host->freq_transition, 11287e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 11297e30b8deSChaithrika U S } 11307e30b8deSChaithrika U S 11317e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11327e30b8deSChaithrika U S { 11337e30b8deSChaithrika U S cpufreq_unregister_notifier(&host->freq_transition, 11347e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 11357e30b8deSChaithrika U S } 11367e30b8deSChaithrika U S #else 11377e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 11387e30b8deSChaithrika U S { 11397e30b8deSChaithrika U S return 0; 11407e30b8deSChaithrika U S } 11417e30b8deSChaithrika U S 11427e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11437e30b8deSChaithrika U S { 11447e30b8deSChaithrika U S } 11457e30b8deSChaithrika U S #endif 1146b4cff454SVipin Bhandari static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1147b4cff454SVipin Bhandari { 1148b4cff454SVipin Bhandari 114906de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1150b4cff454SVipin Bhandari 1151b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCCLK); 1152b4cff454SVipin Bhandari writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1153b4cff454SVipin Bhandari 1154b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1155b4cff454SVipin Bhandari writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1156b4cff454SVipin Bhandari 115706de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1158b4cff454SVipin Bhandari } 1159b4cff454SVipin Bhandari 1160b4cff454SVipin Bhandari static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1161b4cff454SVipin Bhandari { 1162b4cff454SVipin Bhandari struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1163b4cff454SVipin Bhandari struct mmc_davinci_host *host = NULL; 1164b4cff454SVipin Bhandari struct mmc_host *mmc = NULL; 1165b4cff454SVipin Bhandari struct resource *r, *mem = NULL; 1166b4cff454SVipin Bhandari int ret = 0, irq = 0; 1167b4cff454SVipin Bhandari size_t mem_size; 1168b4cff454SVipin Bhandari 1169b4cff454SVipin Bhandari /* REVISIT: when we're fully converted, fail if pdata is NULL */ 1170b4cff454SVipin Bhandari 1171b4cff454SVipin Bhandari ret = -ENODEV; 1172b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1173b4cff454SVipin Bhandari irq = platform_get_irq(pdev, 0); 1174b4cff454SVipin Bhandari if (!r || irq == NO_IRQ) 1175b4cff454SVipin Bhandari goto out; 1176b4cff454SVipin Bhandari 1177b4cff454SVipin Bhandari ret = -EBUSY; 1178b4cff454SVipin Bhandari mem_size = resource_size(r); 1179b4cff454SVipin Bhandari mem = request_mem_region(r->start, mem_size, pdev->name); 1180b4cff454SVipin Bhandari if (!mem) 1181b4cff454SVipin Bhandari goto out; 1182b4cff454SVipin Bhandari 1183b4cff454SVipin Bhandari ret = -ENOMEM; 1184b4cff454SVipin Bhandari mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1185b4cff454SVipin Bhandari if (!mmc) 1186b4cff454SVipin Bhandari goto out; 1187b4cff454SVipin Bhandari 1188b4cff454SVipin Bhandari host = mmc_priv(mmc); 1189b4cff454SVipin Bhandari host->mmc = mmc; /* Important */ 1190b4cff454SVipin Bhandari 1191b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1192b4cff454SVipin Bhandari if (!r) 1193b4cff454SVipin Bhandari goto out; 1194b4cff454SVipin Bhandari host->rxdma = r->start; 1195b4cff454SVipin Bhandari 1196b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1197b4cff454SVipin Bhandari if (!r) 1198b4cff454SVipin Bhandari goto out; 1199b4cff454SVipin Bhandari host->txdma = r->start; 1200b4cff454SVipin Bhandari 1201b4cff454SVipin Bhandari host->mem_res = mem; 1202b4cff454SVipin Bhandari host->base = ioremap(mem->start, mem_size); 1203b4cff454SVipin Bhandari if (!host->base) 1204b4cff454SVipin Bhandari goto out; 1205b4cff454SVipin Bhandari 1206b4cff454SVipin Bhandari ret = -ENXIO; 1207b4cff454SVipin Bhandari host->clk = clk_get(&pdev->dev, "MMCSDCLK"); 1208b4cff454SVipin Bhandari if (IS_ERR(host->clk)) { 1209b4cff454SVipin Bhandari ret = PTR_ERR(host->clk); 1210b4cff454SVipin Bhandari goto out; 1211b4cff454SVipin Bhandari } 1212b4cff454SVipin Bhandari clk_enable(host->clk); 1213b4cff454SVipin Bhandari host->mmc_input_clk = clk_get_rate(host->clk); 1214b4cff454SVipin Bhandari 1215b4cff454SVipin Bhandari init_mmcsd_host(host); 1216b4cff454SVipin Bhandari 1217ca2afb6dSSudhakar Rajashekhara if (pdata->nr_sg) 1218ca2afb6dSSudhakar Rajashekhara host->nr_sg = pdata->nr_sg - 1; 1219ca2afb6dSSudhakar Rajashekhara 1220ca2afb6dSSudhakar Rajashekhara if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1221ca2afb6dSSudhakar Rajashekhara host->nr_sg = MAX_NR_SG; 1222ca2afb6dSSudhakar Rajashekhara 1223b4cff454SVipin Bhandari host->use_dma = use_dma; 1224f9db92cbSAlagu Sankar host->mmc_irq = irq; 1225f9db92cbSAlagu Sankar host->sdio_irq = platform_get_irq(pdev, 1); 1226b4cff454SVipin Bhandari 1227b4cff454SVipin Bhandari if (host->use_dma && davinci_acquire_dma_channels(host) != 0) 1228b4cff454SVipin Bhandari host->use_dma = 0; 1229b4cff454SVipin Bhandari 1230b4cff454SVipin Bhandari /* REVISIT: someday, support IRQ-driven card detection. */ 1231b4cff454SVipin Bhandari mmc->caps |= MMC_CAP_NEEDS_POLL; 1232132f1074SVipin Bhandari mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1233b4cff454SVipin Bhandari 1234132f1074SVipin Bhandari if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1235b4cff454SVipin Bhandari mmc->caps |= MMC_CAP_4_BIT_DATA; 1236b4cff454SVipin Bhandari 1237132f1074SVipin Bhandari if (pdata && (pdata->wires == 8)) 1238132f1074SVipin Bhandari mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1239132f1074SVipin Bhandari 1240b4cff454SVipin Bhandari host->version = pdata->version; 1241b4cff454SVipin Bhandari 1242b4cff454SVipin Bhandari mmc->ops = &mmc_davinci_ops; 1243b4cff454SVipin Bhandari mmc->f_min = 312500; 1244b4cff454SVipin Bhandari mmc->f_max = 25000000; 1245b4cff454SVipin Bhandari if (pdata && pdata->max_freq) 1246b4cff454SVipin Bhandari mmc->f_max = pdata->max_freq; 1247b4cff454SVipin Bhandari if (pdata && pdata->caps) 1248b4cff454SVipin Bhandari mmc->caps |= pdata->caps; 1249b4cff454SVipin Bhandari mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1250b4cff454SVipin Bhandari 1251b4cff454SVipin Bhandari /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1252b4cff454SVipin Bhandari * Each hw_seg uses one EDMA parameter RAM slot, always one 1253b4cff454SVipin Bhandari * channel and then usually some linked slots. 1254b4cff454SVipin Bhandari */ 12555413da81SMatt Porter mmc->max_segs = MAX_NR_SG; 1256b4cff454SVipin Bhandari 1257b4cff454SVipin Bhandari /* EDMA limit per hw segment (one or two MBytes) */ 1258b4cff454SVipin Bhandari mmc->max_seg_size = MAX_CCNT * rw_threshold; 1259b4cff454SVipin Bhandari 1260b4cff454SVipin Bhandari /* MMC/SD controller limits for multiblock requests */ 1261b4cff454SVipin Bhandari mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1262b4cff454SVipin Bhandari mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1263b4cff454SVipin Bhandari mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1264b4cff454SVipin Bhandari 1265a36274e0SMartin K. Petersen dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1266b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1267b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1268b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1269b4cff454SVipin Bhandari 1270b4cff454SVipin Bhandari platform_set_drvdata(pdev, host); 1271b4cff454SVipin Bhandari 12727e30b8deSChaithrika U S ret = mmc_davinci_cpufreq_register(host); 12737e30b8deSChaithrika U S if (ret) { 12747e30b8deSChaithrika U S dev_err(&pdev->dev, "failed to register cpufreq\n"); 12757e30b8deSChaithrika U S goto cpu_freq_fail; 12767e30b8deSChaithrika U S } 12777e30b8deSChaithrika U S 1278b4cff454SVipin Bhandari ret = mmc_add_host(mmc); 1279b4cff454SVipin Bhandari if (ret < 0) 1280b4cff454SVipin Bhandari goto out; 1281b4cff454SVipin Bhandari 1282b4cff454SVipin Bhandari ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host); 1283b4cff454SVipin Bhandari if (ret) 1284b4cff454SVipin Bhandari goto out; 1285b4cff454SVipin Bhandari 1286f9db92cbSAlagu Sankar if (host->sdio_irq >= 0) { 1287f9db92cbSAlagu Sankar ret = request_irq(host->sdio_irq, mmc_davinci_sdio_irq, 0, 1288f9db92cbSAlagu Sankar mmc_hostname(mmc), host); 1289f9db92cbSAlagu Sankar if (!ret) 1290f9db92cbSAlagu Sankar mmc->caps |= MMC_CAP_SDIO_IRQ; 1291f9db92cbSAlagu Sankar } 1292f9db92cbSAlagu Sankar 1293b4cff454SVipin Bhandari rename_region(mem, mmc_hostname(mmc)); 1294b4cff454SVipin Bhandari 1295b4cff454SVipin Bhandari dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1296b4cff454SVipin Bhandari host->use_dma ? "DMA" : "PIO", 1297b4cff454SVipin Bhandari (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1298b4cff454SVipin Bhandari 1299b4cff454SVipin Bhandari return 0; 1300b4cff454SVipin Bhandari 1301b4cff454SVipin Bhandari out: 13027e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 13037e30b8deSChaithrika U S cpu_freq_fail: 1304b4cff454SVipin Bhandari if (host) { 1305b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1306b4cff454SVipin Bhandari 1307b4cff454SVipin Bhandari if (host->clk) { 1308b4cff454SVipin Bhandari clk_disable(host->clk); 1309b4cff454SVipin Bhandari clk_put(host->clk); 1310b4cff454SVipin Bhandari } 1311b4cff454SVipin Bhandari 1312b4cff454SVipin Bhandari if (host->base) 1313b4cff454SVipin Bhandari iounmap(host->base); 1314b4cff454SVipin Bhandari } 1315b4cff454SVipin Bhandari 1316b4cff454SVipin Bhandari if (mmc) 1317b4cff454SVipin Bhandari mmc_free_host(mmc); 1318b4cff454SVipin Bhandari 1319b4cff454SVipin Bhandari if (mem) 1320b4cff454SVipin Bhandari release_resource(mem); 1321b4cff454SVipin Bhandari 1322b4cff454SVipin Bhandari dev_dbg(&pdev->dev, "probe err %d\n", ret); 1323b4cff454SVipin Bhandari 1324b4cff454SVipin Bhandari return ret; 1325b4cff454SVipin Bhandari } 1326b4cff454SVipin Bhandari 1327b4cff454SVipin Bhandari static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1328b4cff454SVipin Bhandari { 1329b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1330b4cff454SVipin Bhandari 1331b4cff454SVipin Bhandari platform_set_drvdata(pdev, NULL); 1332b4cff454SVipin Bhandari if (host) { 13337e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 13347e30b8deSChaithrika U S 1335b4cff454SVipin Bhandari mmc_remove_host(host->mmc); 1336f9db92cbSAlagu Sankar free_irq(host->mmc_irq, host); 1337f9db92cbSAlagu Sankar if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 1338f9db92cbSAlagu Sankar free_irq(host->sdio_irq, host); 1339b4cff454SVipin Bhandari 1340b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1341b4cff454SVipin Bhandari 1342b4cff454SVipin Bhandari clk_disable(host->clk); 1343b4cff454SVipin Bhandari clk_put(host->clk); 1344b4cff454SVipin Bhandari 1345b4cff454SVipin Bhandari iounmap(host->base); 1346b4cff454SVipin Bhandari 1347b4cff454SVipin Bhandari release_resource(host->mem_res); 1348b4cff454SVipin Bhandari 1349b4cff454SVipin Bhandari mmc_free_host(host->mmc); 1350b4cff454SVipin Bhandari } 1351b4cff454SVipin Bhandari 1352b4cff454SVipin Bhandari return 0; 1353b4cff454SVipin Bhandari } 1354b4cff454SVipin Bhandari 1355b4cff454SVipin Bhandari #ifdef CONFIG_PM 1356bbce5802SChaithrika U S static int davinci_mmcsd_suspend(struct device *dev) 1357b4cff454SVipin Bhandari { 1358bbce5802SChaithrika U S struct platform_device *pdev = to_platform_device(dev); 1359b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1360bbce5802SChaithrika U S int ret; 1361b4cff454SVipin Bhandari 13621a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 1363bbce5802SChaithrika U S if (!ret) { 1364bbce5802SChaithrika U S writel(0, host->base + DAVINCI_MMCIM); 1365bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1366bbce5802SChaithrika U S clk_disable(host->clk); 1367bbce5802SChaithrika U S host->suspended = 1; 1368bbce5802SChaithrika U S } else { 1369bbce5802SChaithrika U S host->suspended = 0; 1370b4cff454SVipin Bhandari } 1371b4cff454SVipin Bhandari 1372bbce5802SChaithrika U S return ret; 1373b4cff454SVipin Bhandari } 1374bbce5802SChaithrika U S 1375bbce5802SChaithrika U S static int davinci_mmcsd_resume(struct device *dev) 1376bbce5802SChaithrika U S { 1377bbce5802SChaithrika U S struct platform_device *pdev = to_platform_device(dev); 1378bbce5802SChaithrika U S struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1379bbce5802SChaithrika U S int ret; 1380bbce5802SChaithrika U S 1381bbce5802SChaithrika U S if (!host->suspended) 1382bbce5802SChaithrika U S return 0; 1383bbce5802SChaithrika U S 1384bbce5802SChaithrika U S clk_enable(host->clk); 1385bbce5802SChaithrika U S 1386bbce5802SChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1387bbce5802SChaithrika U S ret = mmc_resume_host(host->mmc); 1388bbce5802SChaithrika U S if (!ret) 1389bbce5802SChaithrika U S host->suspended = 0; 1390bbce5802SChaithrika U S 1391bbce5802SChaithrika U S return ret; 1392bbce5802SChaithrika U S } 1393bbce5802SChaithrika U S 1394bbce5802SChaithrika U S static const struct dev_pm_ops davinci_mmcsd_pm = { 1395bbce5802SChaithrika U S .suspend = davinci_mmcsd_suspend, 1396bbce5802SChaithrika U S .resume = davinci_mmcsd_resume, 1397bbce5802SChaithrika U S }; 1398bbce5802SChaithrika U S 1399bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1400b4cff454SVipin Bhandari #else 1401bbce5802SChaithrika U S #define davinci_mmcsd_pm_ops NULL 1402b4cff454SVipin Bhandari #endif 1403b4cff454SVipin Bhandari 1404b4cff454SVipin Bhandari static struct platform_driver davinci_mmcsd_driver = { 1405b4cff454SVipin Bhandari .driver = { 1406b4cff454SVipin Bhandari .name = "davinci_mmc", 1407b4cff454SVipin Bhandari .owner = THIS_MODULE, 1408bbce5802SChaithrika U S .pm = davinci_mmcsd_pm_ops, 1409b4cff454SVipin Bhandari }, 1410b4cff454SVipin Bhandari .remove = __exit_p(davinci_mmcsd_remove), 1411b4cff454SVipin Bhandari }; 1412b4cff454SVipin Bhandari 1413b4cff454SVipin Bhandari static int __init davinci_mmcsd_init(void) 1414b4cff454SVipin Bhandari { 1415b4cff454SVipin Bhandari return platform_driver_probe(&davinci_mmcsd_driver, 1416b4cff454SVipin Bhandari davinci_mmcsd_probe); 1417b4cff454SVipin Bhandari } 1418b4cff454SVipin Bhandari module_init(davinci_mmcsd_init); 1419b4cff454SVipin Bhandari 1420b4cff454SVipin Bhandari static void __exit davinci_mmcsd_exit(void) 1421b4cff454SVipin Bhandari { 1422b4cff454SVipin Bhandari platform_driver_unregister(&davinci_mmcsd_driver); 1423b4cff454SVipin Bhandari } 1424b4cff454SVipin Bhandari module_exit(davinci_mmcsd_exit); 1425b4cff454SVipin Bhandari 1426b4cff454SVipin Bhandari MODULE_AUTHOR("Texas Instruments India"); 1427b4cff454SVipin Bhandari MODULE_LICENSE("GPL"); 1428b4cff454SVipin Bhandari MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 14297f8bea7fSJan Luebbe MODULE_ALIAS("platform:davinci_mmc"); 1430b4cff454SVipin Bhandari 1431