1b4cff454SVipin Bhandari /* 2b4cff454SVipin Bhandari * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3b4cff454SVipin Bhandari * 4b4cff454SVipin Bhandari * Copyright (C) 2006 Texas Instruments. 5b4cff454SVipin Bhandari * Original author: Purushotam Kumar 6b4cff454SVipin Bhandari * Copyright (C) 2009 David Brownell 7b4cff454SVipin Bhandari * 8b4cff454SVipin Bhandari * This program is free software; you can redistribute it and/or modify 9b4cff454SVipin Bhandari * it under the terms of the GNU General Public License as published by 10b4cff454SVipin Bhandari * the Free Software Foundation; either version 2 of the License, or 11b4cff454SVipin Bhandari * (at your option) any later version. 12b4cff454SVipin Bhandari * 13b4cff454SVipin Bhandari * This program is distributed in the hope that it will be useful, 14b4cff454SVipin Bhandari * but WITHOUT ANY WARRANTY; without even the implied warranty of 15b4cff454SVipin Bhandari * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16b4cff454SVipin Bhandari * GNU General Public License for more details. 17b4cff454SVipin Bhandari * 18b4cff454SVipin Bhandari * You should have received a copy of the GNU General Public License 19b4cff454SVipin Bhandari * along with this program; if not, write to the Free Software 20b4cff454SVipin Bhandari * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21b4cff454SVipin Bhandari */ 22b4cff454SVipin Bhandari 23b4cff454SVipin Bhandari #include <linux/module.h> 24b4cff454SVipin Bhandari #include <linux/ioport.h> 25b4cff454SVipin Bhandari #include <linux/platform_device.h> 26b4cff454SVipin Bhandari #include <linux/clk.h> 27b4cff454SVipin Bhandari #include <linux/err.h> 287e30b8deSChaithrika U S #include <linux/cpufreq.h> 29b4cff454SVipin Bhandari #include <linux/mmc/host.h> 30b4cff454SVipin Bhandari #include <linux/io.h> 31b4cff454SVipin Bhandari #include <linux/irq.h> 32b4cff454SVipin Bhandari #include <linux/delay.h> 33b4cff454SVipin Bhandari #include <linux/dma-mapping.h> 34b4cff454SVipin Bhandari #include <linux/mmc/mmc.h> 35b4cff454SVipin Bhandari 36b4cff454SVipin Bhandari #include <mach/mmc.h> 37b4cff454SVipin Bhandari #include <mach/edma.h> 38b4cff454SVipin Bhandari 39b4cff454SVipin Bhandari /* 40b4cff454SVipin Bhandari * Register Definitions 41b4cff454SVipin Bhandari */ 42b4cff454SVipin Bhandari #define DAVINCI_MMCCTL 0x00 /* Control Register */ 43b4cff454SVipin Bhandari #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 44b4cff454SVipin Bhandari #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 45b4cff454SVipin Bhandari #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 46b4cff454SVipin Bhandari #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 47b4cff454SVipin Bhandari #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 48b4cff454SVipin Bhandari #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 49b4cff454SVipin Bhandari #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 50b4cff454SVipin Bhandari #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 51b4cff454SVipin Bhandari #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 52b4cff454SVipin Bhandari #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 53b4cff454SVipin Bhandari #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 54b4cff454SVipin Bhandari #define DAVINCI_MMCCMD 0x30 /* Command Register */ 55b4cff454SVipin Bhandari #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 56b4cff454SVipin Bhandari #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 57b4cff454SVipin Bhandari #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 58b4cff454SVipin Bhandari #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 59b4cff454SVipin Bhandari #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 60b4cff454SVipin Bhandari #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 61b4cff454SVipin Bhandari #define DAVINCI_MMCETOK 0x4C 62b4cff454SVipin Bhandari #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 63b4cff454SVipin Bhandari #define DAVINCI_MMCCKC 0x54 64b4cff454SVipin Bhandari #define DAVINCI_MMCTORC 0x58 65b4cff454SVipin Bhandari #define DAVINCI_MMCTODC 0x5C 66b4cff454SVipin Bhandari #define DAVINCI_MMCBLNC 0x60 67b4cff454SVipin Bhandari #define DAVINCI_SDIOCTL 0x64 68b4cff454SVipin Bhandari #define DAVINCI_SDIOST0 0x68 69b4cff454SVipin Bhandari #define DAVINCI_SDIOEN 0x6C 70b4cff454SVipin Bhandari #define DAVINCI_SDIOST 0x70 71b4cff454SVipin Bhandari #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 72b4cff454SVipin Bhandari 73b4cff454SVipin Bhandari /* DAVINCI_MMCCTL definitions */ 74b4cff454SVipin Bhandari #define MMCCTL_DATRST (1 << 0) 75b4cff454SVipin Bhandari #define MMCCTL_CMDRST (1 << 1) 76132f1074SVipin Bhandari #define MMCCTL_WIDTH_8_BIT (1 << 8) 77b4cff454SVipin Bhandari #define MMCCTL_WIDTH_4_BIT (1 << 2) 78b4cff454SVipin Bhandari #define MMCCTL_DATEG_DISABLED (0 << 6) 79b4cff454SVipin Bhandari #define MMCCTL_DATEG_RISING (1 << 6) 80b4cff454SVipin Bhandari #define MMCCTL_DATEG_FALLING (2 << 6) 81b4cff454SVipin Bhandari #define MMCCTL_DATEG_BOTH (3 << 6) 82b4cff454SVipin Bhandari #define MMCCTL_PERMDR_LE (0 << 9) 83b4cff454SVipin Bhandari #define MMCCTL_PERMDR_BE (1 << 9) 84b4cff454SVipin Bhandari #define MMCCTL_PERMDX_LE (0 << 10) 85b4cff454SVipin Bhandari #define MMCCTL_PERMDX_BE (1 << 10) 86b4cff454SVipin Bhandari 87b4cff454SVipin Bhandari /* DAVINCI_MMCCLK definitions */ 88b4cff454SVipin Bhandari #define MMCCLK_CLKEN (1 << 8) 89b4cff454SVipin Bhandari #define MMCCLK_CLKRT_MASK (0xFF << 0) 90b4cff454SVipin Bhandari 91b4cff454SVipin Bhandari /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 92b4cff454SVipin Bhandari #define MMCST0_DATDNE BIT(0) /* data done */ 93b4cff454SVipin Bhandari #define MMCST0_BSYDNE BIT(1) /* busy done */ 94b4cff454SVipin Bhandari #define MMCST0_RSPDNE BIT(2) /* command done */ 95b4cff454SVipin Bhandari #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 96b4cff454SVipin Bhandari #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 97b4cff454SVipin Bhandari #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 98b4cff454SVipin Bhandari #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 99b4cff454SVipin Bhandari #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 100b4cff454SVipin Bhandari #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 101b4cff454SVipin Bhandari #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 102b4cff454SVipin Bhandari #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 103b4cff454SVipin Bhandari #define MMCST0_TRNDNE BIT(12) /* transfer done */ 104b4cff454SVipin Bhandari 105b4cff454SVipin Bhandari /* DAVINCI_MMCST1 definitions */ 106b4cff454SVipin Bhandari #define MMCST1_BUSY (1 << 0) 107b4cff454SVipin Bhandari 108b4cff454SVipin Bhandari /* DAVINCI_MMCCMD definitions */ 109b4cff454SVipin Bhandari #define MMCCMD_CMD_MASK (0x3F << 0) 110b4cff454SVipin Bhandari #define MMCCMD_PPLEN (1 << 7) 111b4cff454SVipin Bhandari #define MMCCMD_BSYEXP (1 << 8) 112b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_MASK (3 << 9) 113b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_NONE (0 << 9) 114b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R1456 (1 << 9) 115b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R2 (2 << 9) 116b4cff454SVipin Bhandari #define MMCCMD_RSPFMT_R3 (3 << 9) 117b4cff454SVipin Bhandari #define MMCCMD_DTRW (1 << 11) 118b4cff454SVipin Bhandari #define MMCCMD_STRMTP (1 << 12) 119b4cff454SVipin Bhandari #define MMCCMD_WDATX (1 << 13) 120b4cff454SVipin Bhandari #define MMCCMD_INITCK (1 << 14) 121b4cff454SVipin Bhandari #define MMCCMD_DCLR (1 << 15) 122b4cff454SVipin Bhandari #define MMCCMD_DMATRIG (1 << 16) 123b4cff454SVipin Bhandari 124b4cff454SVipin Bhandari /* DAVINCI_MMCFIFOCTL definitions */ 125b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFORST (1 << 0) 126b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 127b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 128b4cff454SVipin Bhandari #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 129b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 130b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 131b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 132b4cff454SVipin Bhandari #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 133b4cff454SVipin Bhandari 134b4cff454SVipin Bhandari 135b4cff454SVipin Bhandari /* MMCSD Init clock in Hz in opendrain mode */ 136b4cff454SVipin Bhandari #define MMCSD_INIT_CLOCK 200000 137b4cff454SVipin Bhandari 138b4cff454SVipin Bhandari /* 139b4cff454SVipin Bhandari * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 140ca2afb6dSSudhakar Rajashekhara * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 141b4cff454SVipin Bhandari * for drivers with max_hw_segs == 1, making the segments bigger (64KB) 142ca2afb6dSSudhakar Rajashekhara * than the page or two that's otherwise typical. nr_sg (passed from 143ca2afb6dSSudhakar Rajashekhara * platform data) == 16 gives at least the same throughput boost, using 144ca2afb6dSSudhakar Rajashekhara * EDMA transfer linkage instead of spending CPU time copying pages. 145b4cff454SVipin Bhandari */ 146b4cff454SVipin Bhandari #define MAX_CCNT ((1 << 16) - 1) 147b4cff454SVipin Bhandari 148ca2afb6dSSudhakar Rajashekhara #define MAX_NR_SG 16 149b4cff454SVipin Bhandari 150b4cff454SVipin Bhandari static unsigned rw_threshold = 32; 151b4cff454SVipin Bhandari module_param(rw_threshold, uint, S_IRUGO); 152b4cff454SVipin Bhandari MODULE_PARM_DESC(rw_threshold, 153b4cff454SVipin Bhandari "Read/Write threshold. Default = 32"); 154b4cff454SVipin Bhandari 155b4cff454SVipin Bhandari static unsigned __initdata use_dma = 1; 156b4cff454SVipin Bhandari module_param(use_dma, uint, 0); 157b4cff454SVipin Bhandari MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 158b4cff454SVipin Bhandari 159b4cff454SVipin Bhandari struct mmc_davinci_host { 160b4cff454SVipin Bhandari struct mmc_command *cmd; 161b4cff454SVipin Bhandari struct mmc_data *data; 162b4cff454SVipin Bhandari struct mmc_host *mmc; 163b4cff454SVipin Bhandari struct clk *clk; 164b4cff454SVipin Bhandari unsigned int mmc_input_clk; 165b4cff454SVipin Bhandari void __iomem *base; 166b4cff454SVipin Bhandari struct resource *mem_res; 167b4cff454SVipin Bhandari int irq; 168b4cff454SVipin Bhandari unsigned char bus_mode; 169b4cff454SVipin Bhandari 170b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_NONE 0 171b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_READ 1 172b4cff454SVipin Bhandari #define DAVINCI_MMC_DATADIR_WRITE 2 173b4cff454SVipin Bhandari unsigned char data_dir; 174b4cff454SVipin Bhandari 175b4cff454SVipin Bhandari /* buffer is used during PIO of one scatterlist segment, and 176b4cff454SVipin Bhandari * is updated along with buffer_bytes_left. bytes_left applies 177b4cff454SVipin Bhandari * to all N blocks of the PIO transfer. 178b4cff454SVipin Bhandari */ 179b4cff454SVipin Bhandari u8 *buffer; 180b4cff454SVipin Bhandari u32 buffer_bytes_left; 181b4cff454SVipin Bhandari u32 bytes_left; 182b4cff454SVipin Bhandari 1833d348aafSSudhakar Rajashekhara u32 rxdma, txdma; 184b4cff454SVipin Bhandari bool use_dma; 185b4cff454SVipin Bhandari bool do_dma; 186b4cff454SVipin Bhandari 187b4cff454SVipin Bhandari /* Scatterlist DMA uses one or more parameter RAM entries: 188b4cff454SVipin Bhandari * the main one (associated with rxdma or txdma) plus zero or 189b4cff454SVipin Bhandari * more links. The entries for a given transfer differ only 190b4cff454SVipin Bhandari * by memory buffer (address, length) and link field. 191b4cff454SVipin Bhandari */ 192b4cff454SVipin Bhandari struct edmacc_param tx_template; 193b4cff454SVipin Bhandari struct edmacc_param rx_template; 194b4cff454SVipin Bhandari unsigned n_link; 195ca2afb6dSSudhakar Rajashekhara u32 links[MAX_NR_SG - 1]; 196b4cff454SVipin Bhandari 197b4cff454SVipin Bhandari /* For PIO we walk scatterlists one segment at a time. */ 198b4cff454SVipin Bhandari unsigned int sg_len; 199b4cff454SVipin Bhandari struct scatterlist *sg; 200b4cff454SVipin Bhandari 201b4cff454SVipin Bhandari /* Version of the MMC/SD controller */ 202b4cff454SVipin Bhandari u8 version; 203b4cff454SVipin Bhandari /* for ns in one cycle calculation */ 204b4cff454SVipin Bhandari unsigned ns_in_one_cycle; 205ca2afb6dSSudhakar Rajashekhara /* Number of sg segments */ 206ca2afb6dSSudhakar Rajashekhara u8 nr_sg; 2077e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 2087e30b8deSChaithrika U S struct notifier_block freq_transition; 2097e30b8deSChaithrika U S #endif 210b4cff454SVipin Bhandari }; 211b4cff454SVipin Bhandari 212b4cff454SVipin Bhandari 213b4cff454SVipin Bhandari /* PIO only */ 214b4cff454SVipin Bhandari static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 215b4cff454SVipin Bhandari { 216b4cff454SVipin Bhandari host->buffer_bytes_left = sg_dma_len(host->sg); 217b4cff454SVipin Bhandari host->buffer = sg_virt(host->sg); 218b4cff454SVipin Bhandari if (host->buffer_bytes_left > host->bytes_left) 219b4cff454SVipin Bhandari host->buffer_bytes_left = host->bytes_left; 220b4cff454SVipin Bhandari } 221b4cff454SVipin Bhandari 222b4cff454SVipin Bhandari static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 223b4cff454SVipin Bhandari unsigned int n) 224b4cff454SVipin Bhandari { 225b4cff454SVipin Bhandari u8 *p; 226b4cff454SVipin Bhandari unsigned int i; 227b4cff454SVipin Bhandari 228b4cff454SVipin Bhandari if (host->buffer_bytes_left == 0) { 229b4cff454SVipin Bhandari host->sg = sg_next(host->data->sg); 230b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 231b4cff454SVipin Bhandari } 232b4cff454SVipin Bhandari 233b4cff454SVipin Bhandari p = host->buffer; 234b4cff454SVipin Bhandari if (n > host->buffer_bytes_left) 235b4cff454SVipin Bhandari n = host->buffer_bytes_left; 236b4cff454SVipin Bhandari host->buffer_bytes_left -= n; 237b4cff454SVipin Bhandari host->bytes_left -= n; 238b4cff454SVipin Bhandari 239b4cff454SVipin Bhandari /* NOTE: we never transfer more than rw_threshold bytes 240b4cff454SVipin Bhandari * to/from the fifo here; there's no I/O overlap. 241b4cff454SVipin Bhandari * This also assumes that access width( i.e. ACCWD) is 4 bytes 242b4cff454SVipin Bhandari */ 243b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 244b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 245b4cff454SVipin Bhandari writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 246b4cff454SVipin Bhandari p = p + 4; 247b4cff454SVipin Bhandari } 248b4cff454SVipin Bhandari if (n & 3) { 249b4cff454SVipin Bhandari iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 250b4cff454SVipin Bhandari p = p + (n & 3); 251b4cff454SVipin Bhandari } 252b4cff454SVipin Bhandari } else { 253b4cff454SVipin Bhandari for (i = 0; i < (n >> 2); i++) { 254b4cff454SVipin Bhandari *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 255b4cff454SVipin Bhandari p = p + 4; 256b4cff454SVipin Bhandari } 257b4cff454SVipin Bhandari if (n & 3) { 258b4cff454SVipin Bhandari ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 259b4cff454SVipin Bhandari p = p + (n & 3); 260b4cff454SVipin Bhandari } 261b4cff454SVipin Bhandari } 262b4cff454SVipin Bhandari host->buffer = p; 263b4cff454SVipin Bhandari } 264b4cff454SVipin Bhandari 265b4cff454SVipin Bhandari static void mmc_davinci_start_command(struct mmc_davinci_host *host, 266b4cff454SVipin Bhandari struct mmc_command *cmd) 267b4cff454SVipin Bhandari { 268b4cff454SVipin Bhandari u32 cmd_reg = 0; 269b4cff454SVipin Bhandari u32 im_val; 270b4cff454SVipin Bhandari 271b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 272b4cff454SVipin Bhandari cmd->opcode, cmd->arg, 273b4cff454SVipin Bhandari ({ char *s; 274b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 275b4cff454SVipin Bhandari case MMC_RSP_R1: 276b4cff454SVipin Bhandari s = ", R1/R5/R6/R7 response"; 277b4cff454SVipin Bhandari break; 278b4cff454SVipin Bhandari case MMC_RSP_R1B: 279b4cff454SVipin Bhandari s = ", R1b response"; 280b4cff454SVipin Bhandari break; 281b4cff454SVipin Bhandari case MMC_RSP_R2: 282b4cff454SVipin Bhandari s = ", R2 response"; 283b4cff454SVipin Bhandari break; 284b4cff454SVipin Bhandari case MMC_RSP_R3: 285b4cff454SVipin Bhandari s = ", R3/R4 response"; 286b4cff454SVipin Bhandari break; 287b4cff454SVipin Bhandari default: 288b4cff454SVipin Bhandari s = ", (R? response)"; 289b4cff454SVipin Bhandari break; 290b4cff454SVipin Bhandari }; s; })); 291b4cff454SVipin Bhandari host->cmd = cmd; 292b4cff454SVipin Bhandari 293b4cff454SVipin Bhandari switch (mmc_resp_type(cmd)) { 294b4cff454SVipin Bhandari case MMC_RSP_R1B: 295b4cff454SVipin Bhandari /* There's some spec confusion about when R1B is 296b4cff454SVipin Bhandari * allowed, but if the card doesn't issue a BUSY 297b4cff454SVipin Bhandari * then it's harmless for us to allow it. 298b4cff454SVipin Bhandari */ 299b4cff454SVipin Bhandari cmd_reg |= MMCCMD_BSYEXP; 300b4cff454SVipin Bhandari /* FALLTHROUGH */ 301b4cff454SVipin Bhandari case MMC_RSP_R1: /* 48 bits, CRC */ 302b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R1456; 303b4cff454SVipin Bhandari break; 304b4cff454SVipin Bhandari case MMC_RSP_R2: /* 136 bits, CRC */ 305b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R2; 306b4cff454SVipin Bhandari break; 307b4cff454SVipin Bhandari case MMC_RSP_R3: /* 48 bits, no CRC */ 308b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_R3; 309b4cff454SVipin Bhandari break; 310b4cff454SVipin Bhandari default: 311b4cff454SVipin Bhandari cmd_reg |= MMCCMD_RSPFMT_NONE; 312b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 313b4cff454SVipin Bhandari mmc_resp_type(cmd)); 314b4cff454SVipin Bhandari break; 315b4cff454SVipin Bhandari } 316b4cff454SVipin Bhandari 317b4cff454SVipin Bhandari /* Set command index */ 318b4cff454SVipin Bhandari cmd_reg |= cmd->opcode; 319b4cff454SVipin Bhandari 320b4cff454SVipin Bhandari /* Enable EDMA transfer triggers */ 321b4cff454SVipin Bhandari if (host->do_dma) 322b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 323b4cff454SVipin Bhandari 324b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 325b4cff454SVipin Bhandari host->data_dir == DAVINCI_MMC_DATADIR_READ) 326b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DMATRIG; 327b4cff454SVipin Bhandari 328b4cff454SVipin Bhandari /* Setting whether command involves data transfer or not */ 329b4cff454SVipin Bhandari if (cmd->data) 330b4cff454SVipin Bhandari cmd_reg |= MMCCMD_WDATX; 331b4cff454SVipin Bhandari 332b4cff454SVipin Bhandari /* Setting whether stream or block transfer */ 333b4cff454SVipin Bhandari if (cmd->flags & MMC_DATA_STREAM) 334b4cff454SVipin Bhandari cmd_reg |= MMCCMD_STRMTP; 335b4cff454SVipin Bhandari 336b4cff454SVipin Bhandari /* Setting whether data read or write */ 337b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 338b4cff454SVipin Bhandari cmd_reg |= MMCCMD_DTRW; 339b4cff454SVipin Bhandari 340b4cff454SVipin Bhandari if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 341b4cff454SVipin Bhandari cmd_reg |= MMCCMD_PPLEN; 342b4cff454SVipin Bhandari 343b4cff454SVipin Bhandari /* set Command timeout */ 344b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 345b4cff454SVipin Bhandari 346b4cff454SVipin Bhandari /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 347b4cff454SVipin Bhandari im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 348b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 349b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 350b4cff454SVipin Bhandari 351b4cff454SVipin Bhandari if (!host->do_dma) 352b4cff454SVipin Bhandari im_val |= MMCST0_DXRDY; 353b4cff454SVipin Bhandari } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 354b4cff454SVipin Bhandari im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 355b4cff454SVipin Bhandari 356b4cff454SVipin Bhandari if (!host->do_dma) 357b4cff454SVipin Bhandari im_val |= MMCST0_DRRDY; 358b4cff454SVipin Bhandari } 359b4cff454SVipin Bhandari 360b4cff454SVipin Bhandari /* 361b4cff454SVipin Bhandari * Before non-DMA WRITE commands the controller needs priming: 362b4cff454SVipin Bhandari * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 363b4cff454SVipin Bhandari */ 364b4cff454SVipin Bhandari if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 365b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 366b4cff454SVipin Bhandari 367b4cff454SVipin Bhandari writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 368b4cff454SVipin Bhandari writel(cmd_reg, host->base + DAVINCI_MMCCMD); 369b4cff454SVipin Bhandari writel(im_val, host->base + DAVINCI_MMCIM); 370b4cff454SVipin Bhandari } 371b4cff454SVipin Bhandari 372b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 373b4cff454SVipin Bhandari 374b4cff454SVipin Bhandari /* DMA infrastructure */ 375b4cff454SVipin Bhandari 376b4cff454SVipin Bhandari static void davinci_abort_dma(struct mmc_davinci_host *host) 377b4cff454SVipin Bhandari { 378b4cff454SVipin Bhandari int sync_dev; 379b4cff454SVipin Bhandari 380b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 381b4cff454SVipin Bhandari sync_dev = host->rxdma; 382b4cff454SVipin Bhandari else 383b4cff454SVipin Bhandari sync_dev = host->txdma; 384b4cff454SVipin Bhandari 385b4cff454SVipin Bhandari edma_stop(sync_dev); 386b4cff454SVipin Bhandari edma_clean_channel(sync_dev); 387b4cff454SVipin Bhandari } 388b4cff454SVipin Bhandari 389b4cff454SVipin Bhandari static void 390b4cff454SVipin Bhandari mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data); 391b4cff454SVipin Bhandari 392b4cff454SVipin Bhandari static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data) 393b4cff454SVipin Bhandari { 394b4cff454SVipin Bhandari if (DMA_COMPLETE != ch_status) { 395b4cff454SVipin Bhandari struct mmc_davinci_host *host = data; 396b4cff454SVipin Bhandari 397b4cff454SVipin Bhandari /* Currently means: DMA Event Missed, or "null" transfer 398b4cff454SVipin Bhandari * request was seen. In the future, TC errors (like bad 399b4cff454SVipin Bhandari * addresses) might be presented too. 400b4cff454SVipin Bhandari */ 401b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "DMA %s error\n", 402b4cff454SVipin Bhandari (host->data->flags & MMC_DATA_WRITE) 403b4cff454SVipin Bhandari ? "write" : "read"); 404b4cff454SVipin Bhandari host->data->error = -EIO; 405b4cff454SVipin Bhandari mmc_davinci_xfer_done(host, host->data); 406b4cff454SVipin Bhandari } 407b4cff454SVipin Bhandari } 408b4cff454SVipin Bhandari 409b4cff454SVipin Bhandari /* Set up tx or rx template, to be modified and updated later */ 410b4cff454SVipin Bhandari static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host, 411b4cff454SVipin Bhandari bool tx, struct edmacc_param *template) 412b4cff454SVipin Bhandari { 413b4cff454SVipin Bhandari unsigned sync_dev; 414b4cff454SVipin Bhandari const u16 acnt = 4; 415b4cff454SVipin Bhandari const u16 bcnt = rw_threshold >> 2; 416b4cff454SVipin Bhandari const u16 ccnt = 0; 417b4cff454SVipin Bhandari u32 src_port = 0; 418b4cff454SVipin Bhandari u32 dst_port = 0; 419b4cff454SVipin Bhandari s16 src_bidx, dst_bidx; 420b4cff454SVipin Bhandari s16 src_cidx, dst_cidx; 421b4cff454SVipin Bhandari 422b4cff454SVipin Bhandari /* 423b4cff454SVipin Bhandari * A-B Sync transfer: each DMA request is for one "frame" of 424b4cff454SVipin Bhandari * rw_threshold bytes, broken into "acnt"-size chunks repeated 425b4cff454SVipin Bhandari * "bcnt" times. Each segment needs "ccnt" such frames; since 426b4cff454SVipin Bhandari * we tell the block layer our mmc->max_seg_size limit, we can 427b4cff454SVipin Bhandari * trust (later) that it's within bounds. 428b4cff454SVipin Bhandari * 429b4cff454SVipin Bhandari * The FIFOs are read/written in 4-byte chunks (acnt == 4) and 430b4cff454SVipin Bhandari * EDMA will optimize memory operations to use larger bursts. 431b4cff454SVipin Bhandari */ 432b4cff454SVipin Bhandari if (tx) { 433b4cff454SVipin Bhandari sync_dev = host->txdma; 434b4cff454SVipin Bhandari 435b4cff454SVipin Bhandari /* src_prt, ccnt, and link to be set up later */ 436b4cff454SVipin Bhandari src_bidx = acnt; 437b4cff454SVipin Bhandari src_cidx = acnt * bcnt; 438b4cff454SVipin Bhandari 439b4cff454SVipin Bhandari dst_port = host->mem_res->start + DAVINCI_MMCDXR; 440b4cff454SVipin Bhandari dst_bidx = 0; 441b4cff454SVipin Bhandari dst_cidx = 0; 442b4cff454SVipin Bhandari } else { 443b4cff454SVipin Bhandari sync_dev = host->rxdma; 444b4cff454SVipin Bhandari 445b4cff454SVipin Bhandari src_port = host->mem_res->start + DAVINCI_MMCDRR; 446b4cff454SVipin Bhandari src_bidx = 0; 447b4cff454SVipin Bhandari src_cidx = 0; 448b4cff454SVipin Bhandari 449b4cff454SVipin Bhandari /* dst_prt, ccnt, and link to be set up later */ 450b4cff454SVipin Bhandari dst_bidx = acnt; 451b4cff454SVipin Bhandari dst_cidx = acnt * bcnt; 452b4cff454SVipin Bhandari } 453b4cff454SVipin Bhandari 454b4cff454SVipin Bhandari /* 455b4cff454SVipin Bhandari * We can't use FIFO mode for the FIFOs because MMC FIFO addresses 456b4cff454SVipin Bhandari * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT 457b4cff454SVipin Bhandari * parameter is ignored. 458b4cff454SVipin Bhandari */ 459b4cff454SVipin Bhandari edma_set_src(sync_dev, src_port, INCR, W8BIT); 460b4cff454SVipin Bhandari edma_set_dest(sync_dev, dst_port, INCR, W8BIT); 461b4cff454SVipin Bhandari 462b4cff454SVipin Bhandari edma_set_src_index(sync_dev, src_bidx, src_cidx); 463b4cff454SVipin Bhandari edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); 464b4cff454SVipin Bhandari 465b4cff454SVipin Bhandari edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); 466b4cff454SVipin Bhandari 467b4cff454SVipin Bhandari edma_read_slot(sync_dev, template); 468b4cff454SVipin Bhandari 469b4cff454SVipin Bhandari /* don't bother with irqs or chaining */ 470b4cff454SVipin Bhandari template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; 471b4cff454SVipin Bhandari } 472b4cff454SVipin Bhandari 473b4cff454SVipin Bhandari static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 474b4cff454SVipin Bhandari struct mmc_data *data) 475b4cff454SVipin Bhandari { 476b4cff454SVipin Bhandari struct edmacc_param *template; 477b4cff454SVipin Bhandari int channel, slot; 478b4cff454SVipin Bhandari unsigned link; 479b4cff454SVipin Bhandari struct scatterlist *sg; 480b4cff454SVipin Bhandari unsigned sg_len; 481b4cff454SVipin Bhandari unsigned bytes_left = host->bytes_left; 482b4cff454SVipin Bhandari const unsigned shift = ffs(rw_threshold) - 1;; 483b4cff454SVipin Bhandari 484b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 485b4cff454SVipin Bhandari template = &host->tx_template; 486b4cff454SVipin Bhandari channel = host->txdma; 487b4cff454SVipin Bhandari } else { 488b4cff454SVipin Bhandari template = &host->rx_template; 489b4cff454SVipin Bhandari channel = host->rxdma; 490b4cff454SVipin Bhandari } 491b4cff454SVipin Bhandari 492b4cff454SVipin Bhandari /* We know sg_len and ccnt will never be out of range because 493b4cff454SVipin Bhandari * we told the mmc layer which in turn tells the block layer 494b4cff454SVipin Bhandari * to ensure that it only hands us one scatterlist segment 495b4cff454SVipin Bhandari * per EDMA PARAM entry. Update the PARAM 496b4cff454SVipin Bhandari * entries needed for each segment of this scatterlist. 497b4cff454SVipin Bhandari */ 498b4cff454SVipin Bhandari for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len; 499b4cff454SVipin Bhandari sg_len-- != 0 && bytes_left; 500b4cff454SVipin Bhandari sg = sg_next(sg), slot = host->links[link++]) { 501b4cff454SVipin Bhandari u32 buf = sg_dma_address(sg); 502b4cff454SVipin Bhandari unsigned count = sg_dma_len(sg); 503b4cff454SVipin Bhandari 504b4cff454SVipin Bhandari template->link_bcntrld = sg_len 505b4cff454SVipin Bhandari ? (EDMA_CHAN_SLOT(host->links[link]) << 5) 506b4cff454SVipin Bhandari : 0xffff; 507b4cff454SVipin Bhandari 508b4cff454SVipin Bhandari if (count > bytes_left) 509b4cff454SVipin Bhandari count = bytes_left; 510b4cff454SVipin Bhandari bytes_left -= count; 511b4cff454SVipin Bhandari 512b4cff454SVipin Bhandari if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 513b4cff454SVipin Bhandari template->src = buf; 514b4cff454SVipin Bhandari else 515b4cff454SVipin Bhandari template->dst = buf; 516b4cff454SVipin Bhandari template->ccnt = count >> shift; 517b4cff454SVipin Bhandari 518b4cff454SVipin Bhandari edma_write_slot(slot, template); 519b4cff454SVipin Bhandari } 520b4cff454SVipin Bhandari 521b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 522b4cff454SVipin Bhandari edma_clear_event(channel); 523b4cff454SVipin Bhandari 524b4cff454SVipin Bhandari edma_start(channel); 525b4cff454SVipin Bhandari } 526b4cff454SVipin Bhandari 527b4cff454SVipin Bhandari static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 528b4cff454SVipin Bhandari struct mmc_data *data) 529b4cff454SVipin Bhandari { 530b4cff454SVipin Bhandari int i; 531b4cff454SVipin Bhandari int mask = rw_threshold - 1; 532b4cff454SVipin Bhandari 533b4cff454SVipin Bhandari host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 534b4cff454SVipin Bhandari ((data->flags & MMC_DATA_WRITE) 535b4cff454SVipin Bhandari ? DMA_TO_DEVICE 536b4cff454SVipin Bhandari : DMA_FROM_DEVICE)); 537b4cff454SVipin Bhandari 538b4cff454SVipin Bhandari /* no individual DMA segment should need a partial FIFO */ 539b4cff454SVipin Bhandari for (i = 0; i < host->sg_len; i++) { 540b4cff454SVipin Bhandari if (sg_dma_len(data->sg + i) & mask) { 541b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), 542b4cff454SVipin Bhandari data->sg, data->sg_len, 543b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 544b4cff454SVipin Bhandari ? DMA_TO_DEVICE 545b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 546b4cff454SVipin Bhandari return -1; 547b4cff454SVipin Bhandari } 548b4cff454SVipin Bhandari } 549b4cff454SVipin Bhandari 550b4cff454SVipin Bhandari host->do_dma = 1; 551b4cff454SVipin Bhandari mmc_davinci_send_dma_request(host, data); 552b4cff454SVipin Bhandari 553b4cff454SVipin Bhandari return 0; 554b4cff454SVipin Bhandari } 555b4cff454SVipin Bhandari 556b4cff454SVipin Bhandari static void __init_or_module 557b4cff454SVipin Bhandari davinci_release_dma_channels(struct mmc_davinci_host *host) 558b4cff454SVipin Bhandari { 559b4cff454SVipin Bhandari unsigned i; 560b4cff454SVipin Bhandari 561b4cff454SVipin Bhandari if (!host->use_dma) 562b4cff454SVipin Bhandari return; 563b4cff454SVipin Bhandari 564b4cff454SVipin Bhandari for (i = 0; i < host->n_link; i++) 565b4cff454SVipin Bhandari edma_free_slot(host->links[i]); 566b4cff454SVipin Bhandari 567b4cff454SVipin Bhandari edma_free_channel(host->txdma); 568b4cff454SVipin Bhandari edma_free_channel(host->rxdma); 569b4cff454SVipin Bhandari } 570b4cff454SVipin Bhandari 571b4cff454SVipin Bhandari static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 572b4cff454SVipin Bhandari { 573ca2afb6dSSudhakar Rajashekhara u32 link_size; 574b4cff454SVipin Bhandari int r, i; 575b4cff454SVipin Bhandari 576b4cff454SVipin Bhandari /* Acquire master DMA write channel */ 577b4cff454SVipin Bhandari r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host, 578b4cff454SVipin Bhandari EVENTQ_DEFAULT); 579b4cff454SVipin Bhandari if (r < 0) { 580b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 581b4cff454SVipin Bhandari "tx", r); 582b4cff454SVipin Bhandari return r; 583b4cff454SVipin Bhandari } 584b4cff454SVipin Bhandari mmc_davinci_dma_setup(host, true, &host->tx_template); 585b4cff454SVipin Bhandari 586b4cff454SVipin Bhandari /* Acquire master DMA read channel */ 587b4cff454SVipin Bhandari r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host, 588b4cff454SVipin Bhandari EVENTQ_DEFAULT); 589b4cff454SVipin Bhandari if (r < 0) { 590b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 591b4cff454SVipin Bhandari "rx", r); 592b4cff454SVipin Bhandari goto free_master_write; 593b4cff454SVipin Bhandari } 594b4cff454SVipin Bhandari mmc_davinci_dma_setup(host, false, &host->rx_template); 595b4cff454SVipin Bhandari 596b4cff454SVipin Bhandari /* Allocate parameter RAM slots, which will later be bound to a 597b4cff454SVipin Bhandari * channel as needed to handle a scatterlist. 598b4cff454SVipin Bhandari */ 599ca2afb6dSSudhakar Rajashekhara link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); 600ca2afb6dSSudhakar Rajashekhara for (i = 0; i < link_size; i++) { 601b4cff454SVipin Bhandari r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); 602b4cff454SVipin Bhandari if (r < 0) { 603b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n", 604b4cff454SVipin Bhandari r); 605b4cff454SVipin Bhandari break; 606b4cff454SVipin Bhandari } 607b4cff454SVipin Bhandari host->links[i] = r; 608b4cff454SVipin Bhandari } 609b4cff454SVipin Bhandari host->n_link = i; 610b4cff454SVipin Bhandari 611b4cff454SVipin Bhandari return 0; 612b4cff454SVipin Bhandari 613b4cff454SVipin Bhandari free_master_write: 614b4cff454SVipin Bhandari edma_free_channel(host->txdma); 615b4cff454SVipin Bhandari 616b4cff454SVipin Bhandari return r; 617b4cff454SVipin Bhandari } 618b4cff454SVipin Bhandari 619b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 620b4cff454SVipin Bhandari 621b4cff454SVipin Bhandari static void 622b4cff454SVipin Bhandari mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 623b4cff454SVipin Bhandari { 624b4cff454SVipin Bhandari int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 625b4cff454SVipin Bhandari int timeout; 626b4cff454SVipin Bhandari struct mmc_data *data = req->data; 627b4cff454SVipin Bhandari 628b4cff454SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 629b4cff454SVipin Bhandari fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 630b4cff454SVipin Bhandari 631b4cff454SVipin Bhandari host->data = data; 632b4cff454SVipin Bhandari if (data == NULL) { 633b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 634b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCBLEN); 635b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCNBLK); 636b4cff454SVipin Bhandari return; 637b4cff454SVipin Bhandari } 638b4cff454SVipin Bhandari 639b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n", 640b4cff454SVipin Bhandari (data->flags & MMC_DATA_STREAM) ? "stream" : "block", 641b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) ? "write" : "read", 642b4cff454SVipin Bhandari data->blocks, data->blksz); 643b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 644b4cff454SVipin Bhandari data->timeout_clks, data->timeout_ns); 645b4cff454SVipin Bhandari timeout = data->timeout_clks + 646b4cff454SVipin Bhandari (data->timeout_ns / host->ns_in_one_cycle); 647b4cff454SVipin Bhandari if (timeout > 0xffff) 648b4cff454SVipin Bhandari timeout = 0xffff; 649b4cff454SVipin Bhandari 650b4cff454SVipin Bhandari writel(timeout, host->base + DAVINCI_MMCTOD); 651b4cff454SVipin Bhandari writel(data->blocks, host->base + DAVINCI_MMCNBLK); 652b4cff454SVipin Bhandari writel(data->blksz, host->base + DAVINCI_MMCBLEN); 653b4cff454SVipin Bhandari 654b4cff454SVipin Bhandari /* Configure the FIFO */ 655b4cff454SVipin Bhandari switch (data->flags & MMC_DATA_WRITE) { 656b4cff454SVipin Bhandari case MMC_DATA_WRITE: 657b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 658b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 659b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 660b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 661b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 662b4cff454SVipin Bhandari break; 663b4cff454SVipin Bhandari 664b4cff454SVipin Bhandari default: 665b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_READ; 666b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 667b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 668b4cff454SVipin Bhandari writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 669b4cff454SVipin Bhandari host->base + DAVINCI_MMCFIFOCTL); 670b4cff454SVipin Bhandari break; 671b4cff454SVipin Bhandari } 672b4cff454SVipin Bhandari 673b4cff454SVipin Bhandari host->buffer = NULL; 674b4cff454SVipin Bhandari host->bytes_left = data->blocks * data->blksz; 675b4cff454SVipin Bhandari 676b4cff454SVipin Bhandari /* For now we try to use DMA whenever we won't need partial FIFO 677b4cff454SVipin Bhandari * reads or writes, either for the whole transfer (as tested here) 678b4cff454SVipin Bhandari * or for any individual scatterlist segment (tested when we call 679b4cff454SVipin Bhandari * start_dma_transfer). 680b4cff454SVipin Bhandari * 681b4cff454SVipin Bhandari * While we *could* change that, unusual block sizes are rarely 682b4cff454SVipin Bhandari * used. The occasional fallback to PIO should't hurt. 683b4cff454SVipin Bhandari */ 684b4cff454SVipin Bhandari if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 685b4cff454SVipin Bhandari && mmc_davinci_start_dma_transfer(host, data) == 0) { 686b4cff454SVipin Bhandari /* zero this to ensure we take no PIO paths */ 687b4cff454SVipin Bhandari host->bytes_left = 0; 688b4cff454SVipin Bhandari } else { 689b4cff454SVipin Bhandari /* Revert to CPU Copy */ 690b4cff454SVipin Bhandari host->sg_len = data->sg_len; 691b4cff454SVipin Bhandari host->sg = host->data->sg; 692b4cff454SVipin Bhandari mmc_davinci_sg_to_buf(host); 693b4cff454SVipin Bhandari } 694b4cff454SVipin Bhandari } 695b4cff454SVipin Bhandari 696b4cff454SVipin Bhandari static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 697b4cff454SVipin Bhandari { 698b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 699b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(900); 700b4cff454SVipin Bhandari u32 mmcst1 = 0; 701b4cff454SVipin Bhandari 702b4cff454SVipin Bhandari /* Card may still be sending BUSY after a previous operation, 703b4cff454SVipin Bhandari * typically some kind of write. If so, we can't proceed yet. 704b4cff454SVipin Bhandari */ 705b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 706b4cff454SVipin Bhandari mmcst1 = readl(host->base + DAVINCI_MMCST1); 707b4cff454SVipin Bhandari if (!(mmcst1 & MMCST1_BUSY)) 708b4cff454SVipin Bhandari break; 709b4cff454SVipin Bhandari cpu_relax(); 710b4cff454SVipin Bhandari } 711b4cff454SVipin Bhandari if (mmcst1 & MMCST1_BUSY) { 712b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 713b4cff454SVipin Bhandari req->cmd->error = -ETIMEDOUT; 714b4cff454SVipin Bhandari mmc_request_done(mmc, req); 715b4cff454SVipin Bhandari return; 716b4cff454SVipin Bhandari } 717b4cff454SVipin Bhandari 718b4cff454SVipin Bhandari host->do_dma = 0; 719b4cff454SVipin Bhandari mmc_davinci_prepare_data(host, req); 720b4cff454SVipin Bhandari mmc_davinci_start_command(host, req->cmd); 721b4cff454SVipin Bhandari } 722b4cff454SVipin Bhandari 723b4cff454SVipin Bhandari static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 724b4cff454SVipin Bhandari unsigned int mmc_req_freq) 725b4cff454SVipin Bhandari { 726b4cff454SVipin Bhandari unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 727b4cff454SVipin Bhandari 728b4cff454SVipin Bhandari mmc_pclk = host->mmc_input_clk; 729b4cff454SVipin Bhandari if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 730b4cff454SVipin Bhandari mmc_push_pull_divisor = ((unsigned int)mmc_pclk 731b4cff454SVipin Bhandari / (2 * mmc_req_freq)) - 1; 732b4cff454SVipin Bhandari else 733b4cff454SVipin Bhandari mmc_push_pull_divisor = 0; 734b4cff454SVipin Bhandari 735b4cff454SVipin Bhandari mmc_freq = (unsigned int)mmc_pclk 736b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)); 737b4cff454SVipin Bhandari 738b4cff454SVipin Bhandari if (mmc_freq > mmc_req_freq) 739b4cff454SVipin Bhandari mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 740b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 741b4cff454SVipin Bhandari if (mmc_req_freq <= 400000) 742b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 743b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000)); 744b4cff454SVipin Bhandari else 745b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (((mmc_pclk 746b4cff454SVipin Bhandari / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 747b4cff454SVipin Bhandari 748b4cff454SVipin Bhandari return mmc_push_pull_divisor; 749b4cff454SVipin Bhandari } 750b4cff454SVipin Bhandari 7517e30b8deSChaithrika U S static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 752b4cff454SVipin Bhandari { 753b4cff454SVipin Bhandari unsigned int open_drain_freq = 0, mmc_pclk = 0; 754b4cff454SVipin Bhandari unsigned int mmc_push_pull_freq = 0; 755b4cff454SVipin Bhandari struct mmc_davinci_host *host = mmc_priv(mmc); 756b4cff454SVipin Bhandari 757b4cff454SVipin Bhandari if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 758b4cff454SVipin Bhandari u32 temp; 759b4cff454SVipin Bhandari 760b4cff454SVipin Bhandari /* Ignoring the init clock value passed for fixing the inter 761b4cff454SVipin Bhandari * operability with different cards. 762b4cff454SVipin Bhandari */ 763b4cff454SVipin Bhandari open_drain_freq = ((unsigned int)mmc_pclk 764b4cff454SVipin Bhandari / (2 * MMCSD_INIT_CLOCK)) - 1; 765b4cff454SVipin Bhandari 766b4cff454SVipin Bhandari if (open_drain_freq > 0xFF) 767b4cff454SVipin Bhandari open_drain_freq = 0xFF; 768b4cff454SVipin Bhandari 769b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 770b4cff454SVipin Bhandari temp |= open_drain_freq; 771b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 772b4cff454SVipin Bhandari 773b4cff454SVipin Bhandari /* Convert ns to clock cycles */ 774b4cff454SVipin Bhandari host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 775b4cff454SVipin Bhandari } else { 776b4cff454SVipin Bhandari u32 temp; 777b4cff454SVipin Bhandari mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 778b4cff454SVipin Bhandari 779b4cff454SVipin Bhandari if (mmc_push_pull_freq > 0xFF) 780b4cff454SVipin Bhandari mmc_push_pull_freq = 0xFF; 781b4cff454SVipin Bhandari 782b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 783b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 784b4cff454SVipin Bhandari 785b4cff454SVipin Bhandari udelay(10); 786b4cff454SVipin Bhandari 787b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 788b4cff454SVipin Bhandari temp |= mmc_push_pull_freq; 789b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCLK); 790b4cff454SVipin Bhandari 791b4cff454SVipin Bhandari writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 792b4cff454SVipin Bhandari 793b4cff454SVipin Bhandari udelay(10); 794b4cff454SVipin Bhandari } 7957e30b8deSChaithrika U S } 7967e30b8deSChaithrika U S 7977e30b8deSChaithrika U S static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 7987e30b8deSChaithrika U S { 7997e30b8deSChaithrika U S struct mmc_davinci_host *host = mmc_priv(mmc); 8007e30b8deSChaithrika U S 8017e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), 8027e30b8deSChaithrika U S "clock %dHz busmode %d powermode %d Vdd %04x\n", 8037e30b8deSChaithrika U S ios->clock, ios->bus_mode, ios->power_mode, 8047e30b8deSChaithrika U S ios->vdd); 805132f1074SVipin Bhandari 806132f1074SVipin Bhandari switch (ios->bus_width) { 807132f1074SVipin Bhandari case MMC_BUS_WIDTH_8: 808132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 809132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 810132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 811132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 812132f1074SVipin Bhandari break; 813132f1074SVipin Bhandari case MMC_BUS_WIDTH_4: 8147e30b8deSChaithrika U S dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 815132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 816132f1074SVipin Bhandari writel((readl(host->base + DAVINCI_MMCCTL) & 817132f1074SVipin Bhandari ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 8187e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 819132f1074SVipin Bhandari else 820132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) | 821132f1074SVipin Bhandari MMCCTL_WIDTH_4_BIT, 8227e30b8deSChaithrika U S host->base + DAVINCI_MMCCTL); 823132f1074SVipin Bhandari break; 824132f1074SVipin Bhandari case MMC_BUS_WIDTH_1: 825132f1074SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 826132f1074SVipin Bhandari if (host->version == MMC_CTLR_VERSION_2) 827132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 828132f1074SVipin Bhandari ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 829132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 830132f1074SVipin Bhandari else 831132f1074SVipin Bhandari writel(readl(host->base + DAVINCI_MMCCTL) & 832132f1074SVipin Bhandari ~MMCCTL_WIDTH_4_BIT, 833132f1074SVipin Bhandari host->base + DAVINCI_MMCCTL); 834132f1074SVipin Bhandari break; 8357e30b8deSChaithrika U S } 8367e30b8deSChaithrika U S 8377e30b8deSChaithrika U S calculate_clk_divider(mmc, ios); 838b4cff454SVipin Bhandari 839b4cff454SVipin Bhandari host->bus_mode = ios->bus_mode; 840b4cff454SVipin Bhandari if (ios->power_mode == MMC_POWER_UP) { 841b4cff454SVipin Bhandari unsigned long timeout = jiffies + msecs_to_jiffies(50); 842b4cff454SVipin Bhandari bool lose = true; 843b4cff454SVipin Bhandari 844b4cff454SVipin Bhandari /* Send clock cycles, poll completion */ 845b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCARGHL); 846b4cff454SVipin Bhandari writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 847b4cff454SVipin Bhandari while (time_before(jiffies, timeout)) { 848b4cff454SVipin Bhandari u32 tmp = readl(host->base + DAVINCI_MMCST0); 849b4cff454SVipin Bhandari 850b4cff454SVipin Bhandari if (tmp & MMCST0_RSPDNE) { 851b4cff454SVipin Bhandari lose = false; 852b4cff454SVipin Bhandari break; 853b4cff454SVipin Bhandari } 854b4cff454SVipin Bhandari cpu_relax(); 855b4cff454SVipin Bhandari } 856b4cff454SVipin Bhandari if (lose) 857b4cff454SVipin Bhandari dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 858b4cff454SVipin Bhandari } 859b4cff454SVipin Bhandari 860b4cff454SVipin Bhandari /* FIXME on power OFF, reset things ... */ 861b4cff454SVipin Bhandari } 862b4cff454SVipin Bhandari 863b4cff454SVipin Bhandari static void 864b4cff454SVipin Bhandari mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 865b4cff454SVipin Bhandari { 866b4cff454SVipin Bhandari host->data = NULL; 867b4cff454SVipin Bhandari 868b4cff454SVipin Bhandari if (host->do_dma) { 869b4cff454SVipin Bhandari davinci_abort_dma(host); 870b4cff454SVipin Bhandari 871b4cff454SVipin Bhandari dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 872b4cff454SVipin Bhandari (data->flags & MMC_DATA_WRITE) 873b4cff454SVipin Bhandari ? DMA_TO_DEVICE 874b4cff454SVipin Bhandari : DMA_FROM_DEVICE); 875b4cff454SVipin Bhandari host->do_dma = false; 876b4cff454SVipin Bhandari } 877b4cff454SVipin Bhandari host->data_dir = DAVINCI_MMC_DATADIR_NONE; 878b4cff454SVipin Bhandari 879b4cff454SVipin Bhandari if (!data->stop || (host->cmd && host->cmd->error)) { 880b4cff454SVipin Bhandari mmc_request_done(host->mmc, data->mrq); 881b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 882b4cff454SVipin Bhandari } else 883b4cff454SVipin Bhandari mmc_davinci_start_command(host, data->stop); 884b4cff454SVipin Bhandari } 885b4cff454SVipin Bhandari 886b4cff454SVipin Bhandari static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 887b4cff454SVipin Bhandari struct mmc_command *cmd) 888b4cff454SVipin Bhandari { 889b4cff454SVipin Bhandari host->cmd = NULL; 890b4cff454SVipin Bhandari 891b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_PRESENT) { 892b4cff454SVipin Bhandari if (cmd->flags & MMC_RSP_136) { 893b4cff454SVipin Bhandari /* response type 2 */ 894b4cff454SVipin Bhandari cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 895b4cff454SVipin Bhandari cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 896b4cff454SVipin Bhandari cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 897b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 898b4cff454SVipin Bhandari } else { 899b4cff454SVipin Bhandari /* response types 1, 1b, 3, 4, 5, 6 */ 900b4cff454SVipin Bhandari cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 901b4cff454SVipin Bhandari } 902b4cff454SVipin Bhandari } 903b4cff454SVipin Bhandari 904b4cff454SVipin Bhandari if (host->data == NULL || cmd->error) { 905b4cff454SVipin Bhandari if (cmd->error == -ETIMEDOUT) 906b4cff454SVipin Bhandari cmd->mrq->cmd->retries = 0; 907b4cff454SVipin Bhandari mmc_request_done(host->mmc, cmd->mrq); 908b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 909b4cff454SVipin Bhandari } 910b4cff454SVipin Bhandari } 911b4cff454SVipin Bhandari 91206de845fSChaithrika U S static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 91306de845fSChaithrika U S int val) 914b4cff454SVipin Bhandari { 915b4cff454SVipin Bhandari u32 temp; 916b4cff454SVipin Bhandari 917b4cff454SVipin Bhandari temp = readl(host->base + DAVINCI_MMCCTL); 91806de845fSChaithrika U S if (val) /* reset */ 91906de845fSChaithrika U S temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 92006de845fSChaithrika U S else /* enable */ 921b4cff454SVipin Bhandari temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 92206de845fSChaithrika U S 923b4cff454SVipin Bhandari writel(temp, host->base + DAVINCI_MMCCTL); 92406de845fSChaithrika U S udelay(10); 92506de845fSChaithrika U S } 92606de845fSChaithrika U S 92706de845fSChaithrika U S static void 92806de845fSChaithrika U S davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 92906de845fSChaithrika U S { 93006de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 93106de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 932b4cff454SVipin Bhandari } 933b4cff454SVipin Bhandari 934b4cff454SVipin Bhandari static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 935b4cff454SVipin Bhandari { 936b4cff454SVipin Bhandari struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 937b4cff454SVipin Bhandari unsigned int status, qstatus; 938b4cff454SVipin Bhandari int end_command = 0; 939b4cff454SVipin Bhandari int end_transfer = 0; 940b4cff454SVipin Bhandari struct mmc_data *data = host->data; 941b4cff454SVipin Bhandari 942b4cff454SVipin Bhandari if (host->cmd == NULL && host->data == NULL) { 943b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 944b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 945b4cff454SVipin Bhandari "Spurious interrupt 0x%04x\n", status); 946b4cff454SVipin Bhandari /* Disable the interrupt from mmcsd */ 947b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCIM); 948b4cff454SVipin Bhandari return IRQ_NONE; 949b4cff454SVipin Bhandari } 950b4cff454SVipin Bhandari 951b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 952b4cff454SVipin Bhandari qstatus = status; 953b4cff454SVipin Bhandari 954b4cff454SVipin Bhandari /* handle FIFO first when using PIO for data. 955b4cff454SVipin Bhandari * bytes_left will decrease to zero as I/O progress and status will 956b4cff454SVipin Bhandari * read zero over iteration because this controller status 957b4cff454SVipin Bhandari * register(MMCST0) reports any status only once and it is cleared 958b4cff454SVipin Bhandari * by read. So, it is not unbouned loop even in the case of 959b4cff454SVipin Bhandari * non-dma. 960b4cff454SVipin Bhandari */ 961b4cff454SVipin Bhandari while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 962b4cff454SVipin Bhandari davinci_fifo_data_trans(host, rw_threshold); 963b4cff454SVipin Bhandari status = readl(host->base + DAVINCI_MMCST0); 964b4cff454SVipin Bhandari if (!status) 965b4cff454SVipin Bhandari break; 966b4cff454SVipin Bhandari qstatus |= status; 967b4cff454SVipin Bhandari } 968b4cff454SVipin Bhandari 969b4cff454SVipin Bhandari if (qstatus & MMCST0_DATDNE) { 970b4cff454SVipin Bhandari /* All blocks sent/received, and CRC checks passed */ 971b4cff454SVipin Bhandari if (data != NULL) { 972b4cff454SVipin Bhandari if ((host->do_dma == 0) && (host->bytes_left > 0)) { 973b4cff454SVipin Bhandari /* if datasize < rw_threshold 974b4cff454SVipin Bhandari * no RX ints are generated 975b4cff454SVipin Bhandari */ 976b4cff454SVipin Bhandari davinci_fifo_data_trans(host, host->bytes_left); 977b4cff454SVipin Bhandari } 978b4cff454SVipin Bhandari end_transfer = 1; 979b4cff454SVipin Bhandari data->bytes_xfered = data->blocks * data->blksz; 980b4cff454SVipin Bhandari } else { 981b4cff454SVipin Bhandari dev_err(mmc_dev(host->mmc), 982b4cff454SVipin Bhandari "DATDNE with no host->data\n"); 983b4cff454SVipin Bhandari } 984b4cff454SVipin Bhandari } 985b4cff454SVipin Bhandari 986b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRD) { 987b4cff454SVipin Bhandari /* Read data timeout */ 988b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 989b4cff454SVipin Bhandari end_transfer = 1; 990b4cff454SVipin Bhandari 991b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 992b4cff454SVipin Bhandari "read data timeout, status %x\n", 993b4cff454SVipin Bhandari qstatus); 994b4cff454SVipin Bhandari 995b4cff454SVipin Bhandari davinci_abort_data(host, data); 996b4cff454SVipin Bhandari } 997b4cff454SVipin Bhandari 998b4cff454SVipin Bhandari if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 999b4cff454SVipin Bhandari /* Data CRC error */ 1000b4cff454SVipin Bhandari data->error = -EILSEQ; 1001b4cff454SVipin Bhandari end_transfer = 1; 1002b4cff454SVipin Bhandari 1003b4cff454SVipin Bhandari /* NOTE: this controller uses CRCWR to report both CRC 1004b4cff454SVipin Bhandari * errors and timeouts (on writes). MMCDRSP values are 1005b4cff454SVipin Bhandari * only weakly documented, but 0x9f was clearly a timeout 1006b4cff454SVipin Bhandari * case and the two three-bit patterns in various SD specs 1007b4cff454SVipin Bhandari * (101, 010) aren't part of it ... 1008b4cff454SVipin Bhandari */ 1009b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCWR) { 1010b4cff454SVipin Bhandari u32 temp = readb(host->base + DAVINCI_MMCDRSP); 1011b4cff454SVipin Bhandari 1012b4cff454SVipin Bhandari if (temp == 0x9f) 1013b4cff454SVipin Bhandari data->error = -ETIMEDOUT; 1014b4cff454SVipin Bhandari } 1015b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 1016b4cff454SVipin Bhandari (qstatus & MMCST0_CRCWR) ? "write" : "read", 1017b4cff454SVipin Bhandari (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 1018b4cff454SVipin Bhandari 1019b4cff454SVipin Bhandari davinci_abort_data(host, data); 1020b4cff454SVipin Bhandari } 1021b4cff454SVipin Bhandari 1022b4cff454SVipin Bhandari if (qstatus & MMCST0_TOUTRS) { 1023b4cff454SVipin Bhandari /* Command timeout */ 1024b4cff454SVipin Bhandari if (host->cmd) { 1025b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), 1026b4cff454SVipin Bhandari "CMD%d timeout, status %x\n", 1027b4cff454SVipin Bhandari host->cmd->opcode, qstatus); 1028b4cff454SVipin Bhandari host->cmd->error = -ETIMEDOUT; 1029b4cff454SVipin Bhandari if (data) { 1030b4cff454SVipin Bhandari end_transfer = 1; 1031b4cff454SVipin Bhandari davinci_abort_data(host, data); 1032b4cff454SVipin Bhandari } else 1033b4cff454SVipin Bhandari end_command = 1; 1034b4cff454SVipin Bhandari } 1035b4cff454SVipin Bhandari } 1036b4cff454SVipin Bhandari 1037b4cff454SVipin Bhandari if (qstatus & MMCST0_CRCRS) { 1038b4cff454SVipin Bhandari /* Command CRC error */ 1039b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1040b4cff454SVipin Bhandari if (host->cmd) { 1041b4cff454SVipin Bhandari host->cmd->error = -EILSEQ; 1042b4cff454SVipin Bhandari end_command = 1; 1043b4cff454SVipin Bhandari } 1044b4cff454SVipin Bhandari } 1045b4cff454SVipin Bhandari 1046b4cff454SVipin Bhandari if (qstatus & MMCST0_RSPDNE) { 1047b4cff454SVipin Bhandari /* End of command phase */ 1048b4cff454SVipin Bhandari end_command = (int) host->cmd; 1049b4cff454SVipin Bhandari } 1050b4cff454SVipin Bhandari 1051b4cff454SVipin Bhandari if (end_command) 1052b4cff454SVipin Bhandari mmc_davinci_cmd_done(host, host->cmd); 1053b4cff454SVipin Bhandari if (end_transfer) 1054b4cff454SVipin Bhandari mmc_davinci_xfer_done(host, data); 1055b4cff454SVipin Bhandari return IRQ_HANDLED; 1056b4cff454SVipin Bhandari } 1057b4cff454SVipin Bhandari 1058b4cff454SVipin Bhandari static int mmc_davinci_get_cd(struct mmc_host *mmc) 1059b4cff454SVipin Bhandari { 1060b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1061b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1062b4cff454SVipin Bhandari 1063b4cff454SVipin Bhandari if (!config || !config->get_cd) 1064b4cff454SVipin Bhandari return -ENOSYS; 1065b4cff454SVipin Bhandari return config->get_cd(pdev->id); 1066b4cff454SVipin Bhandari } 1067b4cff454SVipin Bhandari 1068b4cff454SVipin Bhandari static int mmc_davinci_get_ro(struct mmc_host *mmc) 1069b4cff454SVipin Bhandari { 1070b4cff454SVipin Bhandari struct platform_device *pdev = to_platform_device(mmc->parent); 1071b4cff454SVipin Bhandari struct davinci_mmc_config *config = pdev->dev.platform_data; 1072b4cff454SVipin Bhandari 1073b4cff454SVipin Bhandari if (!config || !config->get_ro) 1074b4cff454SVipin Bhandari return -ENOSYS; 1075b4cff454SVipin Bhandari return config->get_ro(pdev->id); 1076b4cff454SVipin Bhandari } 1077b4cff454SVipin Bhandari 1078b4cff454SVipin Bhandari static struct mmc_host_ops mmc_davinci_ops = { 1079b4cff454SVipin Bhandari .request = mmc_davinci_request, 1080b4cff454SVipin Bhandari .set_ios = mmc_davinci_set_ios, 1081b4cff454SVipin Bhandari .get_cd = mmc_davinci_get_cd, 1082b4cff454SVipin Bhandari .get_ro = mmc_davinci_get_ro, 1083b4cff454SVipin Bhandari }; 1084b4cff454SVipin Bhandari 1085b4cff454SVipin Bhandari /*----------------------------------------------------------------------*/ 1086b4cff454SVipin Bhandari 10877e30b8deSChaithrika U S #ifdef CONFIG_CPU_FREQ 10887e30b8deSChaithrika U S static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 10897e30b8deSChaithrika U S unsigned long val, void *data) 10907e30b8deSChaithrika U S { 10917e30b8deSChaithrika U S struct mmc_davinci_host *host; 10927e30b8deSChaithrika U S unsigned int mmc_pclk; 10937e30b8deSChaithrika U S struct mmc_host *mmc; 10947e30b8deSChaithrika U S unsigned long flags; 10957e30b8deSChaithrika U S 10967e30b8deSChaithrika U S host = container_of(nb, struct mmc_davinci_host, freq_transition); 10977e30b8deSChaithrika U S mmc = host->mmc; 10987e30b8deSChaithrika U S mmc_pclk = clk_get_rate(host->clk); 10997e30b8deSChaithrika U S 11007e30b8deSChaithrika U S if (val == CPUFREQ_POSTCHANGE) { 11017e30b8deSChaithrika U S spin_lock_irqsave(&mmc->lock, flags); 11027e30b8deSChaithrika U S host->mmc_input_clk = mmc_pclk; 11037e30b8deSChaithrika U S calculate_clk_divider(mmc, &mmc->ios); 11047e30b8deSChaithrika U S spin_unlock_irqrestore(&mmc->lock, flags); 11057e30b8deSChaithrika U S } 11067e30b8deSChaithrika U S 11077e30b8deSChaithrika U S return 0; 11087e30b8deSChaithrika U S } 11097e30b8deSChaithrika U S 11107e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 11117e30b8deSChaithrika U S { 11127e30b8deSChaithrika U S host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 11137e30b8deSChaithrika U S 11147e30b8deSChaithrika U S return cpufreq_register_notifier(&host->freq_transition, 11157e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 11167e30b8deSChaithrika U S } 11177e30b8deSChaithrika U S 11187e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11197e30b8deSChaithrika U S { 11207e30b8deSChaithrika U S cpufreq_unregister_notifier(&host->freq_transition, 11217e30b8deSChaithrika U S CPUFREQ_TRANSITION_NOTIFIER); 11227e30b8deSChaithrika U S } 11237e30b8deSChaithrika U S #else 11247e30b8deSChaithrika U S static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 11257e30b8deSChaithrika U S { 11267e30b8deSChaithrika U S return 0; 11277e30b8deSChaithrika U S } 11287e30b8deSChaithrika U S 11297e30b8deSChaithrika U S static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 11307e30b8deSChaithrika U S { 11317e30b8deSChaithrika U S } 11327e30b8deSChaithrika U S #endif 1133b4cff454SVipin Bhandari static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1134b4cff454SVipin Bhandari { 1135b4cff454SVipin Bhandari 113606de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 1); 1137b4cff454SVipin Bhandari 1138b4cff454SVipin Bhandari writel(0, host->base + DAVINCI_MMCCLK); 1139b4cff454SVipin Bhandari writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1140b4cff454SVipin Bhandari 1141b4cff454SVipin Bhandari writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1142b4cff454SVipin Bhandari writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1143b4cff454SVipin Bhandari 114406de845fSChaithrika U S mmc_davinci_reset_ctrl(host, 0); 1145b4cff454SVipin Bhandari } 1146b4cff454SVipin Bhandari 1147b4cff454SVipin Bhandari static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1148b4cff454SVipin Bhandari { 1149b4cff454SVipin Bhandari struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1150b4cff454SVipin Bhandari struct mmc_davinci_host *host = NULL; 1151b4cff454SVipin Bhandari struct mmc_host *mmc = NULL; 1152b4cff454SVipin Bhandari struct resource *r, *mem = NULL; 1153b4cff454SVipin Bhandari int ret = 0, irq = 0; 1154b4cff454SVipin Bhandari size_t mem_size; 1155b4cff454SVipin Bhandari 1156b4cff454SVipin Bhandari /* REVISIT: when we're fully converted, fail if pdata is NULL */ 1157b4cff454SVipin Bhandari 1158b4cff454SVipin Bhandari ret = -ENODEV; 1159b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1160b4cff454SVipin Bhandari irq = platform_get_irq(pdev, 0); 1161b4cff454SVipin Bhandari if (!r || irq == NO_IRQ) 1162b4cff454SVipin Bhandari goto out; 1163b4cff454SVipin Bhandari 1164b4cff454SVipin Bhandari ret = -EBUSY; 1165b4cff454SVipin Bhandari mem_size = resource_size(r); 1166b4cff454SVipin Bhandari mem = request_mem_region(r->start, mem_size, pdev->name); 1167b4cff454SVipin Bhandari if (!mem) 1168b4cff454SVipin Bhandari goto out; 1169b4cff454SVipin Bhandari 1170b4cff454SVipin Bhandari ret = -ENOMEM; 1171b4cff454SVipin Bhandari mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1172b4cff454SVipin Bhandari if (!mmc) 1173b4cff454SVipin Bhandari goto out; 1174b4cff454SVipin Bhandari 1175b4cff454SVipin Bhandari host = mmc_priv(mmc); 1176b4cff454SVipin Bhandari host->mmc = mmc; /* Important */ 1177b4cff454SVipin Bhandari 1178b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1179b4cff454SVipin Bhandari if (!r) 1180b4cff454SVipin Bhandari goto out; 1181b4cff454SVipin Bhandari host->rxdma = r->start; 1182b4cff454SVipin Bhandari 1183b4cff454SVipin Bhandari r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1184b4cff454SVipin Bhandari if (!r) 1185b4cff454SVipin Bhandari goto out; 1186b4cff454SVipin Bhandari host->txdma = r->start; 1187b4cff454SVipin Bhandari 1188b4cff454SVipin Bhandari host->mem_res = mem; 1189b4cff454SVipin Bhandari host->base = ioremap(mem->start, mem_size); 1190b4cff454SVipin Bhandari if (!host->base) 1191b4cff454SVipin Bhandari goto out; 1192b4cff454SVipin Bhandari 1193b4cff454SVipin Bhandari ret = -ENXIO; 1194b4cff454SVipin Bhandari host->clk = clk_get(&pdev->dev, "MMCSDCLK"); 1195b4cff454SVipin Bhandari if (IS_ERR(host->clk)) { 1196b4cff454SVipin Bhandari ret = PTR_ERR(host->clk); 1197b4cff454SVipin Bhandari goto out; 1198b4cff454SVipin Bhandari } 1199b4cff454SVipin Bhandari clk_enable(host->clk); 1200b4cff454SVipin Bhandari host->mmc_input_clk = clk_get_rate(host->clk); 1201b4cff454SVipin Bhandari 1202b4cff454SVipin Bhandari init_mmcsd_host(host); 1203b4cff454SVipin Bhandari 1204ca2afb6dSSudhakar Rajashekhara if (pdata->nr_sg) 1205ca2afb6dSSudhakar Rajashekhara host->nr_sg = pdata->nr_sg - 1; 1206ca2afb6dSSudhakar Rajashekhara 1207ca2afb6dSSudhakar Rajashekhara if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1208ca2afb6dSSudhakar Rajashekhara host->nr_sg = MAX_NR_SG; 1209ca2afb6dSSudhakar Rajashekhara 1210b4cff454SVipin Bhandari host->use_dma = use_dma; 1211b4cff454SVipin Bhandari host->irq = irq; 1212b4cff454SVipin Bhandari 1213b4cff454SVipin Bhandari if (host->use_dma && davinci_acquire_dma_channels(host) != 0) 1214b4cff454SVipin Bhandari host->use_dma = 0; 1215b4cff454SVipin Bhandari 1216b4cff454SVipin Bhandari /* REVISIT: someday, support IRQ-driven card detection. */ 1217b4cff454SVipin Bhandari mmc->caps |= MMC_CAP_NEEDS_POLL; 1218132f1074SVipin Bhandari mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1219b4cff454SVipin Bhandari 1220132f1074SVipin Bhandari if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1221b4cff454SVipin Bhandari mmc->caps |= MMC_CAP_4_BIT_DATA; 1222b4cff454SVipin Bhandari 1223132f1074SVipin Bhandari if (pdata && (pdata->wires == 8)) 1224132f1074SVipin Bhandari mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1225132f1074SVipin Bhandari 1226b4cff454SVipin Bhandari host->version = pdata->version; 1227b4cff454SVipin Bhandari 1228b4cff454SVipin Bhandari mmc->ops = &mmc_davinci_ops; 1229b4cff454SVipin Bhandari mmc->f_min = 312500; 1230b4cff454SVipin Bhandari mmc->f_max = 25000000; 1231b4cff454SVipin Bhandari if (pdata && pdata->max_freq) 1232b4cff454SVipin Bhandari mmc->f_max = pdata->max_freq; 1233b4cff454SVipin Bhandari if (pdata && pdata->caps) 1234b4cff454SVipin Bhandari mmc->caps |= pdata->caps; 1235b4cff454SVipin Bhandari mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1236b4cff454SVipin Bhandari 1237b4cff454SVipin Bhandari /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1238b4cff454SVipin Bhandari * Each hw_seg uses one EDMA parameter RAM slot, always one 1239b4cff454SVipin Bhandari * channel and then usually some linked slots. 1240b4cff454SVipin Bhandari */ 1241b4cff454SVipin Bhandari mmc->max_hw_segs = 1 + host->n_link; 1242b4cff454SVipin Bhandari mmc->max_phys_segs = mmc->max_hw_segs; 1243b4cff454SVipin Bhandari 1244b4cff454SVipin Bhandari /* EDMA limit per hw segment (one or two MBytes) */ 1245b4cff454SVipin Bhandari mmc->max_seg_size = MAX_CCNT * rw_threshold; 1246b4cff454SVipin Bhandari 1247b4cff454SVipin Bhandari /* MMC/SD controller limits for multiblock requests */ 1248b4cff454SVipin Bhandari mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1249b4cff454SVipin Bhandari mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1250b4cff454SVipin Bhandari mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1251b4cff454SVipin Bhandari 1252b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_phys_segs=%d\n", mmc->max_phys_segs); 1253b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_hw_segs=%d\n", mmc->max_hw_segs); 1254b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1255b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1256b4cff454SVipin Bhandari dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1257b4cff454SVipin Bhandari 1258b4cff454SVipin Bhandari platform_set_drvdata(pdev, host); 1259b4cff454SVipin Bhandari 12607e30b8deSChaithrika U S ret = mmc_davinci_cpufreq_register(host); 12617e30b8deSChaithrika U S if (ret) { 12627e30b8deSChaithrika U S dev_err(&pdev->dev, "failed to register cpufreq\n"); 12637e30b8deSChaithrika U S goto cpu_freq_fail; 12647e30b8deSChaithrika U S } 12657e30b8deSChaithrika U S 1266b4cff454SVipin Bhandari ret = mmc_add_host(mmc); 1267b4cff454SVipin Bhandari if (ret < 0) 1268b4cff454SVipin Bhandari goto out; 1269b4cff454SVipin Bhandari 1270b4cff454SVipin Bhandari ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host); 1271b4cff454SVipin Bhandari if (ret) 1272b4cff454SVipin Bhandari goto out; 1273b4cff454SVipin Bhandari 1274b4cff454SVipin Bhandari rename_region(mem, mmc_hostname(mmc)); 1275b4cff454SVipin Bhandari 1276b4cff454SVipin Bhandari dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1277b4cff454SVipin Bhandari host->use_dma ? "DMA" : "PIO", 1278b4cff454SVipin Bhandari (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1279b4cff454SVipin Bhandari 1280b4cff454SVipin Bhandari return 0; 1281b4cff454SVipin Bhandari 1282b4cff454SVipin Bhandari out: 12837e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 12847e30b8deSChaithrika U S cpu_freq_fail: 1285b4cff454SVipin Bhandari if (host) { 1286b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1287b4cff454SVipin Bhandari 1288b4cff454SVipin Bhandari if (host->clk) { 1289b4cff454SVipin Bhandari clk_disable(host->clk); 1290b4cff454SVipin Bhandari clk_put(host->clk); 1291b4cff454SVipin Bhandari } 1292b4cff454SVipin Bhandari 1293b4cff454SVipin Bhandari if (host->base) 1294b4cff454SVipin Bhandari iounmap(host->base); 1295b4cff454SVipin Bhandari } 1296b4cff454SVipin Bhandari 1297b4cff454SVipin Bhandari if (mmc) 1298b4cff454SVipin Bhandari mmc_free_host(mmc); 1299b4cff454SVipin Bhandari 1300b4cff454SVipin Bhandari if (mem) 1301b4cff454SVipin Bhandari release_resource(mem); 1302b4cff454SVipin Bhandari 1303b4cff454SVipin Bhandari dev_dbg(&pdev->dev, "probe err %d\n", ret); 1304b4cff454SVipin Bhandari 1305b4cff454SVipin Bhandari return ret; 1306b4cff454SVipin Bhandari } 1307b4cff454SVipin Bhandari 1308b4cff454SVipin Bhandari static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1309b4cff454SVipin Bhandari { 1310b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1311b4cff454SVipin Bhandari 1312b4cff454SVipin Bhandari platform_set_drvdata(pdev, NULL); 1313b4cff454SVipin Bhandari if (host) { 13147e30b8deSChaithrika U S mmc_davinci_cpufreq_deregister(host); 13157e30b8deSChaithrika U S 1316b4cff454SVipin Bhandari mmc_remove_host(host->mmc); 1317b4cff454SVipin Bhandari free_irq(host->irq, host); 1318b4cff454SVipin Bhandari 1319b4cff454SVipin Bhandari davinci_release_dma_channels(host); 1320b4cff454SVipin Bhandari 1321b4cff454SVipin Bhandari clk_disable(host->clk); 1322b4cff454SVipin Bhandari clk_put(host->clk); 1323b4cff454SVipin Bhandari 1324b4cff454SVipin Bhandari iounmap(host->base); 1325b4cff454SVipin Bhandari 1326b4cff454SVipin Bhandari release_resource(host->mem_res); 1327b4cff454SVipin Bhandari 1328b4cff454SVipin Bhandari mmc_free_host(host->mmc); 1329b4cff454SVipin Bhandari } 1330b4cff454SVipin Bhandari 1331b4cff454SVipin Bhandari return 0; 1332b4cff454SVipin Bhandari } 1333b4cff454SVipin Bhandari 1334b4cff454SVipin Bhandari #ifdef CONFIG_PM 1335b4cff454SVipin Bhandari static int davinci_mmcsd_suspend(struct platform_device *pdev, pm_message_t msg) 1336b4cff454SVipin Bhandari { 1337b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1338b4cff454SVipin Bhandari 1339b4cff454SVipin Bhandari return mmc_suspend_host(host->mmc, msg); 1340b4cff454SVipin Bhandari } 1341b4cff454SVipin Bhandari 1342b4cff454SVipin Bhandari static int davinci_mmcsd_resume(struct platform_device *pdev) 1343b4cff454SVipin Bhandari { 1344b4cff454SVipin Bhandari struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1345b4cff454SVipin Bhandari 1346b4cff454SVipin Bhandari return mmc_resume_host(host->mmc); 1347b4cff454SVipin Bhandari } 1348b4cff454SVipin Bhandari #else 1349b4cff454SVipin Bhandari #define davinci_mmcsd_suspend NULL 1350b4cff454SVipin Bhandari #define davinci_mmcsd_resume NULL 1351b4cff454SVipin Bhandari #endif 1352b4cff454SVipin Bhandari 1353b4cff454SVipin Bhandari static struct platform_driver davinci_mmcsd_driver = { 1354b4cff454SVipin Bhandari .driver = { 1355b4cff454SVipin Bhandari .name = "davinci_mmc", 1356b4cff454SVipin Bhandari .owner = THIS_MODULE, 1357b4cff454SVipin Bhandari }, 1358b4cff454SVipin Bhandari .remove = __exit_p(davinci_mmcsd_remove), 1359b4cff454SVipin Bhandari .suspend = davinci_mmcsd_suspend, 1360b4cff454SVipin Bhandari .resume = davinci_mmcsd_resume, 1361b4cff454SVipin Bhandari }; 1362b4cff454SVipin Bhandari 1363b4cff454SVipin Bhandari static int __init davinci_mmcsd_init(void) 1364b4cff454SVipin Bhandari { 1365b4cff454SVipin Bhandari return platform_driver_probe(&davinci_mmcsd_driver, 1366b4cff454SVipin Bhandari davinci_mmcsd_probe); 1367b4cff454SVipin Bhandari } 1368b4cff454SVipin Bhandari module_init(davinci_mmcsd_init); 1369b4cff454SVipin Bhandari 1370b4cff454SVipin Bhandari static void __exit davinci_mmcsd_exit(void) 1371b4cff454SVipin Bhandari { 1372b4cff454SVipin Bhandari platform_driver_unregister(&davinci_mmcsd_driver); 1373b4cff454SVipin Bhandari } 1374b4cff454SVipin Bhandari module_exit(davinci_mmcsd_exit); 1375b4cff454SVipin Bhandari 1376b4cff454SVipin Bhandari MODULE_AUTHOR("Texas Instruments India"); 1377b4cff454SVipin Bhandari MODULE_LICENSE("GPL"); 1378b4cff454SVipin Bhandari MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 1379b4cff454SVipin Bhandari 1380