1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 #ifndef LINUX_MMC_CQHCI_H 13 #define LINUX_MMC_CQHCI_H 14 15 #include <linux/compiler.h> 16 #include <linux/bitops.h> 17 #include <linux/spinlock_types.h> 18 #include <linux/types.h> 19 #include <linux/completion.h> 20 #include <linux/wait.h> 21 #include <linux/irqreturn.h> 22 #include <asm/io.h> 23 24 /* registers */ 25 /* version */ 26 #define CQHCI_VER 0x00 27 #define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8) 28 #define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4) 29 #define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0)) 30 31 /* capabilities */ 32 #define CQHCI_CAP 0x04 33 /* configuration */ 34 #define CQHCI_CFG 0x08 35 #define CQHCI_DCMD 0x00001000 36 #define CQHCI_TASK_DESC_SZ 0x00000100 37 #define CQHCI_ENABLE 0x00000001 38 39 /* control */ 40 #define CQHCI_CTL 0x0C 41 #define CQHCI_CLEAR_ALL_TASKS 0x00000100 42 #define CQHCI_HALT 0x00000001 43 44 /* interrupt status */ 45 #define CQHCI_IS 0x10 46 #define CQHCI_IS_HAC BIT(0) 47 #define CQHCI_IS_TCC BIT(1) 48 #define CQHCI_IS_RED BIT(2) 49 #define CQHCI_IS_TCL BIT(3) 50 51 #define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED) 52 53 /* interrupt status enable */ 54 #define CQHCI_ISTE 0x14 55 56 /* interrupt signal enable */ 57 #define CQHCI_ISGE 0x18 58 59 /* interrupt coalescing */ 60 #define CQHCI_IC 0x1C 61 #define CQHCI_IC_ENABLE BIT(31) 62 #define CQHCI_IC_RESET BIT(16) 63 #define CQHCI_IC_ICCTHWEN BIT(15) 64 #define CQHCI_IC_ICCTH(x) ((x & 0x1F) << 8) 65 #define CQHCI_IC_ICTOVALWEN BIT(7) 66 #define CQHCI_IC_ICTOVAL(x) (x & 0x7F) 67 68 /* task list base address */ 69 #define CQHCI_TDLBA 0x20 70 71 /* task list base address upper */ 72 #define CQHCI_TDLBAU 0x24 73 74 /* door-bell */ 75 #define CQHCI_TDBR 0x28 76 77 /* task completion notification */ 78 #define CQHCI_TCN 0x2C 79 80 /* device queue status */ 81 #define CQHCI_DQS 0x30 82 83 /* device pending tasks */ 84 #define CQHCI_DPT 0x34 85 86 /* task clear */ 87 #define CQHCI_TCLR 0x38 88 89 /* send status config 1 */ 90 #define CQHCI_SSC1 0x40 91 92 /* send status config 2 */ 93 #define CQHCI_SSC2 0x44 94 95 /* response for dcmd */ 96 #define CQHCI_CRDCT 0x48 97 98 /* response mode error mask */ 99 #define CQHCI_RMEM 0x50 100 101 /* task error info */ 102 #define CQHCI_TERRI 0x54 103 104 #define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0)) 105 #define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8) 106 #define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15)) 107 #define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16) 108 #define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24) 109 #define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31)) 110 111 /* command response index */ 112 #define CQHCI_CRI 0x58 113 114 /* command response argument */ 115 #define CQHCI_CRA 0x5C 116 117 #define CQHCI_INT_ALL 0xF 118 #define CQHCI_IC_DEFAULT_ICCTH 31 119 #define CQHCI_IC_DEFAULT_ICTOVAL 1 120 121 /* attribute fields */ 122 #define CQHCI_VALID(x) ((x & 1) << 0) 123 #define CQHCI_END(x) ((x & 1) << 1) 124 #define CQHCI_INT(x) ((x & 1) << 2) 125 #define CQHCI_ACT(x) ((x & 0x7) << 3) 126 127 /* data command task descriptor fields */ 128 #define CQHCI_FORCED_PROG(x) ((x & 1) << 6) 129 #define CQHCI_CONTEXT(x) ((x & 0xF) << 7) 130 #define CQHCI_DATA_TAG(x) ((x & 1) << 11) 131 #define CQHCI_DATA_DIR(x) ((x & 1) << 12) 132 #define CQHCI_PRIORITY(x) ((x & 1) << 13) 133 #define CQHCI_QBAR(x) ((x & 1) << 14) 134 #define CQHCI_REL_WRITE(x) ((x & 1) << 15) 135 #define CQHCI_BLK_COUNT(x) ((x & 0xFFFF) << 16) 136 #define CQHCI_BLK_ADDR(x) ((x & 0xFFFFFFFF) << 32) 137 138 /* direct command task descriptor fields */ 139 #define CQHCI_CMD_INDEX(x) ((x & 0x3F) << 16) 140 #define CQHCI_CMD_TIMING(x) ((x & 1) << 22) 141 #define CQHCI_RESP_TYPE(x) ((x & 0x3) << 23) 142 143 /* transfer descriptor fields */ 144 #define CQHCI_DAT_LENGTH(x) ((x & 0xFFFF) << 16) 145 #define CQHCI_DAT_ADDR_LO(x) ((x & 0xFFFFFFFF) << 32) 146 #define CQHCI_DAT_ADDR_HI(x) ((x & 0xFFFFFFFF) << 0) 147 148 struct cqhci_host_ops; 149 struct mmc_host; 150 struct cqhci_slot; 151 152 struct cqhci_host { 153 const struct cqhci_host_ops *ops; 154 void __iomem *mmio; 155 struct mmc_host *mmc; 156 157 spinlock_t lock; 158 159 /* relative card address of device */ 160 unsigned int rca; 161 162 /* 64 bit DMA */ 163 bool dma64; 164 int num_slots; 165 int qcnt; 166 167 u32 dcmd_slot; 168 u32 caps; 169 #define CQHCI_TASK_DESC_SZ_128 0x1 170 171 u32 quirks; 172 #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1 173 174 bool enabled; 175 bool halted; 176 bool init_done; 177 bool activated; 178 bool waiting_for_idle; 179 bool recovery_halt; 180 181 size_t desc_size; 182 size_t data_size; 183 184 u8 *desc_base; 185 186 /* total descriptor size */ 187 u8 slot_sz; 188 189 /* 64/128 bit depends on CQHCI_CFG */ 190 u8 task_desc_len; 191 192 /* 64 bit on 32-bit arch, 128 bit on 64-bit */ 193 u8 link_desc_len; 194 195 u8 *trans_desc_base; 196 /* same length as transfer descriptor */ 197 u8 trans_desc_len; 198 199 dma_addr_t desc_dma_base; 200 dma_addr_t trans_desc_dma_base; 201 202 struct completion halt_comp; 203 wait_queue_head_t wait_queue; 204 struct cqhci_slot *slot; 205 }; 206 207 struct cqhci_host_ops { 208 void (*dumpregs)(struct mmc_host *mmc); 209 void (*write_l)(struct cqhci_host *host, u32 val, int reg); 210 u32 (*read_l)(struct cqhci_host *host, int reg); 211 void (*enable)(struct mmc_host *mmc); 212 void (*disable)(struct mmc_host *mmc, bool recovery); 213 }; 214 215 static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) 216 { 217 if (unlikely(host->ops->write_l)) 218 host->ops->write_l(host, val, reg); 219 else 220 writel_relaxed(val, host->mmio + reg); 221 } 222 223 static inline u32 cqhci_readl(struct cqhci_host *host, int reg) 224 { 225 if (unlikely(host->ops->read_l)) 226 return host->ops->read_l(host, reg); 227 else 228 return readl_relaxed(host->mmio + reg); 229 } 230 231 struct platform_device; 232 233 irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error, 234 int data_error); 235 int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64); 236 struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev); 237 int cqhci_suspend(struct mmc_host *mmc); 238 int cqhci_resume(struct mmc_host *mmc); 239 240 #endif 241