1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 #ifndef LINUX_MMC_CQHCI_H 13 #define LINUX_MMC_CQHCI_H 14 15 #include <linux/compiler.h> 16 #include <linux/bitops.h> 17 #include <linux/spinlock_types.h> 18 #include <linux/types.h> 19 #include <linux/completion.h> 20 #include <linux/wait.h> 21 #include <linux/irqreturn.h> 22 #include <asm/io.h> 23 24 /* registers */ 25 /* version */ 26 #define CQHCI_VER 0x00 27 #define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8) 28 #define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4) 29 #define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0)) 30 31 /* capabilities */ 32 #define CQHCI_CAP 0x04 33 /* configuration */ 34 #define CQHCI_CFG 0x08 35 #define CQHCI_DCMD 0x00001000 36 #define CQHCI_TASK_DESC_SZ 0x00000100 37 #define CQHCI_ENABLE 0x00000001 38 39 /* control */ 40 #define CQHCI_CTL 0x0C 41 #define CQHCI_CLEAR_ALL_TASKS 0x00000100 42 #define CQHCI_HALT 0x00000001 43 44 /* interrupt status */ 45 #define CQHCI_IS 0x10 46 #define CQHCI_IS_HAC BIT(0) 47 #define CQHCI_IS_TCC BIT(1) 48 #define CQHCI_IS_RED BIT(2) 49 #define CQHCI_IS_TCL BIT(3) 50 51 #define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED) 52 53 /* interrupt status enable */ 54 #define CQHCI_ISTE 0x14 55 56 /* interrupt signal enable */ 57 #define CQHCI_ISGE 0x18 58 59 /* interrupt coalescing */ 60 #define CQHCI_IC 0x1C 61 #define CQHCI_IC_ENABLE BIT(31) 62 #define CQHCI_IC_RESET BIT(16) 63 #define CQHCI_IC_ICCTHWEN BIT(15) 64 #define CQHCI_IC_ICCTH(x) (((x) & 0x1F) << 8) 65 #define CQHCI_IC_ICTOVALWEN BIT(7) 66 #define CQHCI_IC_ICTOVAL(x) ((x) & 0x7F) 67 68 /* task list base address */ 69 #define CQHCI_TDLBA 0x20 70 71 /* task list base address upper */ 72 #define CQHCI_TDLBAU 0x24 73 74 /* door-bell */ 75 #define CQHCI_TDBR 0x28 76 77 /* task completion notification */ 78 #define CQHCI_TCN 0x2C 79 80 /* device queue status */ 81 #define CQHCI_DQS 0x30 82 83 /* device pending tasks */ 84 #define CQHCI_DPT 0x34 85 86 /* task clear */ 87 #define CQHCI_TCLR 0x38 88 89 /* send status config 1 */ 90 #define CQHCI_SSC1 0x40 91 #define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) 92 93 /* send status config 2 */ 94 #define CQHCI_SSC2 0x44 95 96 /* response for dcmd */ 97 #define CQHCI_CRDCT 0x48 98 99 /* response mode error mask */ 100 #define CQHCI_RMEM 0x50 101 102 /* task error info */ 103 #define CQHCI_TERRI 0x54 104 105 #define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0)) 106 #define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8) 107 #define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15)) 108 #define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16) 109 #define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24) 110 #define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31)) 111 112 /* command response index */ 113 #define CQHCI_CRI 0x58 114 115 /* command response argument */ 116 #define CQHCI_CRA 0x5C 117 118 #define CQHCI_INT_ALL 0xF 119 #define CQHCI_IC_DEFAULT_ICCTH 31 120 #define CQHCI_IC_DEFAULT_ICTOVAL 1 121 122 /* attribute fields */ 123 #define CQHCI_VALID(x) (((x) & 1) << 0) 124 #define CQHCI_END(x) (((x) & 1) << 1) 125 #define CQHCI_INT(x) (((x) & 1) << 2) 126 #define CQHCI_ACT(x) (((x) & 0x7) << 3) 127 128 /* data command task descriptor fields */ 129 #define CQHCI_FORCED_PROG(x) (((x) & 1) << 6) 130 #define CQHCI_CONTEXT(x) (((x) & 0xF) << 7) 131 #define CQHCI_DATA_TAG(x) (((x) & 1) << 11) 132 #define CQHCI_DATA_DIR(x) (((x) & 1) << 12) 133 #define CQHCI_PRIORITY(x) (((x) & 1) << 13) 134 #define CQHCI_QBAR(x) (((x) & 1) << 14) 135 #define CQHCI_REL_WRITE(x) (((x) & 1) << 15) 136 #define CQHCI_BLK_COUNT(x) (((x) & 0xFFFF) << 16) 137 #define CQHCI_BLK_ADDR(x) (((x) & 0xFFFFFFFF) << 32) 138 139 /* direct command task descriptor fields */ 140 #define CQHCI_CMD_INDEX(x) (((x) & 0x3F) << 16) 141 #define CQHCI_CMD_TIMING(x) (((x) & 1) << 22) 142 #define CQHCI_RESP_TYPE(x) (((x) & 0x3) << 23) 143 144 /* transfer descriptor fields */ 145 #define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16) 146 #define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32) 147 #define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0) 148 149 struct cqhci_host_ops; 150 struct mmc_host; 151 struct mmc_request; 152 struct cqhci_slot; 153 154 struct cqhci_host { 155 const struct cqhci_host_ops *ops; 156 void __iomem *mmio; 157 struct mmc_host *mmc; 158 159 spinlock_t lock; 160 161 /* relative card address of device */ 162 unsigned int rca; 163 164 /* 64 bit DMA */ 165 bool dma64; 166 int num_slots; 167 int qcnt; 168 169 u32 dcmd_slot; 170 u32 caps; 171 #define CQHCI_TASK_DESC_SZ_128 0x1 172 173 u32 quirks; 174 #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1 175 176 bool enabled; 177 bool halted; 178 bool init_done; 179 bool activated; 180 bool waiting_for_idle; 181 bool recovery_halt; 182 183 size_t desc_size; 184 size_t data_size; 185 186 u8 *desc_base; 187 188 /* total descriptor size */ 189 u8 slot_sz; 190 191 /* 64/128 bit depends on CQHCI_CFG */ 192 u8 task_desc_len; 193 194 /* 64 bit on 32-bit arch, 128 bit on 64-bit */ 195 u8 link_desc_len; 196 197 u8 *trans_desc_base; 198 /* same length as transfer descriptor */ 199 u8 trans_desc_len; 200 201 dma_addr_t desc_dma_base; 202 dma_addr_t trans_desc_dma_base; 203 204 struct completion halt_comp; 205 wait_queue_head_t wait_queue; 206 struct cqhci_slot *slot; 207 }; 208 209 struct cqhci_host_ops { 210 void (*dumpregs)(struct mmc_host *mmc); 211 void (*write_l)(struct cqhci_host *host, u32 val, int reg); 212 u32 (*read_l)(struct cqhci_host *host, int reg); 213 void (*enable)(struct mmc_host *mmc); 214 void (*disable)(struct mmc_host *mmc, bool recovery); 215 void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq, 216 u64 *data); 217 }; 218 219 static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) 220 { 221 if (unlikely(host->ops->write_l)) 222 host->ops->write_l(host, val, reg); 223 else 224 writel_relaxed(val, host->mmio + reg); 225 } 226 227 static inline u32 cqhci_readl(struct cqhci_host *host, int reg) 228 { 229 if (unlikely(host->ops->read_l)) 230 return host->ops->read_l(host, reg); 231 else 232 return readl_relaxed(host->mmio + reg); 233 } 234 235 struct platform_device; 236 237 irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error, 238 int data_error); 239 int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64); 240 struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev); 241 int cqhci_suspend(struct mmc_host *mmc); 242 int cqhci_resume(struct mmc_host *mmc); 243 244 #endif 245