197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2a4080225SVenkat Gopalakrishnan /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
3a4080225SVenkat Gopalakrishnan */
4a4080225SVenkat Gopalakrishnan #ifndef LINUX_MMC_CQHCI_H
5a4080225SVenkat Gopalakrishnan #define LINUX_MMC_CQHCI_H
6a4080225SVenkat Gopalakrishnan
7a4080225SVenkat Gopalakrishnan #include <linux/compiler.h>
8*f2764e1fSWenbin Mei #include <linux/bitfield.h>
9a4080225SVenkat Gopalakrishnan #include <linux/bitops.h>
10a4080225SVenkat Gopalakrishnan #include <linux/spinlock_types.h>
11a4080225SVenkat Gopalakrishnan #include <linux/types.h>
12a4080225SVenkat Gopalakrishnan #include <linux/completion.h>
13a4080225SVenkat Gopalakrishnan #include <linux/wait.h>
14a4080225SVenkat Gopalakrishnan #include <linux/irqreturn.h>
15a4080225SVenkat Gopalakrishnan #include <asm/io.h>
16a4080225SVenkat Gopalakrishnan
17a4080225SVenkat Gopalakrishnan /* registers */
18a4080225SVenkat Gopalakrishnan /* version */
19a4080225SVenkat Gopalakrishnan #define CQHCI_VER 0x00
20a4080225SVenkat Gopalakrishnan #define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8)
21a4080225SVenkat Gopalakrishnan #define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4)
22a4080225SVenkat Gopalakrishnan #define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0))
23a4080225SVenkat Gopalakrishnan
24a4080225SVenkat Gopalakrishnan /* capabilities */
25a4080225SVenkat Gopalakrishnan #define CQHCI_CAP 0x04
261e80709bSEric Biggers #define CQHCI_CAP_CS 0x10000000 /* Crypto Support */
27*f2764e1fSWenbin Mei #define CQHCI_CAP_ITCFMUL GENMASK(15, 12)
28*f2764e1fSWenbin Mei #define CQHCI_ITCFMUL(x) FIELD_GET(CQHCI_CAP_ITCFMUL, (x))
291e80709bSEric Biggers
30a4080225SVenkat Gopalakrishnan /* configuration */
31a4080225SVenkat Gopalakrishnan #define CQHCI_CFG 0x08
32a4080225SVenkat Gopalakrishnan #define CQHCI_DCMD 0x00001000
33a4080225SVenkat Gopalakrishnan #define CQHCI_TASK_DESC_SZ 0x00000100
341e80709bSEric Biggers #define CQHCI_CRYPTO_GENERAL_ENABLE 0x00000002
35a4080225SVenkat Gopalakrishnan #define CQHCI_ENABLE 0x00000001
36a4080225SVenkat Gopalakrishnan
37a4080225SVenkat Gopalakrishnan /* control */
38a4080225SVenkat Gopalakrishnan #define CQHCI_CTL 0x0C
39a4080225SVenkat Gopalakrishnan #define CQHCI_CLEAR_ALL_TASKS 0x00000100
40a4080225SVenkat Gopalakrishnan #define CQHCI_HALT 0x00000001
41a4080225SVenkat Gopalakrishnan
42a4080225SVenkat Gopalakrishnan /* interrupt status */
43a4080225SVenkat Gopalakrishnan #define CQHCI_IS 0x10
44a4080225SVenkat Gopalakrishnan #define CQHCI_IS_HAC BIT(0)
45a4080225SVenkat Gopalakrishnan #define CQHCI_IS_TCC BIT(1)
46a4080225SVenkat Gopalakrishnan #define CQHCI_IS_RED BIT(2)
47a4080225SVenkat Gopalakrishnan #define CQHCI_IS_TCL BIT(3)
481e80709bSEric Biggers #define CQHCI_IS_GCE BIT(4) /* General Crypto Error */
491e80709bSEric Biggers #define CQHCI_IS_ICCE BIT(5) /* Invalid Crypto Config Error */
50a4080225SVenkat Gopalakrishnan
511e80709bSEric Biggers #define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \
521e80709bSEric Biggers CQHCI_IS_GCE | CQHCI_IS_ICCE)
53a4080225SVenkat Gopalakrishnan
54a4080225SVenkat Gopalakrishnan /* interrupt status enable */
55a4080225SVenkat Gopalakrishnan #define CQHCI_ISTE 0x14
56a4080225SVenkat Gopalakrishnan
57a4080225SVenkat Gopalakrishnan /* interrupt signal enable */
58a4080225SVenkat Gopalakrishnan #define CQHCI_ISGE 0x18
59a4080225SVenkat Gopalakrishnan
60a4080225SVenkat Gopalakrishnan /* interrupt coalescing */
61a4080225SVenkat Gopalakrishnan #define CQHCI_IC 0x1C
62a4080225SVenkat Gopalakrishnan #define CQHCI_IC_ENABLE BIT(31)
63a4080225SVenkat Gopalakrishnan #define CQHCI_IC_RESET BIT(16)
64a4080225SVenkat Gopalakrishnan #define CQHCI_IC_ICCTHWEN BIT(15)
650562315bSAdrian Hunter #define CQHCI_IC_ICCTH(x) (((x) & 0x1F) << 8)
66a4080225SVenkat Gopalakrishnan #define CQHCI_IC_ICTOVALWEN BIT(7)
670562315bSAdrian Hunter #define CQHCI_IC_ICTOVAL(x) ((x) & 0x7F)
68a4080225SVenkat Gopalakrishnan
69a4080225SVenkat Gopalakrishnan /* task list base address */
70a4080225SVenkat Gopalakrishnan #define CQHCI_TDLBA 0x20
71a4080225SVenkat Gopalakrishnan
72a4080225SVenkat Gopalakrishnan /* task list base address upper */
73a4080225SVenkat Gopalakrishnan #define CQHCI_TDLBAU 0x24
74a4080225SVenkat Gopalakrishnan
75a4080225SVenkat Gopalakrishnan /* door-bell */
76a4080225SVenkat Gopalakrishnan #define CQHCI_TDBR 0x28
77a4080225SVenkat Gopalakrishnan
78a4080225SVenkat Gopalakrishnan /* task completion notification */
79a4080225SVenkat Gopalakrishnan #define CQHCI_TCN 0x2C
80a4080225SVenkat Gopalakrishnan
81a4080225SVenkat Gopalakrishnan /* device queue status */
82a4080225SVenkat Gopalakrishnan #define CQHCI_DQS 0x30
83a4080225SVenkat Gopalakrishnan
84a4080225SVenkat Gopalakrishnan /* device pending tasks */
85a4080225SVenkat Gopalakrishnan #define CQHCI_DPT 0x34
86a4080225SVenkat Gopalakrishnan
87a4080225SVenkat Gopalakrishnan /* task clear */
88a4080225SVenkat Gopalakrishnan #define CQHCI_TCLR 0x38
89a4080225SVenkat Gopalakrishnan
901e80709bSEric Biggers /* task descriptor processing error */
911e80709bSEric Biggers #define CQHCI_TDPE 0x3c
921e80709bSEric Biggers
93a4080225SVenkat Gopalakrishnan /* send status config 1 */
94a4080225SVenkat Gopalakrishnan #define CQHCI_SSC1 0x40
9568895644SSowjanya Komatineni #define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
96a4080225SVenkat Gopalakrishnan
97a4080225SVenkat Gopalakrishnan /* send status config 2 */
98a4080225SVenkat Gopalakrishnan #define CQHCI_SSC2 0x44
99a4080225SVenkat Gopalakrishnan
100a4080225SVenkat Gopalakrishnan /* response for dcmd */
101a4080225SVenkat Gopalakrishnan #define CQHCI_CRDCT 0x48
102a4080225SVenkat Gopalakrishnan
103a4080225SVenkat Gopalakrishnan /* response mode error mask */
104a4080225SVenkat Gopalakrishnan #define CQHCI_RMEM 0x50
105a4080225SVenkat Gopalakrishnan
106a4080225SVenkat Gopalakrishnan /* task error info */
107a4080225SVenkat Gopalakrishnan #define CQHCI_TERRI 0x54
108a4080225SVenkat Gopalakrishnan
109a4080225SVenkat Gopalakrishnan #define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0))
110a4080225SVenkat Gopalakrishnan #define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8)
111a4080225SVenkat Gopalakrishnan #define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15))
112a4080225SVenkat Gopalakrishnan #define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16)
113a4080225SVenkat Gopalakrishnan #define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24)
114a4080225SVenkat Gopalakrishnan #define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31))
115a4080225SVenkat Gopalakrishnan
116a4080225SVenkat Gopalakrishnan /* command response index */
117a4080225SVenkat Gopalakrishnan #define CQHCI_CRI 0x58
118a4080225SVenkat Gopalakrishnan
119a4080225SVenkat Gopalakrishnan /* command response argument */
120a4080225SVenkat Gopalakrishnan #define CQHCI_CRA 0x5C
121a4080225SVenkat Gopalakrishnan
1221e80709bSEric Biggers /* crypto capabilities */
1231e80709bSEric Biggers #define CQHCI_CCAP 0x100
1241e80709bSEric Biggers #define CQHCI_CRYPTOCAP 0x104
1251e80709bSEric Biggers
126a4080225SVenkat Gopalakrishnan #define CQHCI_INT_ALL 0xF
127a4080225SVenkat Gopalakrishnan #define CQHCI_IC_DEFAULT_ICCTH 31
128a4080225SVenkat Gopalakrishnan #define CQHCI_IC_DEFAULT_ICTOVAL 1
129a4080225SVenkat Gopalakrishnan
130a4080225SVenkat Gopalakrishnan /* attribute fields */
1310562315bSAdrian Hunter #define CQHCI_VALID(x) (((x) & 1) << 0)
1320562315bSAdrian Hunter #define CQHCI_END(x) (((x) & 1) << 1)
1330562315bSAdrian Hunter #define CQHCI_INT(x) (((x) & 1) << 2)
1340562315bSAdrian Hunter #define CQHCI_ACT(x) (((x) & 0x7) << 3)
135a4080225SVenkat Gopalakrishnan
136a4080225SVenkat Gopalakrishnan /* data command task descriptor fields */
1370562315bSAdrian Hunter #define CQHCI_FORCED_PROG(x) (((x) & 1) << 6)
1380562315bSAdrian Hunter #define CQHCI_CONTEXT(x) (((x) & 0xF) << 7)
1390562315bSAdrian Hunter #define CQHCI_DATA_TAG(x) (((x) & 1) << 11)
1400562315bSAdrian Hunter #define CQHCI_DATA_DIR(x) (((x) & 1) << 12)
1410562315bSAdrian Hunter #define CQHCI_PRIORITY(x) (((x) & 1) << 13)
1420562315bSAdrian Hunter #define CQHCI_QBAR(x) (((x) & 1) << 14)
1430562315bSAdrian Hunter #define CQHCI_REL_WRITE(x) (((x) & 1) << 15)
1440562315bSAdrian Hunter #define CQHCI_BLK_COUNT(x) (((x) & 0xFFFF) << 16)
1450562315bSAdrian Hunter #define CQHCI_BLK_ADDR(x) (((x) & 0xFFFFFFFF) << 32)
146a4080225SVenkat Gopalakrishnan
147a4080225SVenkat Gopalakrishnan /* direct command task descriptor fields */
1480562315bSAdrian Hunter #define CQHCI_CMD_INDEX(x) (((x) & 0x3F) << 16)
1490562315bSAdrian Hunter #define CQHCI_CMD_TIMING(x) (((x) & 1) << 22)
1500562315bSAdrian Hunter #define CQHCI_RESP_TYPE(x) (((x) & 0x3) << 23)
151a4080225SVenkat Gopalakrishnan
1521e80709bSEric Biggers /* crypto task descriptor fields (for bits 64-127 of task descriptor) */
1531e80709bSEric Biggers #define CQHCI_CRYPTO_ENABLE_BIT (1ULL << 47)
1541e80709bSEric Biggers #define CQHCI_CRYPTO_KEYSLOT(x) ((u64)(x) << 32)
1551e80709bSEric Biggers
156a4080225SVenkat Gopalakrishnan /* transfer descriptor fields */
1570562315bSAdrian Hunter #define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16)
1580562315bSAdrian Hunter #define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
1590562315bSAdrian Hunter #define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
160a4080225SVenkat Gopalakrishnan
1611e80709bSEric Biggers /* CCAP - Crypto Capability 100h */
1621e80709bSEric Biggers union cqhci_crypto_capabilities {
1631e80709bSEric Biggers __le32 reg_val;
1641e80709bSEric Biggers struct {
1651e80709bSEric Biggers u8 num_crypto_cap;
1661e80709bSEric Biggers u8 config_count;
1671e80709bSEric Biggers u8 reserved;
1681e80709bSEric Biggers u8 config_array_ptr;
1691e80709bSEric Biggers };
1701e80709bSEric Biggers };
1711e80709bSEric Biggers
1721e80709bSEric Biggers enum cqhci_crypto_key_size {
1731e80709bSEric Biggers CQHCI_CRYPTO_KEY_SIZE_INVALID = 0,
1741e80709bSEric Biggers CQHCI_CRYPTO_KEY_SIZE_128 = 1,
1751e80709bSEric Biggers CQHCI_CRYPTO_KEY_SIZE_192 = 2,
1761e80709bSEric Biggers CQHCI_CRYPTO_KEY_SIZE_256 = 3,
1771e80709bSEric Biggers CQHCI_CRYPTO_KEY_SIZE_512 = 4,
1781e80709bSEric Biggers };
1791e80709bSEric Biggers
1801e80709bSEric Biggers enum cqhci_crypto_alg {
1811e80709bSEric Biggers CQHCI_CRYPTO_ALG_AES_XTS = 0,
1821e80709bSEric Biggers CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC = 1,
1831e80709bSEric Biggers CQHCI_CRYPTO_ALG_AES_ECB = 2,
1841e80709bSEric Biggers CQHCI_CRYPTO_ALG_ESSIV_AES_CBC = 3,
1851e80709bSEric Biggers };
1861e80709bSEric Biggers
1871e80709bSEric Biggers /* x-CRYPTOCAP - Crypto Capability X */
1881e80709bSEric Biggers union cqhci_crypto_cap_entry {
1891e80709bSEric Biggers __le32 reg_val;
1901e80709bSEric Biggers struct {
1911e80709bSEric Biggers u8 algorithm_id;
1921e80709bSEric Biggers u8 sdus_mask; /* Supported data unit size mask */
1931e80709bSEric Biggers u8 key_size;
1941e80709bSEric Biggers u8 reserved;
1951e80709bSEric Biggers };
1961e80709bSEric Biggers };
1971e80709bSEric Biggers
1981e80709bSEric Biggers #define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
1991e80709bSEric Biggers #define CQHCI_CRYPTO_KEY_MAX_SIZE 64
2001e80709bSEric Biggers /* x-CRYPTOCFG - Crypto Configuration X */
2011e80709bSEric Biggers union cqhci_crypto_cfg_entry {
2021e80709bSEric Biggers __le32 reg_val[32];
2031e80709bSEric Biggers struct {
2041e80709bSEric Biggers u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];
2051e80709bSEric Biggers u8 data_unit_size;
2061e80709bSEric Biggers u8 crypto_cap_idx;
2071e80709bSEric Biggers u8 reserved_1;
2081e80709bSEric Biggers u8 config_enable;
2091e80709bSEric Biggers u8 reserved_multi_host;
2101e80709bSEric Biggers u8 reserved_2;
2111e80709bSEric Biggers u8 vsb[2];
2121e80709bSEric Biggers u8 reserved_3[56];
2131e80709bSEric Biggers };
2141e80709bSEric Biggers };
2151e80709bSEric Biggers
216a4080225SVenkat Gopalakrishnan struct cqhci_host_ops;
217a4080225SVenkat Gopalakrishnan struct mmc_host;
218c46d089aSSowjanya Komatineni struct mmc_request;
219a4080225SVenkat Gopalakrishnan struct cqhci_slot;
220a4080225SVenkat Gopalakrishnan
221a4080225SVenkat Gopalakrishnan struct cqhci_host {
222a4080225SVenkat Gopalakrishnan const struct cqhci_host_ops *ops;
223a4080225SVenkat Gopalakrishnan void __iomem *mmio;
224a4080225SVenkat Gopalakrishnan struct mmc_host *mmc;
225a4080225SVenkat Gopalakrishnan
226a4080225SVenkat Gopalakrishnan spinlock_t lock;
227a4080225SVenkat Gopalakrishnan
228a4080225SVenkat Gopalakrishnan /* relative card address of device */
229a4080225SVenkat Gopalakrishnan unsigned int rca;
230a4080225SVenkat Gopalakrishnan
231a4080225SVenkat Gopalakrishnan /* 64 bit DMA */
232a4080225SVenkat Gopalakrishnan bool dma64;
233a4080225SVenkat Gopalakrishnan int num_slots;
234a4080225SVenkat Gopalakrishnan int qcnt;
235a4080225SVenkat Gopalakrishnan
236a4080225SVenkat Gopalakrishnan u32 dcmd_slot;
237a4080225SVenkat Gopalakrishnan u32 caps;
238a4080225SVenkat Gopalakrishnan #define CQHCI_TASK_DESC_SZ_128 0x1
239a4080225SVenkat Gopalakrishnan
240a4080225SVenkat Gopalakrishnan u32 quirks;
241a4080225SVenkat Gopalakrishnan #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
242a4080225SVenkat Gopalakrishnan
243a4080225SVenkat Gopalakrishnan bool enabled;
244a4080225SVenkat Gopalakrishnan bool halted;
245a4080225SVenkat Gopalakrishnan bool init_done;
246a4080225SVenkat Gopalakrishnan bool activated;
247a4080225SVenkat Gopalakrishnan bool waiting_for_idle;
248a4080225SVenkat Gopalakrishnan bool recovery_halt;
249a4080225SVenkat Gopalakrishnan
250a4080225SVenkat Gopalakrishnan size_t desc_size;
251a4080225SVenkat Gopalakrishnan size_t data_size;
252a4080225SVenkat Gopalakrishnan
253a4080225SVenkat Gopalakrishnan u8 *desc_base;
254a4080225SVenkat Gopalakrishnan
255a4080225SVenkat Gopalakrishnan /* total descriptor size */
256a4080225SVenkat Gopalakrishnan u8 slot_sz;
257a4080225SVenkat Gopalakrishnan
258a4080225SVenkat Gopalakrishnan /* 64/128 bit depends on CQHCI_CFG */
259a4080225SVenkat Gopalakrishnan u8 task_desc_len;
260a4080225SVenkat Gopalakrishnan
261a4080225SVenkat Gopalakrishnan /* 64 bit on 32-bit arch, 128 bit on 64-bit */
262a4080225SVenkat Gopalakrishnan u8 link_desc_len;
263a4080225SVenkat Gopalakrishnan
264a4080225SVenkat Gopalakrishnan u8 *trans_desc_base;
265a4080225SVenkat Gopalakrishnan /* same length as transfer descriptor */
266a4080225SVenkat Gopalakrishnan u8 trans_desc_len;
267a4080225SVenkat Gopalakrishnan
268a4080225SVenkat Gopalakrishnan dma_addr_t desc_dma_base;
269a4080225SVenkat Gopalakrishnan dma_addr_t trans_desc_dma_base;
270a4080225SVenkat Gopalakrishnan
271a4080225SVenkat Gopalakrishnan struct completion halt_comp;
272a4080225SVenkat Gopalakrishnan wait_queue_head_t wait_queue;
273a4080225SVenkat Gopalakrishnan struct cqhci_slot *slot;
2741e80709bSEric Biggers
2751e80709bSEric Biggers #ifdef CONFIG_MMC_CRYPTO
2761e80709bSEric Biggers union cqhci_crypto_capabilities crypto_capabilities;
2771e80709bSEric Biggers union cqhci_crypto_cap_entry *crypto_cap_array;
2781e80709bSEric Biggers u32 crypto_cfg_register;
2791e80709bSEric Biggers #endif
280a4080225SVenkat Gopalakrishnan };
281a4080225SVenkat Gopalakrishnan
282a4080225SVenkat Gopalakrishnan struct cqhci_host_ops {
283a4080225SVenkat Gopalakrishnan void (*dumpregs)(struct mmc_host *mmc);
284a4080225SVenkat Gopalakrishnan void (*write_l)(struct cqhci_host *host, u32 val, int reg);
285a4080225SVenkat Gopalakrishnan u32 (*read_l)(struct cqhci_host *host, int reg);
286a4080225SVenkat Gopalakrishnan void (*enable)(struct mmc_host *mmc);
287a4080225SVenkat Gopalakrishnan void (*disable)(struct mmc_host *mmc, bool recovery);
288c46d089aSSowjanya Komatineni void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
289c46d089aSSowjanya Komatineni u64 *data);
290887ba410SChun-Hung Wu void (*pre_enable)(struct mmc_host *mmc);
291887ba410SChun-Hung Wu void (*post_disable)(struct mmc_host *mmc);
2920a0c866fSEric Biggers #ifdef CONFIG_MMC_CRYPTO
2930a0c866fSEric Biggers int (*program_key)(struct cqhci_host *cq_host,
2940a0c866fSEric Biggers const union cqhci_crypto_cfg_entry *cfg, int slot);
2950a0c866fSEric Biggers #endif
296a4080225SVenkat Gopalakrishnan };
297a4080225SVenkat Gopalakrishnan
cqhci_writel(struct cqhci_host * host,u32 val,int reg)298a4080225SVenkat Gopalakrishnan static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
299a4080225SVenkat Gopalakrishnan {
300a4080225SVenkat Gopalakrishnan if (unlikely(host->ops->write_l))
301a4080225SVenkat Gopalakrishnan host->ops->write_l(host, val, reg);
302a4080225SVenkat Gopalakrishnan else
303a4080225SVenkat Gopalakrishnan writel_relaxed(val, host->mmio + reg);
304a4080225SVenkat Gopalakrishnan }
305a4080225SVenkat Gopalakrishnan
cqhci_readl(struct cqhci_host * host,int reg)306a4080225SVenkat Gopalakrishnan static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
307a4080225SVenkat Gopalakrishnan {
308a4080225SVenkat Gopalakrishnan if (unlikely(host->ops->read_l))
309a4080225SVenkat Gopalakrishnan return host->ops->read_l(host, reg);
310a4080225SVenkat Gopalakrishnan else
311a4080225SVenkat Gopalakrishnan return readl_relaxed(host->mmio + reg);
312a4080225SVenkat Gopalakrishnan }
313a4080225SVenkat Gopalakrishnan
314a4080225SVenkat Gopalakrishnan struct platform_device;
315a4080225SVenkat Gopalakrishnan
316a4080225SVenkat Gopalakrishnan irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
317a4080225SVenkat Gopalakrishnan int data_error);
318a4080225SVenkat Gopalakrishnan int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
319a4080225SVenkat Gopalakrishnan struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
3200ffa6cfbSAdrian Hunter int cqhci_deactivate(struct mmc_host *mmc);
cqhci_suspend(struct mmc_host * mmc)3210ffa6cfbSAdrian Hunter static inline int cqhci_suspend(struct mmc_host *mmc)
3220ffa6cfbSAdrian Hunter {
3230ffa6cfbSAdrian Hunter return cqhci_deactivate(mmc);
3240ffa6cfbSAdrian Hunter }
325a4080225SVenkat Gopalakrishnan int cqhci_resume(struct mmc_host *mmc);
326a4080225SVenkat Gopalakrishnan
327a4080225SVenkat Gopalakrishnan #endif
328