1 /* 2 * cb710/mmc.c 3 * 4 * Copyright by Michał Mirosław, 2008-2009 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/delay.h> 14 #include "cb710-mmc.h" 15 16 static const u8 cb710_clock_divider_log2[8] = { 17 /* 1, 2, 4, 8, 16, 32, 128, 512 */ 18 0, 1, 2, 3, 4, 5, 7, 9 19 }; 20 #define CB710_MAX_DIVIDER_IDX \ 21 (ARRAY_SIZE(cb710_clock_divider_log2) - 1) 22 23 static const u8 cb710_src_freq_mhz[16] = { 24 33, 10, 20, 25, 30, 35, 40, 45, 25 50, 55, 60, 65, 70, 75, 80, 85 26 }; 27 28 static void cb710_mmc_select_clock_divider(struct mmc_host *mmc, int hz) 29 { 30 struct cb710_slot *slot = cb710_mmc_to_slot(mmc); 31 struct pci_dev *pdev = cb710_slot_to_chip(slot)->pdev; 32 u32 src_freq_idx; 33 u32 divider_idx; 34 int src_hz; 35 36 /* on CB710 in HP nx9500: 37 * src_freq_idx == 0 38 * indexes 1-7 work as written in the table 39 * indexes 0,8-15 give no clock output 40 */ 41 pci_read_config_dword(pdev, 0x48, &src_freq_idx); 42 src_freq_idx = (src_freq_idx >> 16) & 0xF; 43 src_hz = cb710_src_freq_mhz[src_freq_idx] * 1000000; 44 45 for (divider_idx = 0; divider_idx < CB710_MAX_DIVIDER_IDX; ++divider_idx) { 46 if (hz >= src_hz >> cb710_clock_divider_log2[divider_idx]) 47 break; 48 } 49 50 if (src_freq_idx) 51 divider_idx |= 0x8; 52 else if (divider_idx == 0) 53 divider_idx = 1; 54 55 cb710_pci_update_config_reg(pdev, 0x40, ~0xF0000000, divider_idx << 28); 56 57 dev_dbg(cb710_slot_dev(slot), 58 "clock set to %d Hz, wanted %d Hz; src_freq_idx = %d, divider_idx = %d|%d\n", 59 src_hz >> cb710_clock_divider_log2[divider_idx & 7], 60 hz, src_freq_idx, divider_idx & 7, divider_idx & 8); 61 } 62 63 static void __cb710_mmc_enable_irq(struct cb710_slot *slot, 64 unsigned short enable, unsigned short mask) 65 { 66 /* clear global IE 67 * - it gets set later if any interrupt sources are enabled */ 68 mask |= CB710_MMC_IE_IRQ_ENABLE; 69 70 /* look like interrupt is fired whenever 71 * WORD[0x0C] & WORD[0x10] != 0; 72 * -> bit 15 port 0x0C seems to be global interrupt enable 73 */ 74 75 enable = (cb710_read_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT) 76 & ~mask) | enable; 77 78 if (enable) 79 enable |= CB710_MMC_IE_IRQ_ENABLE; 80 81 cb710_write_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT, enable); 82 } 83 84 static void cb710_mmc_enable_irq(struct cb710_slot *slot, 85 unsigned short enable, unsigned short mask) 86 { 87 struct cb710_mmc_reader *reader = mmc_priv(cb710_slot_to_mmc(slot)); 88 unsigned long flags; 89 90 spin_lock_irqsave(&reader->irq_lock, flags); 91 /* this is the only thing irq_lock protects */ 92 __cb710_mmc_enable_irq(slot, enable, mask); 93 spin_unlock_irqrestore(&reader->irq_lock, flags); 94 } 95 96 static void cb710_mmc_reset_events(struct cb710_slot *slot) 97 { 98 cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, 0xFF); 99 cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, 0xFF); 100 cb710_write_port_8(slot, CB710_MMC_STATUS2_PORT, 0xFF); 101 } 102 103 static void cb710_mmc_enable_4bit_data(struct cb710_slot *slot, int enable) 104 { 105 dev_dbg(cb710_slot_dev(slot), "configuring %d-data-line%s mode\n", 106 enable ? 4 : 1, enable ? "s" : ""); 107 if (enable) 108 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 109 CB710_MMC_C1_4BIT_DATA_BUS, 0); 110 else 111 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 112 0, CB710_MMC_C1_4BIT_DATA_BUS); 113 } 114 115 static int cb710_check_event(struct cb710_slot *slot, u8 what) 116 { 117 u16 status; 118 119 status = cb710_read_port_16(slot, CB710_MMC_STATUS_PORT); 120 121 if (status & CB710_MMC_S0_FIFO_UNDERFLOW) { 122 /* it is just a guess, so log it */ 123 dev_dbg(cb710_slot_dev(slot), 124 "CHECK : ignoring bit 6 in status %04X\n", status); 125 cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, 126 CB710_MMC_S0_FIFO_UNDERFLOW); 127 status &= ~CB710_MMC_S0_FIFO_UNDERFLOW; 128 } 129 130 if (status & CB710_MMC_STATUS_ERROR_EVENTS) { 131 dev_dbg(cb710_slot_dev(slot), 132 "CHECK : returning EIO on status %04X\n", status); 133 cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, status & 0xFF); 134 cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, 135 CB710_MMC_S1_RESET); 136 return -EIO; 137 } 138 139 /* 'what' is a bit in MMC_STATUS1 */ 140 if ((status >> 8) & what) { 141 cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, what); 142 return 1; 143 } 144 145 return 0; 146 } 147 148 static int cb710_wait_for_event(struct cb710_slot *slot, u8 what) 149 { 150 int err = 0; 151 unsigned limit = 2000000; /* FIXME: real timeout */ 152 153 #ifdef CONFIG_CB710_DEBUG 154 u32 e, x; 155 e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT); 156 #endif 157 158 while (!(err = cb710_check_event(slot, what))) { 159 if (!--limit) { 160 cb710_dump_regs(cb710_slot_to_chip(slot), 161 CB710_DUMP_REGS_MMC); 162 err = -ETIMEDOUT; 163 break; 164 } 165 udelay(1); 166 } 167 168 #ifdef CONFIG_CB710_DEBUG 169 x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT); 170 171 limit = 2000000 - limit; 172 if (limit > 100) 173 dev_dbg(cb710_slot_dev(slot), 174 "WAIT10: waited %d loops, what %d, entry val %08X, exit val %08X\n", 175 limit, what, e, x); 176 #endif 177 return err < 0 ? err : 0; 178 } 179 180 181 static int cb710_wait_while_busy(struct cb710_slot *slot, uint8_t mask) 182 { 183 unsigned limit = 500000; /* FIXME: real timeout */ 184 int err = 0; 185 186 #ifdef CONFIG_CB710_DEBUG 187 u32 e, x; 188 e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT); 189 #endif 190 191 while (cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & mask) { 192 if (!--limit) { 193 cb710_dump_regs(cb710_slot_to_chip(slot), 194 CB710_DUMP_REGS_MMC); 195 err = -ETIMEDOUT; 196 break; 197 } 198 udelay(1); 199 } 200 201 #ifdef CONFIG_CB710_DEBUG 202 x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT); 203 204 limit = 500000 - limit; 205 if (limit > 100) 206 dev_dbg(cb710_slot_dev(slot), 207 "WAIT12: waited %d loops, mask %02X, entry val %08X, exit val %08X\n", 208 limit, mask, e, x); 209 #endif 210 return 0; 211 } 212 213 static void cb710_mmc_set_transfer_size(struct cb710_slot *slot, 214 size_t count, size_t blocksize) 215 { 216 cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20); 217 cb710_write_port_32(slot, CB710_MMC_TRANSFER_SIZE_PORT, 218 ((count - 1) << 16)|(blocksize - 1)); 219 220 dev_vdbg(cb710_slot_dev(slot), "set up for %zu block%s of %zu bytes\n", 221 count, count == 1 ? "" : "s", blocksize); 222 } 223 224 static void cb710_mmc_fifo_hack(struct cb710_slot *slot) 225 { 226 /* without this, received data is prepended with 8-bytes of zeroes */ 227 u32 r1, r2; 228 int ok = 0; 229 230 r1 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT); 231 r2 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT); 232 if (cb710_read_port_8(slot, CB710_MMC_STATUS0_PORT) 233 & CB710_MMC_S0_FIFO_UNDERFLOW) { 234 cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, 235 CB710_MMC_S0_FIFO_UNDERFLOW); 236 ok = 1; 237 } 238 239 dev_dbg(cb710_slot_dev(slot), 240 "FIFO-read-hack: expected STATUS0 bit was %s\n", 241 ok ? "set." : "NOT SET!"); 242 dev_dbg(cb710_slot_dev(slot), 243 "FIFO-read-hack: dwords ignored: %08X %08X - %s\n", 244 r1, r2, (r1|r2) ? "BAD (NOT ZERO)!" : "ok"); 245 } 246 247 static int cb710_mmc_receive_pio(struct cb710_slot *slot, 248 struct sg_mapping_iter *miter, size_t dw_count) 249 { 250 if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & CB710_MMC_S2_FIFO_READY)) { 251 int err = cb710_wait_for_event(slot, 252 CB710_MMC_S1_PIO_TRANSFER_DONE); 253 if (err) 254 return err; 255 } 256 257 cb710_sg_dwiter_write_from_io(miter, 258 slot->iobase + CB710_MMC_DATA_PORT, dw_count); 259 260 return 0; 261 } 262 263 static bool cb710_is_transfer_size_supported(struct mmc_data *data) 264 { 265 return !(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8)); 266 } 267 268 static int cb710_mmc_receive(struct cb710_slot *slot, struct mmc_data *data) 269 { 270 struct sg_mapping_iter miter; 271 size_t len, blocks = data->blocks; 272 int err = 0; 273 274 /* TODO: I don't know how/if the hardware handles non-16B-boundary blocks 275 * except single 8B block */ 276 if (unlikely(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8))) 277 return -EINVAL; 278 279 sg_miter_start(&miter, data->sg, data->sg_len, SG_MITER_TO_SG); 280 281 cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT, 282 15, CB710_MMC_C2_READ_PIO_SIZE_MASK); 283 284 cb710_mmc_fifo_hack(slot); 285 286 while (blocks-- > 0) { 287 len = data->blksz; 288 289 while (len >= 16) { 290 err = cb710_mmc_receive_pio(slot, &miter, 4); 291 if (err) 292 goto out; 293 len -= 16; 294 } 295 296 if (!len) 297 continue; 298 299 cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT, 300 len - 1, CB710_MMC_C2_READ_PIO_SIZE_MASK); 301 302 len = (len >= 8) ? 4 : 2; 303 err = cb710_mmc_receive_pio(slot, &miter, len); 304 if (err) 305 goto out; 306 } 307 out: 308 sg_miter_stop(&miter); 309 return err; 310 } 311 312 static int cb710_mmc_send(struct cb710_slot *slot, struct mmc_data *data) 313 { 314 struct sg_mapping_iter miter; 315 size_t len, blocks = data->blocks; 316 int err = 0; 317 318 /* TODO: I don't know how/if the hardware handles multiple 319 * non-16B-boundary blocks */ 320 if (unlikely(data->blocks > 1 && data->blksz & 15)) 321 return -EINVAL; 322 323 sg_miter_start(&miter, data->sg, data->sg_len, SG_MITER_FROM_SG); 324 325 cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT, 326 0, CB710_MMC_C2_READ_PIO_SIZE_MASK); 327 328 while (blocks-- > 0) { 329 len = (data->blksz + 15) >> 4; 330 do { 331 if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) 332 & CB710_MMC_S2_FIFO_EMPTY)) { 333 err = cb710_wait_for_event(slot, 334 CB710_MMC_S1_PIO_TRANSFER_DONE); 335 if (err) 336 goto out; 337 } 338 cb710_sg_dwiter_read_to_io(&miter, 339 slot->iobase + CB710_MMC_DATA_PORT, 4); 340 } while (--len); 341 } 342 out: 343 sg_miter_stop(&miter); 344 return err; 345 } 346 347 static u16 cb710_encode_cmd_flags(struct cb710_mmc_reader *reader, 348 struct mmc_command *cmd) 349 { 350 unsigned int flags = cmd->flags; 351 u16 cb_flags = 0; 352 353 /* Windows driver returned 0 for commands for which no response 354 * is expected. It happened that there were only two such commands 355 * used: MMC_GO_IDLE_STATE and MMC_GO_INACTIVE_STATE so it might 356 * as well be a bug in that driver. 357 * 358 * Original driver set bit 14 for MMC/SD application 359 * commands. There's no difference 'on the wire' and 360 * it apparently works without it anyway. 361 */ 362 363 switch (flags & MMC_CMD_MASK) { 364 case MMC_CMD_AC: cb_flags = CB710_MMC_CMD_AC; break; 365 case MMC_CMD_ADTC: cb_flags = CB710_MMC_CMD_ADTC; break; 366 case MMC_CMD_BC: cb_flags = CB710_MMC_CMD_BC; break; 367 case MMC_CMD_BCR: cb_flags = CB710_MMC_CMD_BCR; break; 368 } 369 370 if (flags & MMC_RSP_BUSY) 371 cb_flags |= CB710_MMC_RSP_BUSY; 372 373 cb_flags |= cmd->opcode << CB710_MMC_CMD_CODE_SHIFT; 374 375 if (cmd->data && (cmd->data->flags & MMC_DATA_READ)) 376 cb_flags |= CB710_MMC_DATA_READ; 377 378 if (flags & MMC_RSP_PRESENT) { 379 /* Windows driver set 01 at bits 4,3 except for 380 * MMC_SET_BLOCKLEN where it set 10. Maybe the 381 * hardware can do something special about this 382 * command? The original driver looks buggy/incomplete 383 * anyway so we ignore this for now. 384 * 385 * I assume that 00 here means no response is expected. 386 */ 387 cb_flags |= CB710_MMC_RSP_PRESENT; 388 389 if (flags & MMC_RSP_136) 390 cb_flags |= CB710_MMC_RSP_136; 391 if (!(flags & MMC_RSP_CRC)) 392 cb_flags |= CB710_MMC_RSP_NO_CRC; 393 } 394 395 return cb_flags; 396 } 397 398 static void cb710_receive_response(struct cb710_slot *slot, 399 struct mmc_command *cmd) 400 { 401 unsigned rsp_opcode, wanted_opcode; 402 403 /* Looks like final byte with CRC is always stripped (same as SDHCI) */ 404 if (cmd->flags & MMC_RSP_136) { 405 u32 resp[4]; 406 407 resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE3_PORT); 408 resp[1] = cb710_read_port_32(slot, CB710_MMC_RESPONSE2_PORT); 409 resp[2] = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT); 410 resp[3] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT); 411 rsp_opcode = resp[0] >> 24; 412 413 cmd->resp[0] = (resp[0] << 8)|(resp[1] >> 24); 414 cmd->resp[1] = (resp[1] << 8)|(resp[2] >> 24); 415 cmd->resp[2] = (resp[2] << 8)|(resp[3] >> 24); 416 cmd->resp[3] = (resp[3] << 8); 417 } else { 418 rsp_opcode = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT) & 0x3F; 419 cmd->resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT); 420 } 421 422 wanted_opcode = (cmd->flags & MMC_RSP_OPCODE) ? cmd->opcode : 0x3F; 423 if (rsp_opcode != wanted_opcode) 424 cmd->error = -EILSEQ; 425 } 426 427 static int cb710_mmc_transfer_data(struct cb710_slot *slot, 428 struct mmc_data *data) 429 { 430 int error, to; 431 432 if (data->flags & MMC_DATA_READ) 433 error = cb710_mmc_receive(slot, data); 434 else 435 error = cb710_mmc_send(slot, data); 436 437 to = cb710_wait_for_event(slot, CB710_MMC_S1_DATA_TRANSFER_DONE); 438 if (!error) 439 error = to; 440 441 if (!error) 442 data->bytes_xfered = data->blksz * data->blocks; 443 return error; 444 } 445 446 static int cb710_mmc_command(struct mmc_host *mmc, struct mmc_command *cmd) 447 { 448 struct cb710_slot *slot = cb710_mmc_to_slot(mmc); 449 struct cb710_mmc_reader *reader = mmc_priv(mmc); 450 struct mmc_data *data = cmd->data; 451 452 u16 cb_cmd = cb710_encode_cmd_flags(reader, cmd); 453 dev_dbg(cb710_slot_dev(slot), "cmd request: 0x%04X\n", cb_cmd); 454 455 if (data) { 456 if (!cb710_is_transfer_size_supported(data)) { 457 data->error = -EINVAL; 458 return -1; 459 } 460 cb710_mmc_set_transfer_size(slot, data->blocks, data->blksz); 461 } 462 463 cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20|CB710_MMC_S2_BUSY_10); 464 cb710_write_port_16(slot, CB710_MMC_CMD_TYPE_PORT, cb_cmd); 465 cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20); 466 cb710_write_port_32(slot, CB710_MMC_CMD_PARAM_PORT, cmd->arg); 467 cb710_mmc_reset_events(slot); 468 cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20); 469 cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x01, 0); 470 471 cmd->error = cb710_wait_for_event(slot, CB710_MMC_S1_COMMAND_SENT); 472 if (cmd->error) 473 return -1; 474 475 if (cmd->flags & MMC_RSP_PRESENT) { 476 cb710_receive_response(slot, cmd); 477 if (cmd->error) 478 return -1; 479 } 480 481 if (data) 482 data->error = cb710_mmc_transfer_data(slot, data); 483 return 0; 484 } 485 486 static void cb710_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 487 { 488 struct cb710_slot *slot = cb710_mmc_to_slot(mmc); 489 struct cb710_mmc_reader *reader = mmc_priv(mmc); 490 491 WARN_ON(reader->mrq != NULL); 492 493 reader->mrq = mrq; 494 cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0); 495 496 if (!cb710_mmc_command(mmc, mrq->cmd) && mrq->stop) 497 cb710_mmc_command(mmc, mrq->stop); 498 499 tasklet_schedule(&reader->finish_req_tasklet); 500 } 501 502 static int cb710_mmc_powerup(struct cb710_slot *slot) 503 { 504 #ifdef CONFIG_CB710_DEBUG 505 struct cb710_chip *chip = cb710_slot_to_chip(slot); 506 #endif 507 int err; 508 509 /* a lot of magic for now */ 510 dev_dbg(cb710_slot_dev(slot), "bus powerup\n"); 511 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 512 err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20); 513 if (unlikely(err)) 514 return err; 515 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x80, 0); 516 cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x80, 0); 517 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 518 mdelay(1); 519 dev_dbg(cb710_slot_dev(slot), "after delay 1\n"); 520 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 521 err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20); 522 if (unlikely(err)) 523 return err; 524 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x09, 0); 525 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 526 mdelay(1); 527 dev_dbg(cb710_slot_dev(slot), "after delay 2\n"); 528 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 529 err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20); 530 if (unlikely(err)) 531 return err; 532 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x08); 533 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 534 mdelay(2); 535 dev_dbg(cb710_slot_dev(slot), "after delay 3\n"); 536 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 537 cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0); 538 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x70, 0); 539 cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT, 0x80, 0); 540 cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x03, 0); 541 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 542 err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20); 543 if (unlikely(err)) 544 return err; 545 /* This port behaves weird: quick byte reads of 0x08,0x09 return 546 * 0xFF,0x00 after writing 0xFFFF to 0x08; it works correctly when 547 * read/written from userspace... What am I missing here? 548 * (it doesn't depend on write-to-read delay) */ 549 cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0xFFFF); 550 cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0); 551 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 552 dev_dbg(cb710_slot_dev(slot), "bus powerup finished\n"); 553 554 return cb710_check_event(slot, 0); 555 } 556 557 static void cb710_mmc_powerdown(struct cb710_slot *slot) 558 { 559 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x81); 560 cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0, 0x80); 561 } 562 563 static void cb710_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 564 { 565 struct cb710_slot *slot = cb710_mmc_to_slot(mmc); 566 struct cb710_mmc_reader *reader = mmc_priv(mmc); 567 int err; 568 569 cb710_mmc_select_clock_divider(mmc, ios->clock); 570 571 if (ios->power_mode != reader->last_power_mode) 572 switch (ios->power_mode) { 573 case MMC_POWER_ON: 574 err = cb710_mmc_powerup(slot); 575 if (err) { 576 dev_warn(cb710_slot_dev(slot), 577 "powerup failed (%d)- retrying\n", err); 578 cb710_mmc_powerdown(slot); 579 udelay(1); 580 err = cb710_mmc_powerup(slot); 581 if (err) 582 dev_warn(cb710_slot_dev(slot), 583 "powerup retry failed (%d) - expect errors\n", 584 err); 585 } 586 reader->last_power_mode = MMC_POWER_ON; 587 break; 588 case MMC_POWER_OFF: 589 cb710_mmc_powerdown(slot); 590 reader->last_power_mode = MMC_POWER_OFF; 591 break; 592 case MMC_POWER_UP: 593 default: 594 /* ignore */; 595 } 596 597 cb710_mmc_enable_4bit_data(slot, ios->bus_width != MMC_BUS_WIDTH_1); 598 599 cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0); 600 } 601 602 static int cb710_mmc_get_ro(struct mmc_host *mmc) 603 { 604 struct cb710_slot *slot = cb710_mmc_to_slot(mmc); 605 606 return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT) 607 & CB710_MMC_S3_WRITE_PROTECTED; 608 } 609 610 static int cb710_mmc_get_cd(struct mmc_host *mmc) 611 { 612 struct cb710_slot *slot = cb710_mmc_to_slot(mmc); 613 614 return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT) 615 & CB710_MMC_S3_CARD_DETECTED; 616 } 617 618 static int cb710_mmc_irq_handler(struct cb710_slot *slot) 619 { 620 struct mmc_host *mmc = cb710_slot_to_mmc(slot); 621 struct cb710_mmc_reader *reader = mmc_priv(mmc); 622 u32 status, config1, config2, irqen; 623 624 status = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT); 625 irqen = cb710_read_port_32(slot, CB710_MMC_IRQ_ENABLE_PORT); 626 config2 = cb710_read_port_32(slot, CB710_MMC_CONFIGB_PORT); 627 config1 = cb710_read_port_32(slot, CB710_MMC_CONFIG_PORT); 628 629 dev_dbg(cb710_slot_dev(slot), "interrupt; status: %08X, " 630 "ie: %08X, c2: %08X, c1: %08X\n", 631 status, irqen, config2, config1); 632 633 if (status & (CB710_MMC_S1_CARD_CHANGED << 8)) { 634 /* ack the event */ 635 cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, 636 CB710_MMC_S1_CARD_CHANGED); 637 if ((irqen & CB710_MMC_IE_CISTATUS_MASK) 638 == CB710_MMC_IE_CISTATUS_MASK) 639 mmc_detect_change(mmc, HZ/5); 640 } else { 641 dev_dbg(cb710_slot_dev(slot), "unknown interrupt (test)\n"); 642 spin_lock(&reader->irq_lock); 643 __cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_TEST_MASK); 644 spin_unlock(&reader->irq_lock); 645 } 646 647 return 1; 648 } 649 650 static void cb710_mmc_finish_request_tasklet(unsigned long data) 651 { 652 struct mmc_host *mmc = (void *)data; 653 struct cb710_mmc_reader *reader = mmc_priv(mmc); 654 struct mmc_request *mrq = reader->mrq; 655 656 reader->mrq = NULL; 657 mmc_request_done(mmc, mrq); 658 } 659 660 static const struct mmc_host_ops cb710_mmc_host = { 661 .request = cb710_mmc_request, 662 .set_ios = cb710_mmc_set_ios, 663 .get_ro = cb710_mmc_get_ro, 664 .get_cd = cb710_mmc_get_cd, 665 }; 666 667 #ifdef CONFIG_PM 668 669 static int cb710_mmc_suspend(struct platform_device *pdev, pm_message_t state) 670 { 671 struct cb710_slot *slot = cb710_pdev_to_slot(pdev); 672 struct mmc_host *mmc = cb710_slot_to_mmc(slot); 673 int err; 674 675 err = mmc_suspend_host(mmc); 676 if (err) 677 return err; 678 679 cb710_mmc_enable_irq(slot, 0, ~0); 680 return 0; 681 } 682 683 static int cb710_mmc_resume(struct platform_device *pdev) 684 { 685 struct cb710_slot *slot = cb710_pdev_to_slot(pdev); 686 struct mmc_host *mmc = cb710_slot_to_mmc(slot); 687 688 cb710_mmc_enable_irq(slot, 0, ~0); 689 690 return mmc_resume_host(mmc); 691 } 692 693 #endif /* CONFIG_PM */ 694 695 static int __devinit cb710_mmc_init(struct platform_device *pdev) 696 { 697 struct cb710_slot *slot = cb710_pdev_to_slot(pdev); 698 struct cb710_chip *chip = cb710_slot_to_chip(slot); 699 struct mmc_host *mmc; 700 struct cb710_mmc_reader *reader; 701 int err; 702 u32 val; 703 704 mmc = mmc_alloc_host(sizeof(*reader), cb710_slot_dev(slot)); 705 if (!mmc) 706 return -ENOMEM; 707 708 dev_set_drvdata(&pdev->dev, mmc); 709 710 /* harmless (maybe) magic */ 711 pci_read_config_dword(chip->pdev, 0x48, &val); 712 val = cb710_src_freq_mhz[(val >> 16) & 0xF]; 713 dev_dbg(cb710_slot_dev(slot), "source frequency: %dMHz\n", val); 714 val *= 1000000; 715 716 mmc->ops = &cb710_mmc_host; 717 mmc->f_max = val; 718 mmc->f_min = val >> cb710_clock_divider_log2[CB710_MAX_DIVIDER_IDX]; 719 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; 720 mmc->caps = MMC_CAP_4_BIT_DATA; 721 722 reader = mmc_priv(mmc); 723 724 tasklet_init(&reader->finish_req_tasklet, 725 cb710_mmc_finish_request_tasklet, (unsigned long)mmc); 726 spin_lock_init(&reader->irq_lock); 727 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC); 728 729 cb710_mmc_enable_irq(slot, 0, ~0); 730 cb710_set_irq_handler(slot, cb710_mmc_irq_handler); 731 732 err = mmc_add_host(mmc); 733 if (unlikely(err)) 734 goto err_free_mmc; 735 736 dev_dbg(cb710_slot_dev(slot), "mmc_hostname is %s\n", 737 mmc_hostname(mmc)); 738 739 cb710_mmc_enable_irq(slot, CB710_MMC_IE_CARD_INSERTION_STATUS, 0); 740 741 return 0; 742 743 err_free_mmc: 744 dev_dbg(cb710_slot_dev(slot), "mmc_add_host() failed: %d\n", err); 745 746 cb710_set_irq_handler(slot, NULL); 747 mmc_free_host(mmc); 748 return err; 749 } 750 751 static int __devexit cb710_mmc_exit(struct platform_device *pdev) 752 { 753 struct cb710_slot *slot = cb710_pdev_to_slot(pdev); 754 struct mmc_host *mmc = cb710_slot_to_mmc(slot); 755 struct cb710_mmc_reader *reader = mmc_priv(mmc); 756 757 cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_CARD_INSERTION_STATUS); 758 759 mmc_remove_host(mmc); 760 761 /* IRQs should be disabled now, but let's stay on the safe side */ 762 cb710_mmc_enable_irq(slot, 0, ~0); 763 cb710_set_irq_handler(slot, NULL); 764 765 /* clear config ports - just in case */ 766 cb710_write_port_32(slot, CB710_MMC_CONFIG_PORT, 0); 767 cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0); 768 769 tasklet_kill(&reader->finish_req_tasklet); 770 771 mmc_free_host(mmc); 772 return 0; 773 } 774 775 static struct platform_driver cb710_mmc_driver = { 776 .driver.name = "cb710-mmc", 777 .probe = cb710_mmc_init, 778 .remove = __devexit_p(cb710_mmc_exit), 779 #ifdef CONFIG_PM 780 .suspend = cb710_mmc_suspend, 781 .resume = cb710_mmc_resume, 782 #endif 783 }; 784 785 static int __init cb710_mmc_init_module(void) 786 { 787 return platform_driver_register(&cb710_mmc_driver); 788 } 789 790 static void __exit cb710_mmc_cleanup_module(void) 791 { 792 platform_driver_unregister(&cb710_mmc_driver); 793 } 794 795 module_init(cb710_mmc_init_module); 796 module_exit(cb710_mmc_cleanup_module); 797 798 MODULE_AUTHOR("Michał Mirosław <mirq-linux@rere.qmqm.pl>"); 799 MODULE_DESCRIPTION("ENE CB710 memory card reader driver - MMC/SD part"); 800 MODULE_LICENSE("GPL"); 801 MODULE_ALIAS("platform:cb710-mmc"); 802