1ba3869ffSJan Glauber /* 2ba3869ffSJan Glauber * Driver for MMC and SSD cards for Cavium OCTEON and ThunderX SOCs. 3ba3869ffSJan Glauber * 4ba3869ffSJan Glauber * This file is subject to the terms and conditions of the GNU General Public 5ba3869ffSJan Glauber * License. See the file "COPYING" in the main directory of this archive 6ba3869ffSJan Glauber * for more details. 7ba3869ffSJan Glauber * 8ba3869ffSJan Glauber * Copyright (C) 2012-2017 Cavium Inc. 9ba3869ffSJan Glauber */ 10ba3869ffSJan Glauber 11ba3869ffSJan Glauber #ifndef _CAVIUM_MMC_H_ 12ba3869ffSJan Glauber #define _CAVIUM_MMC_H_ 13ba3869ffSJan Glauber 14ba3869ffSJan Glauber #include <linux/bitops.h> 15ba3869ffSJan Glauber #include <linux/clk.h> 16ba3869ffSJan Glauber #include <linux/gpio/consumer.h> 17ba3869ffSJan Glauber #include <linux/io.h> 18ba3869ffSJan Glauber #include <linux/mmc/host.h> 19ba3869ffSJan Glauber #include <linux/of.h> 20ba3869ffSJan Glauber #include <linux/scatterlist.h> 21ba3869ffSJan Glauber #include <linux/semaphore.h> 22ba3869ffSJan Glauber 23ba3869ffSJan Glauber #define CAVIUM_MAX_MMC 4 24ba3869ffSJan Glauber 25ba3869ffSJan Glauber /* DMA register addresses */ 26ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG(x) (0x00 + x->reg_off_dma) 27ba3869ffSJan Glauber 28ba3869ffSJan Glauber /* register addresses */ 29ba3869ffSJan Glauber #define MIO_EMM_CFG(x) (0x00 + x->reg_off) 30ba3869ffSJan Glauber #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off) 31ba3869ffSJan Glauber #define MIO_EMM_DMA(x) (0x50 + x->reg_off) 32ba3869ffSJan Glauber #define MIO_EMM_CMD(x) (0x58 + x->reg_off) 33ba3869ffSJan Glauber #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off) 34ba3869ffSJan Glauber #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off) 35ba3869ffSJan Glauber #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off) 36ba3869ffSJan Glauber #define MIO_EMM_INT(x) (0x78 + x->reg_off) 37ba3869ffSJan Glauber #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off) 38ba3869ffSJan Glauber #define MIO_EMM_WDOG(x) (0x88 + x->reg_off) 39ba3869ffSJan Glauber #define MIO_EMM_SAMPLE(x) (0x90 + x->reg_off) 40ba3869ffSJan Glauber #define MIO_EMM_STS_MASK(x) (0x98 + x->reg_off) 41ba3869ffSJan Glauber #define MIO_EMM_RCA(x) (0xa0 + x->reg_off) 42ba3869ffSJan Glauber #define MIO_EMM_BUF_IDX(x) (0xe0 + x->reg_off) 43ba3869ffSJan Glauber #define MIO_EMM_BUF_DAT(x) (0xe8 + x->reg_off) 44ba3869ffSJan Glauber 45ba3869ffSJan Glauber struct cvm_mmc_host { 46ba3869ffSJan Glauber struct device *dev; 47ba3869ffSJan Glauber void __iomem *base; 48ba3869ffSJan Glauber void __iomem *dma_base; 49ba3869ffSJan Glauber int reg_off; 50ba3869ffSJan Glauber int reg_off_dma; 51ba3869ffSJan Glauber u64 emm_cfg; 52ba3869ffSJan Glauber u64 n_minus_one; /* OCTEON II workaround location */ 53ba3869ffSJan Glauber int last_slot; 54ba3869ffSJan Glauber struct clk *clk; 55ba3869ffSJan Glauber int sys_freq; 56ba3869ffSJan Glauber 57ba3869ffSJan Glauber struct mmc_request *current_req; 58ba3869ffSJan Glauber struct sg_mapping_iter smi; 59ba3869ffSJan Glauber bool dma_active; 60ba3869ffSJan Glauber 61ba3869ffSJan Glauber bool has_ciu3; 62ba3869ffSJan Glauber bool big_dma_addr; 63ba3869ffSJan Glauber bool need_irq_handler_lock; 64ba3869ffSJan Glauber spinlock_t irq_handler_lock; 65ba3869ffSJan Glauber struct semaphore mmc_serializer; 66ba3869ffSJan Glauber 67ba3869ffSJan Glauber struct gpio_desc *global_pwr_gpiod; 68ba3869ffSJan Glauber atomic_t shared_power_users; 69ba3869ffSJan Glauber 70ba3869ffSJan Glauber struct cvm_mmc_slot *slot[CAVIUM_MAX_MMC]; 71ba3869ffSJan Glauber struct platform_device *slot_pdev[CAVIUM_MAX_MMC]; 72ba3869ffSJan Glauber 73ba3869ffSJan Glauber void (*set_shared_power)(struct cvm_mmc_host *, int); 74ba3869ffSJan Glauber void (*acquire_bus)(struct cvm_mmc_host *); 75ba3869ffSJan Glauber void (*release_bus)(struct cvm_mmc_host *); 76ba3869ffSJan Glauber void (*int_enable)(struct cvm_mmc_host *, u64); 77ba3869ffSJan Glauber /* required on some MIPS models */ 78ba3869ffSJan Glauber void (*dmar_fixup)(struct cvm_mmc_host *, struct mmc_command *, 79ba3869ffSJan Glauber struct mmc_data *, u64); 80ba3869ffSJan Glauber void (*dmar_fixup_done)(struct cvm_mmc_host *); 81ba3869ffSJan Glauber }; 82ba3869ffSJan Glauber 83ba3869ffSJan Glauber struct cvm_mmc_slot { 84ba3869ffSJan Glauber struct mmc_host *mmc; /* slot-level mmc_core object */ 85ba3869ffSJan Glauber struct cvm_mmc_host *host; /* common hw for all slots */ 86ba3869ffSJan Glauber 87ba3869ffSJan Glauber u64 clock; 88ba3869ffSJan Glauber 89ba3869ffSJan Glauber u64 cached_switch; 90ba3869ffSJan Glauber u64 cached_rca; 91ba3869ffSJan Glauber 92ba3869ffSJan Glauber unsigned int cmd_cnt; /* sample delay */ 93ba3869ffSJan Glauber unsigned int dat_cnt; /* sample delay */ 94ba3869ffSJan Glauber 95ba3869ffSJan Glauber int bus_id; 96ba3869ffSJan Glauber }; 97ba3869ffSJan Glauber 98ba3869ffSJan Glauber struct cvm_mmc_cr_type { 99ba3869ffSJan Glauber u8 ctype; 100ba3869ffSJan Glauber u8 rtype; 101ba3869ffSJan Glauber }; 102ba3869ffSJan Glauber 103ba3869ffSJan Glauber struct cvm_mmc_cr_mods { 104ba3869ffSJan Glauber u8 ctype_xor; 105ba3869ffSJan Glauber u8 rtype_xor; 106ba3869ffSJan Glauber }; 107ba3869ffSJan Glauber 108ba3869ffSJan Glauber /* Bitfield definitions */ 109ba3869ffSJan Glauber #define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62) 110ba3869ffSJan Glauber #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60) 111ba3869ffSJan Glauber #define MIO_EMM_CMD_VAL BIT_ULL(59) 112ba3869ffSJan Glauber #define MIO_EMM_CMD_DBUF BIT_ULL(55) 113ba3869ffSJan Glauber #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49) 114ba3869ffSJan Glauber #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41) 115ba3869ffSJan Glauber #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38) 116ba3869ffSJan Glauber #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32) 117ba3869ffSJan Glauber #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0) 118ba3869ffSJan Glauber 119ba3869ffSJan Glauber #define MIO_EMM_DMA_SKIP_BUSY BIT_ULL(62) 120ba3869ffSJan Glauber #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60) 121ba3869ffSJan Glauber #define MIO_EMM_DMA_VAL BIT_ULL(59) 122ba3869ffSJan Glauber #define MIO_EMM_DMA_SECTOR BIT_ULL(58) 123ba3869ffSJan Glauber #define MIO_EMM_DMA_DAT_NULL BIT_ULL(57) 124ba3869ffSJan Glauber #define MIO_EMM_DMA_THRES GENMASK_ULL(56, 51) 125ba3869ffSJan Glauber #define MIO_EMM_DMA_REL_WR BIT_ULL(50) 126ba3869ffSJan Glauber #define MIO_EMM_DMA_RW BIT_ULL(49) 127ba3869ffSJan Glauber #define MIO_EMM_DMA_MULTI BIT_ULL(48) 128ba3869ffSJan Glauber #define MIO_EMM_DMA_BLOCK_CNT GENMASK_ULL(47, 32) 129ba3869ffSJan Glauber #define MIO_EMM_DMA_CARD_ADDR GENMASK_ULL(31, 0) 130ba3869ffSJan Glauber 131ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_EN BIT_ULL(63) 132ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_RW BIT_ULL(62) 133ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_CLR BIT_ULL(61) 134ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_SWAP32 BIT_ULL(59) 135ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_SWAP16 BIT_ULL(58) 136ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_SWAP8 BIT_ULL(57) 137ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_ENDIAN BIT_ULL(56) 138ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_SIZE GENMASK_ULL(55, 36) 139ba3869ffSJan Glauber #define MIO_EMM_DMA_CFG_ADR GENMASK_ULL(35, 0) 140ba3869ffSJan Glauber 141ba3869ffSJan Glauber #define MIO_EMM_INT_SWITCH_ERR BIT_ULL(6) 142ba3869ffSJan Glauber #define MIO_EMM_INT_SWITCH_DONE BIT_ULL(5) 143ba3869ffSJan Glauber #define MIO_EMM_INT_DMA_ERR BIT_ULL(4) 144ba3869ffSJan Glauber #define MIO_EMM_INT_CMD_ERR BIT_ULL(3) 145ba3869ffSJan Glauber #define MIO_EMM_INT_DMA_DONE BIT_ULL(2) 146ba3869ffSJan Glauber #define MIO_EMM_INT_CMD_DONE BIT_ULL(1) 147ba3869ffSJan Glauber #define MIO_EMM_INT_BUF_DONE BIT_ULL(0) 148ba3869ffSJan Glauber 149ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_BUS_ID GENMASK_ULL(61, 60) 150ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_CMD_VAL BIT_ULL(59) 151ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_SWITCH_VAL BIT_ULL(58) 152ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_DMA_VAL BIT_ULL(57) 153ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_DMA_PEND BIT_ULL(56) 154ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_DBUF_ERR BIT_ULL(28) 155ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_DBUF BIT_ULL(23) 156ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_BLK_TIMEOUT BIT_ULL(22) 157ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_BLK_CRC_ERR BIT_ULL(21) 158ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_RSP_BUSYBIT BIT_ULL(20) 159ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_STP_TIMEOUT BIT_ULL(19) 160ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_STP_CRC_ERR BIT_ULL(18) 161ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_STP_BAD_STS BIT_ULL(17) 162ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_STP_VAL BIT_ULL(16) 163ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_RSP_TIMEOUT BIT_ULL(15) 164ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_RSP_CRC_ERR BIT_ULL(14) 165ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_RSP_BAD_STS BIT_ULL(13) 166ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_RSP_VAL BIT_ULL(12) 167ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_RSP_TYPE GENMASK_ULL(11, 9) 168ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_CMD_TYPE GENMASK_ULL(8, 7) 169ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_CMD_IDX GENMASK_ULL(6, 1) 170ba3869ffSJan Glauber #define MIO_EMM_RSP_STS_CMD_DONE BIT_ULL(0) 171ba3869ffSJan Glauber 172ba3869ffSJan Glauber #define MIO_EMM_SAMPLE_CMD_CNT GENMASK_ULL(25, 16) 173ba3869ffSJan Glauber #define MIO_EMM_SAMPLE_DAT_CNT GENMASK_ULL(9, 0) 174ba3869ffSJan Glauber 175ba3869ffSJan Glauber #define MIO_EMM_SWITCH_BUS_ID GENMASK_ULL(61, 60) 176ba3869ffSJan Glauber #define MIO_EMM_SWITCH_EXE BIT_ULL(59) 177ba3869ffSJan Glauber #define MIO_EMM_SWITCH_ERR0 BIT_ULL(58) 178ba3869ffSJan Glauber #define MIO_EMM_SWITCH_ERR1 BIT_ULL(57) 179ba3869ffSJan Glauber #define MIO_EMM_SWITCH_ERR2 BIT_ULL(56) 180ba3869ffSJan Glauber #define MIO_EMM_SWITCH_HS_TIMING BIT_ULL(48) 181ba3869ffSJan Glauber #define MIO_EMM_SWITCH_BUS_WIDTH GENMASK_ULL(42, 40) 182ba3869ffSJan Glauber #define MIO_EMM_SWITCH_POWER_CLASS GENMASK_ULL(35, 32) 183ba3869ffSJan Glauber #define MIO_EMM_SWITCH_CLK_HI GENMASK_ULL(31, 16) 184ba3869ffSJan Glauber #define MIO_EMM_SWITCH_CLK_LO GENMASK_ULL(15, 0) 185ba3869ffSJan Glauber 186ba3869ffSJan Glauber /* Protoypes */ 187ba3869ffSJan Glauber irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id); 188ba3869ffSJan Glauber int cvm_mmc_of_slot_probe(struct device *dev, struct cvm_mmc_host *host); 189ba3869ffSJan Glauber int cvm_mmc_of_slot_remove(struct cvm_mmc_slot *slot); 190ba3869ffSJan Glauber extern const char *cvm_mmc_irq_names[]; 191ba3869ffSJan Glauber 192ba3869ffSJan Glauber #endif 193