11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (c) 2005, Advanced Micro Devices, Inc. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * Developed with help from the 2.4.30 MMC AU1XXX controller including 71c6a0718SPierre Ossman * the following copyright notices: 81c6a0718SPierre Ossman * Copyright (c) 2003-2004 Embedded Edge, LLC. 91c6a0718SPierre Ossman * Portions Copyright (C) 2002 Embedix, Inc 101c6a0718SPierre Ossman * Copyright 2002 Hewlett-Packard Company 111c6a0718SPierre Ossman 121c6a0718SPierre Ossman * 2.6 version of this driver inspired by: 131c6a0718SPierre Ossman * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, 141c6a0718SPierre Ossman * All Rights Reserved. 151c6a0718SPierre Ossman * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, 161c6a0718SPierre Ossman * All Rights Reserved. 171c6a0718SPierre Ossman * 181c6a0718SPierre Ossman 191c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 201c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 211c6a0718SPierre Ossman * published by the Free Software Foundation. 221c6a0718SPierre Ossman */ 231c6a0718SPierre Ossman 24e2d26477SManuel Lauss /* Why don't we use the SD controllers' carddetect feature? 251c6a0718SPierre Ossman * 261c6a0718SPierre Ossman * From the AU1100 MMC application guide: 271c6a0718SPierre Ossman * If the Au1100-based design is intended to support both MultiMediaCards 281c6a0718SPierre Ossman * and 1- or 4-data bit SecureDigital cards, then the solution is to 291c6a0718SPierre Ossman * connect a weak (560KOhm) pull-up resistor to connector pin 1. 301c6a0718SPierre Ossman * In doing so, a MMC card never enters SPI-mode communications, 311c6a0718SPierre Ossman * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective 321c6a0718SPierre Ossman * (the low to high transition will not occur). 331c6a0718SPierre Ossman */ 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #include <linux/module.h> 361c6a0718SPierre Ossman #include <linux/init.h> 371c6a0718SPierre Ossman #include <linux/platform_device.h> 381c6a0718SPierre Ossman #include <linux/mm.h> 391c6a0718SPierre Ossman #include <linux/interrupt.h> 401c6a0718SPierre Ossman #include <linux/dma-mapping.h> 410ada7a02SAl Viro #include <linux/scatterlist.h> 42c4223c2cSManuel Lauss #include <linux/leds.h> 431c6a0718SPierre Ossman #include <linux/mmc/host.h> 44c4223c2cSManuel Lauss 451c6a0718SPierre Ossman #include <asm/io.h> 461c6a0718SPierre Ossman #include <asm/mach-au1x00/au1000.h> 471c6a0718SPierre Ossman #include <asm/mach-au1x00/au1xxx_dbdma.h> 481c6a0718SPierre Ossman #include <asm/mach-au1x00/au1100_mmc.h> 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman #define DRIVER_NAME "au1xxx-mmc" 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman /* Set this to enable special debugging macros */ 53c4223c2cSManuel Lauss /* #define DEBUG */ 541c6a0718SPierre Ossman 551c6a0718SPierre Ossman #ifdef DEBUG 565c0a889dSManuel Lauss #define DBG(fmt, idx, args...) \ 575c0a889dSManuel Lauss printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args) 581c6a0718SPierre Ossman #else 595c0a889dSManuel Lauss #define DBG(fmt, idx, args...) do {} while (0) 601c6a0718SPierre Ossman #endif 611c6a0718SPierre Ossman 625c0a889dSManuel Lauss /* Hardware definitions */ 635c0a889dSManuel Lauss #define AU1XMMC_DESCRIPTOR_COUNT 1 645c0a889dSManuel Lauss #define AU1XMMC_DESCRIPTOR_SIZE 2048 655c0a889dSManuel Lauss 665c0a889dSManuel Lauss #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ 675c0a889dSManuel Lauss MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ 685c0a889dSManuel Lauss MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) 695c0a889dSManuel Lauss 705c0a889dSManuel Lauss /* This gives us a hard value for the stop command that we can write directly 715c0a889dSManuel Lauss * to the command register. 725c0a889dSManuel Lauss */ 735c0a889dSManuel Lauss #define STOP_CMD \ 745c0a889dSManuel Lauss (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO) 755c0a889dSManuel Lauss 765c0a889dSManuel Lauss /* This is the set of interrupts that we configure by default. */ 775c0a889dSManuel Lauss #define AU1XMMC_INTERRUPTS \ 785c0a889dSManuel Lauss (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \ 795c0a889dSManuel Lauss SD_CONFIG_CR | SD_CONFIG_I) 805c0a889dSManuel Lauss 815c0a889dSManuel Lauss /* The poll event (looking for insert/remove events runs twice a second. */ 825c0a889dSManuel Lauss #define AU1XMMC_DETECT_TIMEOUT (HZ/2) 835c0a889dSManuel Lauss 845c0a889dSManuel Lauss struct au1xmmc_host { 855c0a889dSManuel Lauss struct mmc_host *mmc; 865c0a889dSManuel Lauss struct mmc_request *mrq; 875c0a889dSManuel Lauss 885c0a889dSManuel Lauss u32 flags; 895c0a889dSManuel Lauss u32 iobase; 905c0a889dSManuel Lauss u32 clock; 915c0a889dSManuel Lauss u32 bus_width; 925c0a889dSManuel Lauss u32 power_mode; 935c0a889dSManuel Lauss 945c0a889dSManuel Lauss int status; 955c0a889dSManuel Lauss 965c0a889dSManuel Lauss struct { 975c0a889dSManuel Lauss int len; 985c0a889dSManuel Lauss int dir; 995c0a889dSManuel Lauss } dma; 1005c0a889dSManuel Lauss 1015c0a889dSManuel Lauss struct { 1025c0a889dSManuel Lauss int index; 1035c0a889dSManuel Lauss int offset; 1045c0a889dSManuel Lauss int len; 1055c0a889dSManuel Lauss } pio; 1065c0a889dSManuel Lauss 1075c0a889dSManuel Lauss u32 tx_chan; 1085c0a889dSManuel Lauss u32 rx_chan; 1095c0a889dSManuel Lauss 1105c0a889dSManuel Lauss int irq; 1115c0a889dSManuel Lauss 1125c0a889dSManuel Lauss struct tasklet_struct finish_task; 1135c0a889dSManuel Lauss struct tasklet_struct data_task; 1145c0a889dSManuel Lauss struct au1xmmc_platform_data *platdata; 1155c0a889dSManuel Lauss struct platform_device *pdev; 1165c0a889dSManuel Lauss struct resource *ioarea; 1175c0a889dSManuel Lauss }; 1185c0a889dSManuel Lauss 1195c0a889dSManuel Lauss /* Status flags used by the host structure */ 1205c0a889dSManuel Lauss #define HOST_F_XMIT 0x0001 1215c0a889dSManuel Lauss #define HOST_F_RECV 0x0002 1225c0a889dSManuel Lauss #define HOST_F_DMA 0x0010 1235c0a889dSManuel Lauss #define HOST_F_ACTIVE 0x0100 1245c0a889dSManuel Lauss #define HOST_F_STOP 0x1000 1255c0a889dSManuel Lauss 1265c0a889dSManuel Lauss #define HOST_S_IDLE 0x0001 1275c0a889dSManuel Lauss #define HOST_S_CMD 0x0002 1285c0a889dSManuel Lauss #define HOST_S_DATA 0x0003 1295c0a889dSManuel Lauss #define HOST_S_STOP 0x0004 1305c0a889dSManuel Lauss 1315c0a889dSManuel Lauss /* Easy access macros */ 1325c0a889dSManuel Lauss #define HOST_STATUS(h) ((h)->iobase + SD_STATUS) 1335c0a889dSManuel Lauss #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) 1345c0a889dSManuel Lauss #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) 1355c0a889dSManuel Lauss #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) 1365c0a889dSManuel Lauss #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) 1375c0a889dSManuel Lauss #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) 1385c0a889dSManuel Lauss #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) 1395c0a889dSManuel Lauss #define HOST_CMD(h) ((h)->iobase + SD_CMD) 1405c0a889dSManuel Lauss #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) 1415c0a889dSManuel Lauss #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) 1425c0a889dSManuel Lauss #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) 1435c0a889dSManuel Lauss 1445c0a889dSManuel Lauss #define DMA_CHANNEL(h) \ 1455c0a889dSManuel Lauss (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) 1465c0a889dSManuel Lauss 1471c6a0718SPierre Ossman static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) 1481c6a0718SPierre Ossman { 1491c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG(host)); 1501c6a0718SPierre Ossman val |= mask; 1511c6a0718SPierre Ossman au_writel(val, HOST_CONFIG(host)); 1521c6a0718SPierre Ossman au_sync(); 1531c6a0718SPierre Ossman } 1541c6a0718SPierre Ossman 1551c6a0718SPierre Ossman static inline void FLUSH_FIFO(struct au1xmmc_host *host) 1561c6a0718SPierre Ossman { 1571c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG2(host)); 1581c6a0718SPierre Ossman 1591c6a0718SPierre Ossman au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); 1601c6a0718SPierre Ossman au_sync_delay(1); 1611c6a0718SPierre Ossman 1621c6a0718SPierre Ossman /* SEND_STOP will turn off clock control - this re-enables it */ 1631c6a0718SPierre Ossman val &= ~SD_CONFIG2_DF; 1641c6a0718SPierre Ossman 1651c6a0718SPierre Ossman au_writel(val, HOST_CONFIG2(host)); 1661c6a0718SPierre Ossman au_sync(); 1671c6a0718SPierre Ossman } 1681c6a0718SPierre Ossman 1691c6a0718SPierre Ossman static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) 1701c6a0718SPierre Ossman { 1711c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG(host)); 1721c6a0718SPierre Ossman val &= ~mask; 1731c6a0718SPierre Ossman au_writel(val, HOST_CONFIG(host)); 1741c6a0718SPierre Ossman au_sync(); 1751c6a0718SPierre Ossman } 1761c6a0718SPierre Ossman 1771c6a0718SPierre Ossman static inline void SEND_STOP(struct au1xmmc_host *host) 1781c6a0718SPierre Ossman { 179281dd23eSManuel Lauss u32 config2; 1801c6a0718SPierre Ossman 1811c6a0718SPierre Ossman WARN_ON(host->status != HOST_S_DATA); 1821c6a0718SPierre Ossman host->status = HOST_S_STOP; 1831c6a0718SPierre Ossman 184281dd23eSManuel Lauss config2 = au_readl(HOST_CONFIG2(host)); 185281dd23eSManuel Lauss au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); 1861c6a0718SPierre Ossman au_sync(); 1871c6a0718SPierre Ossman 1881c6a0718SPierre Ossman /* Send the stop commmand */ 1891c6a0718SPierre Ossman au_writel(STOP_CMD, HOST_CMD(host)); 1901c6a0718SPierre Ossman } 1911c6a0718SPierre Ossman 1921c6a0718SPierre Ossman static void au1xmmc_set_power(struct au1xmmc_host *host, int state) 1931c6a0718SPierre Ossman { 194c4223c2cSManuel Lauss if (host->platdata && host->platdata->set_power) 195c4223c2cSManuel Lauss host->platdata->set_power(host->mmc, state); 1961c6a0718SPierre Ossman } 1971c6a0718SPierre Ossman 198e2d26477SManuel Lauss static int au1xmmc_card_inserted(struct mmc_host *mmc) 1991c6a0718SPierre Ossman { 200e2d26477SManuel Lauss struct au1xmmc_host *host = mmc_priv(mmc); 201c4223c2cSManuel Lauss 202c4223c2cSManuel Lauss if (host->platdata && host->platdata->card_inserted) 203e2d26477SManuel Lauss return !!host->platdata->card_inserted(host->mmc); 204c4223c2cSManuel Lauss 205e2d26477SManuel Lauss return -ENOSYS; 2061c6a0718SPierre Ossman } 2071c6a0718SPierre Ossman 2081c6a0718SPierre Ossman static int au1xmmc_card_readonly(struct mmc_host *mmc) 2091c6a0718SPierre Ossman { 2101c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 211c4223c2cSManuel Lauss 212c4223c2cSManuel Lauss if (host->platdata && host->platdata->card_readonly) 213e2d26477SManuel Lauss return !!host->platdata->card_readonly(mmc); 214c4223c2cSManuel Lauss 215e2d26477SManuel Lauss return -ENOSYS; 2161c6a0718SPierre Ossman } 2171c6a0718SPierre Ossman 2181c6a0718SPierre Ossman static void au1xmmc_finish_request(struct au1xmmc_host *host) 2191c6a0718SPierre Ossman { 2201c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 2211c6a0718SPierre Ossman 2221c6a0718SPierre Ossman host->mrq = NULL; 223c4223c2cSManuel Lauss host->flags &= HOST_F_ACTIVE | HOST_F_DMA; 2241c6a0718SPierre Ossman 2251c6a0718SPierre Ossman host->dma.len = 0; 2261c6a0718SPierre Ossman host->dma.dir = 0; 2271c6a0718SPierre Ossman 2281c6a0718SPierre Ossman host->pio.index = 0; 2291c6a0718SPierre Ossman host->pio.offset = 0; 2301c6a0718SPierre Ossman host->pio.len = 0; 2311c6a0718SPierre Ossman 2321c6a0718SPierre Ossman host->status = HOST_S_IDLE; 2331c6a0718SPierre Ossman 2341c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 2351c6a0718SPierre Ossman } 2361c6a0718SPierre Ossman 2371c6a0718SPierre Ossman static void au1xmmc_tasklet_finish(unsigned long param) 2381c6a0718SPierre Ossman { 2391c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *) param; 2401c6a0718SPierre Ossman au1xmmc_finish_request(host); 2411c6a0718SPierre Ossman } 2421c6a0718SPierre Ossman 2431c6a0718SPierre Ossman static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, 244be0192aaSPierre Ossman struct mmc_command *cmd, struct mmc_data *data) 2451c6a0718SPierre Ossman { 2461c6a0718SPierre Ossman u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); 2471c6a0718SPierre Ossman 2481c6a0718SPierre Ossman switch (mmc_resp_type(cmd)) { 2491c6a0718SPierre Ossman case MMC_RSP_NONE: 2501c6a0718SPierre Ossman break; 2511c6a0718SPierre Ossman case MMC_RSP_R1: 2521c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_1; 2531c6a0718SPierre Ossman break; 2541c6a0718SPierre Ossman case MMC_RSP_R1B: 2551c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_1B; 2561c6a0718SPierre Ossman break; 2571c6a0718SPierre Ossman case MMC_RSP_R2: 2581c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_2; 2591c6a0718SPierre Ossman break; 2601c6a0718SPierre Ossman case MMC_RSP_R3: 2611c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_3; 2621c6a0718SPierre Ossman break; 2631c6a0718SPierre Ossman default: 2641c6a0718SPierre Ossman printk(KERN_INFO "au1xmmc: unhandled response type %02x\n", 2651c6a0718SPierre Ossman mmc_resp_type(cmd)); 26617b0429dSPierre Ossman return -EINVAL; 2671c6a0718SPierre Ossman } 2681c6a0718SPierre Ossman 269be0192aaSPierre Ossman if (data) { 2706356a9d9SPierre Ossman if (data->flags & MMC_DATA_READ) { 271be0192aaSPierre Ossman if (data->blocks > 1) 2721c6a0718SPierre Ossman mmccmd |= SD_CMD_CT_4; 273c0f3b6c7SYoichi Yuasa else 274c0f3b6c7SYoichi Yuasa mmccmd |= SD_CMD_CT_2; 2756356a9d9SPierre Ossman } else if (data->flags & MMC_DATA_WRITE) { 276be0192aaSPierre Ossman if (data->blocks > 1) 2771c6a0718SPierre Ossman mmccmd |= SD_CMD_CT_3; 278c0f3b6c7SYoichi Yuasa else 279c0f3b6c7SYoichi Yuasa mmccmd |= SD_CMD_CT_1; 2801c6a0718SPierre Ossman } 281be0192aaSPierre Ossman } 2821c6a0718SPierre Ossman 2831c6a0718SPierre Ossman au_writel(cmd->arg, HOST_CMDARG(host)); 2841c6a0718SPierre Ossman au_sync(); 2851c6a0718SPierre Ossman 2861c6a0718SPierre Ossman if (wait) 2871c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_CR); 2881c6a0718SPierre Ossman 2891c6a0718SPierre Ossman au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); 2901c6a0718SPierre Ossman au_sync(); 2911c6a0718SPierre Ossman 2921c6a0718SPierre Ossman /* Wait for the command to go on the line */ 2935c0a889dSManuel Lauss while (au_readl(HOST_CMD(host)) & SD_CMD_GO) 2945c0a889dSManuel Lauss /* nop */; 2951c6a0718SPierre Ossman 2961c6a0718SPierre Ossman /* Wait for the command to come back */ 2971c6a0718SPierre Ossman if (wait) { 2981c6a0718SPierre Ossman u32 status = au_readl(HOST_STATUS(host)); 2991c6a0718SPierre Ossman 3001c6a0718SPierre Ossman while (!(status & SD_STATUS_CR)) 3011c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3021c6a0718SPierre Ossman 3031c6a0718SPierre Ossman /* Clear the CR status */ 3041c6a0718SPierre Ossman au_writel(SD_STATUS_CR, HOST_STATUS(host)); 3051c6a0718SPierre Ossman 3061c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_CR); 3071c6a0718SPierre Ossman } 3081c6a0718SPierre Ossman 30917b0429dSPierre Ossman return 0; 3101c6a0718SPierre Ossman } 3111c6a0718SPierre Ossman 3121c6a0718SPierre Ossman static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) 3131c6a0718SPierre Ossman { 3141c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 3151c6a0718SPierre Ossman struct mmc_data *data; 3161c6a0718SPierre Ossman u32 crc; 3171c6a0718SPierre Ossman 3185c0a889dSManuel Lauss WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP)); 3191c6a0718SPierre Ossman 3201c6a0718SPierre Ossman if (host->mrq == NULL) 3211c6a0718SPierre Ossman return; 3221c6a0718SPierre Ossman 3231c6a0718SPierre Ossman data = mrq->cmd->data; 3241c6a0718SPierre Ossman 3251c6a0718SPierre Ossman if (status == 0) 3261c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3271c6a0718SPierre Ossman 3281c6a0718SPierre Ossman /* The transaction is really over when the SD_STATUS_DB bit is clear */ 3291c6a0718SPierre Ossman while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) 3301c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3311c6a0718SPierre Ossman 33217b0429dSPierre Ossman data->error = 0; 3331c6a0718SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); 3341c6a0718SPierre Ossman 3351c6a0718SPierre Ossman /* Process any errors */ 3361c6a0718SPierre Ossman crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); 3371c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) 3381c6a0718SPierre Ossman crc |= ((status & 0x07) == 0x02) ? 0 : 1; 3391c6a0718SPierre Ossman 3401c6a0718SPierre Ossman if (crc) 34117b0429dSPierre Ossman data->error = -EILSEQ; 3421c6a0718SPierre Ossman 3431c6a0718SPierre Ossman /* Clear the CRC bits */ 3441c6a0718SPierre Ossman au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); 3451c6a0718SPierre Ossman 3461c6a0718SPierre Ossman data->bytes_xfered = 0; 3471c6a0718SPierre Ossman 34817b0429dSPierre Ossman if (!data->error) { 3491c6a0718SPierre Ossman if (host->flags & HOST_F_DMA) { 350c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 /* DBDMA */ 3511c6a0718SPierre Ossman u32 chan = DMA_CHANNEL(host); 3521c6a0718SPierre Ossman 3531c6a0718SPierre Ossman chan_tab_t *c = *((chan_tab_t **)chan); 3541c6a0718SPierre Ossman au1x_dma_chan_t *cp = c->chan_ptr; 3551c6a0718SPierre Ossman data->bytes_xfered = cp->ddma_bytecnt; 356c4223c2cSManuel Lauss #endif 3575c0a889dSManuel Lauss } else 3581c6a0718SPierre Ossman data->bytes_xfered = 3595c0a889dSManuel Lauss (data->blocks * data->blksz) - host->pio.len; 3601c6a0718SPierre Ossman } 3611c6a0718SPierre Ossman 3621c6a0718SPierre Ossman au1xmmc_finish_request(host); 3631c6a0718SPierre Ossman } 3641c6a0718SPierre Ossman 3651c6a0718SPierre Ossman static void au1xmmc_tasklet_data(unsigned long param) 3661c6a0718SPierre Ossman { 3671c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *)param; 3681c6a0718SPierre Ossman 3691c6a0718SPierre Ossman u32 status = au_readl(HOST_STATUS(host)); 3701c6a0718SPierre Ossman au1xmmc_data_complete(host, status); 3711c6a0718SPierre Ossman } 3721c6a0718SPierre Ossman 3731c6a0718SPierre Ossman #define AU1XMMC_MAX_TRANSFER 8 3741c6a0718SPierre Ossman 3751c6a0718SPierre Ossman static void au1xmmc_send_pio(struct au1xmmc_host *host) 3761c6a0718SPierre Ossman { 3775c0a889dSManuel Lauss struct mmc_data *data; 3785c0a889dSManuel Lauss int sg_len, max, count; 3795c0a889dSManuel Lauss unsigned char *sg_ptr, val; 3805c0a889dSManuel Lauss u32 status; 3811c6a0718SPierre Ossman struct scatterlist *sg; 3821c6a0718SPierre Ossman 3831c6a0718SPierre Ossman data = host->mrq->data; 3841c6a0718SPierre Ossman 3851c6a0718SPierre Ossman if (!(host->flags & HOST_F_XMIT)) 3861c6a0718SPierre Ossman return; 3871c6a0718SPierre Ossman 3881c6a0718SPierre Ossman /* This is the pointer to the data buffer */ 3891c6a0718SPierre Ossman sg = &data->sg[host->pio.index]; 39045711f1aSJens Axboe sg_ptr = sg_virt(sg) + host->pio.offset; 3911c6a0718SPierre Ossman 3921c6a0718SPierre Ossman /* This is the space left inside the buffer */ 3931c6a0718SPierre Ossman sg_len = data->sg[host->pio.index].length - host->pio.offset; 3941c6a0718SPierre Ossman 3955c0a889dSManuel Lauss /* Check if we need less than the size of the sg_buffer */ 3961c6a0718SPierre Ossman max = (sg_len > host->pio.len) ? host->pio.len : sg_len; 3975c0a889dSManuel Lauss if (max > AU1XMMC_MAX_TRANSFER) 3985c0a889dSManuel Lauss max = AU1XMMC_MAX_TRANSFER; 3991c6a0718SPierre Ossman 4001c6a0718SPierre Ossman for (count = 0; count < max; count++) { 4011c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 4021c6a0718SPierre Ossman 4031c6a0718SPierre Ossman if (!(status & SD_STATUS_TH)) 4041c6a0718SPierre Ossman break; 4051c6a0718SPierre Ossman 4061c6a0718SPierre Ossman val = *sg_ptr++; 4071c6a0718SPierre Ossman 4081c6a0718SPierre Ossman au_writel((unsigned long)val, HOST_TXPORT(host)); 4091c6a0718SPierre Ossman au_sync(); 4101c6a0718SPierre Ossman } 4111c6a0718SPierre Ossman 4121c6a0718SPierre Ossman host->pio.len -= count; 4131c6a0718SPierre Ossman host->pio.offset += count; 4141c6a0718SPierre Ossman 4151c6a0718SPierre Ossman if (count == sg_len) { 4161c6a0718SPierre Ossman host->pio.index++; 4171c6a0718SPierre Ossman host->pio.offset = 0; 4181c6a0718SPierre Ossman } 4191c6a0718SPierre Ossman 4201c6a0718SPierre Ossman if (host->pio.len == 0) { 4211c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_TH); 4221c6a0718SPierre Ossman 4231c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 4241c6a0718SPierre Ossman SEND_STOP(host); 4251c6a0718SPierre Ossman 4261c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 4271c6a0718SPierre Ossman } 4281c6a0718SPierre Ossman } 4291c6a0718SPierre Ossman 4301c6a0718SPierre Ossman static void au1xmmc_receive_pio(struct au1xmmc_host *host) 4311c6a0718SPierre Ossman { 4325c0a889dSManuel Lauss struct mmc_data *data; 4335c0a889dSManuel Lauss int max, count, sg_len = 0; 4345c0a889dSManuel Lauss unsigned char *sg_ptr = NULL; 4355c0a889dSManuel Lauss u32 status, val; 4361c6a0718SPierre Ossman struct scatterlist *sg; 4371c6a0718SPierre Ossman 4381c6a0718SPierre Ossman data = host->mrq->data; 4391c6a0718SPierre Ossman 4401c6a0718SPierre Ossman if (!(host->flags & HOST_F_RECV)) 4411c6a0718SPierre Ossman return; 4421c6a0718SPierre Ossman 4431c6a0718SPierre Ossman max = host->pio.len; 4441c6a0718SPierre Ossman 4451c6a0718SPierre Ossman if (host->pio.index < host->dma.len) { 4461c6a0718SPierre Ossman sg = &data->sg[host->pio.index]; 44745711f1aSJens Axboe sg_ptr = sg_virt(sg) + host->pio.offset; 4481c6a0718SPierre Ossman 4491c6a0718SPierre Ossman /* This is the space left inside the buffer */ 4501c6a0718SPierre Ossman sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; 4511c6a0718SPierre Ossman 4525c0a889dSManuel Lauss /* Check if we need less than the size of the sg_buffer */ 4535c0a889dSManuel Lauss if (sg_len < max) 4545c0a889dSManuel Lauss max = sg_len; 4551c6a0718SPierre Ossman } 4561c6a0718SPierre Ossman 4571c6a0718SPierre Ossman if (max > AU1XMMC_MAX_TRANSFER) 4581c6a0718SPierre Ossman max = AU1XMMC_MAX_TRANSFER; 4591c6a0718SPierre Ossman 4601c6a0718SPierre Ossman for (count = 0; count < max; count++) { 4611c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 4621c6a0718SPierre Ossman 4631c6a0718SPierre Ossman if (!(status & SD_STATUS_NE)) 4641c6a0718SPierre Ossman break; 4651c6a0718SPierre Ossman 4661c6a0718SPierre Ossman if (status & SD_STATUS_RC) { 467c4223c2cSManuel Lauss DBG("RX CRC Error [%d + %d].\n", host->pdev->id, 4681c6a0718SPierre Ossman host->pio.len, count); 4691c6a0718SPierre Ossman break; 4701c6a0718SPierre Ossman } 4711c6a0718SPierre Ossman 4721c6a0718SPierre Ossman if (status & SD_STATUS_RO) { 473c4223c2cSManuel Lauss DBG("RX Overrun [%d + %d]\n", host->pdev->id, 4741c6a0718SPierre Ossman host->pio.len, count); 4751c6a0718SPierre Ossman break; 4761c6a0718SPierre Ossman } 4771c6a0718SPierre Ossman else if (status & SD_STATUS_RU) { 478c4223c2cSManuel Lauss DBG("RX Underrun [%d + %d]\n", host->pdev->id, 4791c6a0718SPierre Ossman host->pio.len, count); 4801c6a0718SPierre Ossman break; 4811c6a0718SPierre Ossman } 4821c6a0718SPierre Ossman 4831c6a0718SPierre Ossman val = au_readl(HOST_RXPORT(host)); 4841c6a0718SPierre Ossman 4851c6a0718SPierre Ossman if (sg_ptr) 4861c6a0718SPierre Ossman *sg_ptr++ = (unsigned char)(val & 0xFF); 4871c6a0718SPierre Ossman } 4881c6a0718SPierre Ossman 4891c6a0718SPierre Ossman host->pio.len -= count; 4901c6a0718SPierre Ossman host->pio.offset += count; 4911c6a0718SPierre Ossman 4921c6a0718SPierre Ossman if (sg_len && count == sg_len) { 4931c6a0718SPierre Ossman host->pio.index++; 4941c6a0718SPierre Ossman host->pio.offset = 0; 4951c6a0718SPierre Ossman } 4961c6a0718SPierre Ossman 4971c6a0718SPierre Ossman if (host->pio.len == 0) { 4985c0a889dSManuel Lauss /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 4991c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_NE); 5001c6a0718SPierre Ossman 5011c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 5021c6a0718SPierre Ossman SEND_STOP(host); 5031c6a0718SPierre Ossman 5041c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 5051c6a0718SPierre Ossman } 5061c6a0718SPierre Ossman } 5071c6a0718SPierre Ossman 5085c0a889dSManuel Lauss /* This is called when a command has been completed - grab the response 5095c0a889dSManuel Lauss * and check for errors. Then start the data transfer if it is indicated. 5101c6a0718SPierre Ossman */ 5111c6a0718SPierre Ossman static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) 5121c6a0718SPierre Ossman { 5131c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 5141c6a0718SPierre Ossman struct mmc_command *cmd; 5155c0a889dSManuel Lauss u32 r[4]; 5165c0a889dSManuel Lauss int i, trans; 5171c6a0718SPierre Ossman 5181c6a0718SPierre Ossman if (!host->mrq) 5191c6a0718SPierre Ossman return; 5201c6a0718SPierre Ossman 5211c6a0718SPierre Ossman cmd = mrq->cmd; 52217b0429dSPierre Ossman cmd->error = 0; 5231c6a0718SPierre Ossman 5241c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 5251c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) { 5261c6a0718SPierre Ossman r[0] = au_readl(host->iobase + SD_RESP3); 5271c6a0718SPierre Ossman r[1] = au_readl(host->iobase + SD_RESP2); 5281c6a0718SPierre Ossman r[2] = au_readl(host->iobase + SD_RESP1); 5291c6a0718SPierre Ossman r[3] = au_readl(host->iobase + SD_RESP0); 5301c6a0718SPierre Ossman 5311c6a0718SPierre Ossman /* The CRC is omitted from the response, so really 5321c6a0718SPierre Ossman * we only got 120 bytes, but the engine expects 5335c0a889dSManuel Lauss * 128 bits, so we have to shift things up. 5341c6a0718SPierre Ossman */ 5351c6a0718SPierre Ossman for (i = 0; i < 4; i++) { 5361c6a0718SPierre Ossman cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; 5371c6a0718SPierre Ossman if (i != 3) 5381c6a0718SPierre Ossman cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; 5391c6a0718SPierre Ossman } 5401c6a0718SPierre Ossman } else { 5411c6a0718SPierre Ossman /* Techincally, we should be getting all 48 bits of 5421c6a0718SPierre Ossman * the response (SD_RESP1 + SD_RESP2), but because 5431c6a0718SPierre Ossman * our response omits the CRC, our data ends up 5441c6a0718SPierre Ossman * being shifted 8 bits to the right. In this case, 5451c6a0718SPierre Ossman * that means that the OSR data starts at bit 31, 5465c0a889dSManuel Lauss * so we can just read RESP0 and return that. 5471c6a0718SPierre Ossman */ 5481c6a0718SPierre Ossman cmd->resp[0] = au_readl(host->iobase + SD_RESP0); 5491c6a0718SPierre Ossman } 5501c6a0718SPierre Ossman } 5511c6a0718SPierre Ossman 5521c6a0718SPierre Ossman /* Figure out errors */ 5531c6a0718SPierre Ossman if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) 55417b0429dSPierre Ossman cmd->error = -EILSEQ; 5551c6a0718SPierre Ossman 5561c6a0718SPierre Ossman trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); 5571c6a0718SPierre Ossman 55817b0429dSPierre Ossman if (!trans || cmd->error) { 5591c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); 5601c6a0718SPierre Ossman tasklet_schedule(&host->finish_task); 5611c6a0718SPierre Ossman return; 5621c6a0718SPierre Ossman } 5631c6a0718SPierre Ossman 5641c6a0718SPierre Ossman host->status = HOST_S_DATA; 5651c6a0718SPierre Ossman 5661c6a0718SPierre Ossman if (host->flags & HOST_F_DMA) { 567c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 /* DBDMA */ 5681c6a0718SPierre Ossman u32 channel = DMA_CHANNEL(host); 5691c6a0718SPierre Ossman 5701c6a0718SPierre Ossman /* Start the DMA as soon as the buffer gets something in it */ 5711c6a0718SPierre Ossman 5721c6a0718SPierre Ossman if (host->flags & HOST_F_RECV) { 5731c6a0718SPierre Ossman u32 mask = SD_STATUS_DB | SD_STATUS_NE; 5741c6a0718SPierre Ossman 5751c6a0718SPierre Ossman while((status & mask) != mask) 5761c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 5771c6a0718SPierre Ossman } 5781c6a0718SPierre Ossman 5791c6a0718SPierre Ossman au1xxx_dbdma_start(channel); 580c4223c2cSManuel Lauss #endif 5811c6a0718SPierre Ossman } 5821c6a0718SPierre Ossman } 5831c6a0718SPierre Ossman 5841c6a0718SPierre Ossman static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) 5851c6a0718SPierre Ossman { 5861c6a0718SPierre Ossman unsigned int pbus = get_au1x00_speed(); 5871c6a0718SPierre Ossman unsigned int divisor; 5881c6a0718SPierre Ossman u32 config; 5891c6a0718SPierre Ossman 5901c6a0718SPierre Ossman /* From databook: 5915c0a889dSManuel Lauss * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1 5921c6a0718SPierre Ossman */ 5931c6a0718SPierre Ossman pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2); 5941c6a0718SPierre Ossman pbus /= 2; 5951c6a0718SPierre Ossman divisor = ((pbus / rate) / 2) - 1; 5961c6a0718SPierre Ossman 5971c6a0718SPierre Ossman config = au_readl(HOST_CONFIG(host)); 5981c6a0718SPierre Ossman 5991c6a0718SPierre Ossman config &= ~(SD_CONFIG_DIV); 6001c6a0718SPierre Ossman config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; 6011c6a0718SPierre Ossman 6021c6a0718SPierre Ossman au_writel(config, HOST_CONFIG(host)); 6031c6a0718SPierre Ossman au_sync(); 6041c6a0718SPierre Ossman } 6051c6a0718SPierre Ossman 6065c0a889dSManuel Lauss static int au1xmmc_prepare_data(struct au1xmmc_host *host, 6075c0a889dSManuel Lauss struct mmc_data *data) 6081c6a0718SPierre Ossman { 6091c6a0718SPierre Ossman int datalen = data->blocks * data->blksz; 6101c6a0718SPierre Ossman 6111c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 6121c6a0718SPierre Ossman host->flags |= HOST_F_RECV; 6131c6a0718SPierre Ossman else 6141c6a0718SPierre Ossman host->flags |= HOST_F_XMIT; 6151c6a0718SPierre Ossman 6161c6a0718SPierre Ossman if (host->mrq->stop) 6171c6a0718SPierre Ossman host->flags |= HOST_F_STOP; 6181c6a0718SPierre Ossman 6191c6a0718SPierre Ossman host->dma.dir = DMA_BIDIRECTIONAL; 6201c6a0718SPierre Ossman 6211c6a0718SPierre Ossman host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, 6221c6a0718SPierre Ossman data->sg_len, host->dma.dir); 6231c6a0718SPierre Ossman 6241c6a0718SPierre Ossman if (host->dma.len == 0) 62517b0429dSPierre Ossman return -ETIMEDOUT; 6261c6a0718SPierre Ossman 6271c6a0718SPierre Ossman au_writel(data->blksz - 1, HOST_BLKSIZE(host)); 6281c6a0718SPierre Ossman 6291c6a0718SPierre Ossman if (host->flags & HOST_F_DMA) { 630c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 /* DBDMA */ 6311c6a0718SPierre Ossman int i; 6321c6a0718SPierre Ossman u32 channel = DMA_CHANNEL(host); 6331c6a0718SPierre Ossman 6341c6a0718SPierre Ossman au1xxx_dbdma_stop(channel); 6351c6a0718SPierre Ossman 6361c6a0718SPierre Ossman for (i = 0; i < host->dma.len; i++) { 6371c6a0718SPierre Ossman u32 ret = 0, flags = DDMA_FLAGS_NOIE; 6381c6a0718SPierre Ossman struct scatterlist *sg = &data->sg[i]; 6391c6a0718SPierre Ossman int sg_len = sg->length; 6401c6a0718SPierre Ossman 6411c6a0718SPierre Ossman int len = (datalen > sg_len) ? sg_len : datalen; 6421c6a0718SPierre Ossman 6431c6a0718SPierre Ossman if (i == host->dma.len - 1) 6441c6a0718SPierre Ossman flags = DDMA_FLAGS_IE; 6451c6a0718SPierre Ossman 6461c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) { 6471c6a0718SPierre Ossman ret = au1xxx_dbdma_put_source_flags(channel, 64845711f1aSJens Axboe (void *)sg_virt(sg), len, flags); 6495c0a889dSManuel Lauss } else { 6501c6a0718SPierre Ossman ret = au1xxx_dbdma_put_dest_flags(channel, 6515c0a889dSManuel Lauss (void *)sg_virt(sg), len, flags); 6521c6a0718SPierre Ossman } 6531c6a0718SPierre Ossman 6541c6a0718SPierre Ossman if (!ret) 6551c6a0718SPierre Ossman goto dataerr; 6561c6a0718SPierre Ossman 6571c6a0718SPierre Ossman datalen -= len; 6581c6a0718SPierre Ossman } 659c4223c2cSManuel Lauss #endif 6605c0a889dSManuel Lauss } else { 6611c6a0718SPierre Ossman host->pio.index = 0; 6621c6a0718SPierre Ossman host->pio.offset = 0; 6631c6a0718SPierre Ossman host->pio.len = datalen; 6641c6a0718SPierre Ossman 6651c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) 6661c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_TH); 6671c6a0718SPierre Ossman else 6681c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_NE); 6695c0a889dSManuel Lauss /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 6701c6a0718SPierre Ossman } 6711c6a0718SPierre Ossman 67217b0429dSPierre Ossman return 0; 6731c6a0718SPierre Ossman 6741c6a0718SPierre Ossman dataerr: 675c4223c2cSManuel Lauss dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 676c4223c2cSManuel Lauss host->dma.dir); 67717b0429dSPierre Ossman return -ETIMEDOUT; 6781c6a0718SPierre Ossman } 6791c6a0718SPierre Ossman 6805c0a889dSManuel Lauss /* This actually starts a command or data transaction */ 6811c6a0718SPierre Ossman static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) 6821c6a0718SPierre Ossman { 6831c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 68417b0429dSPierre Ossman int ret = 0; 6851c6a0718SPierre Ossman 6861c6a0718SPierre Ossman WARN_ON(irqs_disabled()); 6871c6a0718SPierre Ossman WARN_ON(host->status != HOST_S_IDLE); 6881c6a0718SPierre Ossman 6891c6a0718SPierre Ossman host->mrq = mrq; 6901c6a0718SPierre Ossman host->status = HOST_S_CMD; 6911c6a0718SPierre Ossman 69288b8d9a8SManuel Lauss /* fail request immediately if no card is present */ 693e2d26477SManuel Lauss if (0 == au1xmmc_card_inserted(mmc)) { 69488b8d9a8SManuel Lauss mrq->cmd->error = -ENOMEDIUM; 69588b8d9a8SManuel Lauss au1xmmc_finish_request(host); 69688b8d9a8SManuel Lauss return; 69788b8d9a8SManuel Lauss } 69888b8d9a8SManuel Lauss 6991c6a0718SPierre Ossman if (mrq->data) { 7001c6a0718SPierre Ossman FLUSH_FIFO(host); 7011c6a0718SPierre Ossman ret = au1xmmc_prepare_data(host, mrq->data); 7021c6a0718SPierre Ossman } 7031c6a0718SPierre Ossman 70417b0429dSPierre Ossman if (!ret) 705be0192aaSPierre Ossman ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data); 7061c6a0718SPierre Ossman 70717b0429dSPierre Ossman if (ret) { 7081c6a0718SPierre Ossman mrq->cmd->error = ret; 7091c6a0718SPierre Ossman au1xmmc_finish_request(host); 7101c6a0718SPierre Ossman } 7111c6a0718SPierre Ossman } 7121c6a0718SPierre Ossman 7131c6a0718SPierre Ossman static void au1xmmc_reset_controller(struct au1xmmc_host *host) 7141c6a0718SPierre Ossman { 7151c6a0718SPierre Ossman /* Apply the clock */ 7161c6a0718SPierre Ossman au_writel(SD_ENABLE_CE, HOST_ENABLE(host)); 7171c6a0718SPierre Ossman au_sync_delay(1); 7181c6a0718SPierre Ossman 7191c6a0718SPierre Ossman au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); 7201c6a0718SPierre Ossman au_sync_delay(5); 7211c6a0718SPierre Ossman 7221c6a0718SPierre Ossman au_writel(~0, HOST_STATUS(host)); 7231c6a0718SPierre Ossman au_sync(); 7241c6a0718SPierre Ossman 7251c6a0718SPierre Ossman au_writel(0, HOST_BLKSIZE(host)); 7261c6a0718SPierre Ossman au_writel(0x001fffff, HOST_TIMEOUT(host)); 7271c6a0718SPierre Ossman au_sync(); 7281c6a0718SPierre Ossman 7291c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 7301c6a0718SPierre Ossman au_sync(); 7311c6a0718SPierre Ossman 7321c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); 7331c6a0718SPierre Ossman au_sync_delay(1); 7341c6a0718SPierre Ossman 7351c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 7361c6a0718SPierre Ossman au_sync(); 7371c6a0718SPierre Ossman 7381c6a0718SPierre Ossman /* Configure interrupts */ 7391c6a0718SPierre Ossman au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); 7401c6a0718SPierre Ossman au_sync(); 7411c6a0718SPierre Ossman } 7421c6a0718SPierre Ossman 7431c6a0718SPierre Ossman 7441c6a0718SPierre Ossman static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 7451c6a0718SPierre Ossman { 7461c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 747281dd23eSManuel Lauss u32 config2; 7481c6a0718SPierre Ossman 7491c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) 7501c6a0718SPierre Ossman au1xmmc_set_power(host, 0); 7511c6a0718SPierre Ossman else if (ios->power_mode == MMC_POWER_ON) { 7521c6a0718SPierre Ossman au1xmmc_set_power(host, 1); 7531c6a0718SPierre Ossman } 7541c6a0718SPierre Ossman 7551c6a0718SPierre Ossman if (ios->clock && ios->clock != host->clock) { 7561c6a0718SPierre Ossman au1xmmc_set_clock(host, ios->clock); 7571c6a0718SPierre Ossman host->clock = ios->clock; 7581c6a0718SPierre Ossman } 759281dd23eSManuel Lauss 760281dd23eSManuel Lauss config2 = au_readl(HOST_CONFIG2(host)); 761281dd23eSManuel Lauss switch (ios->bus_width) { 762281dd23eSManuel Lauss case MMC_BUS_WIDTH_4: 763281dd23eSManuel Lauss config2 |= SD_CONFIG2_WB; 764281dd23eSManuel Lauss break; 765281dd23eSManuel Lauss case MMC_BUS_WIDTH_1: 766281dd23eSManuel Lauss config2 &= ~SD_CONFIG2_WB; 767281dd23eSManuel Lauss break; 768281dd23eSManuel Lauss } 769281dd23eSManuel Lauss au_writel(config2, HOST_CONFIG2(host)); 770281dd23eSManuel Lauss au_sync(); 7711c6a0718SPierre Ossman } 7721c6a0718SPierre Ossman 773c4223c2cSManuel Lauss #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) 774c4223c2cSManuel Lauss #define STATUS_DATA_IN (SD_STATUS_NE) 775c4223c2cSManuel Lauss #define STATUS_DATA_OUT (SD_STATUS_TH) 776c4223c2cSManuel Lauss 777c4223c2cSManuel Lauss static irqreturn_t au1xmmc_irq(int irq, void *dev_id) 778c4223c2cSManuel Lauss { 779c4223c2cSManuel Lauss struct au1xmmc_host *host = dev_id; 780c4223c2cSManuel Lauss u32 status; 781c4223c2cSManuel Lauss 782c4223c2cSManuel Lauss status = au_readl(HOST_STATUS(host)); 783c4223c2cSManuel Lauss 784c4223c2cSManuel Lauss if (!(status & SD_STATUS_I)) 785c4223c2cSManuel Lauss return IRQ_NONE; /* not ours */ 786c4223c2cSManuel Lauss 78720f522ffSManuel Lauss if (status & SD_STATUS_SI) /* SDIO */ 78820f522ffSManuel Lauss mmc_signal_sdio_irq(host->mmc); 78920f522ffSManuel Lauss 790c4223c2cSManuel Lauss if (host->mrq && (status & STATUS_TIMEOUT)) { 791c4223c2cSManuel Lauss if (status & SD_STATUS_RAT) 792c4223c2cSManuel Lauss host->mrq->cmd->error = -ETIMEDOUT; 793c4223c2cSManuel Lauss else if (status & SD_STATUS_DT) 794c4223c2cSManuel Lauss host->mrq->data->error = -ETIMEDOUT; 795c4223c2cSManuel Lauss 796c4223c2cSManuel Lauss /* In PIO mode, interrupts might still be enabled */ 797c4223c2cSManuel Lauss IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); 798c4223c2cSManuel Lauss 799c4223c2cSManuel Lauss /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ 800c4223c2cSManuel Lauss tasklet_schedule(&host->finish_task); 801c4223c2cSManuel Lauss } 802c4223c2cSManuel Lauss #if 0 803c4223c2cSManuel Lauss else if (status & SD_STATUS_DD) { 804c4223c2cSManuel Lauss /* Sometimes we get a DD before a NE in PIO mode */ 805c4223c2cSManuel Lauss if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) 806c4223c2cSManuel Lauss au1xmmc_receive_pio(host); 807c4223c2cSManuel Lauss else { 808c4223c2cSManuel Lauss au1xmmc_data_complete(host, status); 809c4223c2cSManuel Lauss /* tasklet_schedule(&host->data_task); */ 810c4223c2cSManuel Lauss } 811c4223c2cSManuel Lauss } 812c4223c2cSManuel Lauss #endif 813c4223c2cSManuel Lauss else if (status & SD_STATUS_CR) { 814c4223c2cSManuel Lauss if (host->status == HOST_S_CMD) 815c4223c2cSManuel Lauss au1xmmc_cmd_complete(host, status); 816c4223c2cSManuel Lauss 817c4223c2cSManuel Lauss } else if (!(host->flags & HOST_F_DMA)) { 818c4223c2cSManuel Lauss if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) 819c4223c2cSManuel Lauss au1xmmc_send_pio(host); 820c4223c2cSManuel Lauss else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) 821c4223c2cSManuel Lauss au1xmmc_receive_pio(host); 822c4223c2cSManuel Lauss 823c4223c2cSManuel Lauss } else if (status & 0x203F3C70) { 824c4223c2cSManuel Lauss DBG("Unhandled status %8.8x\n", host->pdev->id, 825c4223c2cSManuel Lauss status); 826c4223c2cSManuel Lauss } 827c4223c2cSManuel Lauss 828c4223c2cSManuel Lauss au_writel(status, HOST_STATUS(host)); 829c4223c2cSManuel Lauss au_sync(); 830c4223c2cSManuel Lauss 831c4223c2cSManuel Lauss return IRQ_HANDLED; 832c4223c2cSManuel Lauss } 833c4223c2cSManuel Lauss 834c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 835c4223c2cSManuel Lauss /* 8bit memory DMA device */ 836c4223c2cSManuel Lauss static dbdev_tab_t au1xmmc_mem_dbdev = { 837c4223c2cSManuel Lauss .dev_id = DSCR_CMD0_ALWAYS, 838c4223c2cSManuel Lauss .dev_flags = DEV_FLAGS_ANYUSE, 839c4223c2cSManuel Lauss .dev_tsize = 0, 840c4223c2cSManuel Lauss .dev_devwidth = 8, 841c4223c2cSManuel Lauss .dev_physaddr = 0x00000000, 842c4223c2cSManuel Lauss .dev_intlevel = 0, 843c4223c2cSManuel Lauss .dev_intpolarity = 0, 844c4223c2cSManuel Lauss }; 845c4223c2cSManuel Lauss static int memid; 846c4223c2cSManuel Lauss 847c4223c2cSManuel Lauss static void au1xmmc_dbdma_callback(int irq, void *dev_id) 8481c6a0718SPierre Ossman { 8491c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; 8501c6a0718SPierre Ossman 8511c6a0718SPierre Ossman /* Avoid spurious interrupts */ 8521c6a0718SPierre Ossman if (!host->mrq) 8531c6a0718SPierre Ossman return; 8541c6a0718SPierre Ossman 8551c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 8561c6a0718SPierre Ossman SEND_STOP(host); 8571c6a0718SPierre Ossman 8581c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 8591c6a0718SPierre Ossman } 8601c6a0718SPierre Ossman 861c4223c2cSManuel Lauss static int au1xmmc_dbdma_init(struct au1xmmc_host *host) 8621c6a0718SPierre Ossman { 863c4223c2cSManuel Lauss struct resource *res; 864c4223c2cSManuel Lauss int txid, rxid; 8651c6a0718SPierre Ossman 866c4223c2cSManuel Lauss res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); 867c4223c2cSManuel Lauss if (!res) 868c4223c2cSManuel Lauss return -ENODEV; 869c4223c2cSManuel Lauss txid = res->start; 8701c6a0718SPierre Ossman 871c4223c2cSManuel Lauss res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); 872c4223c2cSManuel Lauss if (!res) 873c4223c2cSManuel Lauss return -ENODEV; 874c4223c2cSManuel Lauss rxid = res->start; 8751c6a0718SPierre Ossman 876c4223c2cSManuel Lauss if (!memid) 877c4223c2cSManuel Lauss return -ENODEV; 8781c6a0718SPierre Ossman 879c4223c2cSManuel Lauss host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, 880c4223c2cSManuel Lauss au1xmmc_dbdma_callback, (void *)host); 881c4223c2cSManuel Lauss if (!host->tx_chan) { 882c4223c2cSManuel Lauss dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); 883c4223c2cSManuel Lauss return -ENODEV; 8841c6a0718SPierre Ossman } 8851c6a0718SPierre Ossman 886c4223c2cSManuel Lauss host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, 887c4223c2cSManuel Lauss au1xmmc_dbdma_callback, (void *)host); 888c4223c2cSManuel Lauss if (!host->rx_chan) { 889c4223c2cSManuel Lauss dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); 890c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->tx_chan); 891c4223c2cSManuel Lauss return -ENODEV; 892c4223c2cSManuel Lauss } 8931c6a0718SPierre Ossman 894c4223c2cSManuel Lauss au1xxx_dbdma_set_devwidth(host->tx_chan, 8); 895c4223c2cSManuel Lauss au1xxx_dbdma_set_devwidth(host->rx_chan, 8); 896c4223c2cSManuel Lauss 897c4223c2cSManuel Lauss au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); 898c4223c2cSManuel Lauss au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); 899c4223c2cSManuel Lauss 900c4223c2cSManuel Lauss /* DBDMA is good to go */ 901c4223c2cSManuel Lauss host->flags |= HOST_F_DMA; 902c4223c2cSManuel Lauss 903c4223c2cSManuel Lauss return 0; 904c4223c2cSManuel Lauss } 905c4223c2cSManuel Lauss 906c4223c2cSManuel Lauss static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) 907c4223c2cSManuel Lauss { 908c4223c2cSManuel Lauss if (host->flags & HOST_F_DMA) { 909c4223c2cSManuel Lauss host->flags &= ~HOST_F_DMA; 910c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->tx_chan); 911c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->rx_chan); 9121c6a0718SPierre Ossman } 9131c6a0718SPierre Ossman } 9141c6a0718SPierre Ossman #endif 9151c6a0718SPierre Ossman 91620f522ffSManuel Lauss static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) 91720f522ffSManuel Lauss { 91820f522ffSManuel Lauss struct au1xmmc_host *host = mmc_priv(mmc); 91920f522ffSManuel Lauss 92020f522ffSManuel Lauss if (en) 92120f522ffSManuel Lauss IRQ_ON(host, SD_CONFIG_SI); 92220f522ffSManuel Lauss else 92320f522ffSManuel Lauss IRQ_OFF(host, SD_CONFIG_SI); 92420f522ffSManuel Lauss } 92520f522ffSManuel Lauss 9261c6a0718SPierre Ossman static const struct mmc_host_ops au1xmmc_ops = { 9271c6a0718SPierre Ossman .request = au1xmmc_request, 9281c6a0718SPierre Ossman .set_ios = au1xmmc_set_ios, 9291c6a0718SPierre Ossman .get_ro = au1xmmc_card_readonly, 930e2d26477SManuel Lauss .get_cd = au1xmmc_card_inserted, 93120f522ffSManuel Lauss .enable_sdio_irq = au1xmmc_enable_sdio_irq, 9321c6a0718SPierre Ossman }; 9331c6a0718SPierre Ossman 934c4223c2cSManuel Lauss static int __devinit au1xmmc_probe(struct platform_device *pdev) 935c4223c2cSManuel Lauss { 936c4223c2cSManuel Lauss struct mmc_host *mmc; 937c4223c2cSManuel Lauss struct au1xmmc_host *host; 938c4223c2cSManuel Lauss struct resource *r; 939c4223c2cSManuel Lauss int ret; 940c4223c2cSManuel Lauss 941c4223c2cSManuel Lauss mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); 9421c6a0718SPierre Ossman if (!mmc) { 943c4223c2cSManuel Lauss dev_err(&pdev->dev, "no memory for mmc_host\n"); 944c4223c2cSManuel Lauss ret = -ENOMEM; 945c4223c2cSManuel Lauss goto out0; 946c4223c2cSManuel Lauss } 947c4223c2cSManuel Lauss 948c4223c2cSManuel Lauss host = mmc_priv(mmc); 949c4223c2cSManuel Lauss host->mmc = mmc; 950c4223c2cSManuel Lauss host->platdata = pdev->dev.platform_data; 951c4223c2cSManuel Lauss host->pdev = pdev; 952c4223c2cSManuel Lauss 953c4223c2cSManuel Lauss ret = -ENODEV; 954c4223c2cSManuel Lauss r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 955c4223c2cSManuel Lauss if (!r) { 956c4223c2cSManuel Lauss dev_err(&pdev->dev, "no mmio defined\n"); 957c4223c2cSManuel Lauss goto out1; 958c4223c2cSManuel Lauss } 959c4223c2cSManuel Lauss 960c4223c2cSManuel Lauss host->ioarea = request_mem_region(r->start, r->end - r->start + 1, 961c4223c2cSManuel Lauss pdev->name); 962c4223c2cSManuel Lauss if (!host->ioarea) { 963c4223c2cSManuel Lauss dev_err(&pdev->dev, "mmio already in use\n"); 964c4223c2cSManuel Lauss goto out1; 965c4223c2cSManuel Lauss } 966c4223c2cSManuel Lauss 967c4223c2cSManuel Lauss host->iobase = (unsigned long)ioremap(r->start, 0x3c); 968c4223c2cSManuel Lauss if (!host->iobase) { 969c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot remap mmio\n"); 970c4223c2cSManuel Lauss goto out2; 971c4223c2cSManuel Lauss } 972c4223c2cSManuel Lauss 973c4223c2cSManuel Lauss r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 974c4223c2cSManuel Lauss if (!r) { 975c4223c2cSManuel Lauss dev_err(&pdev->dev, "no IRQ defined\n"); 976c4223c2cSManuel Lauss goto out3; 977c4223c2cSManuel Lauss } 978c4223c2cSManuel Lauss 979c4223c2cSManuel Lauss host->irq = r->start; 980c4223c2cSManuel Lauss /* IRQ is shared among both SD controllers */ 981c4223c2cSManuel Lauss ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED, 982c4223c2cSManuel Lauss DRIVER_NAME, host); 983c4223c2cSManuel Lauss if (ret) { 984c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot grab IRQ\n"); 985c4223c2cSManuel Lauss goto out3; 9861c6a0718SPierre Ossman } 9871c6a0718SPierre Ossman 9881c6a0718SPierre Ossman mmc->ops = &au1xmmc_ops; 9891c6a0718SPierre Ossman 9901c6a0718SPierre Ossman mmc->f_min = 450000; 9911c6a0718SPierre Ossman mmc->f_max = 24000000; 9921c6a0718SPierre Ossman 9931c6a0718SPierre Ossman mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; 9941c6a0718SPierre Ossman mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; 9951c6a0718SPierre Ossman 9961c6a0718SPierre Ossman mmc->max_blk_size = 2048; 9971c6a0718SPierre Ossman mmc->max_blk_count = 512; 9981c6a0718SPierre Ossman 9991c6a0718SPierre Ossman mmc->ocr_avail = AU1XMMC_OCR; 100020f522ffSManuel Lauss mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 10011c6a0718SPierre Ossman 10021c6a0718SPierre Ossman host->status = HOST_S_IDLE; 10031c6a0718SPierre Ossman 1004c4223c2cSManuel Lauss /* board-specific carddetect setup, if any */ 1005c4223c2cSManuel Lauss if (host->platdata && host->platdata->cd_setup) { 1006c4223c2cSManuel Lauss ret = host->platdata->cd_setup(mmc, 1); 1007c4223c2cSManuel Lauss if (ret) { 1008e2d26477SManuel Lauss dev_warn(&pdev->dev, "board CD setup failed\n"); 1009e2d26477SManuel Lauss mmc->caps |= MMC_CAP_NEEDS_POLL; 1010c4223c2cSManuel Lauss } 1011e2d26477SManuel Lauss } else 1012e2d26477SManuel Lauss mmc->caps |= MMC_CAP_NEEDS_POLL; 10131c6a0718SPierre Ossman 10141c6a0718SPierre Ossman tasklet_init(&host->data_task, au1xmmc_tasklet_data, 10151c6a0718SPierre Ossman (unsigned long)host); 10161c6a0718SPierre Ossman 10171c6a0718SPierre Ossman tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, 10181c6a0718SPierre Ossman (unsigned long)host); 10191c6a0718SPierre Ossman 1020c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1021c4223c2cSManuel Lauss ret = au1xmmc_dbdma_init(host); 1022c4223c2cSManuel Lauss if (ret) 1023c4223c2cSManuel Lauss printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n"); 1024c4223c2cSManuel Lauss #endif 10251c6a0718SPierre Ossman 1026c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1027c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) { 1028c4223c2cSManuel Lauss struct led_classdev *led = host->platdata->led; 1029c4223c2cSManuel Lauss led->name = mmc_hostname(mmc); 1030c4223c2cSManuel Lauss led->brightness = LED_OFF; 1031c4223c2cSManuel Lauss led->default_trigger = mmc_hostname(mmc); 1032c4223c2cSManuel Lauss ret = led_classdev_register(mmc_dev(mmc), led); 1033c4223c2cSManuel Lauss if (ret) 1034c4223c2cSManuel Lauss goto out5; 1035c4223c2cSManuel Lauss } 1036c4223c2cSManuel Lauss #endif 10371c6a0718SPierre Ossman 10381c6a0718SPierre Ossman au1xmmc_reset_controller(host); 10391c6a0718SPierre Ossman 1040c4223c2cSManuel Lauss ret = mmc_add_host(mmc); 1041c4223c2cSManuel Lauss if (ret) { 1042c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot add mmc host\n"); 1043c4223c2cSManuel Lauss goto out6; 1044c4223c2cSManuel Lauss } 10451c6a0718SPierre Ossman 1046dd8572afSManuel Lauss platform_set_drvdata(pdev, host); 1047c4223c2cSManuel Lauss 1048c4223c2cSManuel Lauss printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X" 1049c4223c2cSManuel Lauss " (mode=%s)\n", pdev->id, host->iobase, 1050c4223c2cSManuel Lauss host->flags & HOST_F_DMA ? "dma" : "pio"); 10511c6a0718SPierre Ossman 1052c4223c2cSManuel Lauss return 0; /* all ok */ 10531c6a0718SPierre Ossman 1054c4223c2cSManuel Lauss out6: 1055c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1056c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) 1057c4223c2cSManuel Lauss led_classdev_unregister(host->platdata->led); 1058c4223c2cSManuel Lauss out5: 1059c4223c2cSManuel Lauss #endif 1060c4223c2cSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1061c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1062c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1063c4223c2cSManuel Lauss au_sync(); 10641c6a0718SPierre Ossman 1065c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1066c4223c2cSManuel Lauss au1xmmc_dbdma_shutdown(host); 1067c4223c2cSManuel Lauss #endif 10681c6a0718SPierre Ossman 10691c6a0718SPierre Ossman tasklet_kill(&host->data_task); 10701c6a0718SPierre Ossman tasklet_kill(&host->finish_task); 10711c6a0718SPierre Ossman 1072e2d26477SManuel Lauss if (host->platdata && host->platdata->cd_setup && 1073e2d26477SManuel Lauss !(mmc->caps & MMC_CAP_NEEDS_POLL)) 1074c4223c2cSManuel Lauss host->platdata->cd_setup(mmc, 0); 1075e2d26477SManuel Lauss 1076c4223c2cSManuel Lauss free_irq(host->irq, host); 1077c4223c2cSManuel Lauss out3: 1078c4223c2cSManuel Lauss iounmap((void *)host->iobase); 1079c4223c2cSManuel Lauss out2: 1080c4223c2cSManuel Lauss release_resource(host->ioarea); 1081c4223c2cSManuel Lauss kfree(host->ioarea); 1082c4223c2cSManuel Lauss out1: 1083c4223c2cSManuel Lauss mmc_free_host(mmc); 1084c4223c2cSManuel Lauss out0: 1085c4223c2cSManuel Lauss return ret; 10861c6a0718SPierre Ossman } 10871c6a0718SPierre Ossman 1088c4223c2cSManuel Lauss static int __devexit au1xmmc_remove(struct platform_device *pdev) 1089c4223c2cSManuel Lauss { 1090dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1091c4223c2cSManuel Lauss 1092dd8572afSManuel Lauss if (host) { 1093dd8572afSManuel Lauss mmc_remove_host(host->mmc); 1094c4223c2cSManuel Lauss 1095c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1096c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) 1097c4223c2cSManuel Lauss led_classdev_unregister(host->platdata->led); 1098c4223c2cSManuel Lauss #endif 1099c4223c2cSManuel Lauss 1100e2d26477SManuel Lauss if (host->platdata && host->platdata->cd_setup && 1101dd8572afSManuel Lauss !(host->mmc->caps & MMC_CAP_NEEDS_POLL)) 1102dd8572afSManuel Lauss host->platdata->cd_setup(host->mmc, 0); 1103c4223c2cSManuel Lauss 1104c4223c2cSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1105c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1106c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1107c4223c2cSManuel Lauss au_sync(); 1108c4223c2cSManuel Lauss 1109c4223c2cSManuel Lauss tasklet_kill(&host->data_task); 1110c4223c2cSManuel Lauss tasklet_kill(&host->finish_task); 1111c4223c2cSManuel Lauss 1112c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1113c4223c2cSManuel Lauss au1xmmc_dbdma_shutdown(host); 1114c4223c2cSManuel Lauss #endif 1115c4223c2cSManuel Lauss au1xmmc_set_power(host, 0); 1116c4223c2cSManuel Lauss 1117c4223c2cSManuel Lauss free_irq(host->irq, host); 1118c4223c2cSManuel Lauss iounmap((void *)host->iobase); 1119c4223c2cSManuel Lauss release_resource(host->ioarea); 1120c4223c2cSManuel Lauss kfree(host->ioarea); 1121c4223c2cSManuel Lauss 1122dd8572afSManuel Lauss mmc_free_host(host->mmc); 1123dd8572afSManuel Lauss platform_set_drvdata(pdev, NULL); 1124c4223c2cSManuel Lauss } 11251c6a0718SPierre Ossman return 0; 11261c6a0718SPierre Ossman } 11271c6a0718SPierre Ossman 1128dd8572afSManuel Lauss #ifdef CONFIG_PM 1129dd8572afSManuel Lauss static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state) 1130dd8572afSManuel Lauss { 1131dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1132dd8572afSManuel Lauss int ret; 1133dd8572afSManuel Lauss 1134dd8572afSManuel Lauss ret = mmc_suspend_host(host->mmc, state); 1135dd8572afSManuel Lauss if (ret) 1136dd8572afSManuel Lauss return ret; 1137dd8572afSManuel Lauss 1138dd8572afSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1139dd8572afSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1140dd8572afSManuel Lauss au_writel(0xffffffff, HOST_STATUS(host)); 1141dd8572afSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1142dd8572afSManuel Lauss au_sync(); 1143dd8572afSManuel Lauss 1144dd8572afSManuel Lauss return 0; 1145dd8572afSManuel Lauss } 1146dd8572afSManuel Lauss 1147dd8572afSManuel Lauss static int au1xmmc_resume(struct platform_device *pdev) 1148dd8572afSManuel Lauss { 1149dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1150dd8572afSManuel Lauss 1151dd8572afSManuel Lauss au1xmmc_reset_controller(host); 1152dd8572afSManuel Lauss 1153dd8572afSManuel Lauss return mmc_resume_host(host->mmc); 1154dd8572afSManuel Lauss } 1155dd8572afSManuel Lauss #else 1156dd8572afSManuel Lauss #define au1xmmc_suspend NULL 1157dd8572afSManuel Lauss #define au1xmmc_resume NULL 1158dd8572afSManuel Lauss #endif 1159dd8572afSManuel Lauss 11601c6a0718SPierre Ossman static struct platform_driver au1xmmc_driver = { 11611c6a0718SPierre Ossman .probe = au1xmmc_probe, 11621c6a0718SPierre Ossman .remove = au1xmmc_remove, 1163dd8572afSManuel Lauss .suspend = au1xmmc_suspend, 1164dd8572afSManuel Lauss .resume = au1xmmc_resume, 11651c6a0718SPierre Ossman .driver = { 11661c6a0718SPierre Ossman .name = DRIVER_NAME, 1167bc65c724SKay Sievers .owner = THIS_MODULE, 11681c6a0718SPierre Ossman }, 11691c6a0718SPierre Ossman }; 11701c6a0718SPierre Ossman 11711c6a0718SPierre Ossman static int __init au1xmmc_init(void) 11721c6a0718SPierre Ossman { 1173c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1174c4223c2cSManuel Lauss /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride 1175c4223c2cSManuel Lauss * of 8 bits. And since devices are shared, we need to create 1176c4223c2cSManuel Lauss * our own to avoid freaking out other devices. 1177c4223c2cSManuel Lauss */ 1178c4223c2cSManuel Lauss memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); 1179c4223c2cSManuel Lauss if (!memid) 1180c4223c2cSManuel Lauss printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n"); 1181c4223c2cSManuel Lauss #endif 11821c6a0718SPierre Ossman return platform_driver_register(&au1xmmc_driver); 11831c6a0718SPierre Ossman } 11841c6a0718SPierre Ossman 11851c6a0718SPierre Ossman static void __exit au1xmmc_exit(void) 11861c6a0718SPierre Ossman { 1187c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1188c4223c2cSManuel Lauss if (memid) 1189c4223c2cSManuel Lauss au1xxx_ddma_del_device(memid); 1190c4223c2cSManuel Lauss #endif 11911c6a0718SPierre Ossman platform_driver_unregister(&au1xmmc_driver); 11921c6a0718SPierre Ossman } 11931c6a0718SPierre Ossman 11941c6a0718SPierre Ossman module_init(au1xmmc_init); 11951c6a0718SPierre Ossman module_exit(au1xmmc_exit); 11961c6a0718SPierre Ossman 11971c6a0718SPierre Ossman MODULE_AUTHOR("Advanced Micro Devices, Inc"); 11981c6a0718SPierre Ossman MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); 11991c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1200bc65c724SKay Sievers MODULE_ALIAS("platform:au1xxx-mmc"); 1201