11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (c) 2005, Advanced Micro Devices, Inc. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * Developed with help from the 2.4.30 MMC AU1XXX controller including 71c6a0718SPierre Ossman * the following copyright notices: 81c6a0718SPierre Ossman * Copyright (c) 2003-2004 Embedded Edge, LLC. 91c6a0718SPierre Ossman * Portions Copyright (C) 2002 Embedix, Inc 101c6a0718SPierre Ossman * Copyright 2002 Hewlett-Packard Company 111c6a0718SPierre Ossman 121c6a0718SPierre Ossman * 2.6 version of this driver inspired by: 131c6a0718SPierre Ossman * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, 141c6a0718SPierre Ossman * All Rights Reserved. 151c6a0718SPierre Ossman * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, 161c6a0718SPierre Ossman * All Rights Reserved. 171c6a0718SPierre Ossman * 181c6a0718SPierre Ossman 191c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 201c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 211c6a0718SPierre Ossman * published by the Free Software Foundation. 221c6a0718SPierre Ossman */ 231c6a0718SPierre Ossman 24e2d26477SManuel Lauss /* Why don't we use the SD controllers' carddetect feature? 251c6a0718SPierre Ossman * 261c6a0718SPierre Ossman * From the AU1100 MMC application guide: 271c6a0718SPierre Ossman * If the Au1100-based design is intended to support both MultiMediaCards 281c6a0718SPierre Ossman * and 1- or 4-data bit SecureDigital cards, then the solution is to 291c6a0718SPierre Ossman * connect a weak (560KOhm) pull-up resistor to connector pin 1. 301c6a0718SPierre Ossman * In doing so, a MMC card never enters SPI-mode communications, 311c6a0718SPierre Ossman * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective 321c6a0718SPierre Ossman * (the low to high transition will not occur). 331c6a0718SPierre Ossman */ 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #include <linux/module.h> 361c6a0718SPierre Ossman #include <linux/init.h> 371c6a0718SPierre Ossman #include <linux/platform_device.h> 381c6a0718SPierre Ossman #include <linux/mm.h> 391c6a0718SPierre Ossman #include <linux/interrupt.h> 401c6a0718SPierre Ossman #include <linux/dma-mapping.h> 410ada7a02SAl Viro #include <linux/scatterlist.h> 42c4223c2cSManuel Lauss #include <linux/leds.h> 431c6a0718SPierre Ossman #include <linux/mmc/host.h> 44c4223c2cSManuel Lauss 451c6a0718SPierre Ossman #include <asm/io.h> 461c6a0718SPierre Ossman #include <asm/mach-au1x00/au1000.h> 471c6a0718SPierre Ossman #include <asm/mach-au1x00/au1xxx_dbdma.h> 481c6a0718SPierre Ossman #include <asm/mach-au1x00/au1100_mmc.h> 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman #define DRIVER_NAME "au1xxx-mmc" 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman /* Set this to enable special debugging macros */ 53c4223c2cSManuel Lauss /* #define DEBUG */ 541c6a0718SPierre Ossman 551c6a0718SPierre Ossman #ifdef DEBUG 565c0a889dSManuel Lauss #define DBG(fmt, idx, args...) \ 575c0a889dSManuel Lauss printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args) 581c6a0718SPierre Ossman #else 595c0a889dSManuel Lauss #define DBG(fmt, idx, args...) do {} while (0) 601c6a0718SPierre Ossman #endif 611c6a0718SPierre Ossman 625c0a889dSManuel Lauss /* Hardware definitions */ 635c0a889dSManuel Lauss #define AU1XMMC_DESCRIPTOR_COUNT 1 64e491d230SManuel Lauss 65e491d230SManuel Lauss /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */ 66e491d230SManuel Lauss #ifdef CONFIG_SOC_AU1100 67e491d230SManuel Lauss #define AU1XMMC_DESCRIPTOR_SIZE 0x0000ffff 68e491d230SManuel Lauss #else /* Au1200 */ 69e491d230SManuel Lauss #define AU1XMMC_DESCRIPTOR_SIZE 0x003fffff 70e491d230SManuel Lauss #endif 715c0a889dSManuel Lauss 725c0a889dSManuel Lauss #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ 735c0a889dSManuel Lauss MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ 745c0a889dSManuel Lauss MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) 755c0a889dSManuel Lauss 765c0a889dSManuel Lauss /* This gives us a hard value for the stop command that we can write directly 775c0a889dSManuel Lauss * to the command register. 785c0a889dSManuel Lauss */ 795c0a889dSManuel Lauss #define STOP_CMD \ 805c0a889dSManuel Lauss (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO) 815c0a889dSManuel Lauss 825c0a889dSManuel Lauss /* This is the set of interrupts that we configure by default. */ 835c0a889dSManuel Lauss #define AU1XMMC_INTERRUPTS \ 845c0a889dSManuel Lauss (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \ 855c0a889dSManuel Lauss SD_CONFIG_CR | SD_CONFIG_I) 865c0a889dSManuel Lauss 875c0a889dSManuel Lauss /* The poll event (looking for insert/remove events runs twice a second. */ 885c0a889dSManuel Lauss #define AU1XMMC_DETECT_TIMEOUT (HZ/2) 895c0a889dSManuel Lauss 905c0a889dSManuel Lauss struct au1xmmc_host { 915c0a889dSManuel Lauss struct mmc_host *mmc; 925c0a889dSManuel Lauss struct mmc_request *mrq; 935c0a889dSManuel Lauss 945c0a889dSManuel Lauss u32 flags; 955c0a889dSManuel Lauss u32 iobase; 965c0a889dSManuel Lauss u32 clock; 975c0a889dSManuel Lauss u32 bus_width; 985c0a889dSManuel Lauss u32 power_mode; 995c0a889dSManuel Lauss 1005c0a889dSManuel Lauss int status; 1015c0a889dSManuel Lauss 1025c0a889dSManuel Lauss struct { 1035c0a889dSManuel Lauss int len; 1045c0a889dSManuel Lauss int dir; 1055c0a889dSManuel Lauss } dma; 1065c0a889dSManuel Lauss 1075c0a889dSManuel Lauss struct { 1085c0a889dSManuel Lauss int index; 1095c0a889dSManuel Lauss int offset; 1105c0a889dSManuel Lauss int len; 1115c0a889dSManuel Lauss } pio; 1125c0a889dSManuel Lauss 1135c0a889dSManuel Lauss u32 tx_chan; 1145c0a889dSManuel Lauss u32 rx_chan; 1155c0a889dSManuel Lauss 1165c0a889dSManuel Lauss int irq; 1175c0a889dSManuel Lauss 1185c0a889dSManuel Lauss struct tasklet_struct finish_task; 1195c0a889dSManuel Lauss struct tasklet_struct data_task; 1205c0a889dSManuel Lauss struct au1xmmc_platform_data *platdata; 1215c0a889dSManuel Lauss struct platform_device *pdev; 1225c0a889dSManuel Lauss struct resource *ioarea; 1235c0a889dSManuel Lauss }; 1245c0a889dSManuel Lauss 1255c0a889dSManuel Lauss /* Status flags used by the host structure */ 1265c0a889dSManuel Lauss #define HOST_F_XMIT 0x0001 1275c0a889dSManuel Lauss #define HOST_F_RECV 0x0002 1285c0a889dSManuel Lauss #define HOST_F_DMA 0x0010 1295c0a889dSManuel Lauss #define HOST_F_ACTIVE 0x0100 1305c0a889dSManuel Lauss #define HOST_F_STOP 0x1000 1315c0a889dSManuel Lauss 1325c0a889dSManuel Lauss #define HOST_S_IDLE 0x0001 1335c0a889dSManuel Lauss #define HOST_S_CMD 0x0002 1345c0a889dSManuel Lauss #define HOST_S_DATA 0x0003 1355c0a889dSManuel Lauss #define HOST_S_STOP 0x0004 1365c0a889dSManuel Lauss 1375c0a889dSManuel Lauss /* Easy access macros */ 1385c0a889dSManuel Lauss #define HOST_STATUS(h) ((h)->iobase + SD_STATUS) 1395c0a889dSManuel Lauss #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) 1405c0a889dSManuel Lauss #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) 1415c0a889dSManuel Lauss #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) 1425c0a889dSManuel Lauss #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) 1435c0a889dSManuel Lauss #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) 1445c0a889dSManuel Lauss #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) 1455c0a889dSManuel Lauss #define HOST_CMD(h) ((h)->iobase + SD_CMD) 1465c0a889dSManuel Lauss #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) 1475c0a889dSManuel Lauss #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) 1485c0a889dSManuel Lauss #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) 1495c0a889dSManuel Lauss 1505c0a889dSManuel Lauss #define DMA_CHANNEL(h) \ 1515c0a889dSManuel Lauss (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) 1525c0a889dSManuel Lauss 1531c6a0718SPierre Ossman static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) 1541c6a0718SPierre Ossman { 1551c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG(host)); 1561c6a0718SPierre Ossman val |= mask; 1571c6a0718SPierre Ossman au_writel(val, HOST_CONFIG(host)); 1581c6a0718SPierre Ossman au_sync(); 1591c6a0718SPierre Ossman } 1601c6a0718SPierre Ossman 1611c6a0718SPierre Ossman static inline void FLUSH_FIFO(struct au1xmmc_host *host) 1621c6a0718SPierre Ossman { 1631c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG2(host)); 1641c6a0718SPierre Ossman 1651c6a0718SPierre Ossman au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); 1661c6a0718SPierre Ossman au_sync_delay(1); 1671c6a0718SPierre Ossman 1681c6a0718SPierre Ossman /* SEND_STOP will turn off clock control - this re-enables it */ 1691c6a0718SPierre Ossman val &= ~SD_CONFIG2_DF; 1701c6a0718SPierre Ossman 1711c6a0718SPierre Ossman au_writel(val, HOST_CONFIG2(host)); 1721c6a0718SPierre Ossman au_sync(); 1731c6a0718SPierre Ossman } 1741c6a0718SPierre Ossman 1751c6a0718SPierre Ossman static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) 1761c6a0718SPierre Ossman { 1771c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG(host)); 1781c6a0718SPierre Ossman val &= ~mask; 1791c6a0718SPierre Ossman au_writel(val, HOST_CONFIG(host)); 1801c6a0718SPierre Ossman au_sync(); 1811c6a0718SPierre Ossman } 1821c6a0718SPierre Ossman 1831c6a0718SPierre Ossman static inline void SEND_STOP(struct au1xmmc_host *host) 1841c6a0718SPierre Ossman { 185281dd23eSManuel Lauss u32 config2; 1861c6a0718SPierre Ossman 1871c6a0718SPierre Ossman WARN_ON(host->status != HOST_S_DATA); 1881c6a0718SPierre Ossman host->status = HOST_S_STOP; 1891c6a0718SPierre Ossman 190281dd23eSManuel Lauss config2 = au_readl(HOST_CONFIG2(host)); 191281dd23eSManuel Lauss au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); 1921c6a0718SPierre Ossman au_sync(); 1931c6a0718SPierre Ossman 1941c6a0718SPierre Ossman /* Send the stop commmand */ 1951c6a0718SPierre Ossman au_writel(STOP_CMD, HOST_CMD(host)); 1961c6a0718SPierre Ossman } 1971c6a0718SPierre Ossman 1981c6a0718SPierre Ossman static void au1xmmc_set_power(struct au1xmmc_host *host, int state) 1991c6a0718SPierre Ossman { 200c4223c2cSManuel Lauss if (host->platdata && host->platdata->set_power) 201c4223c2cSManuel Lauss host->platdata->set_power(host->mmc, state); 2021c6a0718SPierre Ossman } 2031c6a0718SPierre Ossman 204e2d26477SManuel Lauss static int au1xmmc_card_inserted(struct mmc_host *mmc) 2051c6a0718SPierre Ossman { 206e2d26477SManuel Lauss struct au1xmmc_host *host = mmc_priv(mmc); 207c4223c2cSManuel Lauss 208c4223c2cSManuel Lauss if (host->platdata && host->platdata->card_inserted) 209e2d26477SManuel Lauss return !!host->platdata->card_inserted(host->mmc); 210c4223c2cSManuel Lauss 211e2d26477SManuel Lauss return -ENOSYS; 2121c6a0718SPierre Ossman } 2131c6a0718SPierre Ossman 2141c6a0718SPierre Ossman static int au1xmmc_card_readonly(struct mmc_host *mmc) 2151c6a0718SPierre Ossman { 2161c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 217c4223c2cSManuel Lauss 218c4223c2cSManuel Lauss if (host->platdata && host->platdata->card_readonly) 219e2d26477SManuel Lauss return !!host->platdata->card_readonly(mmc); 220c4223c2cSManuel Lauss 221e2d26477SManuel Lauss return -ENOSYS; 2221c6a0718SPierre Ossman } 2231c6a0718SPierre Ossman 2241c6a0718SPierre Ossman static void au1xmmc_finish_request(struct au1xmmc_host *host) 2251c6a0718SPierre Ossman { 2261c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 2271c6a0718SPierre Ossman 2281c6a0718SPierre Ossman host->mrq = NULL; 229c4223c2cSManuel Lauss host->flags &= HOST_F_ACTIVE | HOST_F_DMA; 2301c6a0718SPierre Ossman 2311c6a0718SPierre Ossman host->dma.len = 0; 2321c6a0718SPierre Ossman host->dma.dir = 0; 2331c6a0718SPierre Ossman 2341c6a0718SPierre Ossman host->pio.index = 0; 2351c6a0718SPierre Ossman host->pio.offset = 0; 2361c6a0718SPierre Ossman host->pio.len = 0; 2371c6a0718SPierre Ossman 2381c6a0718SPierre Ossman host->status = HOST_S_IDLE; 2391c6a0718SPierre Ossman 2401c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 2411c6a0718SPierre Ossman } 2421c6a0718SPierre Ossman 2431c6a0718SPierre Ossman static void au1xmmc_tasklet_finish(unsigned long param) 2441c6a0718SPierre Ossman { 2451c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *) param; 2461c6a0718SPierre Ossman au1xmmc_finish_request(host); 2471c6a0718SPierre Ossman } 2481c6a0718SPierre Ossman 2491c6a0718SPierre Ossman static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, 250be0192aaSPierre Ossman struct mmc_command *cmd, struct mmc_data *data) 2511c6a0718SPierre Ossman { 2521c6a0718SPierre Ossman u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); 2531c6a0718SPierre Ossman 2541c6a0718SPierre Ossman switch (mmc_resp_type(cmd)) { 2551c6a0718SPierre Ossman case MMC_RSP_NONE: 2561c6a0718SPierre Ossman break; 2571c6a0718SPierre Ossman case MMC_RSP_R1: 2581c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_1; 2591c6a0718SPierre Ossman break; 2601c6a0718SPierre Ossman case MMC_RSP_R1B: 2611c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_1B; 2621c6a0718SPierre Ossman break; 2631c6a0718SPierre Ossman case MMC_RSP_R2: 2641c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_2; 2651c6a0718SPierre Ossman break; 2661c6a0718SPierre Ossman case MMC_RSP_R3: 2671c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_3; 2681c6a0718SPierre Ossman break; 2691c6a0718SPierre Ossman default: 2701c6a0718SPierre Ossman printk(KERN_INFO "au1xmmc: unhandled response type %02x\n", 2711c6a0718SPierre Ossman mmc_resp_type(cmd)); 27217b0429dSPierre Ossman return -EINVAL; 2731c6a0718SPierre Ossman } 2741c6a0718SPierre Ossman 275be0192aaSPierre Ossman if (data) { 2766356a9d9SPierre Ossman if (data->flags & MMC_DATA_READ) { 277be0192aaSPierre Ossman if (data->blocks > 1) 2781c6a0718SPierre Ossman mmccmd |= SD_CMD_CT_4; 279c0f3b6c7SYoichi Yuasa else 280c0f3b6c7SYoichi Yuasa mmccmd |= SD_CMD_CT_2; 2816356a9d9SPierre Ossman } else if (data->flags & MMC_DATA_WRITE) { 282be0192aaSPierre Ossman if (data->blocks > 1) 2831c6a0718SPierre Ossman mmccmd |= SD_CMD_CT_3; 284c0f3b6c7SYoichi Yuasa else 285c0f3b6c7SYoichi Yuasa mmccmd |= SD_CMD_CT_1; 2861c6a0718SPierre Ossman } 287be0192aaSPierre Ossman } 2881c6a0718SPierre Ossman 2891c6a0718SPierre Ossman au_writel(cmd->arg, HOST_CMDARG(host)); 2901c6a0718SPierre Ossman au_sync(); 2911c6a0718SPierre Ossman 2921c6a0718SPierre Ossman if (wait) 2931c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_CR); 2941c6a0718SPierre Ossman 2951c6a0718SPierre Ossman au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); 2961c6a0718SPierre Ossman au_sync(); 2971c6a0718SPierre Ossman 2981c6a0718SPierre Ossman /* Wait for the command to go on the line */ 2995c0a889dSManuel Lauss while (au_readl(HOST_CMD(host)) & SD_CMD_GO) 3005c0a889dSManuel Lauss /* nop */; 3011c6a0718SPierre Ossman 3021c6a0718SPierre Ossman /* Wait for the command to come back */ 3031c6a0718SPierre Ossman if (wait) { 3041c6a0718SPierre Ossman u32 status = au_readl(HOST_STATUS(host)); 3051c6a0718SPierre Ossman 3061c6a0718SPierre Ossman while (!(status & SD_STATUS_CR)) 3071c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3081c6a0718SPierre Ossman 3091c6a0718SPierre Ossman /* Clear the CR status */ 3101c6a0718SPierre Ossman au_writel(SD_STATUS_CR, HOST_STATUS(host)); 3111c6a0718SPierre Ossman 3121c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_CR); 3131c6a0718SPierre Ossman } 3141c6a0718SPierre Ossman 31517b0429dSPierre Ossman return 0; 3161c6a0718SPierre Ossman } 3171c6a0718SPierre Ossman 3181c6a0718SPierre Ossman static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) 3191c6a0718SPierre Ossman { 3201c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 3211c6a0718SPierre Ossman struct mmc_data *data; 3221c6a0718SPierre Ossman u32 crc; 3231c6a0718SPierre Ossman 3245c0a889dSManuel Lauss WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP)); 3251c6a0718SPierre Ossman 3261c6a0718SPierre Ossman if (host->mrq == NULL) 3271c6a0718SPierre Ossman return; 3281c6a0718SPierre Ossman 3291c6a0718SPierre Ossman data = mrq->cmd->data; 3301c6a0718SPierre Ossman 3311c6a0718SPierre Ossman if (status == 0) 3321c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3331c6a0718SPierre Ossman 3341c6a0718SPierre Ossman /* The transaction is really over when the SD_STATUS_DB bit is clear */ 3351c6a0718SPierre Ossman while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) 3361c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3371c6a0718SPierre Ossman 33817b0429dSPierre Ossman data->error = 0; 3391c6a0718SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); 3401c6a0718SPierre Ossman 3411c6a0718SPierre Ossman /* Process any errors */ 3421c6a0718SPierre Ossman crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); 3431c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) 3441c6a0718SPierre Ossman crc |= ((status & 0x07) == 0x02) ? 0 : 1; 3451c6a0718SPierre Ossman 3461c6a0718SPierre Ossman if (crc) 34717b0429dSPierre Ossman data->error = -EILSEQ; 3481c6a0718SPierre Ossman 3491c6a0718SPierre Ossman /* Clear the CRC bits */ 3501c6a0718SPierre Ossman au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); 3511c6a0718SPierre Ossman 3521c6a0718SPierre Ossman data->bytes_xfered = 0; 3531c6a0718SPierre Ossman 35417b0429dSPierre Ossman if (!data->error) { 3551c6a0718SPierre Ossman if (host->flags & HOST_F_DMA) { 356c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 /* DBDMA */ 3571c6a0718SPierre Ossman u32 chan = DMA_CHANNEL(host); 3581c6a0718SPierre Ossman 3591c6a0718SPierre Ossman chan_tab_t *c = *((chan_tab_t **)chan); 3601c6a0718SPierre Ossman au1x_dma_chan_t *cp = c->chan_ptr; 3611c6a0718SPierre Ossman data->bytes_xfered = cp->ddma_bytecnt; 362c4223c2cSManuel Lauss #endif 3635c0a889dSManuel Lauss } else 3641c6a0718SPierre Ossman data->bytes_xfered = 3655c0a889dSManuel Lauss (data->blocks * data->blksz) - host->pio.len; 3661c6a0718SPierre Ossman } 3671c6a0718SPierre Ossman 3681c6a0718SPierre Ossman au1xmmc_finish_request(host); 3691c6a0718SPierre Ossman } 3701c6a0718SPierre Ossman 3711c6a0718SPierre Ossman static void au1xmmc_tasklet_data(unsigned long param) 3721c6a0718SPierre Ossman { 3731c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *)param; 3741c6a0718SPierre Ossman 3751c6a0718SPierre Ossman u32 status = au_readl(HOST_STATUS(host)); 3761c6a0718SPierre Ossman au1xmmc_data_complete(host, status); 3771c6a0718SPierre Ossman } 3781c6a0718SPierre Ossman 3791c6a0718SPierre Ossman #define AU1XMMC_MAX_TRANSFER 8 3801c6a0718SPierre Ossman 3811c6a0718SPierre Ossman static void au1xmmc_send_pio(struct au1xmmc_host *host) 3821c6a0718SPierre Ossman { 3835c0a889dSManuel Lauss struct mmc_data *data; 3845c0a889dSManuel Lauss int sg_len, max, count; 3855c0a889dSManuel Lauss unsigned char *sg_ptr, val; 3865c0a889dSManuel Lauss u32 status; 3871c6a0718SPierre Ossman struct scatterlist *sg; 3881c6a0718SPierre Ossman 3891c6a0718SPierre Ossman data = host->mrq->data; 3901c6a0718SPierre Ossman 3911c6a0718SPierre Ossman if (!(host->flags & HOST_F_XMIT)) 3921c6a0718SPierre Ossman return; 3931c6a0718SPierre Ossman 3941c6a0718SPierre Ossman /* This is the pointer to the data buffer */ 3951c6a0718SPierre Ossman sg = &data->sg[host->pio.index]; 39645711f1aSJens Axboe sg_ptr = sg_virt(sg) + host->pio.offset; 3971c6a0718SPierre Ossman 3981c6a0718SPierre Ossman /* This is the space left inside the buffer */ 3991c6a0718SPierre Ossman sg_len = data->sg[host->pio.index].length - host->pio.offset; 4001c6a0718SPierre Ossman 4015c0a889dSManuel Lauss /* Check if we need less than the size of the sg_buffer */ 4021c6a0718SPierre Ossman max = (sg_len > host->pio.len) ? host->pio.len : sg_len; 4035c0a889dSManuel Lauss if (max > AU1XMMC_MAX_TRANSFER) 4045c0a889dSManuel Lauss max = AU1XMMC_MAX_TRANSFER; 4051c6a0718SPierre Ossman 4061c6a0718SPierre Ossman for (count = 0; count < max; count++) { 4071c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 4081c6a0718SPierre Ossman 4091c6a0718SPierre Ossman if (!(status & SD_STATUS_TH)) 4101c6a0718SPierre Ossman break; 4111c6a0718SPierre Ossman 4121c6a0718SPierre Ossman val = *sg_ptr++; 4131c6a0718SPierre Ossman 4141c6a0718SPierre Ossman au_writel((unsigned long)val, HOST_TXPORT(host)); 4151c6a0718SPierre Ossman au_sync(); 4161c6a0718SPierre Ossman } 4171c6a0718SPierre Ossman 4181c6a0718SPierre Ossman host->pio.len -= count; 4191c6a0718SPierre Ossman host->pio.offset += count; 4201c6a0718SPierre Ossman 4211c6a0718SPierre Ossman if (count == sg_len) { 4221c6a0718SPierre Ossman host->pio.index++; 4231c6a0718SPierre Ossman host->pio.offset = 0; 4241c6a0718SPierre Ossman } 4251c6a0718SPierre Ossman 4261c6a0718SPierre Ossman if (host->pio.len == 0) { 4271c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_TH); 4281c6a0718SPierre Ossman 4291c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 4301c6a0718SPierre Ossman SEND_STOP(host); 4311c6a0718SPierre Ossman 4321c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 4331c6a0718SPierre Ossman } 4341c6a0718SPierre Ossman } 4351c6a0718SPierre Ossman 4361c6a0718SPierre Ossman static void au1xmmc_receive_pio(struct au1xmmc_host *host) 4371c6a0718SPierre Ossman { 4385c0a889dSManuel Lauss struct mmc_data *data; 4395c0a889dSManuel Lauss int max, count, sg_len = 0; 4405c0a889dSManuel Lauss unsigned char *sg_ptr = NULL; 4415c0a889dSManuel Lauss u32 status, val; 4421c6a0718SPierre Ossman struct scatterlist *sg; 4431c6a0718SPierre Ossman 4441c6a0718SPierre Ossman data = host->mrq->data; 4451c6a0718SPierre Ossman 4461c6a0718SPierre Ossman if (!(host->flags & HOST_F_RECV)) 4471c6a0718SPierre Ossman return; 4481c6a0718SPierre Ossman 4491c6a0718SPierre Ossman max = host->pio.len; 4501c6a0718SPierre Ossman 4511c6a0718SPierre Ossman if (host->pio.index < host->dma.len) { 4521c6a0718SPierre Ossman sg = &data->sg[host->pio.index]; 45345711f1aSJens Axboe sg_ptr = sg_virt(sg) + host->pio.offset; 4541c6a0718SPierre Ossman 4551c6a0718SPierre Ossman /* This is the space left inside the buffer */ 4561c6a0718SPierre Ossman sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; 4571c6a0718SPierre Ossman 4585c0a889dSManuel Lauss /* Check if we need less than the size of the sg_buffer */ 4595c0a889dSManuel Lauss if (sg_len < max) 4605c0a889dSManuel Lauss max = sg_len; 4611c6a0718SPierre Ossman } 4621c6a0718SPierre Ossman 4631c6a0718SPierre Ossman if (max > AU1XMMC_MAX_TRANSFER) 4641c6a0718SPierre Ossman max = AU1XMMC_MAX_TRANSFER; 4651c6a0718SPierre Ossman 4661c6a0718SPierre Ossman for (count = 0; count < max; count++) { 4671c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 4681c6a0718SPierre Ossman 4691c6a0718SPierre Ossman if (!(status & SD_STATUS_NE)) 4701c6a0718SPierre Ossman break; 4711c6a0718SPierre Ossman 4721c6a0718SPierre Ossman if (status & SD_STATUS_RC) { 473c4223c2cSManuel Lauss DBG("RX CRC Error [%d + %d].\n", host->pdev->id, 4741c6a0718SPierre Ossman host->pio.len, count); 4751c6a0718SPierre Ossman break; 4761c6a0718SPierre Ossman } 4771c6a0718SPierre Ossman 4781c6a0718SPierre Ossman if (status & SD_STATUS_RO) { 479c4223c2cSManuel Lauss DBG("RX Overrun [%d + %d]\n", host->pdev->id, 4801c6a0718SPierre Ossman host->pio.len, count); 4811c6a0718SPierre Ossman break; 4821c6a0718SPierre Ossman } 4831c6a0718SPierre Ossman else if (status & SD_STATUS_RU) { 484c4223c2cSManuel Lauss DBG("RX Underrun [%d + %d]\n", host->pdev->id, 4851c6a0718SPierre Ossman host->pio.len, count); 4861c6a0718SPierre Ossman break; 4871c6a0718SPierre Ossman } 4881c6a0718SPierre Ossman 4891c6a0718SPierre Ossman val = au_readl(HOST_RXPORT(host)); 4901c6a0718SPierre Ossman 4911c6a0718SPierre Ossman if (sg_ptr) 4921c6a0718SPierre Ossman *sg_ptr++ = (unsigned char)(val & 0xFF); 4931c6a0718SPierre Ossman } 4941c6a0718SPierre Ossman 4951c6a0718SPierre Ossman host->pio.len -= count; 4961c6a0718SPierre Ossman host->pio.offset += count; 4971c6a0718SPierre Ossman 4981c6a0718SPierre Ossman if (sg_len && count == sg_len) { 4991c6a0718SPierre Ossman host->pio.index++; 5001c6a0718SPierre Ossman host->pio.offset = 0; 5011c6a0718SPierre Ossman } 5021c6a0718SPierre Ossman 5031c6a0718SPierre Ossman if (host->pio.len == 0) { 5045c0a889dSManuel Lauss /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 5051c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_NE); 5061c6a0718SPierre Ossman 5071c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 5081c6a0718SPierre Ossman SEND_STOP(host); 5091c6a0718SPierre Ossman 5101c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 5111c6a0718SPierre Ossman } 5121c6a0718SPierre Ossman } 5131c6a0718SPierre Ossman 5145c0a889dSManuel Lauss /* This is called when a command has been completed - grab the response 5155c0a889dSManuel Lauss * and check for errors. Then start the data transfer if it is indicated. 5161c6a0718SPierre Ossman */ 5171c6a0718SPierre Ossman static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) 5181c6a0718SPierre Ossman { 5191c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 5201c6a0718SPierre Ossman struct mmc_command *cmd; 5215c0a889dSManuel Lauss u32 r[4]; 5225c0a889dSManuel Lauss int i, trans; 5231c6a0718SPierre Ossman 5241c6a0718SPierre Ossman if (!host->mrq) 5251c6a0718SPierre Ossman return; 5261c6a0718SPierre Ossman 5271c6a0718SPierre Ossman cmd = mrq->cmd; 52817b0429dSPierre Ossman cmd->error = 0; 5291c6a0718SPierre Ossman 5301c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 5311c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) { 5321c6a0718SPierre Ossman r[0] = au_readl(host->iobase + SD_RESP3); 5331c6a0718SPierre Ossman r[1] = au_readl(host->iobase + SD_RESP2); 5341c6a0718SPierre Ossman r[2] = au_readl(host->iobase + SD_RESP1); 5351c6a0718SPierre Ossman r[3] = au_readl(host->iobase + SD_RESP0); 5361c6a0718SPierre Ossman 5371c6a0718SPierre Ossman /* The CRC is omitted from the response, so really 5381c6a0718SPierre Ossman * we only got 120 bytes, but the engine expects 5395c0a889dSManuel Lauss * 128 bits, so we have to shift things up. 5401c6a0718SPierre Ossman */ 5411c6a0718SPierre Ossman for (i = 0; i < 4; i++) { 5421c6a0718SPierre Ossman cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; 5431c6a0718SPierre Ossman if (i != 3) 5441c6a0718SPierre Ossman cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; 5451c6a0718SPierre Ossman } 5461c6a0718SPierre Ossman } else { 5471c6a0718SPierre Ossman /* Techincally, we should be getting all 48 bits of 5481c6a0718SPierre Ossman * the response (SD_RESP1 + SD_RESP2), but because 5491c6a0718SPierre Ossman * our response omits the CRC, our data ends up 5501c6a0718SPierre Ossman * being shifted 8 bits to the right. In this case, 5511c6a0718SPierre Ossman * that means that the OSR data starts at bit 31, 5525c0a889dSManuel Lauss * so we can just read RESP0 and return that. 5531c6a0718SPierre Ossman */ 5541c6a0718SPierre Ossman cmd->resp[0] = au_readl(host->iobase + SD_RESP0); 5551c6a0718SPierre Ossman } 5561c6a0718SPierre Ossman } 5571c6a0718SPierre Ossman 5581c6a0718SPierre Ossman /* Figure out errors */ 5591c6a0718SPierre Ossman if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) 56017b0429dSPierre Ossman cmd->error = -EILSEQ; 5611c6a0718SPierre Ossman 5621c6a0718SPierre Ossman trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); 5631c6a0718SPierre Ossman 56417b0429dSPierre Ossman if (!trans || cmd->error) { 5651c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); 5661c6a0718SPierre Ossman tasklet_schedule(&host->finish_task); 5671c6a0718SPierre Ossman return; 5681c6a0718SPierre Ossman } 5691c6a0718SPierre Ossman 5701c6a0718SPierre Ossman host->status = HOST_S_DATA; 5711c6a0718SPierre Ossman 5721c6a0718SPierre Ossman if (host->flags & HOST_F_DMA) { 573c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 /* DBDMA */ 5741c6a0718SPierre Ossman u32 channel = DMA_CHANNEL(host); 5751c6a0718SPierre Ossman 5761c6a0718SPierre Ossman /* Start the DMA as soon as the buffer gets something in it */ 5771c6a0718SPierre Ossman 5781c6a0718SPierre Ossman if (host->flags & HOST_F_RECV) { 5791c6a0718SPierre Ossman u32 mask = SD_STATUS_DB | SD_STATUS_NE; 5801c6a0718SPierre Ossman 5811c6a0718SPierre Ossman while((status & mask) != mask) 5821c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 5831c6a0718SPierre Ossman } 5841c6a0718SPierre Ossman 5851c6a0718SPierre Ossman au1xxx_dbdma_start(channel); 586c4223c2cSManuel Lauss #endif 5871c6a0718SPierre Ossman } 5881c6a0718SPierre Ossman } 5891c6a0718SPierre Ossman 5901c6a0718SPierre Ossman static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) 5911c6a0718SPierre Ossman { 5921c6a0718SPierre Ossman unsigned int pbus = get_au1x00_speed(); 5931c6a0718SPierre Ossman unsigned int divisor; 5941c6a0718SPierre Ossman u32 config; 5951c6a0718SPierre Ossman 5961c6a0718SPierre Ossman /* From databook: 5975c0a889dSManuel Lauss * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1 5981c6a0718SPierre Ossman */ 5991c6a0718SPierre Ossman pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2); 6001c6a0718SPierre Ossman pbus /= 2; 6011c6a0718SPierre Ossman divisor = ((pbus / rate) / 2) - 1; 6021c6a0718SPierre Ossman 6031c6a0718SPierre Ossman config = au_readl(HOST_CONFIG(host)); 6041c6a0718SPierre Ossman 6051c6a0718SPierre Ossman config &= ~(SD_CONFIG_DIV); 6061c6a0718SPierre Ossman config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; 6071c6a0718SPierre Ossman 6081c6a0718SPierre Ossman au_writel(config, HOST_CONFIG(host)); 6091c6a0718SPierre Ossman au_sync(); 6101c6a0718SPierre Ossman } 6111c6a0718SPierre Ossman 6125c0a889dSManuel Lauss static int au1xmmc_prepare_data(struct au1xmmc_host *host, 6135c0a889dSManuel Lauss struct mmc_data *data) 6141c6a0718SPierre Ossman { 6151c6a0718SPierre Ossman int datalen = data->blocks * data->blksz; 6161c6a0718SPierre Ossman 6171c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 6181c6a0718SPierre Ossman host->flags |= HOST_F_RECV; 6191c6a0718SPierre Ossman else 6201c6a0718SPierre Ossman host->flags |= HOST_F_XMIT; 6211c6a0718SPierre Ossman 6221c6a0718SPierre Ossman if (host->mrq->stop) 6231c6a0718SPierre Ossman host->flags |= HOST_F_STOP; 6241c6a0718SPierre Ossman 6251c6a0718SPierre Ossman host->dma.dir = DMA_BIDIRECTIONAL; 6261c6a0718SPierre Ossman 6271c6a0718SPierre Ossman host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, 6281c6a0718SPierre Ossman data->sg_len, host->dma.dir); 6291c6a0718SPierre Ossman 6301c6a0718SPierre Ossman if (host->dma.len == 0) 63117b0429dSPierre Ossman return -ETIMEDOUT; 6321c6a0718SPierre Ossman 6331c6a0718SPierre Ossman au_writel(data->blksz - 1, HOST_BLKSIZE(host)); 6341c6a0718SPierre Ossman 6351c6a0718SPierre Ossman if (host->flags & HOST_F_DMA) { 636c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 /* DBDMA */ 6371c6a0718SPierre Ossman int i; 6381c6a0718SPierre Ossman u32 channel = DMA_CHANNEL(host); 6391c6a0718SPierre Ossman 6401c6a0718SPierre Ossman au1xxx_dbdma_stop(channel); 6411c6a0718SPierre Ossman 6421c6a0718SPierre Ossman for (i = 0; i < host->dma.len; i++) { 6431c6a0718SPierre Ossman u32 ret = 0, flags = DDMA_FLAGS_NOIE; 6441c6a0718SPierre Ossman struct scatterlist *sg = &data->sg[i]; 6451c6a0718SPierre Ossman int sg_len = sg->length; 6461c6a0718SPierre Ossman 6471c6a0718SPierre Ossman int len = (datalen > sg_len) ? sg_len : datalen; 6481c6a0718SPierre Ossman 6491c6a0718SPierre Ossman if (i == host->dma.len - 1) 6501c6a0718SPierre Ossman flags = DDMA_FLAGS_IE; 6511c6a0718SPierre Ossman 6521c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) { 653ea071cc7SManuel Lauss ret = au1xxx_dbdma_put_source(channel, 654963accbcSManuel Lauss sg_phys(sg), len, flags); 6555c0a889dSManuel Lauss } else { 656ea071cc7SManuel Lauss ret = au1xxx_dbdma_put_dest(channel, 657963accbcSManuel Lauss sg_phys(sg), len, flags); 6581c6a0718SPierre Ossman } 6591c6a0718SPierre Ossman 6601c6a0718SPierre Ossman if (!ret) 6611c6a0718SPierre Ossman goto dataerr; 6621c6a0718SPierre Ossman 6631c6a0718SPierre Ossman datalen -= len; 6641c6a0718SPierre Ossman } 665c4223c2cSManuel Lauss #endif 6665c0a889dSManuel Lauss } else { 6671c6a0718SPierre Ossman host->pio.index = 0; 6681c6a0718SPierre Ossman host->pio.offset = 0; 6691c6a0718SPierre Ossman host->pio.len = datalen; 6701c6a0718SPierre Ossman 6711c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) 6721c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_TH); 6731c6a0718SPierre Ossman else 6741c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_NE); 6755c0a889dSManuel Lauss /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 6761c6a0718SPierre Ossman } 6771c6a0718SPierre Ossman 67817b0429dSPierre Ossman return 0; 6791c6a0718SPierre Ossman 6801c6a0718SPierre Ossman dataerr: 681c4223c2cSManuel Lauss dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 682c4223c2cSManuel Lauss host->dma.dir); 68317b0429dSPierre Ossman return -ETIMEDOUT; 6841c6a0718SPierre Ossman } 6851c6a0718SPierre Ossman 6865c0a889dSManuel Lauss /* This actually starts a command or data transaction */ 6871c6a0718SPierre Ossman static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) 6881c6a0718SPierre Ossman { 6891c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 69017b0429dSPierre Ossman int ret = 0; 6911c6a0718SPierre Ossman 6921c6a0718SPierre Ossman WARN_ON(irqs_disabled()); 6931c6a0718SPierre Ossman WARN_ON(host->status != HOST_S_IDLE); 6941c6a0718SPierre Ossman 6951c6a0718SPierre Ossman host->mrq = mrq; 6961c6a0718SPierre Ossman host->status = HOST_S_CMD; 6971c6a0718SPierre Ossman 69888b8d9a8SManuel Lauss /* fail request immediately if no card is present */ 699e2d26477SManuel Lauss if (0 == au1xmmc_card_inserted(mmc)) { 70088b8d9a8SManuel Lauss mrq->cmd->error = -ENOMEDIUM; 70188b8d9a8SManuel Lauss au1xmmc_finish_request(host); 70288b8d9a8SManuel Lauss return; 70388b8d9a8SManuel Lauss } 70488b8d9a8SManuel Lauss 7051c6a0718SPierre Ossman if (mrq->data) { 7061c6a0718SPierre Ossman FLUSH_FIFO(host); 7071c6a0718SPierre Ossman ret = au1xmmc_prepare_data(host, mrq->data); 7081c6a0718SPierre Ossman } 7091c6a0718SPierre Ossman 71017b0429dSPierre Ossman if (!ret) 711be0192aaSPierre Ossman ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data); 7121c6a0718SPierre Ossman 71317b0429dSPierre Ossman if (ret) { 7141c6a0718SPierre Ossman mrq->cmd->error = ret; 7151c6a0718SPierre Ossman au1xmmc_finish_request(host); 7161c6a0718SPierre Ossman } 7171c6a0718SPierre Ossman } 7181c6a0718SPierre Ossman 7191c6a0718SPierre Ossman static void au1xmmc_reset_controller(struct au1xmmc_host *host) 7201c6a0718SPierre Ossman { 7211c6a0718SPierre Ossman /* Apply the clock */ 7221c6a0718SPierre Ossman au_writel(SD_ENABLE_CE, HOST_ENABLE(host)); 7231c6a0718SPierre Ossman au_sync_delay(1); 7241c6a0718SPierre Ossman 7251c6a0718SPierre Ossman au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); 7261c6a0718SPierre Ossman au_sync_delay(5); 7271c6a0718SPierre Ossman 7281c6a0718SPierre Ossman au_writel(~0, HOST_STATUS(host)); 7291c6a0718SPierre Ossman au_sync(); 7301c6a0718SPierre Ossman 7311c6a0718SPierre Ossman au_writel(0, HOST_BLKSIZE(host)); 7321c6a0718SPierre Ossman au_writel(0x001fffff, HOST_TIMEOUT(host)); 7331c6a0718SPierre Ossman au_sync(); 7341c6a0718SPierre Ossman 7351c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 7361c6a0718SPierre Ossman au_sync(); 7371c6a0718SPierre Ossman 7381c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); 7391c6a0718SPierre Ossman au_sync_delay(1); 7401c6a0718SPierre Ossman 7411c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 7421c6a0718SPierre Ossman au_sync(); 7431c6a0718SPierre Ossman 7441c6a0718SPierre Ossman /* Configure interrupts */ 7451c6a0718SPierre Ossman au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); 7461c6a0718SPierre Ossman au_sync(); 7471c6a0718SPierre Ossman } 7481c6a0718SPierre Ossman 7491c6a0718SPierre Ossman 7501c6a0718SPierre Ossman static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 7511c6a0718SPierre Ossman { 7521c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 753281dd23eSManuel Lauss u32 config2; 7541c6a0718SPierre Ossman 7551c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) 7561c6a0718SPierre Ossman au1xmmc_set_power(host, 0); 7571c6a0718SPierre Ossman else if (ios->power_mode == MMC_POWER_ON) { 7581c6a0718SPierre Ossman au1xmmc_set_power(host, 1); 7591c6a0718SPierre Ossman } 7601c6a0718SPierre Ossman 7611c6a0718SPierre Ossman if (ios->clock && ios->clock != host->clock) { 7621c6a0718SPierre Ossman au1xmmc_set_clock(host, ios->clock); 7631c6a0718SPierre Ossman host->clock = ios->clock; 7641c6a0718SPierre Ossman } 765281dd23eSManuel Lauss 766281dd23eSManuel Lauss config2 = au_readl(HOST_CONFIG2(host)); 767281dd23eSManuel Lauss switch (ios->bus_width) { 768281dd23eSManuel Lauss case MMC_BUS_WIDTH_4: 769281dd23eSManuel Lauss config2 |= SD_CONFIG2_WB; 770281dd23eSManuel Lauss break; 771281dd23eSManuel Lauss case MMC_BUS_WIDTH_1: 772281dd23eSManuel Lauss config2 &= ~SD_CONFIG2_WB; 773281dd23eSManuel Lauss break; 774281dd23eSManuel Lauss } 775281dd23eSManuel Lauss au_writel(config2, HOST_CONFIG2(host)); 776281dd23eSManuel Lauss au_sync(); 7771c6a0718SPierre Ossman } 7781c6a0718SPierre Ossman 779c4223c2cSManuel Lauss #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) 780c4223c2cSManuel Lauss #define STATUS_DATA_IN (SD_STATUS_NE) 781c4223c2cSManuel Lauss #define STATUS_DATA_OUT (SD_STATUS_TH) 782c4223c2cSManuel Lauss 783c4223c2cSManuel Lauss static irqreturn_t au1xmmc_irq(int irq, void *dev_id) 784c4223c2cSManuel Lauss { 785c4223c2cSManuel Lauss struct au1xmmc_host *host = dev_id; 786c4223c2cSManuel Lauss u32 status; 787c4223c2cSManuel Lauss 788c4223c2cSManuel Lauss status = au_readl(HOST_STATUS(host)); 789c4223c2cSManuel Lauss 790c4223c2cSManuel Lauss if (!(status & SD_STATUS_I)) 791c4223c2cSManuel Lauss return IRQ_NONE; /* not ours */ 792c4223c2cSManuel Lauss 79320f522ffSManuel Lauss if (status & SD_STATUS_SI) /* SDIO */ 79420f522ffSManuel Lauss mmc_signal_sdio_irq(host->mmc); 79520f522ffSManuel Lauss 796c4223c2cSManuel Lauss if (host->mrq && (status & STATUS_TIMEOUT)) { 797c4223c2cSManuel Lauss if (status & SD_STATUS_RAT) 798c4223c2cSManuel Lauss host->mrq->cmd->error = -ETIMEDOUT; 799c4223c2cSManuel Lauss else if (status & SD_STATUS_DT) 800c4223c2cSManuel Lauss host->mrq->data->error = -ETIMEDOUT; 801c4223c2cSManuel Lauss 802c4223c2cSManuel Lauss /* In PIO mode, interrupts might still be enabled */ 803c4223c2cSManuel Lauss IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); 804c4223c2cSManuel Lauss 805c4223c2cSManuel Lauss /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ 806c4223c2cSManuel Lauss tasklet_schedule(&host->finish_task); 807c4223c2cSManuel Lauss } 808c4223c2cSManuel Lauss #if 0 809c4223c2cSManuel Lauss else if (status & SD_STATUS_DD) { 810c4223c2cSManuel Lauss /* Sometimes we get a DD before a NE in PIO mode */ 811c4223c2cSManuel Lauss if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) 812c4223c2cSManuel Lauss au1xmmc_receive_pio(host); 813c4223c2cSManuel Lauss else { 814c4223c2cSManuel Lauss au1xmmc_data_complete(host, status); 815c4223c2cSManuel Lauss /* tasklet_schedule(&host->data_task); */ 816c4223c2cSManuel Lauss } 817c4223c2cSManuel Lauss } 818c4223c2cSManuel Lauss #endif 819c4223c2cSManuel Lauss else if (status & SD_STATUS_CR) { 820c4223c2cSManuel Lauss if (host->status == HOST_S_CMD) 821c4223c2cSManuel Lauss au1xmmc_cmd_complete(host, status); 822c4223c2cSManuel Lauss 823c4223c2cSManuel Lauss } else if (!(host->flags & HOST_F_DMA)) { 824c4223c2cSManuel Lauss if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) 825c4223c2cSManuel Lauss au1xmmc_send_pio(host); 826c4223c2cSManuel Lauss else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) 827c4223c2cSManuel Lauss au1xmmc_receive_pio(host); 828c4223c2cSManuel Lauss 829c4223c2cSManuel Lauss } else if (status & 0x203F3C70) { 830c4223c2cSManuel Lauss DBG("Unhandled status %8.8x\n", host->pdev->id, 831c4223c2cSManuel Lauss status); 832c4223c2cSManuel Lauss } 833c4223c2cSManuel Lauss 834c4223c2cSManuel Lauss au_writel(status, HOST_STATUS(host)); 835c4223c2cSManuel Lauss au_sync(); 836c4223c2cSManuel Lauss 837c4223c2cSManuel Lauss return IRQ_HANDLED; 838c4223c2cSManuel Lauss } 839c4223c2cSManuel Lauss 840c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 841c4223c2cSManuel Lauss /* 8bit memory DMA device */ 842c4223c2cSManuel Lauss static dbdev_tab_t au1xmmc_mem_dbdev = { 843c4223c2cSManuel Lauss .dev_id = DSCR_CMD0_ALWAYS, 844c4223c2cSManuel Lauss .dev_flags = DEV_FLAGS_ANYUSE, 845c4223c2cSManuel Lauss .dev_tsize = 0, 846c4223c2cSManuel Lauss .dev_devwidth = 8, 847c4223c2cSManuel Lauss .dev_physaddr = 0x00000000, 848c4223c2cSManuel Lauss .dev_intlevel = 0, 849c4223c2cSManuel Lauss .dev_intpolarity = 0, 850c4223c2cSManuel Lauss }; 851c4223c2cSManuel Lauss static int memid; 852c4223c2cSManuel Lauss 853c4223c2cSManuel Lauss static void au1xmmc_dbdma_callback(int irq, void *dev_id) 8541c6a0718SPierre Ossman { 8551c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; 8561c6a0718SPierre Ossman 8571c6a0718SPierre Ossman /* Avoid spurious interrupts */ 8581c6a0718SPierre Ossman if (!host->mrq) 8591c6a0718SPierre Ossman return; 8601c6a0718SPierre Ossman 8611c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 8621c6a0718SPierre Ossman SEND_STOP(host); 8631c6a0718SPierre Ossman 8641c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 8651c6a0718SPierre Ossman } 8661c6a0718SPierre Ossman 867c4223c2cSManuel Lauss static int au1xmmc_dbdma_init(struct au1xmmc_host *host) 8681c6a0718SPierre Ossman { 869c4223c2cSManuel Lauss struct resource *res; 870c4223c2cSManuel Lauss int txid, rxid; 8711c6a0718SPierre Ossman 872c4223c2cSManuel Lauss res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); 873c4223c2cSManuel Lauss if (!res) 874c4223c2cSManuel Lauss return -ENODEV; 875c4223c2cSManuel Lauss txid = res->start; 8761c6a0718SPierre Ossman 877c4223c2cSManuel Lauss res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); 878c4223c2cSManuel Lauss if (!res) 879c4223c2cSManuel Lauss return -ENODEV; 880c4223c2cSManuel Lauss rxid = res->start; 8811c6a0718SPierre Ossman 882c4223c2cSManuel Lauss if (!memid) 883c4223c2cSManuel Lauss return -ENODEV; 8841c6a0718SPierre Ossman 885c4223c2cSManuel Lauss host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, 886c4223c2cSManuel Lauss au1xmmc_dbdma_callback, (void *)host); 887c4223c2cSManuel Lauss if (!host->tx_chan) { 888c4223c2cSManuel Lauss dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); 889c4223c2cSManuel Lauss return -ENODEV; 8901c6a0718SPierre Ossman } 8911c6a0718SPierre Ossman 892c4223c2cSManuel Lauss host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, 893c4223c2cSManuel Lauss au1xmmc_dbdma_callback, (void *)host); 894c4223c2cSManuel Lauss if (!host->rx_chan) { 895c4223c2cSManuel Lauss dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); 896c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->tx_chan); 897c4223c2cSManuel Lauss return -ENODEV; 898c4223c2cSManuel Lauss } 8991c6a0718SPierre Ossman 900c4223c2cSManuel Lauss au1xxx_dbdma_set_devwidth(host->tx_chan, 8); 901c4223c2cSManuel Lauss au1xxx_dbdma_set_devwidth(host->rx_chan, 8); 902c4223c2cSManuel Lauss 903c4223c2cSManuel Lauss au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); 904c4223c2cSManuel Lauss au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); 905c4223c2cSManuel Lauss 906c4223c2cSManuel Lauss /* DBDMA is good to go */ 907c4223c2cSManuel Lauss host->flags |= HOST_F_DMA; 908c4223c2cSManuel Lauss 909c4223c2cSManuel Lauss return 0; 910c4223c2cSManuel Lauss } 911c4223c2cSManuel Lauss 912c4223c2cSManuel Lauss static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) 913c4223c2cSManuel Lauss { 914c4223c2cSManuel Lauss if (host->flags & HOST_F_DMA) { 915c4223c2cSManuel Lauss host->flags &= ~HOST_F_DMA; 916c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->tx_chan); 917c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->rx_chan); 9181c6a0718SPierre Ossman } 9191c6a0718SPierre Ossman } 9201c6a0718SPierre Ossman #endif 9211c6a0718SPierre Ossman 92220f522ffSManuel Lauss static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) 92320f522ffSManuel Lauss { 92420f522ffSManuel Lauss struct au1xmmc_host *host = mmc_priv(mmc); 92520f522ffSManuel Lauss 92620f522ffSManuel Lauss if (en) 92720f522ffSManuel Lauss IRQ_ON(host, SD_CONFIG_SI); 92820f522ffSManuel Lauss else 92920f522ffSManuel Lauss IRQ_OFF(host, SD_CONFIG_SI); 93020f522ffSManuel Lauss } 93120f522ffSManuel Lauss 9321c6a0718SPierre Ossman static const struct mmc_host_ops au1xmmc_ops = { 9331c6a0718SPierre Ossman .request = au1xmmc_request, 9341c6a0718SPierre Ossman .set_ios = au1xmmc_set_ios, 9351c6a0718SPierre Ossman .get_ro = au1xmmc_card_readonly, 936e2d26477SManuel Lauss .get_cd = au1xmmc_card_inserted, 93720f522ffSManuel Lauss .enable_sdio_irq = au1xmmc_enable_sdio_irq, 9381c6a0718SPierre Ossman }; 9391c6a0718SPierre Ossman 940c4223c2cSManuel Lauss static int __devinit au1xmmc_probe(struct platform_device *pdev) 941c4223c2cSManuel Lauss { 942c4223c2cSManuel Lauss struct mmc_host *mmc; 943c4223c2cSManuel Lauss struct au1xmmc_host *host; 944c4223c2cSManuel Lauss struct resource *r; 945c4223c2cSManuel Lauss int ret; 946c4223c2cSManuel Lauss 947c4223c2cSManuel Lauss mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); 9481c6a0718SPierre Ossman if (!mmc) { 949c4223c2cSManuel Lauss dev_err(&pdev->dev, "no memory for mmc_host\n"); 950c4223c2cSManuel Lauss ret = -ENOMEM; 951c4223c2cSManuel Lauss goto out0; 952c4223c2cSManuel Lauss } 953c4223c2cSManuel Lauss 954c4223c2cSManuel Lauss host = mmc_priv(mmc); 955c4223c2cSManuel Lauss host->mmc = mmc; 956c4223c2cSManuel Lauss host->platdata = pdev->dev.platform_data; 957c4223c2cSManuel Lauss host->pdev = pdev; 958c4223c2cSManuel Lauss 959c4223c2cSManuel Lauss ret = -ENODEV; 960c4223c2cSManuel Lauss r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 961c4223c2cSManuel Lauss if (!r) { 962c4223c2cSManuel Lauss dev_err(&pdev->dev, "no mmio defined\n"); 963c4223c2cSManuel Lauss goto out1; 964c4223c2cSManuel Lauss } 965c4223c2cSManuel Lauss 966c4223c2cSManuel Lauss host->ioarea = request_mem_region(r->start, r->end - r->start + 1, 967c4223c2cSManuel Lauss pdev->name); 968c4223c2cSManuel Lauss if (!host->ioarea) { 969c4223c2cSManuel Lauss dev_err(&pdev->dev, "mmio already in use\n"); 970c4223c2cSManuel Lauss goto out1; 971c4223c2cSManuel Lauss } 972c4223c2cSManuel Lauss 973c4223c2cSManuel Lauss host->iobase = (unsigned long)ioremap(r->start, 0x3c); 974c4223c2cSManuel Lauss if (!host->iobase) { 975c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot remap mmio\n"); 976c4223c2cSManuel Lauss goto out2; 977c4223c2cSManuel Lauss } 978c4223c2cSManuel Lauss 979c4223c2cSManuel Lauss r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 980c4223c2cSManuel Lauss if (!r) { 981c4223c2cSManuel Lauss dev_err(&pdev->dev, "no IRQ defined\n"); 982c4223c2cSManuel Lauss goto out3; 983c4223c2cSManuel Lauss } 984c4223c2cSManuel Lauss 985c4223c2cSManuel Lauss host->irq = r->start; 986c4223c2cSManuel Lauss /* IRQ is shared among both SD controllers */ 987c4223c2cSManuel Lauss ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED, 988c4223c2cSManuel Lauss DRIVER_NAME, host); 989c4223c2cSManuel Lauss if (ret) { 990c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot grab IRQ\n"); 991c4223c2cSManuel Lauss goto out3; 9921c6a0718SPierre Ossman } 9931c6a0718SPierre Ossman 9941c6a0718SPierre Ossman mmc->ops = &au1xmmc_ops; 9951c6a0718SPierre Ossman 9961c6a0718SPierre Ossman mmc->f_min = 450000; 9971c6a0718SPierre Ossman mmc->f_max = 24000000; 9981c6a0718SPierre Ossman 9991c6a0718SPierre Ossman mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; 10001c6a0718SPierre Ossman mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; 10011c6a0718SPierre Ossman 10021c6a0718SPierre Ossman mmc->max_blk_size = 2048; 10031c6a0718SPierre Ossman mmc->max_blk_count = 512; 10041c6a0718SPierre Ossman 10051c6a0718SPierre Ossman mmc->ocr_avail = AU1XMMC_OCR; 100620f522ffSManuel Lauss mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 10071c6a0718SPierre Ossman 10081c6a0718SPierre Ossman host->status = HOST_S_IDLE; 10091c6a0718SPierre Ossman 1010c4223c2cSManuel Lauss /* board-specific carddetect setup, if any */ 1011c4223c2cSManuel Lauss if (host->platdata && host->platdata->cd_setup) { 1012c4223c2cSManuel Lauss ret = host->platdata->cd_setup(mmc, 1); 1013c4223c2cSManuel Lauss if (ret) { 1014e2d26477SManuel Lauss dev_warn(&pdev->dev, "board CD setup failed\n"); 1015e2d26477SManuel Lauss mmc->caps |= MMC_CAP_NEEDS_POLL; 1016c4223c2cSManuel Lauss } 1017e2d26477SManuel Lauss } else 1018e2d26477SManuel Lauss mmc->caps |= MMC_CAP_NEEDS_POLL; 10191c6a0718SPierre Ossman 10201c6a0718SPierre Ossman tasklet_init(&host->data_task, au1xmmc_tasklet_data, 10211c6a0718SPierre Ossman (unsigned long)host); 10221c6a0718SPierre Ossman 10231c6a0718SPierre Ossman tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, 10241c6a0718SPierre Ossman (unsigned long)host); 10251c6a0718SPierre Ossman 1026c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1027c4223c2cSManuel Lauss ret = au1xmmc_dbdma_init(host); 1028c4223c2cSManuel Lauss if (ret) 1029c4223c2cSManuel Lauss printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n"); 1030c4223c2cSManuel Lauss #endif 10311c6a0718SPierre Ossman 1032c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1033c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) { 1034c4223c2cSManuel Lauss struct led_classdev *led = host->platdata->led; 1035c4223c2cSManuel Lauss led->name = mmc_hostname(mmc); 1036c4223c2cSManuel Lauss led->brightness = LED_OFF; 1037c4223c2cSManuel Lauss led->default_trigger = mmc_hostname(mmc); 1038c4223c2cSManuel Lauss ret = led_classdev_register(mmc_dev(mmc), led); 1039c4223c2cSManuel Lauss if (ret) 1040c4223c2cSManuel Lauss goto out5; 1041c4223c2cSManuel Lauss } 1042c4223c2cSManuel Lauss #endif 10431c6a0718SPierre Ossman 10441c6a0718SPierre Ossman au1xmmc_reset_controller(host); 10451c6a0718SPierre Ossman 1046c4223c2cSManuel Lauss ret = mmc_add_host(mmc); 1047c4223c2cSManuel Lauss if (ret) { 1048c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot add mmc host\n"); 1049c4223c2cSManuel Lauss goto out6; 1050c4223c2cSManuel Lauss } 10511c6a0718SPierre Ossman 1052dd8572afSManuel Lauss platform_set_drvdata(pdev, host); 1053c4223c2cSManuel Lauss 1054c4223c2cSManuel Lauss printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X" 1055c4223c2cSManuel Lauss " (mode=%s)\n", pdev->id, host->iobase, 1056c4223c2cSManuel Lauss host->flags & HOST_F_DMA ? "dma" : "pio"); 10571c6a0718SPierre Ossman 1058c4223c2cSManuel Lauss return 0; /* all ok */ 10591c6a0718SPierre Ossman 1060c4223c2cSManuel Lauss out6: 1061c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1062c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) 1063c4223c2cSManuel Lauss led_classdev_unregister(host->platdata->led); 1064c4223c2cSManuel Lauss out5: 1065c4223c2cSManuel Lauss #endif 1066c4223c2cSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1067c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1068c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1069c4223c2cSManuel Lauss au_sync(); 10701c6a0718SPierre Ossman 1071c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1072c4223c2cSManuel Lauss au1xmmc_dbdma_shutdown(host); 1073c4223c2cSManuel Lauss #endif 10741c6a0718SPierre Ossman 10751c6a0718SPierre Ossman tasklet_kill(&host->data_task); 10761c6a0718SPierre Ossman tasklet_kill(&host->finish_task); 10771c6a0718SPierre Ossman 1078e2d26477SManuel Lauss if (host->platdata && host->platdata->cd_setup && 1079e2d26477SManuel Lauss !(mmc->caps & MMC_CAP_NEEDS_POLL)) 1080c4223c2cSManuel Lauss host->platdata->cd_setup(mmc, 0); 1081e2d26477SManuel Lauss 1082c4223c2cSManuel Lauss free_irq(host->irq, host); 1083c4223c2cSManuel Lauss out3: 1084c4223c2cSManuel Lauss iounmap((void *)host->iobase); 1085c4223c2cSManuel Lauss out2: 1086c4223c2cSManuel Lauss release_resource(host->ioarea); 1087c4223c2cSManuel Lauss kfree(host->ioarea); 1088c4223c2cSManuel Lauss out1: 1089c4223c2cSManuel Lauss mmc_free_host(mmc); 1090c4223c2cSManuel Lauss out0: 1091c4223c2cSManuel Lauss return ret; 10921c6a0718SPierre Ossman } 10931c6a0718SPierre Ossman 1094c4223c2cSManuel Lauss static int __devexit au1xmmc_remove(struct platform_device *pdev) 1095c4223c2cSManuel Lauss { 1096dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1097c4223c2cSManuel Lauss 1098dd8572afSManuel Lauss if (host) { 1099dd8572afSManuel Lauss mmc_remove_host(host->mmc); 1100c4223c2cSManuel Lauss 1101c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1102c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) 1103c4223c2cSManuel Lauss led_classdev_unregister(host->platdata->led); 1104c4223c2cSManuel Lauss #endif 1105c4223c2cSManuel Lauss 1106e2d26477SManuel Lauss if (host->platdata && host->platdata->cd_setup && 1107dd8572afSManuel Lauss !(host->mmc->caps & MMC_CAP_NEEDS_POLL)) 1108dd8572afSManuel Lauss host->platdata->cd_setup(host->mmc, 0); 1109c4223c2cSManuel Lauss 1110c4223c2cSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1111c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1112c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1113c4223c2cSManuel Lauss au_sync(); 1114c4223c2cSManuel Lauss 1115c4223c2cSManuel Lauss tasklet_kill(&host->data_task); 1116c4223c2cSManuel Lauss tasklet_kill(&host->finish_task); 1117c4223c2cSManuel Lauss 1118c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1119c4223c2cSManuel Lauss au1xmmc_dbdma_shutdown(host); 1120c4223c2cSManuel Lauss #endif 1121c4223c2cSManuel Lauss au1xmmc_set_power(host, 0); 1122c4223c2cSManuel Lauss 1123c4223c2cSManuel Lauss free_irq(host->irq, host); 1124c4223c2cSManuel Lauss iounmap((void *)host->iobase); 1125c4223c2cSManuel Lauss release_resource(host->ioarea); 1126c4223c2cSManuel Lauss kfree(host->ioarea); 1127c4223c2cSManuel Lauss 1128dd8572afSManuel Lauss mmc_free_host(host->mmc); 1129dd8572afSManuel Lauss platform_set_drvdata(pdev, NULL); 1130c4223c2cSManuel Lauss } 11311c6a0718SPierre Ossman return 0; 11321c6a0718SPierre Ossman } 11331c6a0718SPierre Ossman 1134dd8572afSManuel Lauss #ifdef CONFIG_PM 1135dd8572afSManuel Lauss static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state) 1136dd8572afSManuel Lauss { 1137dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1138dd8572afSManuel Lauss int ret; 1139dd8572afSManuel Lauss 1140dd8572afSManuel Lauss ret = mmc_suspend_host(host->mmc, state); 1141dd8572afSManuel Lauss if (ret) 1142dd8572afSManuel Lauss return ret; 1143dd8572afSManuel Lauss 1144dd8572afSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1145dd8572afSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1146dd8572afSManuel Lauss au_writel(0xffffffff, HOST_STATUS(host)); 1147dd8572afSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1148dd8572afSManuel Lauss au_sync(); 1149dd8572afSManuel Lauss 1150dd8572afSManuel Lauss return 0; 1151dd8572afSManuel Lauss } 1152dd8572afSManuel Lauss 1153dd8572afSManuel Lauss static int au1xmmc_resume(struct platform_device *pdev) 1154dd8572afSManuel Lauss { 1155dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1156dd8572afSManuel Lauss 1157dd8572afSManuel Lauss au1xmmc_reset_controller(host); 1158dd8572afSManuel Lauss 1159dd8572afSManuel Lauss return mmc_resume_host(host->mmc); 1160dd8572afSManuel Lauss } 1161dd8572afSManuel Lauss #else 1162dd8572afSManuel Lauss #define au1xmmc_suspend NULL 1163dd8572afSManuel Lauss #define au1xmmc_resume NULL 1164dd8572afSManuel Lauss #endif 1165dd8572afSManuel Lauss 11661c6a0718SPierre Ossman static struct platform_driver au1xmmc_driver = { 11671c6a0718SPierre Ossman .probe = au1xmmc_probe, 11681c6a0718SPierre Ossman .remove = au1xmmc_remove, 1169dd8572afSManuel Lauss .suspend = au1xmmc_suspend, 1170dd8572afSManuel Lauss .resume = au1xmmc_resume, 11711c6a0718SPierre Ossman .driver = { 11721c6a0718SPierre Ossman .name = DRIVER_NAME, 1173bc65c724SKay Sievers .owner = THIS_MODULE, 11741c6a0718SPierre Ossman }, 11751c6a0718SPierre Ossman }; 11761c6a0718SPierre Ossman 11771c6a0718SPierre Ossman static int __init au1xmmc_init(void) 11781c6a0718SPierre Ossman { 1179c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1180c4223c2cSManuel Lauss /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride 1181c4223c2cSManuel Lauss * of 8 bits. And since devices are shared, we need to create 1182c4223c2cSManuel Lauss * our own to avoid freaking out other devices. 1183c4223c2cSManuel Lauss */ 1184c4223c2cSManuel Lauss memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); 1185c4223c2cSManuel Lauss if (!memid) 1186c4223c2cSManuel Lauss printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n"); 1187c4223c2cSManuel Lauss #endif 11881c6a0718SPierre Ossman return platform_driver_register(&au1xmmc_driver); 11891c6a0718SPierre Ossman } 11901c6a0718SPierre Ossman 11911c6a0718SPierre Ossman static void __exit au1xmmc_exit(void) 11921c6a0718SPierre Ossman { 1193c4223c2cSManuel Lauss #ifdef CONFIG_SOC_AU1200 1194c4223c2cSManuel Lauss if (memid) 1195c4223c2cSManuel Lauss au1xxx_ddma_del_device(memid); 1196c4223c2cSManuel Lauss #endif 11971c6a0718SPierre Ossman platform_driver_unregister(&au1xmmc_driver); 11981c6a0718SPierre Ossman } 11991c6a0718SPierre Ossman 12001c6a0718SPierre Ossman module_init(au1xmmc_init); 12011c6a0718SPierre Ossman module_exit(au1xmmc_exit); 12021c6a0718SPierre Ossman 12031c6a0718SPierre Ossman MODULE_AUTHOR("Advanced Micro Devices, Inc"); 12041c6a0718SPierre Ossman MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); 12051c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1206bc65c724SKay Sievers MODULE_ALIAS("platform:au1xxx-mmc"); 1207