1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 21c6a0718SPierre Ossman /* 370f10482SPierre Ossman * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver 41c6a0718SPierre Ossman * 51c6a0718SPierre Ossman * Copyright (c) 2005, Advanced Micro Devices, Inc. 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * Developed with help from the 2.4.30 MMC AU1XXX controller including 81c6a0718SPierre Ossman * the following copyright notices: 91c6a0718SPierre Ossman * Copyright (c) 2003-2004 Embedded Edge, LLC. 101c6a0718SPierre Ossman * Portions Copyright (C) 2002 Embedix, Inc 111c6a0718SPierre Ossman * Copyright 2002 Hewlett-Packard Company 121c6a0718SPierre Ossman 131c6a0718SPierre Ossman * 2.6 version of this driver inspired by: 141c6a0718SPierre Ossman * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, 151c6a0718SPierre Ossman * All Rights Reserved. 161c6a0718SPierre Ossman * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, 171c6a0718SPierre Ossman * All Rights Reserved. 181c6a0718SPierre Ossman * 191c6a0718SPierre Ossman 201c6a0718SPierre Ossman */ 211c6a0718SPierre Ossman 22e2d26477SManuel Lauss /* Why don't we use the SD controllers' carddetect feature? 231c6a0718SPierre Ossman * 241c6a0718SPierre Ossman * From the AU1100 MMC application guide: 251c6a0718SPierre Ossman * If the Au1100-based design is intended to support both MultiMediaCards 261c6a0718SPierre Ossman * and 1- or 4-data bit SecureDigital cards, then the solution is to 271c6a0718SPierre Ossman * connect a weak (560KOhm) pull-up resistor to connector pin 1. 281c6a0718SPierre Ossman * In doing so, a MMC card never enters SPI-mode communications, 291c6a0718SPierre Ossman * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective 301c6a0718SPierre Ossman * (the low to high transition will not occur). 311c6a0718SPierre Ossman */ 321c6a0718SPierre Ossman 33b6507596SManuel Lauss #include <linux/clk.h> 341c6a0718SPierre Ossman #include <linux/module.h> 351c6a0718SPierre Ossman #include <linux/init.h> 361c6a0718SPierre Ossman #include <linux/platform_device.h> 371c6a0718SPierre Ossman #include <linux/mm.h> 381c6a0718SPierre Ossman #include <linux/interrupt.h> 391c6a0718SPierre Ossman #include <linux/dma-mapping.h> 400ada7a02SAl Viro #include <linux/scatterlist.h> 41a6720c02SChristoph Hellwig #include <linux/highmem.h> 42c4223c2cSManuel Lauss #include <linux/leds.h> 431c6a0718SPierre Ossman #include <linux/mmc/host.h> 445a0e3ad6STejun Heo #include <linux/slab.h> 45c4223c2cSManuel Lauss 461c6a0718SPierre Ossman #include <asm/io.h> 471c6a0718SPierre Ossman #include <asm/mach-au1x00/au1000.h> 481c6a0718SPierre Ossman #include <asm/mach-au1x00/au1xxx_dbdma.h> 491c6a0718SPierre Ossman #include <asm/mach-au1x00/au1100_mmc.h> 501c6a0718SPierre Ossman 511c6a0718SPierre Ossman #define DRIVER_NAME "au1xxx-mmc" 521c6a0718SPierre Ossman 531c6a0718SPierre Ossman /* Set this to enable special debugging macros */ 54c4223c2cSManuel Lauss /* #define DEBUG */ 551c6a0718SPierre Ossman 561c6a0718SPierre Ossman #ifdef DEBUG 575c0a889dSManuel Lauss #define DBG(fmt, idx, args...) \ 58a3c76eb9SGirish K S pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args) 591c6a0718SPierre Ossman #else 605c0a889dSManuel Lauss #define DBG(fmt, idx, args...) do {} while (0) 611c6a0718SPierre Ossman #endif 621c6a0718SPierre Ossman 635c0a889dSManuel Lauss /* Hardware definitions */ 645c0a889dSManuel Lauss #define AU1XMMC_DESCRIPTOR_COUNT 1 65e491d230SManuel Lauss 66e491d230SManuel Lauss /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */ 671177d99dSManuel Lauss #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff 681177d99dSManuel Lauss #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff 695c0a889dSManuel Lauss 705c0a889dSManuel Lauss #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ 715c0a889dSManuel Lauss MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ 725c0a889dSManuel Lauss MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) 735c0a889dSManuel Lauss 745c0a889dSManuel Lauss /* This gives us a hard value for the stop command that we can write directly 755c0a889dSManuel Lauss * to the command register. 765c0a889dSManuel Lauss */ 775c0a889dSManuel Lauss #define STOP_CMD \ 785c0a889dSManuel Lauss (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO) 795c0a889dSManuel Lauss 805c0a889dSManuel Lauss /* This is the set of interrupts that we configure by default. */ 815c0a889dSManuel Lauss #define AU1XMMC_INTERRUPTS \ 825c0a889dSManuel Lauss (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \ 835c0a889dSManuel Lauss SD_CONFIG_CR | SD_CONFIG_I) 845c0a889dSManuel Lauss 855c0a889dSManuel Lauss /* The poll event (looking for insert/remove events runs twice a second. */ 865c0a889dSManuel Lauss #define AU1XMMC_DETECT_TIMEOUT (HZ/2) 875c0a889dSManuel Lauss 885c0a889dSManuel Lauss struct au1xmmc_host { 895c0a889dSManuel Lauss struct mmc_host *mmc; 905c0a889dSManuel Lauss struct mmc_request *mrq; 915c0a889dSManuel Lauss 925c0a889dSManuel Lauss u32 flags; 932f73bfbeSManuel Lauss void __iomem *iobase; 945c0a889dSManuel Lauss u32 clock; 955c0a889dSManuel Lauss u32 bus_width; 965c0a889dSManuel Lauss u32 power_mode; 975c0a889dSManuel Lauss 985c0a889dSManuel Lauss int status; 995c0a889dSManuel Lauss 1005c0a889dSManuel Lauss struct { 1015c0a889dSManuel Lauss int len; 1025c0a889dSManuel Lauss int dir; 1035c0a889dSManuel Lauss } dma; 1045c0a889dSManuel Lauss 1055c0a889dSManuel Lauss struct { 1065c0a889dSManuel Lauss int index; 1075c0a889dSManuel Lauss int offset; 1085c0a889dSManuel Lauss int len; 1095c0a889dSManuel Lauss } pio; 1105c0a889dSManuel Lauss 1115c0a889dSManuel Lauss u32 tx_chan; 1125c0a889dSManuel Lauss u32 rx_chan; 1135c0a889dSManuel Lauss 1145c0a889dSManuel Lauss int irq; 1155c0a889dSManuel Lauss 1165c0a889dSManuel Lauss struct tasklet_struct finish_task; 1175c0a889dSManuel Lauss struct tasklet_struct data_task; 1185c0a889dSManuel Lauss struct au1xmmc_platform_data *platdata; 1195c0a889dSManuel Lauss struct platform_device *pdev; 1205c0a889dSManuel Lauss struct resource *ioarea; 121b6507596SManuel Lauss struct clk *clk; 1225c0a889dSManuel Lauss }; 1235c0a889dSManuel Lauss 1245c0a889dSManuel Lauss /* Status flags used by the host structure */ 1255c0a889dSManuel Lauss #define HOST_F_XMIT 0x0001 1265c0a889dSManuel Lauss #define HOST_F_RECV 0x0002 1275c0a889dSManuel Lauss #define HOST_F_DMA 0x0010 1281177d99dSManuel Lauss #define HOST_F_DBDMA 0x0020 1295c0a889dSManuel Lauss #define HOST_F_ACTIVE 0x0100 1305c0a889dSManuel Lauss #define HOST_F_STOP 0x1000 1315c0a889dSManuel Lauss 1325c0a889dSManuel Lauss #define HOST_S_IDLE 0x0001 1335c0a889dSManuel Lauss #define HOST_S_CMD 0x0002 1345c0a889dSManuel Lauss #define HOST_S_DATA 0x0003 1355c0a889dSManuel Lauss #define HOST_S_STOP 0x0004 1365c0a889dSManuel Lauss 1375c0a889dSManuel Lauss /* Easy access macros */ 1385c0a889dSManuel Lauss #define HOST_STATUS(h) ((h)->iobase + SD_STATUS) 1395c0a889dSManuel Lauss #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) 1405c0a889dSManuel Lauss #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) 1415c0a889dSManuel Lauss #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) 1425c0a889dSManuel Lauss #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) 1435c0a889dSManuel Lauss #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) 1445c0a889dSManuel Lauss #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) 1455c0a889dSManuel Lauss #define HOST_CMD(h) ((h)->iobase + SD_CMD) 1465c0a889dSManuel Lauss #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) 1475c0a889dSManuel Lauss #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) 1485c0a889dSManuel Lauss #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) 1495c0a889dSManuel Lauss 1505c0a889dSManuel Lauss #define DMA_CHANNEL(h) \ 1515c0a889dSManuel Lauss (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) 1525c0a889dSManuel Lauss 1531177d99dSManuel Lauss static inline int has_dbdma(void) 1541177d99dSManuel Lauss { 1551177d99dSManuel Lauss switch (alchemy_get_cputype()) { 1561177d99dSManuel Lauss case ALCHEMY_CPU_AU1200: 157809f36c6SManuel Lauss case ALCHEMY_CPU_AU1300: 1581177d99dSManuel Lauss return 1; 1591177d99dSManuel Lauss default: 1601177d99dSManuel Lauss return 0; 1611177d99dSManuel Lauss } 1621177d99dSManuel Lauss } 1631177d99dSManuel Lauss 1641c6a0718SPierre Ossman static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) 1651c6a0718SPierre Ossman { 1662f73bfbeSManuel Lauss u32 val = __raw_readl(HOST_CONFIG(host)); 1671c6a0718SPierre Ossman val |= mask; 1682f73bfbeSManuel Lauss __raw_writel(val, HOST_CONFIG(host)); 1692f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 1701c6a0718SPierre Ossman } 1711c6a0718SPierre Ossman 1721c6a0718SPierre Ossman static inline void FLUSH_FIFO(struct au1xmmc_host *host) 1731c6a0718SPierre Ossman { 1742f73bfbeSManuel Lauss u32 val = __raw_readl(HOST_CONFIG2(host)); 1751c6a0718SPierre Ossman 1762f73bfbeSManuel Lauss __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); 1772f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 1782f73bfbeSManuel Lauss mdelay(1); 1791c6a0718SPierre Ossman 1801c6a0718SPierre Ossman /* SEND_STOP will turn off clock control - this re-enables it */ 1811c6a0718SPierre Ossman val &= ~SD_CONFIG2_DF; 1821c6a0718SPierre Ossman 1832f73bfbeSManuel Lauss __raw_writel(val, HOST_CONFIG2(host)); 1842f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 1851c6a0718SPierre Ossman } 1861c6a0718SPierre Ossman 1871c6a0718SPierre Ossman static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) 1881c6a0718SPierre Ossman { 1892f73bfbeSManuel Lauss u32 val = __raw_readl(HOST_CONFIG(host)); 1901c6a0718SPierre Ossman val &= ~mask; 1912f73bfbeSManuel Lauss __raw_writel(val, HOST_CONFIG(host)); 1922f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 1931c6a0718SPierre Ossman } 1941c6a0718SPierre Ossman 1951c6a0718SPierre Ossman static inline void SEND_STOP(struct au1xmmc_host *host) 1961c6a0718SPierre Ossman { 197281dd23eSManuel Lauss u32 config2; 1981c6a0718SPierre Ossman 1991c6a0718SPierre Ossman WARN_ON(host->status != HOST_S_DATA); 2001c6a0718SPierre Ossman host->status = HOST_S_STOP; 2011c6a0718SPierre Ossman 2022f73bfbeSManuel Lauss config2 = __raw_readl(HOST_CONFIG2(host)); 2032f73bfbeSManuel Lauss __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); 2042f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 2051c6a0718SPierre Ossman 206b595076aSUwe Kleine-König /* Send the stop command */ 2072f73bfbeSManuel Lauss __raw_writel(STOP_CMD, HOST_CMD(host)); 2082f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 2091c6a0718SPierre Ossman } 2101c6a0718SPierre Ossman 2111c6a0718SPierre Ossman static void au1xmmc_set_power(struct au1xmmc_host *host, int state) 2121c6a0718SPierre Ossman { 213c4223c2cSManuel Lauss if (host->platdata && host->platdata->set_power) 214c4223c2cSManuel Lauss host->platdata->set_power(host->mmc, state); 2151c6a0718SPierre Ossman } 2161c6a0718SPierre Ossman 217e2d26477SManuel Lauss static int au1xmmc_card_inserted(struct mmc_host *mmc) 2181c6a0718SPierre Ossman { 219e2d26477SManuel Lauss struct au1xmmc_host *host = mmc_priv(mmc); 220c4223c2cSManuel Lauss 221c4223c2cSManuel Lauss if (host->platdata && host->platdata->card_inserted) 222e2d26477SManuel Lauss return !!host->platdata->card_inserted(host->mmc); 223c4223c2cSManuel Lauss 224e2d26477SManuel Lauss return -ENOSYS; 2251c6a0718SPierre Ossman } 2261c6a0718SPierre Ossman 2271c6a0718SPierre Ossman static int au1xmmc_card_readonly(struct mmc_host *mmc) 2281c6a0718SPierre Ossman { 2291c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 230c4223c2cSManuel Lauss 231c4223c2cSManuel Lauss if (host->platdata && host->platdata->card_readonly) 232e2d26477SManuel Lauss return !!host->platdata->card_readonly(mmc); 233c4223c2cSManuel Lauss 234e2d26477SManuel Lauss return -ENOSYS; 2351c6a0718SPierre Ossman } 2361c6a0718SPierre Ossman 2371c6a0718SPierre Ossman static void au1xmmc_finish_request(struct au1xmmc_host *host) 2381c6a0718SPierre Ossman { 2391c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 2401c6a0718SPierre Ossman 2411c6a0718SPierre Ossman host->mrq = NULL; 242c4223c2cSManuel Lauss host->flags &= HOST_F_ACTIVE | HOST_F_DMA; 2431c6a0718SPierre Ossman 2441c6a0718SPierre Ossman host->dma.len = 0; 2451c6a0718SPierre Ossman host->dma.dir = 0; 2461c6a0718SPierre Ossman 2471c6a0718SPierre Ossman host->pio.index = 0; 2481c6a0718SPierre Ossman host->pio.offset = 0; 2491c6a0718SPierre Ossman host->pio.len = 0; 2501c6a0718SPierre Ossman 2511c6a0718SPierre Ossman host->status = HOST_S_IDLE; 2521c6a0718SPierre Ossman 2531c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 2541c6a0718SPierre Ossman } 2551c6a0718SPierre Ossman 2561c6a0718SPierre Ossman static void au1xmmc_tasklet_finish(unsigned long param) 2571c6a0718SPierre Ossman { 2581c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *) param; 2591c6a0718SPierre Ossman au1xmmc_finish_request(host); 2601c6a0718SPierre Ossman } 2611c6a0718SPierre Ossman 2621c6a0718SPierre Ossman static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, 263be0192aaSPierre Ossman struct mmc_command *cmd, struct mmc_data *data) 2641c6a0718SPierre Ossman { 2651c6a0718SPierre Ossman u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); 2661c6a0718SPierre Ossman 2671c6a0718SPierre Ossman switch (mmc_resp_type(cmd)) { 2681c6a0718SPierre Ossman case MMC_RSP_NONE: 2691c6a0718SPierre Ossman break; 2701c6a0718SPierre Ossman case MMC_RSP_R1: 2711c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_1; 2721c6a0718SPierre Ossman break; 2731c6a0718SPierre Ossman case MMC_RSP_R1B: 2741c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_1B; 2751c6a0718SPierre Ossman break; 2761c6a0718SPierre Ossman case MMC_RSP_R2: 2771c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_2; 2781c6a0718SPierre Ossman break; 2791c6a0718SPierre Ossman case MMC_RSP_R3: 2801c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_3; 2811c6a0718SPierre Ossman break; 2821c6a0718SPierre Ossman default: 283a3c76eb9SGirish K S pr_info("au1xmmc: unhandled response type %02x\n", 2841c6a0718SPierre Ossman mmc_resp_type(cmd)); 28517b0429dSPierre Ossman return -EINVAL; 2861c6a0718SPierre Ossman } 2871c6a0718SPierre Ossman 288be0192aaSPierre Ossman if (data) { 2896356a9d9SPierre Ossman if (data->flags & MMC_DATA_READ) { 290be0192aaSPierre Ossman if (data->blocks > 1) 2911c6a0718SPierre Ossman mmccmd |= SD_CMD_CT_4; 292c0f3b6c7SYoichi Yuasa else 293c0f3b6c7SYoichi Yuasa mmccmd |= SD_CMD_CT_2; 2946356a9d9SPierre Ossman } else if (data->flags & MMC_DATA_WRITE) { 295be0192aaSPierre Ossman if (data->blocks > 1) 2961c6a0718SPierre Ossman mmccmd |= SD_CMD_CT_3; 297c0f3b6c7SYoichi Yuasa else 298c0f3b6c7SYoichi Yuasa mmccmd |= SD_CMD_CT_1; 2991c6a0718SPierre Ossman } 300be0192aaSPierre Ossman } 3011c6a0718SPierre Ossman 3022f73bfbeSManuel Lauss __raw_writel(cmd->arg, HOST_CMDARG(host)); 3032f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 3041c6a0718SPierre Ossman 3051c6a0718SPierre Ossman if (wait) 3061c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_CR); 3071c6a0718SPierre Ossman 3082f73bfbeSManuel Lauss __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); 3092f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 3101c6a0718SPierre Ossman 3111c6a0718SPierre Ossman /* Wait for the command to go on the line */ 3122f73bfbeSManuel Lauss while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO) 3135c0a889dSManuel Lauss /* nop */; 3141c6a0718SPierre Ossman 3151c6a0718SPierre Ossman /* Wait for the command to come back */ 3161c6a0718SPierre Ossman if (wait) { 3172f73bfbeSManuel Lauss u32 status = __raw_readl(HOST_STATUS(host)); 3181c6a0718SPierre Ossman 3191c6a0718SPierre Ossman while (!(status & SD_STATUS_CR)) 3202f73bfbeSManuel Lauss status = __raw_readl(HOST_STATUS(host)); 3211c6a0718SPierre Ossman 3221c6a0718SPierre Ossman /* Clear the CR status */ 3232f73bfbeSManuel Lauss __raw_writel(SD_STATUS_CR, HOST_STATUS(host)); 3241c6a0718SPierre Ossman 3251c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_CR); 3261c6a0718SPierre Ossman } 3271c6a0718SPierre Ossman 32817b0429dSPierre Ossman return 0; 3291c6a0718SPierre Ossman } 3301c6a0718SPierre Ossman 3311c6a0718SPierre Ossman static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) 3321c6a0718SPierre Ossman { 3331c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 3341c6a0718SPierre Ossman struct mmc_data *data; 3351c6a0718SPierre Ossman u32 crc; 3361c6a0718SPierre Ossman 3375c0a889dSManuel Lauss WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP)); 3381c6a0718SPierre Ossman 3391c6a0718SPierre Ossman if (host->mrq == NULL) 3401c6a0718SPierre Ossman return; 3411c6a0718SPierre Ossman 3421c6a0718SPierre Ossman data = mrq->cmd->data; 3431c6a0718SPierre Ossman 3441c6a0718SPierre Ossman if (status == 0) 3452f73bfbeSManuel Lauss status = __raw_readl(HOST_STATUS(host)); 3461c6a0718SPierre Ossman 3471c6a0718SPierre Ossman /* The transaction is really over when the SD_STATUS_DB bit is clear */ 3481c6a0718SPierre Ossman while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) 3492f73bfbeSManuel Lauss status = __raw_readl(HOST_STATUS(host)); 3501c6a0718SPierre Ossman 35117b0429dSPierre Ossman data->error = 0; 3521c6a0718SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); 3531c6a0718SPierre Ossman 3541c6a0718SPierre Ossman /* Process any errors */ 3551c6a0718SPierre Ossman crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); 3561c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) 3571c6a0718SPierre Ossman crc |= ((status & 0x07) == 0x02) ? 0 : 1; 3581c6a0718SPierre Ossman 3591c6a0718SPierre Ossman if (crc) 36017b0429dSPierre Ossman data->error = -EILSEQ; 3611c6a0718SPierre Ossman 3621c6a0718SPierre Ossman /* Clear the CRC bits */ 3632f73bfbeSManuel Lauss __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); 3641c6a0718SPierre Ossman 3651c6a0718SPierre Ossman data->bytes_xfered = 0; 3661c6a0718SPierre Ossman 36717b0429dSPierre Ossman if (!data->error) { 3681177d99dSManuel Lauss if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { 3691c6a0718SPierre Ossman u32 chan = DMA_CHANNEL(host); 3701c6a0718SPierre Ossman 3711c6a0718SPierre Ossman chan_tab_t *c = *((chan_tab_t **)chan); 3721c6a0718SPierre Ossman au1x_dma_chan_t *cp = c->chan_ptr; 3731c6a0718SPierre Ossman data->bytes_xfered = cp->ddma_bytecnt; 3745c0a889dSManuel Lauss } else 3751c6a0718SPierre Ossman data->bytes_xfered = 3765c0a889dSManuel Lauss (data->blocks * data->blksz) - host->pio.len; 3771c6a0718SPierre Ossman } 3781c6a0718SPierre Ossman 3791c6a0718SPierre Ossman au1xmmc_finish_request(host); 3801c6a0718SPierre Ossman } 3811c6a0718SPierre Ossman 3821c6a0718SPierre Ossman static void au1xmmc_tasklet_data(unsigned long param) 3831c6a0718SPierre Ossman { 3841c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *)param; 3851c6a0718SPierre Ossman 3862f73bfbeSManuel Lauss u32 status = __raw_readl(HOST_STATUS(host)); 3871c6a0718SPierre Ossman au1xmmc_data_complete(host, status); 3881c6a0718SPierre Ossman } 3891c6a0718SPierre Ossman 3901c6a0718SPierre Ossman #define AU1XMMC_MAX_TRANSFER 8 3911c6a0718SPierre Ossman 3921c6a0718SPierre Ossman static void au1xmmc_send_pio(struct au1xmmc_host *host) 3931c6a0718SPierre Ossman { 3945c0a889dSManuel Lauss struct mmc_data *data; 3955c0a889dSManuel Lauss int sg_len, max, count; 3965c0a889dSManuel Lauss unsigned char *sg_ptr, val; 3975c0a889dSManuel Lauss u32 status; 3981c6a0718SPierre Ossman struct scatterlist *sg; 3991c6a0718SPierre Ossman 4001c6a0718SPierre Ossman data = host->mrq->data; 4011c6a0718SPierre Ossman 4021c6a0718SPierre Ossman if (!(host->flags & HOST_F_XMIT)) 4031c6a0718SPierre Ossman return; 4041c6a0718SPierre Ossman 4051c6a0718SPierre Ossman /* This is the pointer to the data buffer */ 4061c6a0718SPierre Ossman sg = &data->sg[host->pio.index]; 407a6720c02SChristoph Hellwig sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset; 4081c6a0718SPierre Ossman 4091c6a0718SPierre Ossman /* This is the space left inside the buffer */ 4101c6a0718SPierre Ossman sg_len = data->sg[host->pio.index].length - host->pio.offset; 4111c6a0718SPierre Ossman 4125c0a889dSManuel Lauss /* Check if we need less than the size of the sg_buffer */ 4131c6a0718SPierre Ossman max = (sg_len > host->pio.len) ? host->pio.len : sg_len; 4145c0a889dSManuel Lauss if (max > AU1XMMC_MAX_TRANSFER) 4155c0a889dSManuel Lauss max = AU1XMMC_MAX_TRANSFER; 4161c6a0718SPierre Ossman 4171c6a0718SPierre Ossman for (count = 0; count < max; count++) { 4182f73bfbeSManuel Lauss status = __raw_readl(HOST_STATUS(host)); 4191c6a0718SPierre Ossman 4201c6a0718SPierre Ossman if (!(status & SD_STATUS_TH)) 4211c6a0718SPierre Ossman break; 4221c6a0718SPierre Ossman 423a6720c02SChristoph Hellwig val = sg_ptr[count]; 4241c6a0718SPierre Ossman 4252f73bfbeSManuel Lauss __raw_writel((unsigned long)val, HOST_TXPORT(host)); 4262f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 4271c6a0718SPierre Ossman } 428a6720c02SChristoph Hellwig kunmap_atomic(sg_ptr); 4291c6a0718SPierre Ossman 4301c6a0718SPierre Ossman host->pio.len -= count; 4311c6a0718SPierre Ossman host->pio.offset += count; 4321c6a0718SPierre Ossman 4331c6a0718SPierre Ossman if (count == sg_len) { 4341c6a0718SPierre Ossman host->pio.index++; 4351c6a0718SPierre Ossman host->pio.offset = 0; 4361c6a0718SPierre Ossman } 4371c6a0718SPierre Ossman 4381c6a0718SPierre Ossman if (host->pio.len == 0) { 4391c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_TH); 4401c6a0718SPierre Ossman 4411c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 4421c6a0718SPierre Ossman SEND_STOP(host); 4431c6a0718SPierre Ossman 4441c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 4451c6a0718SPierre Ossman } 4461c6a0718SPierre Ossman } 4471c6a0718SPierre Ossman 4481c6a0718SPierre Ossman static void au1xmmc_receive_pio(struct au1xmmc_host *host) 4491c6a0718SPierre Ossman { 4505c0a889dSManuel Lauss struct mmc_data *data; 4515c0a889dSManuel Lauss int max, count, sg_len = 0; 4525c0a889dSManuel Lauss unsigned char *sg_ptr = NULL; 4535c0a889dSManuel Lauss u32 status, val; 4541c6a0718SPierre Ossman struct scatterlist *sg; 4551c6a0718SPierre Ossman 4561c6a0718SPierre Ossman data = host->mrq->data; 4571c6a0718SPierre Ossman 4581c6a0718SPierre Ossman if (!(host->flags & HOST_F_RECV)) 4591c6a0718SPierre Ossman return; 4601c6a0718SPierre Ossman 4611c6a0718SPierre Ossman max = host->pio.len; 4621c6a0718SPierre Ossman 4631c6a0718SPierre Ossman if (host->pio.index < host->dma.len) { 4641c6a0718SPierre Ossman sg = &data->sg[host->pio.index]; 465a6720c02SChristoph Hellwig sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset; 4661c6a0718SPierre Ossman 4671c6a0718SPierre Ossman /* This is the space left inside the buffer */ 4681c6a0718SPierre Ossman sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; 4691c6a0718SPierre Ossman 4705c0a889dSManuel Lauss /* Check if we need less than the size of the sg_buffer */ 4715c0a889dSManuel Lauss if (sg_len < max) 4725c0a889dSManuel Lauss max = sg_len; 4731c6a0718SPierre Ossman } 4741c6a0718SPierre Ossman 4751c6a0718SPierre Ossman if (max > AU1XMMC_MAX_TRANSFER) 4761c6a0718SPierre Ossman max = AU1XMMC_MAX_TRANSFER; 4771c6a0718SPierre Ossman 4781c6a0718SPierre Ossman for (count = 0; count < max; count++) { 4792f73bfbeSManuel Lauss status = __raw_readl(HOST_STATUS(host)); 4801c6a0718SPierre Ossman 4811c6a0718SPierre Ossman if (!(status & SD_STATUS_NE)) 4821c6a0718SPierre Ossman break; 4831c6a0718SPierre Ossman 4841c6a0718SPierre Ossman if (status & SD_STATUS_RC) { 485c4223c2cSManuel Lauss DBG("RX CRC Error [%d + %d].\n", host->pdev->id, 4861c6a0718SPierre Ossman host->pio.len, count); 4871c6a0718SPierre Ossman break; 4881c6a0718SPierre Ossman } 4891c6a0718SPierre Ossman 4901c6a0718SPierre Ossman if (status & SD_STATUS_RO) { 491c4223c2cSManuel Lauss DBG("RX Overrun [%d + %d]\n", host->pdev->id, 4921c6a0718SPierre Ossman host->pio.len, count); 4931c6a0718SPierre Ossman break; 4941c6a0718SPierre Ossman } 4951c6a0718SPierre Ossman else if (status & SD_STATUS_RU) { 496c4223c2cSManuel Lauss DBG("RX Underrun [%d + %d]\n", host->pdev->id, 4971c6a0718SPierre Ossman host->pio.len, count); 4981c6a0718SPierre Ossman break; 4991c6a0718SPierre Ossman } 5001c6a0718SPierre Ossman 5012f73bfbeSManuel Lauss val = __raw_readl(HOST_RXPORT(host)); 5021c6a0718SPierre Ossman 5031c6a0718SPierre Ossman if (sg_ptr) 504a6720c02SChristoph Hellwig sg_ptr[count] = (unsigned char)(val & 0xFF); 5051c6a0718SPierre Ossman } 506a6720c02SChristoph Hellwig if (sg_ptr) 507a6720c02SChristoph Hellwig kunmap_atomic(sg_ptr); 5081c6a0718SPierre Ossman 5091c6a0718SPierre Ossman host->pio.len -= count; 5101c6a0718SPierre Ossman host->pio.offset += count; 5111c6a0718SPierre Ossman 5121c6a0718SPierre Ossman if (sg_len && count == sg_len) { 5131c6a0718SPierre Ossman host->pio.index++; 5141c6a0718SPierre Ossman host->pio.offset = 0; 5151c6a0718SPierre Ossman } 5161c6a0718SPierre Ossman 5171c6a0718SPierre Ossman if (host->pio.len == 0) { 5185c0a889dSManuel Lauss /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 5191c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_NE); 5201c6a0718SPierre Ossman 5211c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 5221c6a0718SPierre Ossman SEND_STOP(host); 5231c6a0718SPierre Ossman 5241c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 5251c6a0718SPierre Ossman } 5261c6a0718SPierre Ossman } 5271c6a0718SPierre Ossman 5285c0a889dSManuel Lauss /* This is called when a command has been completed - grab the response 5295c0a889dSManuel Lauss * and check for errors. Then start the data transfer if it is indicated. 5301c6a0718SPierre Ossman */ 5311c6a0718SPierre Ossman static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) 5321c6a0718SPierre Ossman { 5331c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 5341c6a0718SPierre Ossman struct mmc_command *cmd; 5355c0a889dSManuel Lauss u32 r[4]; 5365c0a889dSManuel Lauss int i, trans; 5371c6a0718SPierre Ossman 5381c6a0718SPierre Ossman if (!host->mrq) 5391c6a0718SPierre Ossman return; 5401c6a0718SPierre Ossman 5411c6a0718SPierre Ossman cmd = mrq->cmd; 54217b0429dSPierre Ossman cmd->error = 0; 5431c6a0718SPierre Ossman 5441c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 5451c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) { 5462f73bfbeSManuel Lauss r[0] = __raw_readl(host->iobase + SD_RESP3); 5472f73bfbeSManuel Lauss r[1] = __raw_readl(host->iobase + SD_RESP2); 5482f73bfbeSManuel Lauss r[2] = __raw_readl(host->iobase + SD_RESP1); 5492f73bfbeSManuel Lauss r[3] = __raw_readl(host->iobase + SD_RESP0); 5501c6a0718SPierre Ossman 5511c6a0718SPierre Ossman /* The CRC is omitted from the response, so really 5521c6a0718SPierre Ossman * we only got 120 bytes, but the engine expects 5535c0a889dSManuel Lauss * 128 bits, so we have to shift things up. 5541c6a0718SPierre Ossman */ 5551c6a0718SPierre Ossman for (i = 0; i < 4; i++) { 5561c6a0718SPierre Ossman cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; 5571c6a0718SPierre Ossman if (i != 3) 5581c6a0718SPierre Ossman cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; 5591c6a0718SPierre Ossman } 5601c6a0718SPierre Ossman } else { 5611c6a0718SPierre Ossman /* Techincally, we should be getting all 48 bits of 5621c6a0718SPierre Ossman * the response (SD_RESP1 + SD_RESP2), but because 5631c6a0718SPierre Ossman * our response omits the CRC, our data ends up 5641c6a0718SPierre Ossman * being shifted 8 bits to the right. In this case, 5651c6a0718SPierre Ossman * that means that the OSR data starts at bit 31, 5665c0a889dSManuel Lauss * so we can just read RESP0 and return that. 5671c6a0718SPierre Ossman */ 5682f73bfbeSManuel Lauss cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0); 5691c6a0718SPierre Ossman } 5701c6a0718SPierre Ossman } 5711c6a0718SPierre Ossman 5721c6a0718SPierre Ossman /* Figure out errors */ 5731c6a0718SPierre Ossman if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) 57417b0429dSPierre Ossman cmd->error = -EILSEQ; 5751c6a0718SPierre Ossman 5761c6a0718SPierre Ossman trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); 5771c6a0718SPierre Ossman 57817b0429dSPierre Ossman if (!trans || cmd->error) { 5791c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); 5801c6a0718SPierre Ossman tasklet_schedule(&host->finish_task); 5811c6a0718SPierre Ossman return; 5821c6a0718SPierre Ossman } 5831c6a0718SPierre Ossman 5841c6a0718SPierre Ossman host->status = HOST_S_DATA; 5851c6a0718SPierre Ossman 5861177d99dSManuel Lauss if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) { 5871c6a0718SPierre Ossman u32 channel = DMA_CHANNEL(host); 5881c6a0718SPierre Ossman 5891177d99dSManuel Lauss /* Start the DBDMA as soon as the buffer gets something in it */ 5901c6a0718SPierre Ossman 5911c6a0718SPierre Ossman if (host->flags & HOST_F_RECV) { 5921c6a0718SPierre Ossman u32 mask = SD_STATUS_DB | SD_STATUS_NE; 5931c6a0718SPierre Ossman 5941c6a0718SPierre Ossman while((status & mask) != mask) 5952f73bfbeSManuel Lauss status = __raw_readl(HOST_STATUS(host)); 5961c6a0718SPierre Ossman } 5971c6a0718SPierre Ossman 5981c6a0718SPierre Ossman au1xxx_dbdma_start(channel); 5991c6a0718SPierre Ossman } 6001c6a0718SPierre Ossman } 6011c6a0718SPierre Ossman 6021c6a0718SPierre Ossman static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) 6031c6a0718SPierre Ossman { 604b6507596SManuel Lauss unsigned int pbus = clk_get_rate(host->clk); 605b6507596SManuel Lauss unsigned int divisor = ((pbus / rate) / 2) - 1; 6061c6a0718SPierre Ossman u32 config; 6071c6a0718SPierre Ossman 6082f73bfbeSManuel Lauss config = __raw_readl(HOST_CONFIG(host)); 6091c6a0718SPierre Ossman 6101c6a0718SPierre Ossman config &= ~(SD_CONFIG_DIV); 6111c6a0718SPierre Ossman config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; 6121c6a0718SPierre Ossman 6132f73bfbeSManuel Lauss __raw_writel(config, HOST_CONFIG(host)); 6142f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 6151c6a0718SPierre Ossman } 6161c6a0718SPierre Ossman 6175c0a889dSManuel Lauss static int au1xmmc_prepare_data(struct au1xmmc_host *host, 6185c0a889dSManuel Lauss struct mmc_data *data) 6191c6a0718SPierre Ossman { 6201c6a0718SPierre Ossman int datalen = data->blocks * data->blksz; 6211c6a0718SPierre Ossman 6221c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 6231c6a0718SPierre Ossman host->flags |= HOST_F_RECV; 6241c6a0718SPierre Ossman else 6251c6a0718SPierre Ossman host->flags |= HOST_F_XMIT; 6261c6a0718SPierre Ossman 6271c6a0718SPierre Ossman if (host->mrq->stop) 6281c6a0718SPierre Ossman host->flags |= HOST_F_STOP; 6291c6a0718SPierre Ossman 6301c6a0718SPierre Ossman host->dma.dir = DMA_BIDIRECTIONAL; 6311c6a0718SPierre Ossman 6321c6a0718SPierre Ossman host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, 6331c6a0718SPierre Ossman data->sg_len, host->dma.dir); 6341c6a0718SPierre Ossman 6351c6a0718SPierre Ossman if (host->dma.len == 0) 63617b0429dSPierre Ossman return -ETIMEDOUT; 6371c6a0718SPierre Ossman 6382f73bfbeSManuel Lauss __raw_writel(data->blksz - 1, HOST_BLKSIZE(host)); 6391c6a0718SPierre Ossman 6401177d99dSManuel Lauss if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { 6411c6a0718SPierre Ossman int i; 6421c6a0718SPierre Ossman u32 channel = DMA_CHANNEL(host); 6431c6a0718SPierre Ossman 6441c6a0718SPierre Ossman au1xxx_dbdma_stop(channel); 6451c6a0718SPierre Ossman 6461c6a0718SPierre Ossman for (i = 0; i < host->dma.len; i++) { 6471c6a0718SPierre Ossman u32 ret = 0, flags = DDMA_FLAGS_NOIE; 6481c6a0718SPierre Ossman struct scatterlist *sg = &data->sg[i]; 6491c6a0718SPierre Ossman int sg_len = sg->length; 6501c6a0718SPierre Ossman 6511c6a0718SPierre Ossman int len = (datalen > sg_len) ? sg_len : datalen; 6521c6a0718SPierre Ossman 6531c6a0718SPierre Ossman if (i == host->dma.len - 1) 6541c6a0718SPierre Ossman flags = DDMA_FLAGS_IE; 6551c6a0718SPierre Ossman 6561c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) { 657ea071cc7SManuel Lauss ret = au1xxx_dbdma_put_source(channel, 658963accbcSManuel Lauss sg_phys(sg), len, flags); 6595c0a889dSManuel Lauss } else { 660ea071cc7SManuel Lauss ret = au1xxx_dbdma_put_dest(channel, 661963accbcSManuel Lauss sg_phys(sg), len, flags); 6621c6a0718SPierre Ossman } 6631c6a0718SPierre Ossman 6641c6a0718SPierre Ossman if (!ret) 6651c6a0718SPierre Ossman goto dataerr; 6661c6a0718SPierre Ossman 6671c6a0718SPierre Ossman datalen -= len; 6681c6a0718SPierre Ossman } 6695c0a889dSManuel Lauss } else { 6701c6a0718SPierre Ossman host->pio.index = 0; 6711c6a0718SPierre Ossman host->pio.offset = 0; 6721c6a0718SPierre Ossman host->pio.len = datalen; 6731c6a0718SPierre Ossman 6741c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) 6751c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_TH); 6761c6a0718SPierre Ossman else 6771c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_NE); 6785c0a889dSManuel Lauss /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 6791c6a0718SPierre Ossman } 6801c6a0718SPierre Ossman 68117b0429dSPierre Ossman return 0; 6821c6a0718SPierre Ossman 6831c6a0718SPierre Ossman dataerr: 684c4223c2cSManuel Lauss dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 685c4223c2cSManuel Lauss host->dma.dir); 68617b0429dSPierre Ossman return -ETIMEDOUT; 6871c6a0718SPierre Ossman } 6881c6a0718SPierre Ossman 6895c0a889dSManuel Lauss /* This actually starts a command or data transaction */ 6901c6a0718SPierre Ossman static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) 6911c6a0718SPierre Ossman { 6921c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 69317b0429dSPierre Ossman int ret = 0; 6941c6a0718SPierre Ossman 6951c6a0718SPierre Ossman WARN_ON(irqs_disabled()); 6961c6a0718SPierre Ossman WARN_ON(host->status != HOST_S_IDLE); 6971c6a0718SPierre Ossman 6981c6a0718SPierre Ossman host->mrq = mrq; 6991c6a0718SPierre Ossman host->status = HOST_S_CMD; 7001c6a0718SPierre Ossman 70188b8d9a8SManuel Lauss /* fail request immediately if no card is present */ 702e2d26477SManuel Lauss if (0 == au1xmmc_card_inserted(mmc)) { 70388b8d9a8SManuel Lauss mrq->cmd->error = -ENOMEDIUM; 70488b8d9a8SManuel Lauss au1xmmc_finish_request(host); 70588b8d9a8SManuel Lauss return; 70688b8d9a8SManuel Lauss } 70788b8d9a8SManuel Lauss 7081c6a0718SPierre Ossman if (mrq->data) { 7091c6a0718SPierre Ossman FLUSH_FIFO(host); 7101c6a0718SPierre Ossman ret = au1xmmc_prepare_data(host, mrq->data); 7111c6a0718SPierre Ossman } 7121c6a0718SPierre Ossman 71317b0429dSPierre Ossman if (!ret) 714be0192aaSPierre Ossman ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data); 7151c6a0718SPierre Ossman 71617b0429dSPierre Ossman if (ret) { 7171c6a0718SPierre Ossman mrq->cmd->error = ret; 7181c6a0718SPierre Ossman au1xmmc_finish_request(host); 7191c6a0718SPierre Ossman } 7201c6a0718SPierre Ossman } 7211c6a0718SPierre Ossman 7221c6a0718SPierre Ossman static void au1xmmc_reset_controller(struct au1xmmc_host *host) 7231c6a0718SPierre Ossman { 7241c6a0718SPierre Ossman /* Apply the clock */ 7252f73bfbeSManuel Lauss __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host)); 7262f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7272f73bfbeSManuel Lauss mdelay(1); 7281c6a0718SPierre Ossman 7292f73bfbeSManuel Lauss __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); 7302f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7312f73bfbeSManuel Lauss mdelay(5); 7321c6a0718SPierre Ossman 7332f73bfbeSManuel Lauss __raw_writel(~0, HOST_STATUS(host)); 7342f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7351c6a0718SPierre Ossman 7362f73bfbeSManuel Lauss __raw_writel(0, HOST_BLKSIZE(host)); 7372f73bfbeSManuel Lauss __raw_writel(0x001fffff, HOST_TIMEOUT(host)); 7382f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7391c6a0718SPierre Ossman 7402f73bfbeSManuel Lauss __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 7412f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7421c6a0718SPierre Ossman 7432f73bfbeSManuel Lauss __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); 7442f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7452f73bfbeSManuel Lauss mdelay(1); 7461c6a0718SPierre Ossman 7472f73bfbeSManuel Lauss __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 7482f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7491c6a0718SPierre Ossman 7501c6a0718SPierre Ossman /* Configure interrupts */ 7512f73bfbeSManuel Lauss __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); 7522f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7531c6a0718SPierre Ossman } 7541c6a0718SPierre Ossman 7551c6a0718SPierre Ossman 7561c6a0718SPierre Ossman static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 7571c6a0718SPierre Ossman { 7581c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 759281dd23eSManuel Lauss u32 config2; 7601c6a0718SPierre Ossman 7611c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) 7621c6a0718SPierre Ossman au1xmmc_set_power(host, 0); 7631c6a0718SPierre Ossman else if (ios->power_mode == MMC_POWER_ON) { 7641c6a0718SPierre Ossman au1xmmc_set_power(host, 1); 7651c6a0718SPierre Ossman } 7661c6a0718SPierre Ossman 7671c6a0718SPierre Ossman if (ios->clock && ios->clock != host->clock) { 7681c6a0718SPierre Ossman au1xmmc_set_clock(host, ios->clock); 7691c6a0718SPierre Ossman host->clock = ios->clock; 7701c6a0718SPierre Ossman } 771281dd23eSManuel Lauss 7722f73bfbeSManuel Lauss config2 = __raw_readl(HOST_CONFIG2(host)); 773281dd23eSManuel Lauss switch (ios->bus_width) { 774809f36c6SManuel Lauss case MMC_BUS_WIDTH_8: 775809f36c6SManuel Lauss config2 |= SD_CONFIG2_BB; 776809f36c6SManuel Lauss break; 777281dd23eSManuel Lauss case MMC_BUS_WIDTH_4: 778809f36c6SManuel Lauss config2 &= ~SD_CONFIG2_BB; 779281dd23eSManuel Lauss config2 |= SD_CONFIG2_WB; 780281dd23eSManuel Lauss break; 781281dd23eSManuel Lauss case MMC_BUS_WIDTH_1: 782809f36c6SManuel Lauss config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB); 783281dd23eSManuel Lauss break; 784281dd23eSManuel Lauss } 7852f73bfbeSManuel Lauss __raw_writel(config2, HOST_CONFIG2(host)); 7862f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 7871c6a0718SPierre Ossman } 7881c6a0718SPierre Ossman 789c4223c2cSManuel Lauss #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) 790c4223c2cSManuel Lauss #define STATUS_DATA_IN (SD_STATUS_NE) 791c4223c2cSManuel Lauss #define STATUS_DATA_OUT (SD_STATUS_TH) 792c4223c2cSManuel Lauss 793c4223c2cSManuel Lauss static irqreturn_t au1xmmc_irq(int irq, void *dev_id) 794c4223c2cSManuel Lauss { 795c4223c2cSManuel Lauss struct au1xmmc_host *host = dev_id; 796c4223c2cSManuel Lauss u32 status; 797c4223c2cSManuel Lauss 7982f73bfbeSManuel Lauss status = __raw_readl(HOST_STATUS(host)); 799c4223c2cSManuel Lauss 800c4223c2cSManuel Lauss if (!(status & SD_STATUS_I)) 801c4223c2cSManuel Lauss return IRQ_NONE; /* not ours */ 802c4223c2cSManuel Lauss 80320f522ffSManuel Lauss if (status & SD_STATUS_SI) /* SDIO */ 80420f522ffSManuel Lauss mmc_signal_sdio_irq(host->mmc); 80520f522ffSManuel Lauss 806c4223c2cSManuel Lauss if (host->mrq && (status & STATUS_TIMEOUT)) { 807c4223c2cSManuel Lauss if (status & SD_STATUS_RAT) 808c4223c2cSManuel Lauss host->mrq->cmd->error = -ETIMEDOUT; 809c4223c2cSManuel Lauss else if (status & SD_STATUS_DT) 810c4223c2cSManuel Lauss host->mrq->data->error = -ETIMEDOUT; 811c4223c2cSManuel Lauss 812c4223c2cSManuel Lauss /* In PIO mode, interrupts might still be enabled */ 813c4223c2cSManuel Lauss IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); 814c4223c2cSManuel Lauss 815c4223c2cSManuel Lauss /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ 816c4223c2cSManuel Lauss tasklet_schedule(&host->finish_task); 817c4223c2cSManuel Lauss } 818c4223c2cSManuel Lauss #if 0 819c4223c2cSManuel Lauss else if (status & SD_STATUS_DD) { 820c4223c2cSManuel Lauss /* Sometimes we get a DD before a NE in PIO mode */ 821c4223c2cSManuel Lauss if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) 822c4223c2cSManuel Lauss au1xmmc_receive_pio(host); 823c4223c2cSManuel Lauss else { 824c4223c2cSManuel Lauss au1xmmc_data_complete(host, status); 825c4223c2cSManuel Lauss /* tasklet_schedule(&host->data_task); */ 826c4223c2cSManuel Lauss } 827c4223c2cSManuel Lauss } 828c4223c2cSManuel Lauss #endif 829c4223c2cSManuel Lauss else if (status & SD_STATUS_CR) { 830c4223c2cSManuel Lauss if (host->status == HOST_S_CMD) 831c4223c2cSManuel Lauss au1xmmc_cmd_complete(host, status); 832c4223c2cSManuel Lauss 833c4223c2cSManuel Lauss } else if (!(host->flags & HOST_F_DMA)) { 834c4223c2cSManuel Lauss if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) 835c4223c2cSManuel Lauss au1xmmc_send_pio(host); 836c4223c2cSManuel Lauss else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) 837c4223c2cSManuel Lauss au1xmmc_receive_pio(host); 838c4223c2cSManuel Lauss 839c4223c2cSManuel Lauss } else if (status & 0x203F3C70) { 840c4223c2cSManuel Lauss DBG("Unhandled status %8.8x\n", host->pdev->id, 841c4223c2cSManuel Lauss status); 842c4223c2cSManuel Lauss } 843c4223c2cSManuel Lauss 8442f73bfbeSManuel Lauss __raw_writel(status, HOST_STATUS(host)); 8452f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 846c4223c2cSManuel Lauss 847c4223c2cSManuel Lauss return IRQ_HANDLED; 848c4223c2cSManuel Lauss } 849c4223c2cSManuel Lauss 850c4223c2cSManuel Lauss /* 8bit memory DMA device */ 851c4223c2cSManuel Lauss static dbdev_tab_t au1xmmc_mem_dbdev = { 852c4223c2cSManuel Lauss .dev_id = DSCR_CMD0_ALWAYS, 853c4223c2cSManuel Lauss .dev_flags = DEV_FLAGS_ANYUSE, 854c4223c2cSManuel Lauss .dev_tsize = 0, 855c4223c2cSManuel Lauss .dev_devwidth = 8, 856c4223c2cSManuel Lauss .dev_physaddr = 0x00000000, 857c4223c2cSManuel Lauss .dev_intlevel = 0, 858c4223c2cSManuel Lauss .dev_intpolarity = 0, 859c4223c2cSManuel Lauss }; 860c4223c2cSManuel Lauss static int memid; 861c4223c2cSManuel Lauss 862c4223c2cSManuel Lauss static void au1xmmc_dbdma_callback(int irq, void *dev_id) 8631c6a0718SPierre Ossman { 8641c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; 8651c6a0718SPierre Ossman 8661c6a0718SPierre Ossman /* Avoid spurious interrupts */ 8671c6a0718SPierre Ossman if (!host->mrq) 8681c6a0718SPierre Ossman return; 8691c6a0718SPierre Ossman 8701c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 8711c6a0718SPierre Ossman SEND_STOP(host); 8721c6a0718SPierre Ossman 8731c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 8741c6a0718SPierre Ossman } 8751c6a0718SPierre Ossman 876c4223c2cSManuel Lauss static int au1xmmc_dbdma_init(struct au1xmmc_host *host) 8771c6a0718SPierre Ossman { 878c4223c2cSManuel Lauss struct resource *res; 879c4223c2cSManuel Lauss int txid, rxid; 8801c6a0718SPierre Ossman 881c4223c2cSManuel Lauss res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); 882c4223c2cSManuel Lauss if (!res) 883c4223c2cSManuel Lauss return -ENODEV; 884c4223c2cSManuel Lauss txid = res->start; 8851c6a0718SPierre Ossman 886c4223c2cSManuel Lauss res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); 887c4223c2cSManuel Lauss if (!res) 888c4223c2cSManuel Lauss return -ENODEV; 889c4223c2cSManuel Lauss rxid = res->start; 8901c6a0718SPierre Ossman 891c4223c2cSManuel Lauss if (!memid) 892c4223c2cSManuel Lauss return -ENODEV; 8931c6a0718SPierre Ossman 894c4223c2cSManuel Lauss host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, 895c4223c2cSManuel Lauss au1xmmc_dbdma_callback, (void *)host); 896c4223c2cSManuel Lauss if (!host->tx_chan) { 897c4223c2cSManuel Lauss dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); 898c4223c2cSManuel Lauss return -ENODEV; 8991c6a0718SPierre Ossman } 9001c6a0718SPierre Ossman 901c4223c2cSManuel Lauss host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, 902c4223c2cSManuel Lauss au1xmmc_dbdma_callback, (void *)host); 903c4223c2cSManuel Lauss if (!host->rx_chan) { 904c4223c2cSManuel Lauss dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); 905c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->tx_chan); 906c4223c2cSManuel Lauss return -ENODEV; 907c4223c2cSManuel Lauss } 9081c6a0718SPierre Ossman 909c4223c2cSManuel Lauss au1xxx_dbdma_set_devwidth(host->tx_chan, 8); 910c4223c2cSManuel Lauss au1xxx_dbdma_set_devwidth(host->rx_chan, 8); 911c4223c2cSManuel Lauss 912c4223c2cSManuel Lauss au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); 913c4223c2cSManuel Lauss au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); 914c4223c2cSManuel Lauss 915c4223c2cSManuel Lauss /* DBDMA is good to go */ 9161177d99dSManuel Lauss host->flags |= HOST_F_DMA | HOST_F_DBDMA; 917c4223c2cSManuel Lauss 918c4223c2cSManuel Lauss return 0; 919c4223c2cSManuel Lauss } 920c4223c2cSManuel Lauss 921c4223c2cSManuel Lauss static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) 922c4223c2cSManuel Lauss { 923c4223c2cSManuel Lauss if (host->flags & HOST_F_DMA) { 924c4223c2cSManuel Lauss host->flags &= ~HOST_F_DMA; 925c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->tx_chan); 926c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->rx_chan); 9271c6a0718SPierre Ossman } 9281c6a0718SPierre Ossman } 9291c6a0718SPierre Ossman 93020f522ffSManuel Lauss static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) 93120f522ffSManuel Lauss { 93220f522ffSManuel Lauss struct au1xmmc_host *host = mmc_priv(mmc); 93320f522ffSManuel Lauss 93420f522ffSManuel Lauss if (en) 93520f522ffSManuel Lauss IRQ_ON(host, SD_CONFIG_SI); 93620f522ffSManuel Lauss else 93720f522ffSManuel Lauss IRQ_OFF(host, SD_CONFIG_SI); 93820f522ffSManuel Lauss } 93920f522ffSManuel Lauss 9401c6a0718SPierre Ossman static const struct mmc_host_ops au1xmmc_ops = { 9411c6a0718SPierre Ossman .request = au1xmmc_request, 9421c6a0718SPierre Ossman .set_ios = au1xmmc_set_ios, 9431c6a0718SPierre Ossman .get_ro = au1xmmc_card_readonly, 944e2d26477SManuel Lauss .get_cd = au1xmmc_card_inserted, 94520f522ffSManuel Lauss .enable_sdio_irq = au1xmmc_enable_sdio_irq, 9461c6a0718SPierre Ossman }; 9471c6a0718SPierre Ossman 948c3be1efdSBill Pemberton static int au1xmmc_probe(struct platform_device *pdev) 949c4223c2cSManuel Lauss { 950c4223c2cSManuel Lauss struct mmc_host *mmc; 951c4223c2cSManuel Lauss struct au1xmmc_host *host; 952c4223c2cSManuel Lauss struct resource *r; 953809f36c6SManuel Lauss int ret, iflag; 954c4223c2cSManuel Lauss 955c4223c2cSManuel Lauss mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); 9561c6a0718SPierre Ossman if (!mmc) { 957c4223c2cSManuel Lauss dev_err(&pdev->dev, "no memory for mmc_host\n"); 958c4223c2cSManuel Lauss ret = -ENOMEM; 959c4223c2cSManuel Lauss goto out0; 960c4223c2cSManuel Lauss } 961c4223c2cSManuel Lauss 962c4223c2cSManuel Lauss host = mmc_priv(mmc); 963c4223c2cSManuel Lauss host->mmc = mmc; 964c4223c2cSManuel Lauss host->platdata = pdev->dev.platform_data; 965c4223c2cSManuel Lauss host->pdev = pdev; 966c4223c2cSManuel Lauss 967c4223c2cSManuel Lauss ret = -ENODEV; 968c4223c2cSManuel Lauss r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 969c4223c2cSManuel Lauss if (!r) { 970c4223c2cSManuel Lauss dev_err(&pdev->dev, "no mmio defined\n"); 971c4223c2cSManuel Lauss goto out1; 972c4223c2cSManuel Lauss } 973c4223c2cSManuel Lauss 9747a5ea56aSH Hartley Sweeten host->ioarea = request_mem_region(r->start, resource_size(r), 975c4223c2cSManuel Lauss pdev->name); 976c4223c2cSManuel Lauss if (!host->ioarea) { 977c4223c2cSManuel Lauss dev_err(&pdev->dev, "mmio already in use\n"); 978c4223c2cSManuel Lauss goto out1; 979c4223c2cSManuel Lauss } 980c4223c2cSManuel Lauss 9812f73bfbeSManuel Lauss host->iobase = ioremap(r->start, 0x3c); 982c4223c2cSManuel Lauss if (!host->iobase) { 983c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot remap mmio\n"); 984c4223c2cSManuel Lauss goto out2; 985c4223c2cSManuel Lauss } 986c4223c2cSManuel Lauss 98767d7d920SYangtao Li host->irq = platform_get_irq(pdev, 0); 98867d7d920SYangtao Li if (host->irq < 0) 989c4223c2cSManuel Lauss goto out3; 9901c6a0718SPierre Ossman 9911c6a0718SPierre Ossman mmc->ops = &au1xmmc_ops; 9921c6a0718SPierre Ossman 9931c6a0718SPierre Ossman mmc->f_min = 450000; 9941c6a0718SPierre Ossman mmc->f_max = 24000000; 9951c6a0718SPierre Ossman 9961c6a0718SPierre Ossman mmc->max_blk_size = 2048; 9971c6a0718SPierre Ossman mmc->max_blk_count = 512; 9981c6a0718SPierre Ossman 9991c6a0718SPierre Ossman mmc->ocr_avail = AU1XMMC_OCR; 100020f522ffSManuel Lauss mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1001809f36c6SManuel Lauss mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; 1002809f36c6SManuel Lauss 1003809f36c6SManuel Lauss iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */ 1004809f36c6SManuel Lauss 1005809f36c6SManuel Lauss switch (alchemy_get_cputype()) { 1006809f36c6SManuel Lauss case ALCHEMY_CPU_AU1100: 1007809f36c6SManuel Lauss mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; 1008809f36c6SManuel Lauss break; 1009809f36c6SManuel Lauss case ALCHEMY_CPU_AU1200: 1010809f36c6SManuel Lauss mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; 1011809f36c6SManuel Lauss break; 1012809f36c6SManuel Lauss case ALCHEMY_CPU_AU1300: 1013809f36c6SManuel Lauss iflag = 0; /* nothing is shared */ 1014809f36c6SManuel Lauss mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; 1015809f36c6SManuel Lauss mmc->f_max = 52000000; 1016809f36c6SManuel Lauss if (host->ioarea->start == AU1100_SD0_PHYS_ADDR) 1017809f36c6SManuel Lauss mmc->caps |= MMC_CAP_8_BIT_DATA; 1018809f36c6SManuel Lauss break; 1019809f36c6SManuel Lauss } 1020809f36c6SManuel Lauss 1021809f36c6SManuel Lauss ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host); 1022809f36c6SManuel Lauss if (ret) { 1023809f36c6SManuel Lauss dev_err(&pdev->dev, "cannot grab IRQ\n"); 1024809f36c6SManuel Lauss goto out3; 1025809f36c6SManuel Lauss } 10261c6a0718SPierre Ossman 1027b6507596SManuel Lauss host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK); 1028b6507596SManuel Lauss if (IS_ERR(host->clk)) { 1029b6507596SManuel Lauss dev_err(&pdev->dev, "cannot find clock\n"); 1030ee9d19d4SWei Yongjun ret = PTR_ERR(host->clk); 1031b6507596SManuel Lauss goto out_irq; 1032b6507596SManuel Lauss } 1033ee9d19d4SWei Yongjun 1034ee9d19d4SWei Yongjun ret = clk_prepare_enable(host->clk); 1035ee9d19d4SWei Yongjun if (ret) { 1036b6507596SManuel Lauss dev_err(&pdev->dev, "cannot enable clock\n"); 1037b6507596SManuel Lauss goto out_clk; 1038b6507596SManuel Lauss } 1039b6507596SManuel Lauss 10401c6a0718SPierre Ossman host->status = HOST_S_IDLE; 10411c6a0718SPierre Ossman 1042c4223c2cSManuel Lauss /* board-specific carddetect setup, if any */ 1043c4223c2cSManuel Lauss if (host->platdata && host->platdata->cd_setup) { 1044c4223c2cSManuel Lauss ret = host->platdata->cd_setup(mmc, 1); 1045c4223c2cSManuel Lauss if (ret) { 1046e2d26477SManuel Lauss dev_warn(&pdev->dev, "board CD setup failed\n"); 1047e2d26477SManuel Lauss mmc->caps |= MMC_CAP_NEEDS_POLL; 1048c4223c2cSManuel Lauss } 1049e2d26477SManuel Lauss } else 1050e2d26477SManuel Lauss mmc->caps |= MMC_CAP_NEEDS_POLL; 10511c6a0718SPierre Ossman 10523b839070SManuel Lauss /* platform may not be able to use all advertised caps */ 10533b839070SManuel Lauss if (host->platdata) 10543b839070SManuel Lauss mmc->caps &= ~(host->platdata->mask_host_caps); 10553b839070SManuel Lauss 10561c6a0718SPierre Ossman tasklet_init(&host->data_task, au1xmmc_tasklet_data, 10571c6a0718SPierre Ossman (unsigned long)host); 10581c6a0718SPierre Ossman 10591c6a0718SPierre Ossman tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, 10601c6a0718SPierre Ossman (unsigned long)host); 10611c6a0718SPierre Ossman 10621177d99dSManuel Lauss if (has_dbdma()) { 1063c4223c2cSManuel Lauss ret = au1xmmc_dbdma_init(host); 1064c4223c2cSManuel Lauss if (ret) 1065a3c76eb9SGirish K S pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n"); 10661177d99dSManuel Lauss } 10671c6a0718SPierre Ossman 1068c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1069c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) { 1070c4223c2cSManuel Lauss struct led_classdev *led = host->platdata->led; 1071c4223c2cSManuel Lauss led->name = mmc_hostname(mmc); 1072c4223c2cSManuel Lauss led->brightness = LED_OFF; 1073c4223c2cSManuel Lauss led->default_trigger = mmc_hostname(mmc); 1074c4223c2cSManuel Lauss ret = led_classdev_register(mmc_dev(mmc), led); 1075c4223c2cSManuel Lauss if (ret) 1076c4223c2cSManuel Lauss goto out5; 1077c4223c2cSManuel Lauss } 1078c4223c2cSManuel Lauss #endif 10791c6a0718SPierre Ossman 10801c6a0718SPierre Ossman au1xmmc_reset_controller(host); 10811c6a0718SPierre Ossman 1082c4223c2cSManuel Lauss ret = mmc_add_host(mmc); 1083c4223c2cSManuel Lauss if (ret) { 1084c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot add mmc host\n"); 1085c4223c2cSManuel Lauss goto out6; 1086c4223c2cSManuel Lauss } 10871c6a0718SPierre Ossman 1088dd8572afSManuel Lauss platform_set_drvdata(pdev, host); 1089c4223c2cSManuel Lauss 10902f73bfbeSManuel Lauss pr_info(DRIVER_NAME ": MMC Controller %d set up at %p" 1091c4223c2cSManuel Lauss " (mode=%s)\n", pdev->id, host->iobase, 1092c4223c2cSManuel Lauss host->flags & HOST_F_DMA ? "dma" : "pio"); 10931c6a0718SPierre Ossman 1094c4223c2cSManuel Lauss return 0; /* all ok */ 10951c6a0718SPierre Ossman 1096c4223c2cSManuel Lauss out6: 1097c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1098c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) 1099c4223c2cSManuel Lauss led_classdev_unregister(host->platdata->led); 1100c4223c2cSManuel Lauss out5: 1101c4223c2cSManuel Lauss #endif 11022f73bfbeSManuel Lauss __raw_writel(0, HOST_ENABLE(host)); 11032f73bfbeSManuel Lauss __raw_writel(0, HOST_CONFIG(host)); 11042f73bfbeSManuel Lauss __raw_writel(0, HOST_CONFIG2(host)); 11052f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 11061c6a0718SPierre Ossman 11071177d99dSManuel Lauss if (host->flags & HOST_F_DBDMA) 1108c4223c2cSManuel Lauss au1xmmc_dbdma_shutdown(host); 11091c6a0718SPierre Ossman 11101c6a0718SPierre Ossman tasklet_kill(&host->data_task); 11111c6a0718SPierre Ossman tasklet_kill(&host->finish_task); 11121c6a0718SPierre Ossman 1113e2d26477SManuel Lauss if (host->platdata && host->platdata->cd_setup && 1114e2d26477SManuel Lauss !(mmc->caps & MMC_CAP_NEEDS_POLL)) 1115c4223c2cSManuel Lauss host->platdata->cd_setup(mmc, 0); 1116b6507596SManuel Lauss out_clk: 1117b6507596SManuel Lauss clk_disable_unprepare(host->clk); 1118b6507596SManuel Lauss clk_put(host->clk); 1119b6507596SManuel Lauss out_irq: 1120c4223c2cSManuel Lauss free_irq(host->irq, host); 1121c4223c2cSManuel Lauss out3: 1122c4223c2cSManuel Lauss iounmap((void *)host->iobase); 1123c4223c2cSManuel Lauss out2: 1124c4223c2cSManuel Lauss release_resource(host->ioarea); 1125c4223c2cSManuel Lauss kfree(host->ioarea); 1126c4223c2cSManuel Lauss out1: 1127c4223c2cSManuel Lauss mmc_free_host(mmc); 1128c4223c2cSManuel Lauss out0: 1129c4223c2cSManuel Lauss return ret; 11301c6a0718SPierre Ossman } 11311c6a0718SPierre Ossman 11326e0ee714SBill Pemberton static int au1xmmc_remove(struct platform_device *pdev) 1133c4223c2cSManuel Lauss { 1134dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1135c4223c2cSManuel Lauss 1136dd8572afSManuel Lauss if (host) { 1137dd8572afSManuel Lauss mmc_remove_host(host->mmc); 1138c4223c2cSManuel Lauss 1139c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1140c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) 1141c4223c2cSManuel Lauss led_classdev_unregister(host->platdata->led); 1142c4223c2cSManuel Lauss #endif 1143c4223c2cSManuel Lauss 1144e2d26477SManuel Lauss if (host->platdata && host->platdata->cd_setup && 1145dd8572afSManuel Lauss !(host->mmc->caps & MMC_CAP_NEEDS_POLL)) 1146dd8572afSManuel Lauss host->platdata->cd_setup(host->mmc, 0); 1147c4223c2cSManuel Lauss 11482f73bfbeSManuel Lauss __raw_writel(0, HOST_ENABLE(host)); 11492f73bfbeSManuel Lauss __raw_writel(0, HOST_CONFIG(host)); 11502f73bfbeSManuel Lauss __raw_writel(0, HOST_CONFIG2(host)); 11512f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 1152c4223c2cSManuel Lauss 1153c4223c2cSManuel Lauss tasklet_kill(&host->data_task); 1154c4223c2cSManuel Lauss tasklet_kill(&host->finish_task); 1155c4223c2cSManuel Lauss 11561177d99dSManuel Lauss if (host->flags & HOST_F_DBDMA) 1157c4223c2cSManuel Lauss au1xmmc_dbdma_shutdown(host); 11581177d99dSManuel Lauss 1159c4223c2cSManuel Lauss au1xmmc_set_power(host, 0); 1160c4223c2cSManuel Lauss 1161b6507596SManuel Lauss clk_disable_unprepare(host->clk); 1162b6507596SManuel Lauss clk_put(host->clk); 1163b6507596SManuel Lauss 1164c4223c2cSManuel Lauss free_irq(host->irq, host); 1165c4223c2cSManuel Lauss iounmap((void *)host->iobase); 1166c4223c2cSManuel Lauss release_resource(host->ioarea); 1167c4223c2cSManuel Lauss kfree(host->ioarea); 1168c4223c2cSManuel Lauss 1169dd8572afSManuel Lauss mmc_free_host(host->mmc); 1170c4223c2cSManuel Lauss } 11711c6a0718SPierre Ossman return 0; 11721c6a0718SPierre Ossman } 11731c6a0718SPierre Ossman 1174dd8572afSManuel Lauss #ifdef CONFIG_PM 1175dd8572afSManuel Lauss static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state) 1176dd8572afSManuel Lauss { 1177dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1178dd8572afSManuel Lauss 11792f73bfbeSManuel Lauss __raw_writel(0, HOST_CONFIG2(host)); 11802f73bfbeSManuel Lauss __raw_writel(0, HOST_CONFIG(host)); 11812f73bfbeSManuel Lauss __raw_writel(0xffffffff, HOST_STATUS(host)); 11822f73bfbeSManuel Lauss __raw_writel(0, HOST_ENABLE(host)); 11832f73bfbeSManuel Lauss wmb(); /* drain writebuffer */ 1184dd8572afSManuel Lauss 1185dd8572afSManuel Lauss return 0; 1186dd8572afSManuel Lauss } 1187dd8572afSManuel Lauss 1188dd8572afSManuel Lauss static int au1xmmc_resume(struct platform_device *pdev) 1189dd8572afSManuel Lauss { 1190dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1191dd8572afSManuel Lauss 1192dd8572afSManuel Lauss au1xmmc_reset_controller(host); 1193dd8572afSManuel Lauss 11941e63d485SUlf Hansson return 0; 1195dd8572afSManuel Lauss } 1196dd8572afSManuel Lauss #else 1197dd8572afSManuel Lauss #define au1xmmc_suspend NULL 1198dd8572afSManuel Lauss #define au1xmmc_resume NULL 1199dd8572afSManuel Lauss #endif 1200dd8572afSManuel Lauss 12011c6a0718SPierre Ossman static struct platform_driver au1xmmc_driver = { 12021c6a0718SPierre Ossman .probe = au1xmmc_probe, 12031c6a0718SPierre Ossman .remove = au1xmmc_remove, 1204dd8572afSManuel Lauss .suspend = au1xmmc_suspend, 1205dd8572afSManuel Lauss .resume = au1xmmc_resume, 12061c6a0718SPierre Ossman .driver = { 12071c6a0718SPierre Ossman .name = DRIVER_NAME, 12081c6a0718SPierre Ossman }, 12091c6a0718SPierre Ossman }; 12101c6a0718SPierre Ossman 12111c6a0718SPierre Ossman static int __init au1xmmc_init(void) 12121c6a0718SPierre Ossman { 12131177d99dSManuel Lauss if (has_dbdma()) { 1214c4223c2cSManuel Lauss /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride 1215c4223c2cSManuel Lauss * of 8 bits. And since devices are shared, we need to create 1216c4223c2cSManuel Lauss * our own to avoid freaking out other devices. 1217c4223c2cSManuel Lauss */ 1218c4223c2cSManuel Lauss memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); 1219c4223c2cSManuel Lauss if (!memid) 1220d6748066SLinus Torvalds pr_err("au1xmmc: cannot add memory dbdma\n"); 12211177d99dSManuel Lauss } 12221c6a0718SPierre Ossman return platform_driver_register(&au1xmmc_driver); 12231c6a0718SPierre Ossman } 12241c6a0718SPierre Ossman 12251c6a0718SPierre Ossman static void __exit au1xmmc_exit(void) 12261c6a0718SPierre Ossman { 12271177d99dSManuel Lauss if (has_dbdma() && memid) 1228c4223c2cSManuel Lauss au1xxx_ddma_del_device(memid); 12291177d99dSManuel Lauss 12301c6a0718SPierre Ossman platform_driver_unregister(&au1xmmc_driver); 12311c6a0718SPierre Ossman } 12321c6a0718SPierre Ossman 12331c6a0718SPierre Ossman module_init(au1xmmc_init); 12341c6a0718SPierre Ossman module_exit(au1xmmc_exit); 12351c6a0718SPierre Ossman 12361c6a0718SPierre Ossman MODULE_AUTHOR("Advanced Micro Devices, Inc"); 12371c6a0718SPierre Ossman MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); 12381c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1239bc65c724SKay Sievers MODULE_ALIAS("platform:au1xxx-mmc"); 1240