11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (c) 2005, Advanced Micro Devices, Inc. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * Developed with help from the 2.4.30 MMC AU1XXX controller including 71c6a0718SPierre Ossman * the following copyright notices: 81c6a0718SPierre Ossman * Copyright (c) 2003-2004 Embedded Edge, LLC. 91c6a0718SPierre Ossman * Portions Copyright (C) 2002 Embedix, Inc 101c6a0718SPierre Ossman * Copyright 2002 Hewlett-Packard Company 111c6a0718SPierre Ossman 121c6a0718SPierre Ossman * 2.6 version of this driver inspired by: 131c6a0718SPierre Ossman * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, 141c6a0718SPierre Ossman * All Rights Reserved. 151c6a0718SPierre Ossman * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, 161c6a0718SPierre Ossman * All Rights Reserved. 171c6a0718SPierre Ossman * 181c6a0718SPierre Ossman 191c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 201c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 211c6a0718SPierre Ossman * published by the Free Software Foundation. 221c6a0718SPierre Ossman */ 231c6a0718SPierre Ossman 24e2d26477SManuel Lauss /* Why don't we use the SD controllers' carddetect feature? 251c6a0718SPierre Ossman * 261c6a0718SPierre Ossman * From the AU1100 MMC application guide: 271c6a0718SPierre Ossman * If the Au1100-based design is intended to support both MultiMediaCards 281c6a0718SPierre Ossman * and 1- or 4-data bit SecureDigital cards, then the solution is to 291c6a0718SPierre Ossman * connect a weak (560KOhm) pull-up resistor to connector pin 1. 301c6a0718SPierre Ossman * In doing so, a MMC card never enters SPI-mode communications, 311c6a0718SPierre Ossman * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective 321c6a0718SPierre Ossman * (the low to high transition will not occur). 331c6a0718SPierre Ossman */ 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #include <linux/module.h> 361c6a0718SPierre Ossman #include <linux/init.h> 371c6a0718SPierre Ossman #include <linux/platform_device.h> 381c6a0718SPierre Ossman #include <linux/mm.h> 391c6a0718SPierre Ossman #include <linux/interrupt.h> 401c6a0718SPierre Ossman #include <linux/dma-mapping.h> 410ada7a02SAl Viro #include <linux/scatterlist.h> 42c4223c2cSManuel Lauss #include <linux/leds.h> 431c6a0718SPierre Ossman #include <linux/mmc/host.h> 445a0e3ad6STejun Heo #include <linux/slab.h> 45c4223c2cSManuel Lauss 461c6a0718SPierre Ossman #include <asm/io.h> 471c6a0718SPierre Ossman #include <asm/mach-au1x00/au1000.h> 481c6a0718SPierre Ossman #include <asm/mach-au1x00/au1xxx_dbdma.h> 491c6a0718SPierre Ossman #include <asm/mach-au1x00/au1100_mmc.h> 501c6a0718SPierre Ossman 511c6a0718SPierre Ossman #define DRIVER_NAME "au1xxx-mmc" 521c6a0718SPierre Ossman 531c6a0718SPierre Ossman /* Set this to enable special debugging macros */ 54c4223c2cSManuel Lauss /* #define DEBUG */ 551c6a0718SPierre Ossman 561c6a0718SPierre Ossman #ifdef DEBUG 575c0a889dSManuel Lauss #define DBG(fmt, idx, args...) \ 58a3c76eb9SGirish K S pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args) 591c6a0718SPierre Ossman #else 605c0a889dSManuel Lauss #define DBG(fmt, idx, args...) do {} while (0) 611c6a0718SPierre Ossman #endif 621c6a0718SPierre Ossman 635c0a889dSManuel Lauss /* Hardware definitions */ 645c0a889dSManuel Lauss #define AU1XMMC_DESCRIPTOR_COUNT 1 65e491d230SManuel Lauss 66e491d230SManuel Lauss /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */ 671177d99dSManuel Lauss #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff 681177d99dSManuel Lauss #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff 695c0a889dSManuel Lauss 705c0a889dSManuel Lauss #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ 715c0a889dSManuel Lauss MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ 725c0a889dSManuel Lauss MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) 735c0a889dSManuel Lauss 745c0a889dSManuel Lauss /* This gives us a hard value for the stop command that we can write directly 755c0a889dSManuel Lauss * to the command register. 765c0a889dSManuel Lauss */ 775c0a889dSManuel Lauss #define STOP_CMD \ 785c0a889dSManuel Lauss (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO) 795c0a889dSManuel Lauss 805c0a889dSManuel Lauss /* This is the set of interrupts that we configure by default. */ 815c0a889dSManuel Lauss #define AU1XMMC_INTERRUPTS \ 825c0a889dSManuel Lauss (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \ 835c0a889dSManuel Lauss SD_CONFIG_CR | SD_CONFIG_I) 845c0a889dSManuel Lauss 855c0a889dSManuel Lauss /* The poll event (looking for insert/remove events runs twice a second. */ 865c0a889dSManuel Lauss #define AU1XMMC_DETECT_TIMEOUT (HZ/2) 875c0a889dSManuel Lauss 885c0a889dSManuel Lauss struct au1xmmc_host { 895c0a889dSManuel Lauss struct mmc_host *mmc; 905c0a889dSManuel Lauss struct mmc_request *mrq; 915c0a889dSManuel Lauss 925c0a889dSManuel Lauss u32 flags; 935c0a889dSManuel Lauss u32 iobase; 945c0a889dSManuel Lauss u32 clock; 955c0a889dSManuel Lauss u32 bus_width; 965c0a889dSManuel Lauss u32 power_mode; 975c0a889dSManuel Lauss 985c0a889dSManuel Lauss int status; 995c0a889dSManuel Lauss 1005c0a889dSManuel Lauss struct { 1015c0a889dSManuel Lauss int len; 1025c0a889dSManuel Lauss int dir; 1035c0a889dSManuel Lauss } dma; 1045c0a889dSManuel Lauss 1055c0a889dSManuel Lauss struct { 1065c0a889dSManuel Lauss int index; 1075c0a889dSManuel Lauss int offset; 1085c0a889dSManuel Lauss int len; 1095c0a889dSManuel Lauss } pio; 1105c0a889dSManuel Lauss 1115c0a889dSManuel Lauss u32 tx_chan; 1125c0a889dSManuel Lauss u32 rx_chan; 1135c0a889dSManuel Lauss 1145c0a889dSManuel Lauss int irq; 1155c0a889dSManuel Lauss 1165c0a889dSManuel Lauss struct tasklet_struct finish_task; 1175c0a889dSManuel Lauss struct tasklet_struct data_task; 1185c0a889dSManuel Lauss struct au1xmmc_platform_data *platdata; 1195c0a889dSManuel Lauss struct platform_device *pdev; 1205c0a889dSManuel Lauss struct resource *ioarea; 1215c0a889dSManuel Lauss }; 1225c0a889dSManuel Lauss 1235c0a889dSManuel Lauss /* Status flags used by the host structure */ 1245c0a889dSManuel Lauss #define HOST_F_XMIT 0x0001 1255c0a889dSManuel Lauss #define HOST_F_RECV 0x0002 1265c0a889dSManuel Lauss #define HOST_F_DMA 0x0010 1271177d99dSManuel Lauss #define HOST_F_DBDMA 0x0020 1285c0a889dSManuel Lauss #define HOST_F_ACTIVE 0x0100 1295c0a889dSManuel Lauss #define HOST_F_STOP 0x1000 1305c0a889dSManuel Lauss 1315c0a889dSManuel Lauss #define HOST_S_IDLE 0x0001 1325c0a889dSManuel Lauss #define HOST_S_CMD 0x0002 1335c0a889dSManuel Lauss #define HOST_S_DATA 0x0003 1345c0a889dSManuel Lauss #define HOST_S_STOP 0x0004 1355c0a889dSManuel Lauss 1365c0a889dSManuel Lauss /* Easy access macros */ 1375c0a889dSManuel Lauss #define HOST_STATUS(h) ((h)->iobase + SD_STATUS) 1385c0a889dSManuel Lauss #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) 1395c0a889dSManuel Lauss #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) 1405c0a889dSManuel Lauss #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) 1415c0a889dSManuel Lauss #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) 1425c0a889dSManuel Lauss #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) 1435c0a889dSManuel Lauss #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) 1445c0a889dSManuel Lauss #define HOST_CMD(h) ((h)->iobase + SD_CMD) 1455c0a889dSManuel Lauss #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) 1465c0a889dSManuel Lauss #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) 1475c0a889dSManuel Lauss #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) 1485c0a889dSManuel Lauss 1495c0a889dSManuel Lauss #define DMA_CHANNEL(h) \ 1505c0a889dSManuel Lauss (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) 1515c0a889dSManuel Lauss 1521177d99dSManuel Lauss static inline int has_dbdma(void) 1531177d99dSManuel Lauss { 1541177d99dSManuel Lauss switch (alchemy_get_cputype()) { 1551177d99dSManuel Lauss case ALCHEMY_CPU_AU1200: 156809f36c6SManuel Lauss case ALCHEMY_CPU_AU1300: 1571177d99dSManuel Lauss return 1; 1581177d99dSManuel Lauss default: 1591177d99dSManuel Lauss return 0; 1601177d99dSManuel Lauss } 1611177d99dSManuel Lauss } 1621177d99dSManuel Lauss 1631c6a0718SPierre Ossman static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) 1641c6a0718SPierre Ossman { 1651c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG(host)); 1661c6a0718SPierre Ossman val |= mask; 1671c6a0718SPierre Ossman au_writel(val, HOST_CONFIG(host)); 1681c6a0718SPierre Ossman au_sync(); 1691c6a0718SPierre Ossman } 1701c6a0718SPierre Ossman 1711c6a0718SPierre Ossman static inline void FLUSH_FIFO(struct au1xmmc_host *host) 1721c6a0718SPierre Ossman { 1731c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG2(host)); 1741c6a0718SPierre Ossman 1751c6a0718SPierre Ossman au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); 1761c6a0718SPierre Ossman au_sync_delay(1); 1771c6a0718SPierre Ossman 1781c6a0718SPierre Ossman /* SEND_STOP will turn off clock control - this re-enables it */ 1791c6a0718SPierre Ossman val &= ~SD_CONFIG2_DF; 1801c6a0718SPierre Ossman 1811c6a0718SPierre Ossman au_writel(val, HOST_CONFIG2(host)); 1821c6a0718SPierre Ossman au_sync(); 1831c6a0718SPierre Ossman } 1841c6a0718SPierre Ossman 1851c6a0718SPierre Ossman static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) 1861c6a0718SPierre Ossman { 1871c6a0718SPierre Ossman u32 val = au_readl(HOST_CONFIG(host)); 1881c6a0718SPierre Ossman val &= ~mask; 1891c6a0718SPierre Ossman au_writel(val, HOST_CONFIG(host)); 1901c6a0718SPierre Ossman au_sync(); 1911c6a0718SPierre Ossman } 1921c6a0718SPierre Ossman 1931c6a0718SPierre Ossman static inline void SEND_STOP(struct au1xmmc_host *host) 1941c6a0718SPierre Ossman { 195281dd23eSManuel Lauss u32 config2; 1961c6a0718SPierre Ossman 1971c6a0718SPierre Ossman WARN_ON(host->status != HOST_S_DATA); 1981c6a0718SPierre Ossman host->status = HOST_S_STOP; 1991c6a0718SPierre Ossman 200281dd23eSManuel Lauss config2 = au_readl(HOST_CONFIG2(host)); 201281dd23eSManuel Lauss au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); 2021c6a0718SPierre Ossman au_sync(); 2031c6a0718SPierre Ossman 204b595076aSUwe Kleine-König /* Send the stop command */ 2051c6a0718SPierre Ossman au_writel(STOP_CMD, HOST_CMD(host)); 2061c6a0718SPierre Ossman } 2071c6a0718SPierre Ossman 2081c6a0718SPierre Ossman static void au1xmmc_set_power(struct au1xmmc_host *host, int state) 2091c6a0718SPierre Ossman { 210c4223c2cSManuel Lauss if (host->platdata && host->platdata->set_power) 211c4223c2cSManuel Lauss host->platdata->set_power(host->mmc, state); 2121c6a0718SPierre Ossman } 2131c6a0718SPierre Ossman 214e2d26477SManuel Lauss static int au1xmmc_card_inserted(struct mmc_host *mmc) 2151c6a0718SPierre Ossman { 216e2d26477SManuel Lauss struct au1xmmc_host *host = mmc_priv(mmc); 217c4223c2cSManuel Lauss 218c4223c2cSManuel Lauss if (host->platdata && host->platdata->card_inserted) 219e2d26477SManuel Lauss return !!host->platdata->card_inserted(host->mmc); 220c4223c2cSManuel Lauss 221e2d26477SManuel Lauss return -ENOSYS; 2221c6a0718SPierre Ossman } 2231c6a0718SPierre Ossman 2241c6a0718SPierre Ossman static int au1xmmc_card_readonly(struct mmc_host *mmc) 2251c6a0718SPierre Ossman { 2261c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 227c4223c2cSManuel Lauss 228c4223c2cSManuel Lauss if (host->platdata && host->platdata->card_readonly) 229e2d26477SManuel Lauss return !!host->platdata->card_readonly(mmc); 230c4223c2cSManuel Lauss 231e2d26477SManuel Lauss return -ENOSYS; 2321c6a0718SPierre Ossman } 2331c6a0718SPierre Ossman 2341c6a0718SPierre Ossman static void au1xmmc_finish_request(struct au1xmmc_host *host) 2351c6a0718SPierre Ossman { 2361c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 2371c6a0718SPierre Ossman 2381c6a0718SPierre Ossman host->mrq = NULL; 239c4223c2cSManuel Lauss host->flags &= HOST_F_ACTIVE | HOST_F_DMA; 2401c6a0718SPierre Ossman 2411c6a0718SPierre Ossman host->dma.len = 0; 2421c6a0718SPierre Ossman host->dma.dir = 0; 2431c6a0718SPierre Ossman 2441c6a0718SPierre Ossman host->pio.index = 0; 2451c6a0718SPierre Ossman host->pio.offset = 0; 2461c6a0718SPierre Ossman host->pio.len = 0; 2471c6a0718SPierre Ossman 2481c6a0718SPierre Ossman host->status = HOST_S_IDLE; 2491c6a0718SPierre Ossman 2501c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 2511c6a0718SPierre Ossman } 2521c6a0718SPierre Ossman 2531c6a0718SPierre Ossman static void au1xmmc_tasklet_finish(unsigned long param) 2541c6a0718SPierre Ossman { 2551c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *) param; 2561c6a0718SPierre Ossman au1xmmc_finish_request(host); 2571c6a0718SPierre Ossman } 2581c6a0718SPierre Ossman 2591c6a0718SPierre Ossman static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, 260be0192aaSPierre Ossman struct mmc_command *cmd, struct mmc_data *data) 2611c6a0718SPierre Ossman { 2621c6a0718SPierre Ossman u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); 2631c6a0718SPierre Ossman 2641c6a0718SPierre Ossman switch (mmc_resp_type(cmd)) { 2651c6a0718SPierre Ossman case MMC_RSP_NONE: 2661c6a0718SPierre Ossman break; 2671c6a0718SPierre Ossman case MMC_RSP_R1: 2681c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_1; 2691c6a0718SPierre Ossman break; 2701c6a0718SPierre Ossman case MMC_RSP_R1B: 2711c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_1B; 2721c6a0718SPierre Ossman break; 2731c6a0718SPierre Ossman case MMC_RSP_R2: 2741c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_2; 2751c6a0718SPierre Ossman break; 2761c6a0718SPierre Ossman case MMC_RSP_R3: 2771c6a0718SPierre Ossman mmccmd |= SD_CMD_RT_3; 2781c6a0718SPierre Ossman break; 2791c6a0718SPierre Ossman default: 280a3c76eb9SGirish K S pr_info("au1xmmc: unhandled response type %02x\n", 2811c6a0718SPierre Ossman mmc_resp_type(cmd)); 28217b0429dSPierre Ossman return -EINVAL; 2831c6a0718SPierre Ossman } 2841c6a0718SPierre Ossman 285be0192aaSPierre Ossman if (data) { 2866356a9d9SPierre Ossman if (data->flags & MMC_DATA_READ) { 287be0192aaSPierre Ossman if (data->blocks > 1) 2881c6a0718SPierre Ossman mmccmd |= SD_CMD_CT_4; 289c0f3b6c7SYoichi Yuasa else 290c0f3b6c7SYoichi Yuasa mmccmd |= SD_CMD_CT_2; 2916356a9d9SPierre Ossman } else if (data->flags & MMC_DATA_WRITE) { 292be0192aaSPierre Ossman if (data->blocks > 1) 2931c6a0718SPierre Ossman mmccmd |= SD_CMD_CT_3; 294c0f3b6c7SYoichi Yuasa else 295c0f3b6c7SYoichi Yuasa mmccmd |= SD_CMD_CT_1; 2961c6a0718SPierre Ossman } 297be0192aaSPierre Ossman } 2981c6a0718SPierre Ossman 2991c6a0718SPierre Ossman au_writel(cmd->arg, HOST_CMDARG(host)); 3001c6a0718SPierre Ossman au_sync(); 3011c6a0718SPierre Ossman 3021c6a0718SPierre Ossman if (wait) 3031c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_CR); 3041c6a0718SPierre Ossman 3051c6a0718SPierre Ossman au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); 3061c6a0718SPierre Ossman au_sync(); 3071c6a0718SPierre Ossman 3081c6a0718SPierre Ossman /* Wait for the command to go on the line */ 3095c0a889dSManuel Lauss while (au_readl(HOST_CMD(host)) & SD_CMD_GO) 3105c0a889dSManuel Lauss /* nop */; 3111c6a0718SPierre Ossman 3121c6a0718SPierre Ossman /* Wait for the command to come back */ 3131c6a0718SPierre Ossman if (wait) { 3141c6a0718SPierre Ossman u32 status = au_readl(HOST_STATUS(host)); 3151c6a0718SPierre Ossman 3161c6a0718SPierre Ossman while (!(status & SD_STATUS_CR)) 3171c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3181c6a0718SPierre Ossman 3191c6a0718SPierre Ossman /* Clear the CR status */ 3201c6a0718SPierre Ossman au_writel(SD_STATUS_CR, HOST_STATUS(host)); 3211c6a0718SPierre Ossman 3221c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_CR); 3231c6a0718SPierre Ossman } 3241c6a0718SPierre Ossman 32517b0429dSPierre Ossman return 0; 3261c6a0718SPierre Ossman } 3271c6a0718SPierre Ossman 3281c6a0718SPierre Ossman static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) 3291c6a0718SPierre Ossman { 3301c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 3311c6a0718SPierre Ossman struct mmc_data *data; 3321c6a0718SPierre Ossman u32 crc; 3331c6a0718SPierre Ossman 3345c0a889dSManuel Lauss WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP)); 3351c6a0718SPierre Ossman 3361c6a0718SPierre Ossman if (host->mrq == NULL) 3371c6a0718SPierre Ossman return; 3381c6a0718SPierre Ossman 3391c6a0718SPierre Ossman data = mrq->cmd->data; 3401c6a0718SPierre Ossman 3411c6a0718SPierre Ossman if (status == 0) 3421c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3431c6a0718SPierre Ossman 3441c6a0718SPierre Ossman /* The transaction is really over when the SD_STATUS_DB bit is clear */ 3451c6a0718SPierre Ossman while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) 3461c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 3471c6a0718SPierre Ossman 34817b0429dSPierre Ossman data->error = 0; 3491c6a0718SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); 3501c6a0718SPierre Ossman 3511c6a0718SPierre Ossman /* Process any errors */ 3521c6a0718SPierre Ossman crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); 3531c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) 3541c6a0718SPierre Ossman crc |= ((status & 0x07) == 0x02) ? 0 : 1; 3551c6a0718SPierre Ossman 3561c6a0718SPierre Ossman if (crc) 35717b0429dSPierre Ossman data->error = -EILSEQ; 3581c6a0718SPierre Ossman 3591c6a0718SPierre Ossman /* Clear the CRC bits */ 3601c6a0718SPierre Ossman au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); 3611c6a0718SPierre Ossman 3621c6a0718SPierre Ossman data->bytes_xfered = 0; 3631c6a0718SPierre Ossman 36417b0429dSPierre Ossman if (!data->error) { 3651177d99dSManuel Lauss if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { 3661c6a0718SPierre Ossman u32 chan = DMA_CHANNEL(host); 3671c6a0718SPierre Ossman 3681c6a0718SPierre Ossman chan_tab_t *c = *((chan_tab_t **)chan); 3691c6a0718SPierre Ossman au1x_dma_chan_t *cp = c->chan_ptr; 3701c6a0718SPierre Ossman data->bytes_xfered = cp->ddma_bytecnt; 3715c0a889dSManuel Lauss } else 3721c6a0718SPierre Ossman data->bytes_xfered = 3735c0a889dSManuel Lauss (data->blocks * data->blksz) - host->pio.len; 3741c6a0718SPierre Ossman } 3751c6a0718SPierre Ossman 3761c6a0718SPierre Ossman au1xmmc_finish_request(host); 3771c6a0718SPierre Ossman } 3781c6a0718SPierre Ossman 3791c6a0718SPierre Ossman static void au1xmmc_tasklet_data(unsigned long param) 3801c6a0718SPierre Ossman { 3811c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *)param; 3821c6a0718SPierre Ossman 3831c6a0718SPierre Ossman u32 status = au_readl(HOST_STATUS(host)); 3841c6a0718SPierre Ossman au1xmmc_data_complete(host, status); 3851c6a0718SPierre Ossman } 3861c6a0718SPierre Ossman 3871c6a0718SPierre Ossman #define AU1XMMC_MAX_TRANSFER 8 3881c6a0718SPierre Ossman 3891c6a0718SPierre Ossman static void au1xmmc_send_pio(struct au1xmmc_host *host) 3901c6a0718SPierre Ossman { 3915c0a889dSManuel Lauss struct mmc_data *data; 3925c0a889dSManuel Lauss int sg_len, max, count; 3935c0a889dSManuel Lauss unsigned char *sg_ptr, val; 3945c0a889dSManuel Lauss u32 status; 3951c6a0718SPierre Ossman struct scatterlist *sg; 3961c6a0718SPierre Ossman 3971c6a0718SPierre Ossman data = host->mrq->data; 3981c6a0718SPierre Ossman 3991c6a0718SPierre Ossman if (!(host->flags & HOST_F_XMIT)) 4001c6a0718SPierre Ossman return; 4011c6a0718SPierre Ossman 4021c6a0718SPierre Ossman /* This is the pointer to the data buffer */ 4031c6a0718SPierre Ossman sg = &data->sg[host->pio.index]; 40445711f1aSJens Axboe sg_ptr = sg_virt(sg) + host->pio.offset; 4051c6a0718SPierre Ossman 4061c6a0718SPierre Ossman /* This is the space left inside the buffer */ 4071c6a0718SPierre Ossman sg_len = data->sg[host->pio.index].length - host->pio.offset; 4081c6a0718SPierre Ossman 4095c0a889dSManuel Lauss /* Check if we need less than the size of the sg_buffer */ 4101c6a0718SPierre Ossman max = (sg_len > host->pio.len) ? host->pio.len : sg_len; 4115c0a889dSManuel Lauss if (max > AU1XMMC_MAX_TRANSFER) 4125c0a889dSManuel Lauss max = AU1XMMC_MAX_TRANSFER; 4131c6a0718SPierre Ossman 4141c6a0718SPierre Ossman for (count = 0; count < max; count++) { 4151c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 4161c6a0718SPierre Ossman 4171c6a0718SPierre Ossman if (!(status & SD_STATUS_TH)) 4181c6a0718SPierre Ossman break; 4191c6a0718SPierre Ossman 4201c6a0718SPierre Ossman val = *sg_ptr++; 4211c6a0718SPierre Ossman 4221c6a0718SPierre Ossman au_writel((unsigned long)val, HOST_TXPORT(host)); 4231c6a0718SPierre Ossman au_sync(); 4241c6a0718SPierre Ossman } 4251c6a0718SPierre Ossman 4261c6a0718SPierre Ossman host->pio.len -= count; 4271c6a0718SPierre Ossman host->pio.offset += count; 4281c6a0718SPierre Ossman 4291c6a0718SPierre Ossman if (count == sg_len) { 4301c6a0718SPierre Ossman host->pio.index++; 4311c6a0718SPierre Ossman host->pio.offset = 0; 4321c6a0718SPierre Ossman } 4331c6a0718SPierre Ossman 4341c6a0718SPierre Ossman if (host->pio.len == 0) { 4351c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_TH); 4361c6a0718SPierre Ossman 4371c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 4381c6a0718SPierre Ossman SEND_STOP(host); 4391c6a0718SPierre Ossman 4401c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 4411c6a0718SPierre Ossman } 4421c6a0718SPierre Ossman } 4431c6a0718SPierre Ossman 4441c6a0718SPierre Ossman static void au1xmmc_receive_pio(struct au1xmmc_host *host) 4451c6a0718SPierre Ossman { 4465c0a889dSManuel Lauss struct mmc_data *data; 4475c0a889dSManuel Lauss int max, count, sg_len = 0; 4485c0a889dSManuel Lauss unsigned char *sg_ptr = NULL; 4495c0a889dSManuel Lauss u32 status, val; 4501c6a0718SPierre Ossman struct scatterlist *sg; 4511c6a0718SPierre Ossman 4521c6a0718SPierre Ossman data = host->mrq->data; 4531c6a0718SPierre Ossman 4541c6a0718SPierre Ossman if (!(host->flags & HOST_F_RECV)) 4551c6a0718SPierre Ossman return; 4561c6a0718SPierre Ossman 4571c6a0718SPierre Ossman max = host->pio.len; 4581c6a0718SPierre Ossman 4591c6a0718SPierre Ossman if (host->pio.index < host->dma.len) { 4601c6a0718SPierre Ossman sg = &data->sg[host->pio.index]; 46145711f1aSJens Axboe sg_ptr = sg_virt(sg) + host->pio.offset; 4621c6a0718SPierre Ossman 4631c6a0718SPierre Ossman /* This is the space left inside the buffer */ 4641c6a0718SPierre Ossman sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; 4651c6a0718SPierre Ossman 4665c0a889dSManuel Lauss /* Check if we need less than the size of the sg_buffer */ 4675c0a889dSManuel Lauss if (sg_len < max) 4685c0a889dSManuel Lauss max = sg_len; 4691c6a0718SPierre Ossman } 4701c6a0718SPierre Ossman 4711c6a0718SPierre Ossman if (max > AU1XMMC_MAX_TRANSFER) 4721c6a0718SPierre Ossman max = AU1XMMC_MAX_TRANSFER; 4731c6a0718SPierre Ossman 4741c6a0718SPierre Ossman for (count = 0; count < max; count++) { 4751c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 4761c6a0718SPierre Ossman 4771c6a0718SPierre Ossman if (!(status & SD_STATUS_NE)) 4781c6a0718SPierre Ossman break; 4791c6a0718SPierre Ossman 4801c6a0718SPierre Ossman if (status & SD_STATUS_RC) { 481c4223c2cSManuel Lauss DBG("RX CRC Error [%d + %d].\n", host->pdev->id, 4821c6a0718SPierre Ossman host->pio.len, count); 4831c6a0718SPierre Ossman break; 4841c6a0718SPierre Ossman } 4851c6a0718SPierre Ossman 4861c6a0718SPierre Ossman if (status & SD_STATUS_RO) { 487c4223c2cSManuel Lauss DBG("RX Overrun [%d + %d]\n", host->pdev->id, 4881c6a0718SPierre Ossman host->pio.len, count); 4891c6a0718SPierre Ossman break; 4901c6a0718SPierre Ossman } 4911c6a0718SPierre Ossman else if (status & SD_STATUS_RU) { 492c4223c2cSManuel Lauss DBG("RX Underrun [%d + %d]\n", host->pdev->id, 4931c6a0718SPierre Ossman host->pio.len, count); 4941c6a0718SPierre Ossman break; 4951c6a0718SPierre Ossman } 4961c6a0718SPierre Ossman 4971c6a0718SPierre Ossman val = au_readl(HOST_RXPORT(host)); 4981c6a0718SPierre Ossman 4991c6a0718SPierre Ossman if (sg_ptr) 5001c6a0718SPierre Ossman *sg_ptr++ = (unsigned char)(val & 0xFF); 5011c6a0718SPierre Ossman } 5021c6a0718SPierre Ossman 5031c6a0718SPierre Ossman host->pio.len -= count; 5041c6a0718SPierre Ossman host->pio.offset += count; 5051c6a0718SPierre Ossman 5061c6a0718SPierre Ossman if (sg_len && count == sg_len) { 5071c6a0718SPierre Ossman host->pio.index++; 5081c6a0718SPierre Ossman host->pio.offset = 0; 5091c6a0718SPierre Ossman } 5101c6a0718SPierre Ossman 5111c6a0718SPierre Ossman if (host->pio.len == 0) { 5125c0a889dSManuel Lauss /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 5131c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_NE); 5141c6a0718SPierre Ossman 5151c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 5161c6a0718SPierre Ossman SEND_STOP(host); 5171c6a0718SPierre Ossman 5181c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 5191c6a0718SPierre Ossman } 5201c6a0718SPierre Ossman } 5211c6a0718SPierre Ossman 5225c0a889dSManuel Lauss /* This is called when a command has been completed - grab the response 5235c0a889dSManuel Lauss * and check for errors. Then start the data transfer if it is indicated. 5241c6a0718SPierre Ossman */ 5251c6a0718SPierre Ossman static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) 5261c6a0718SPierre Ossman { 5271c6a0718SPierre Ossman struct mmc_request *mrq = host->mrq; 5281c6a0718SPierre Ossman struct mmc_command *cmd; 5295c0a889dSManuel Lauss u32 r[4]; 5305c0a889dSManuel Lauss int i, trans; 5311c6a0718SPierre Ossman 5321c6a0718SPierre Ossman if (!host->mrq) 5331c6a0718SPierre Ossman return; 5341c6a0718SPierre Ossman 5351c6a0718SPierre Ossman cmd = mrq->cmd; 53617b0429dSPierre Ossman cmd->error = 0; 5371c6a0718SPierre Ossman 5381c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 5391c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) { 5401c6a0718SPierre Ossman r[0] = au_readl(host->iobase + SD_RESP3); 5411c6a0718SPierre Ossman r[1] = au_readl(host->iobase + SD_RESP2); 5421c6a0718SPierre Ossman r[2] = au_readl(host->iobase + SD_RESP1); 5431c6a0718SPierre Ossman r[3] = au_readl(host->iobase + SD_RESP0); 5441c6a0718SPierre Ossman 5451c6a0718SPierre Ossman /* The CRC is omitted from the response, so really 5461c6a0718SPierre Ossman * we only got 120 bytes, but the engine expects 5475c0a889dSManuel Lauss * 128 bits, so we have to shift things up. 5481c6a0718SPierre Ossman */ 5491c6a0718SPierre Ossman for (i = 0; i < 4; i++) { 5501c6a0718SPierre Ossman cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; 5511c6a0718SPierre Ossman if (i != 3) 5521c6a0718SPierre Ossman cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; 5531c6a0718SPierre Ossman } 5541c6a0718SPierre Ossman } else { 5551c6a0718SPierre Ossman /* Techincally, we should be getting all 48 bits of 5561c6a0718SPierre Ossman * the response (SD_RESP1 + SD_RESP2), but because 5571c6a0718SPierre Ossman * our response omits the CRC, our data ends up 5581c6a0718SPierre Ossman * being shifted 8 bits to the right. In this case, 5591c6a0718SPierre Ossman * that means that the OSR data starts at bit 31, 5605c0a889dSManuel Lauss * so we can just read RESP0 and return that. 5611c6a0718SPierre Ossman */ 5621c6a0718SPierre Ossman cmd->resp[0] = au_readl(host->iobase + SD_RESP0); 5631c6a0718SPierre Ossman } 5641c6a0718SPierre Ossman } 5651c6a0718SPierre Ossman 5661c6a0718SPierre Ossman /* Figure out errors */ 5671c6a0718SPierre Ossman if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) 56817b0429dSPierre Ossman cmd->error = -EILSEQ; 5691c6a0718SPierre Ossman 5701c6a0718SPierre Ossman trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); 5711c6a0718SPierre Ossman 57217b0429dSPierre Ossman if (!trans || cmd->error) { 5731c6a0718SPierre Ossman IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); 5741c6a0718SPierre Ossman tasklet_schedule(&host->finish_task); 5751c6a0718SPierre Ossman return; 5761c6a0718SPierre Ossman } 5771c6a0718SPierre Ossman 5781c6a0718SPierre Ossman host->status = HOST_S_DATA; 5791c6a0718SPierre Ossman 5801177d99dSManuel Lauss if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) { 5811c6a0718SPierre Ossman u32 channel = DMA_CHANNEL(host); 5821c6a0718SPierre Ossman 5831177d99dSManuel Lauss /* Start the DBDMA as soon as the buffer gets something in it */ 5841c6a0718SPierre Ossman 5851c6a0718SPierre Ossman if (host->flags & HOST_F_RECV) { 5861c6a0718SPierre Ossman u32 mask = SD_STATUS_DB | SD_STATUS_NE; 5871c6a0718SPierre Ossman 5881c6a0718SPierre Ossman while((status & mask) != mask) 5891c6a0718SPierre Ossman status = au_readl(HOST_STATUS(host)); 5901c6a0718SPierre Ossman } 5911c6a0718SPierre Ossman 5921c6a0718SPierre Ossman au1xxx_dbdma_start(channel); 5931c6a0718SPierre Ossman } 5941c6a0718SPierre Ossman } 5951c6a0718SPierre Ossman 5961c6a0718SPierre Ossman static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) 5971c6a0718SPierre Ossman { 5981c6a0718SPierre Ossman unsigned int pbus = get_au1x00_speed(); 5991c6a0718SPierre Ossman unsigned int divisor; 6001c6a0718SPierre Ossman u32 config; 6011c6a0718SPierre Ossman 6021c6a0718SPierre Ossman /* From databook: 6035c0a889dSManuel Lauss * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1 6041c6a0718SPierre Ossman */ 6051c6a0718SPierre Ossman pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2); 6061c6a0718SPierre Ossman pbus /= 2; 6071c6a0718SPierre Ossman divisor = ((pbus / rate) / 2) - 1; 6081c6a0718SPierre Ossman 6091c6a0718SPierre Ossman config = au_readl(HOST_CONFIG(host)); 6101c6a0718SPierre Ossman 6111c6a0718SPierre Ossman config &= ~(SD_CONFIG_DIV); 6121c6a0718SPierre Ossman config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; 6131c6a0718SPierre Ossman 6141c6a0718SPierre Ossman au_writel(config, HOST_CONFIG(host)); 6151c6a0718SPierre Ossman au_sync(); 6161c6a0718SPierre Ossman } 6171c6a0718SPierre Ossman 6185c0a889dSManuel Lauss static int au1xmmc_prepare_data(struct au1xmmc_host *host, 6195c0a889dSManuel Lauss struct mmc_data *data) 6201c6a0718SPierre Ossman { 6211c6a0718SPierre Ossman int datalen = data->blocks * data->blksz; 6221c6a0718SPierre Ossman 6231c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 6241c6a0718SPierre Ossman host->flags |= HOST_F_RECV; 6251c6a0718SPierre Ossman else 6261c6a0718SPierre Ossman host->flags |= HOST_F_XMIT; 6271c6a0718SPierre Ossman 6281c6a0718SPierre Ossman if (host->mrq->stop) 6291c6a0718SPierre Ossman host->flags |= HOST_F_STOP; 6301c6a0718SPierre Ossman 6311c6a0718SPierre Ossman host->dma.dir = DMA_BIDIRECTIONAL; 6321c6a0718SPierre Ossman 6331c6a0718SPierre Ossman host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, 6341c6a0718SPierre Ossman data->sg_len, host->dma.dir); 6351c6a0718SPierre Ossman 6361c6a0718SPierre Ossman if (host->dma.len == 0) 63717b0429dSPierre Ossman return -ETIMEDOUT; 6381c6a0718SPierre Ossman 6391c6a0718SPierre Ossman au_writel(data->blksz - 1, HOST_BLKSIZE(host)); 6401c6a0718SPierre Ossman 6411177d99dSManuel Lauss if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { 6421c6a0718SPierre Ossman int i; 6431c6a0718SPierre Ossman u32 channel = DMA_CHANNEL(host); 6441c6a0718SPierre Ossman 6451c6a0718SPierre Ossman au1xxx_dbdma_stop(channel); 6461c6a0718SPierre Ossman 6471c6a0718SPierre Ossman for (i = 0; i < host->dma.len; i++) { 6481c6a0718SPierre Ossman u32 ret = 0, flags = DDMA_FLAGS_NOIE; 6491c6a0718SPierre Ossman struct scatterlist *sg = &data->sg[i]; 6501c6a0718SPierre Ossman int sg_len = sg->length; 6511c6a0718SPierre Ossman 6521c6a0718SPierre Ossman int len = (datalen > sg_len) ? sg_len : datalen; 6531c6a0718SPierre Ossman 6541c6a0718SPierre Ossman if (i == host->dma.len - 1) 6551c6a0718SPierre Ossman flags = DDMA_FLAGS_IE; 6561c6a0718SPierre Ossman 6571c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) { 658ea071cc7SManuel Lauss ret = au1xxx_dbdma_put_source(channel, 659963accbcSManuel Lauss sg_phys(sg), len, flags); 6605c0a889dSManuel Lauss } else { 661ea071cc7SManuel Lauss ret = au1xxx_dbdma_put_dest(channel, 662963accbcSManuel Lauss sg_phys(sg), len, flags); 6631c6a0718SPierre Ossman } 6641c6a0718SPierre Ossman 6651c6a0718SPierre Ossman if (!ret) 6661c6a0718SPierre Ossman goto dataerr; 6671c6a0718SPierre Ossman 6681c6a0718SPierre Ossman datalen -= len; 6691c6a0718SPierre Ossman } 6705c0a889dSManuel Lauss } else { 6711c6a0718SPierre Ossman host->pio.index = 0; 6721c6a0718SPierre Ossman host->pio.offset = 0; 6731c6a0718SPierre Ossman host->pio.len = datalen; 6741c6a0718SPierre Ossman 6751c6a0718SPierre Ossman if (host->flags & HOST_F_XMIT) 6761c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_TH); 6771c6a0718SPierre Ossman else 6781c6a0718SPierre Ossman IRQ_ON(host, SD_CONFIG_NE); 6795c0a889dSManuel Lauss /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */ 6801c6a0718SPierre Ossman } 6811c6a0718SPierre Ossman 68217b0429dSPierre Ossman return 0; 6831c6a0718SPierre Ossman 6841c6a0718SPierre Ossman dataerr: 685c4223c2cSManuel Lauss dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 686c4223c2cSManuel Lauss host->dma.dir); 68717b0429dSPierre Ossman return -ETIMEDOUT; 6881c6a0718SPierre Ossman } 6891c6a0718SPierre Ossman 6905c0a889dSManuel Lauss /* This actually starts a command or data transaction */ 6911c6a0718SPierre Ossman static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) 6921c6a0718SPierre Ossman { 6931c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 69417b0429dSPierre Ossman int ret = 0; 6951c6a0718SPierre Ossman 6961c6a0718SPierre Ossman WARN_ON(irqs_disabled()); 6971c6a0718SPierre Ossman WARN_ON(host->status != HOST_S_IDLE); 6981c6a0718SPierre Ossman 6991c6a0718SPierre Ossman host->mrq = mrq; 7001c6a0718SPierre Ossman host->status = HOST_S_CMD; 7011c6a0718SPierre Ossman 70288b8d9a8SManuel Lauss /* fail request immediately if no card is present */ 703e2d26477SManuel Lauss if (0 == au1xmmc_card_inserted(mmc)) { 70488b8d9a8SManuel Lauss mrq->cmd->error = -ENOMEDIUM; 70588b8d9a8SManuel Lauss au1xmmc_finish_request(host); 70688b8d9a8SManuel Lauss return; 70788b8d9a8SManuel Lauss } 70888b8d9a8SManuel Lauss 7091c6a0718SPierre Ossman if (mrq->data) { 7101c6a0718SPierre Ossman FLUSH_FIFO(host); 7111c6a0718SPierre Ossman ret = au1xmmc_prepare_data(host, mrq->data); 7121c6a0718SPierre Ossman } 7131c6a0718SPierre Ossman 71417b0429dSPierre Ossman if (!ret) 715be0192aaSPierre Ossman ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data); 7161c6a0718SPierre Ossman 71717b0429dSPierre Ossman if (ret) { 7181c6a0718SPierre Ossman mrq->cmd->error = ret; 7191c6a0718SPierre Ossman au1xmmc_finish_request(host); 7201c6a0718SPierre Ossman } 7211c6a0718SPierre Ossman } 7221c6a0718SPierre Ossman 7231c6a0718SPierre Ossman static void au1xmmc_reset_controller(struct au1xmmc_host *host) 7241c6a0718SPierre Ossman { 7251c6a0718SPierre Ossman /* Apply the clock */ 7261c6a0718SPierre Ossman au_writel(SD_ENABLE_CE, HOST_ENABLE(host)); 7271c6a0718SPierre Ossman au_sync_delay(1); 7281c6a0718SPierre Ossman 7291c6a0718SPierre Ossman au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); 7301c6a0718SPierre Ossman au_sync_delay(5); 7311c6a0718SPierre Ossman 7321c6a0718SPierre Ossman au_writel(~0, HOST_STATUS(host)); 7331c6a0718SPierre Ossman au_sync(); 7341c6a0718SPierre Ossman 7351c6a0718SPierre Ossman au_writel(0, HOST_BLKSIZE(host)); 7361c6a0718SPierre Ossman au_writel(0x001fffff, HOST_TIMEOUT(host)); 7371c6a0718SPierre Ossman au_sync(); 7381c6a0718SPierre Ossman 7391c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 7401c6a0718SPierre Ossman au_sync(); 7411c6a0718SPierre Ossman 7421c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); 7431c6a0718SPierre Ossman au_sync_delay(1); 7441c6a0718SPierre Ossman 7451c6a0718SPierre Ossman au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 7461c6a0718SPierre Ossman au_sync(); 7471c6a0718SPierre Ossman 7481c6a0718SPierre Ossman /* Configure interrupts */ 7491c6a0718SPierre Ossman au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); 7501c6a0718SPierre Ossman au_sync(); 7511c6a0718SPierre Ossman } 7521c6a0718SPierre Ossman 7531c6a0718SPierre Ossman 7541c6a0718SPierre Ossman static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 7551c6a0718SPierre Ossman { 7561c6a0718SPierre Ossman struct au1xmmc_host *host = mmc_priv(mmc); 757281dd23eSManuel Lauss u32 config2; 7581c6a0718SPierre Ossman 7591c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) 7601c6a0718SPierre Ossman au1xmmc_set_power(host, 0); 7611c6a0718SPierre Ossman else if (ios->power_mode == MMC_POWER_ON) { 7621c6a0718SPierre Ossman au1xmmc_set_power(host, 1); 7631c6a0718SPierre Ossman } 7641c6a0718SPierre Ossman 7651c6a0718SPierre Ossman if (ios->clock && ios->clock != host->clock) { 7661c6a0718SPierre Ossman au1xmmc_set_clock(host, ios->clock); 7671c6a0718SPierre Ossman host->clock = ios->clock; 7681c6a0718SPierre Ossman } 769281dd23eSManuel Lauss 770281dd23eSManuel Lauss config2 = au_readl(HOST_CONFIG2(host)); 771281dd23eSManuel Lauss switch (ios->bus_width) { 772809f36c6SManuel Lauss case MMC_BUS_WIDTH_8: 773809f36c6SManuel Lauss config2 |= SD_CONFIG2_BB; 774809f36c6SManuel Lauss break; 775281dd23eSManuel Lauss case MMC_BUS_WIDTH_4: 776809f36c6SManuel Lauss config2 &= ~SD_CONFIG2_BB; 777281dd23eSManuel Lauss config2 |= SD_CONFIG2_WB; 778281dd23eSManuel Lauss break; 779281dd23eSManuel Lauss case MMC_BUS_WIDTH_1: 780809f36c6SManuel Lauss config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB); 781281dd23eSManuel Lauss break; 782281dd23eSManuel Lauss } 783281dd23eSManuel Lauss au_writel(config2, HOST_CONFIG2(host)); 784281dd23eSManuel Lauss au_sync(); 7851c6a0718SPierre Ossman } 7861c6a0718SPierre Ossman 787c4223c2cSManuel Lauss #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) 788c4223c2cSManuel Lauss #define STATUS_DATA_IN (SD_STATUS_NE) 789c4223c2cSManuel Lauss #define STATUS_DATA_OUT (SD_STATUS_TH) 790c4223c2cSManuel Lauss 791c4223c2cSManuel Lauss static irqreturn_t au1xmmc_irq(int irq, void *dev_id) 792c4223c2cSManuel Lauss { 793c4223c2cSManuel Lauss struct au1xmmc_host *host = dev_id; 794c4223c2cSManuel Lauss u32 status; 795c4223c2cSManuel Lauss 796c4223c2cSManuel Lauss status = au_readl(HOST_STATUS(host)); 797c4223c2cSManuel Lauss 798c4223c2cSManuel Lauss if (!(status & SD_STATUS_I)) 799c4223c2cSManuel Lauss return IRQ_NONE; /* not ours */ 800c4223c2cSManuel Lauss 80120f522ffSManuel Lauss if (status & SD_STATUS_SI) /* SDIO */ 80220f522ffSManuel Lauss mmc_signal_sdio_irq(host->mmc); 80320f522ffSManuel Lauss 804c4223c2cSManuel Lauss if (host->mrq && (status & STATUS_TIMEOUT)) { 805c4223c2cSManuel Lauss if (status & SD_STATUS_RAT) 806c4223c2cSManuel Lauss host->mrq->cmd->error = -ETIMEDOUT; 807c4223c2cSManuel Lauss else if (status & SD_STATUS_DT) 808c4223c2cSManuel Lauss host->mrq->data->error = -ETIMEDOUT; 809c4223c2cSManuel Lauss 810c4223c2cSManuel Lauss /* In PIO mode, interrupts might still be enabled */ 811c4223c2cSManuel Lauss IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); 812c4223c2cSManuel Lauss 813c4223c2cSManuel Lauss /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ 814c4223c2cSManuel Lauss tasklet_schedule(&host->finish_task); 815c4223c2cSManuel Lauss } 816c4223c2cSManuel Lauss #if 0 817c4223c2cSManuel Lauss else if (status & SD_STATUS_DD) { 818c4223c2cSManuel Lauss /* Sometimes we get a DD before a NE in PIO mode */ 819c4223c2cSManuel Lauss if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) 820c4223c2cSManuel Lauss au1xmmc_receive_pio(host); 821c4223c2cSManuel Lauss else { 822c4223c2cSManuel Lauss au1xmmc_data_complete(host, status); 823c4223c2cSManuel Lauss /* tasklet_schedule(&host->data_task); */ 824c4223c2cSManuel Lauss } 825c4223c2cSManuel Lauss } 826c4223c2cSManuel Lauss #endif 827c4223c2cSManuel Lauss else if (status & SD_STATUS_CR) { 828c4223c2cSManuel Lauss if (host->status == HOST_S_CMD) 829c4223c2cSManuel Lauss au1xmmc_cmd_complete(host, status); 830c4223c2cSManuel Lauss 831c4223c2cSManuel Lauss } else if (!(host->flags & HOST_F_DMA)) { 832c4223c2cSManuel Lauss if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) 833c4223c2cSManuel Lauss au1xmmc_send_pio(host); 834c4223c2cSManuel Lauss else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) 835c4223c2cSManuel Lauss au1xmmc_receive_pio(host); 836c4223c2cSManuel Lauss 837c4223c2cSManuel Lauss } else if (status & 0x203F3C70) { 838c4223c2cSManuel Lauss DBG("Unhandled status %8.8x\n", host->pdev->id, 839c4223c2cSManuel Lauss status); 840c4223c2cSManuel Lauss } 841c4223c2cSManuel Lauss 842c4223c2cSManuel Lauss au_writel(status, HOST_STATUS(host)); 843c4223c2cSManuel Lauss au_sync(); 844c4223c2cSManuel Lauss 845c4223c2cSManuel Lauss return IRQ_HANDLED; 846c4223c2cSManuel Lauss } 847c4223c2cSManuel Lauss 848c4223c2cSManuel Lauss /* 8bit memory DMA device */ 849c4223c2cSManuel Lauss static dbdev_tab_t au1xmmc_mem_dbdev = { 850c4223c2cSManuel Lauss .dev_id = DSCR_CMD0_ALWAYS, 851c4223c2cSManuel Lauss .dev_flags = DEV_FLAGS_ANYUSE, 852c4223c2cSManuel Lauss .dev_tsize = 0, 853c4223c2cSManuel Lauss .dev_devwidth = 8, 854c4223c2cSManuel Lauss .dev_physaddr = 0x00000000, 855c4223c2cSManuel Lauss .dev_intlevel = 0, 856c4223c2cSManuel Lauss .dev_intpolarity = 0, 857c4223c2cSManuel Lauss }; 858c4223c2cSManuel Lauss static int memid; 859c4223c2cSManuel Lauss 860c4223c2cSManuel Lauss static void au1xmmc_dbdma_callback(int irq, void *dev_id) 8611c6a0718SPierre Ossman { 8621c6a0718SPierre Ossman struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; 8631c6a0718SPierre Ossman 8641c6a0718SPierre Ossman /* Avoid spurious interrupts */ 8651c6a0718SPierre Ossman if (!host->mrq) 8661c6a0718SPierre Ossman return; 8671c6a0718SPierre Ossman 8681c6a0718SPierre Ossman if (host->flags & HOST_F_STOP) 8691c6a0718SPierre Ossman SEND_STOP(host); 8701c6a0718SPierre Ossman 8711c6a0718SPierre Ossman tasklet_schedule(&host->data_task); 8721c6a0718SPierre Ossman } 8731c6a0718SPierre Ossman 874c4223c2cSManuel Lauss static int au1xmmc_dbdma_init(struct au1xmmc_host *host) 8751c6a0718SPierre Ossman { 876c4223c2cSManuel Lauss struct resource *res; 877c4223c2cSManuel Lauss int txid, rxid; 8781c6a0718SPierre Ossman 879c4223c2cSManuel Lauss res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); 880c4223c2cSManuel Lauss if (!res) 881c4223c2cSManuel Lauss return -ENODEV; 882c4223c2cSManuel Lauss txid = res->start; 8831c6a0718SPierre Ossman 884c4223c2cSManuel Lauss res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); 885c4223c2cSManuel Lauss if (!res) 886c4223c2cSManuel Lauss return -ENODEV; 887c4223c2cSManuel Lauss rxid = res->start; 8881c6a0718SPierre Ossman 889c4223c2cSManuel Lauss if (!memid) 890c4223c2cSManuel Lauss return -ENODEV; 8911c6a0718SPierre Ossman 892c4223c2cSManuel Lauss host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, 893c4223c2cSManuel Lauss au1xmmc_dbdma_callback, (void *)host); 894c4223c2cSManuel Lauss if (!host->tx_chan) { 895c4223c2cSManuel Lauss dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); 896c4223c2cSManuel Lauss return -ENODEV; 8971c6a0718SPierre Ossman } 8981c6a0718SPierre Ossman 899c4223c2cSManuel Lauss host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, 900c4223c2cSManuel Lauss au1xmmc_dbdma_callback, (void *)host); 901c4223c2cSManuel Lauss if (!host->rx_chan) { 902c4223c2cSManuel Lauss dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); 903c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->tx_chan); 904c4223c2cSManuel Lauss return -ENODEV; 905c4223c2cSManuel Lauss } 9061c6a0718SPierre Ossman 907c4223c2cSManuel Lauss au1xxx_dbdma_set_devwidth(host->tx_chan, 8); 908c4223c2cSManuel Lauss au1xxx_dbdma_set_devwidth(host->rx_chan, 8); 909c4223c2cSManuel Lauss 910c4223c2cSManuel Lauss au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); 911c4223c2cSManuel Lauss au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); 912c4223c2cSManuel Lauss 913c4223c2cSManuel Lauss /* DBDMA is good to go */ 9141177d99dSManuel Lauss host->flags |= HOST_F_DMA | HOST_F_DBDMA; 915c4223c2cSManuel Lauss 916c4223c2cSManuel Lauss return 0; 917c4223c2cSManuel Lauss } 918c4223c2cSManuel Lauss 919c4223c2cSManuel Lauss static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) 920c4223c2cSManuel Lauss { 921c4223c2cSManuel Lauss if (host->flags & HOST_F_DMA) { 922c4223c2cSManuel Lauss host->flags &= ~HOST_F_DMA; 923c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->tx_chan); 924c4223c2cSManuel Lauss au1xxx_dbdma_chan_free(host->rx_chan); 9251c6a0718SPierre Ossman } 9261c6a0718SPierre Ossman } 9271c6a0718SPierre Ossman 92820f522ffSManuel Lauss static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) 92920f522ffSManuel Lauss { 93020f522ffSManuel Lauss struct au1xmmc_host *host = mmc_priv(mmc); 93120f522ffSManuel Lauss 93220f522ffSManuel Lauss if (en) 93320f522ffSManuel Lauss IRQ_ON(host, SD_CONFIG_SI); 93420f522ffSManuel Lauss else 93520f522ffSManuel Lauss IRQ_OFF(host, SD_CONFIG_SI); 93620f522ffSManuel Lauss } 93720f522ffSManuel Lauss 9381c6a0718SPierre Ossman static const struct mmc_host_ops au1xmmc_ops = { 9391c6a0718SPierre Ossman .request = au1xmmc_request, 9401c6a0718SPierre Ossman .set_ios = au1xmmc_set_ios, 9411c6a0718SPierre Ossman .get_ro = au1xmmc_card_readonly, 942e2d26477SManuel Lauss .get_cd = au1xmmc_card_inserted, 94320f522ffSManuel Lauss .enable_sdio_irq = au1xmmc_enable_sdio_irq, 9441c6a0718SPierre Ossman }; 9451c6a0718SPierre Ossman 946c3be1efdSBill Pemberton static int au1xmmc_probe(struct platform_device *pdev) 947c4223c2cSManuel Lauss { 948c4223c2cSManuel Lauss struct mmc_host *mmc; 949c4223c2cSManuel Lauss struct au1xmmc_host *host; 950c4223c2cSManuel Lauss struct resource *r; 951809f36c6SManuel Lauss int ret, iflag; 952c4223c2cSManuel Lauss 953c4223c2cSManuel Lauss mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); 9541c6a0718SPierre Ossman if (!mmc) { 955c4223c2cSManuel Lauss dev_err(&pdev->dev, "no memory for mmc_host\n"); 956c4223c2cSManuel Lauss ret = -ENOMEM; 957c4223c2cSManuel Lauss goto out0; 958c4223c2cSManuel Lauss } 959c4223c2cSManuel Lauss 960c4223c2cSManuel Lauss host = mmc_priv(mmc); 961c4223c2cSManuel Lauss host->mmc = mmc; 962c4223c2cSManuel Lauss host->platdata = pdev->dev.platform_data; 963c4223c2cSManuel Lauss host->pdev = pdev; 964c4223c2cSManuel Lauss 965c4223c2cSManuel Lauss ret = -ENODEV; 966c4223c2cSManuel Lauss r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 967c4223c2cSManuel Lauss if (!r) { 968c4223c2cSManuel Lauss dev_err(&pdev->dev, "no mmio defined\n"); 969c4223c2cSManuel Lauss goto out1; 970c4223c2cSManuel Lauss } 971c4223c2cSManuel Lauss 9727a5ea56aSH Hartley Sweeten host->ioarea = request_mem_region(r->start, resource_size(r), 973c4223c2cSManuel Lauss pdev->name); 974c4223c2cSManuel Lauss if (!host->ioarea) { 975c4223c2cSManuel Lauss dev_err(&pdev->dev, "mmio already in use\n"); 976c4223c2cSManuel Lauss goto out1; 977c4223c2cSManuel Lauss } 978c4223c2cSManuel Lauss 979c4223c2cSManuel Lauss host->iobase = (unsigned long)ioremap(r->start, 0x3c); 980c4223c2cSManuel Lauss if (!host->iobase) { 981c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot remap mmio\n"); 982c4223c2cSManuel Lauss goto out2; 983c4223c2cSManuel Lauss } 984c4223c2cSManuel Lauss 985c4223c2cSManuel Lauss r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 986c4223c2cSManuel Lauss if (!r) { 987c4223c2cSManuel Lauss dev_err(&pdev->dev, "no IRQ defined\n"); 988c4223c2cSManuel Lauss goto out3; 989c4223c2cSManuel Lauss } 990c4223c2cSManuel Lauss host->irq = r->start; 9911c6a0718SPierre Ossman 9921c6a0718SPierre Ossman mmc->ops = &au1xmmc_ops; 9931c6a0718SPierre Ossman 9941c6a0718SPierre Ossman mmc->f_min = 450000; 9951c6a0718SPierre Ossman mmc->f_max = 24000000; 9961c6a0718SPierre Ossman 9971c6a0718SPierre Ossman mmc->max_blk_size = 2048; 9981c6a0718SPierre Ossman mmc->max_blk_count = 512; 9991c6a0718SPierre Ossman 10001c6a0718SPierre Ossman mmc->ocr_avail = AU1XMMC_OCR; 100120f522ffSManuel Lauss mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1002809f36c6SManuel Lauss mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; 1003809f36c6SManuel Lauss 1004809f36c6SManuel Lauss iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */ 1005809f36c6SManuel Lauss 1006809f36c6SManuel Lauss switch (alchemy_get_cputype()) { 1007809f36c6SManuel Lauss case ALCHEMY_CPU_AU1100: 1008809f36c6SManuel Lauss mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; 1009809f36c6SManuel Lauss break; 1010809f36c6SManuel Lauss case ALCHEMY_CPU_AU1200: 1011809f36c6SManuel Lauss mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; 1012809f36c6SManuel Lauss break; 1013809f36c6SManuel Lauss case ALCHEMY_CPU_AU1300: 1014809f36c6SManuel Lauss iflag = 0; /* nothing is shared */ 1015809f36c6SManuel Lauss mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; 1016809f36c6SManuel Lauss mmc->f_max = 52000000; 1017809f36c6SManuel Lauss if (host->ioarea->start == AU1100_SD0_PHYS_ADDR) 1018809f36c6SManuel Lauss mmc->caps |= MMC_CAP_8_BIT_DATA; 1019809f36c6SManuel Lauss break; 1020809f36c6SManuel Lauss } 1021809f36c6SManuel Lauss 1022809f36c6SManuel Lauss ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host); 1023809f36c6SManuel Lauss if (ret) { 1024809f36c6SManuel Lauss dev_err(&pdev->dev, "cannot grab IRQ\n"); 1025809f36c6SManuel Lauss goto out3; 1026809f36c6SManuel Lauss } 10271c6a0718SPierre Ossman 10281c6a0718SPierre Ossman host->status = HOST_S_IDLE; 10291c6a0718SPierre Ossman 1030c4223c2cSManuel Lauss /* board-specific carddetect setup, if any */ 1031c4223c2cSManuel Lauss if (host->platdata && host->platdata->cd_setup) { 1032c4223c2cSManuel Lauss ret = host->platdata->cd_setup(mmc, 1); 1033c4223c2cSManuel Lauss if (ret) { 1034e2d26477SManuel Lauss dev_warn(&pdev->dev, "board CD setup failed\n"); 1035e2d26477SManuel Lauss mmc->caps |= MMC_CAP_NEEDS_POLL; 1036c4223c2cSManuel Lauss } 1037e2d26477SManuel Lauss } else 1038e2d26477SManuel Lauss mmc->caps |= MMC_CAP_NEEDS_POLL; 10391c6a0718SPierre Ossman 10403b839070SManuel Lauss /* platform may not be able to use all advertised caps */ 10413b839070SManuel Lauss if (host->platdata) 10423b839070SManuel Lauss mmc->caps &= ~(host->platdata->mask_host_caps); 10433b839070SManuel Lauss 10441c6a0718SPierre Ossman tasklet_init(&host->data_task, au1xmmc_tasklet_data, 10451c6a0718SPierre Ossman (unsigned long)host); 10461c6a0718SPierre Ossman 10471c6a0718SPierre Ossman tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, 10481c6a0718SPierre Ossman (unsigned long)host); 10491c6a0718SPierre Ossman 10501177d99dSManuel Lauss if (has_dbdma()) { 1051c4223c2cSManuel Lauss ret = au1xmmc_dbdma_init(host); 1052c4223c2cSManuel Lauss if (ret) 1053a3c76eb9SGirish K S pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n"); 10541177d99dSManuel Lauss } 10551c6a0718SPierre Ossman 1056c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1057c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) { 1058c4223c2cSManuel Lauss struct led_classdev *led = host->platdata->led; 1059c4223c2cSManuel Lauss led->name = mmc_hostname(mmc); 1060c4223c2cSManuel Lauss led->brightness = LED_OFF; 1061c4223c2cSManuel Lauss led->default_trigger = mmc_hostname(mmc); 1062c4223c2cSManuel Lauss ret = led_classdev_register(mmc_dev(mmc), led); 1063c4223c2cSManuel Lauss if (ret) 1064c4223c2cSManuel Lauss goto out5; 1065c4223c2cSManuel Lauss } 1066c4223c2cSManuel Lauss #endif 10671c6a0718SPierre Ossman 10681c6a0718SPierre Ossman au1xmmc_reset_controller(host); 10691c6a0718SPierre Ossman 1070c4223c2cSManuel Lauss ret = mmc_add_host(mmc); 1071c4223c2cSManuel Lauss if (ret) { 1072c4223c2cSManuel Lauss dev_err(&pdev->dev, "cannot add mmc host\n"); 1073c4223c2cSManuel Lauss goto out6; 1074c4223c2cSManuel Lauss } 10751c6a0718SPierre Ossman 1076dd8572afSManuel Lauss platform_set_drvdata(pdev, host); 1077c4223c2cSManuel Lauss 1078a3c76eb9SGirish K S pr_info(DRIVER_NAME ": MMC Controller %d set up at %8.8X" 1079c4223c2cSManuel Lauss " (mode=%s)\n", pdev->id, host->iobase, 1080c4223c2cSManuel Lauss host->flags & HOST_F_DMA ? "dma" : "pio"); 10811c6a0718SPierre Ossman 1082c4223c2cSManuel Lauss return 0; /* all ok */ 10831c6a0718SPierre Ossman 1084c4223c2cSManuel Lauss out6: 1085c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1086c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) 1087c4223c2cSManuel Lauss led_classdev_unregister(host->platdata->led); 1088c4223c2cSManuel Lauss out5: 1089c4223c2cSManuel Lauss #endif 1090c4223c2cSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1091c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1092c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1093c4223c2cSManuel Lauss au_sync(); 10941c6a0718SPierre Ossman 10951177d99dSManuel Lauss if (host->flags & HOST_F_DBDMA) 1096c4223c2cSManuel Lauss au1xmmc_dbdma_shutdown(host); 10971c6a0718SPierre Ossman 10981c6a0718SPierre Ossman tasklet_kill(&host->data_task); 10991c6a0718SPierre Ossman tasklet_kill(&host->finish_task); 11001c6a0718SPierre Ossman 1101e2d26477SManuel Lauss if (host->platdata && host->platdata->cd_setup && 1102e2d26477SManuel Lauss !(mmc->caps & MMC_CAP_NEEDS_POLL)) 1103c4223c2cSManuel Lauss host->platdata->cd_setup(mmc, 0); 1104e2d26477SManuel Lauss 1105c4223c2cSManuel Lauss free_irq(host->irq, host); 1106c4223c2cSManuel Lauss out3: 1107c4223c2cSManuel Lauss iounmap((void *)host->iobase); 1108c4223c2cSManuel Lauss out2: 1109c4223c2cSManuel Lauss release_resource(host->ioarea); 1110c4223c2cSManuel Lauss kfree(host->ioarea); 1111c4223c2cSManuel Lauss out1: 1112c4223c2cSManuel Lauss mmc_free_host(mmc); 1113c4223c2cSManuel Lauss out0: 1114c4223c2cSManuel Lauss return ret; 11151c6a0718SPierre Ossman } 11161c6a0718SPierre Ossman 11176e0ee714SBill Pemberton static int au1xmmc_remove(struct platform_device *pdev) 1118c4223c2cSManuel Lauss { 1119dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1120c4223c2cSManuel Lauss 1121dd8572afSManuel Lauss if (host) { 1122dd8572afSManuel Lauss mmc_remove_host(host->mmc); 1123c4223c2cSManuel Lauss 1124c4223c2cSManuel Lauss #ifdef CONFIG_LEDS_CLASS 1125c4223c2cSManuel Lauss if (host->platdata && host->platdata->led) 1126c4223c2cSManuel Lauss led_classdev_unregister(host->platdata->led); 1127c4223c2cSManuel Lauss #endif 1128c4223c2cSManuel Lauss 1129e2d26477SManuel Lauss if (host->platdata && host->platdata->cd_setup && 1130dd8572afSManuel Lauss !(host->mmc->caps & MMC_CAP_NEEDS_POLL)) 1131dd8572afSManuel Lauss host->platdata->cd_setup(host->mmc, 0); 1132c4223c2cSManuel Lauss 1133c4223c2cSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1134c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1135c4223c2cSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1136c4223c2cSManuel Lauss au_sync(); 1137c4223c2cSManuel Lauss 1138c4223c2cSManuel Lauss tasklet_kill(&host->data_task); 1139c4223c2cSManuel Lauss tasklet_kill(&host->finish_task); 1140c4223c2cSManuel Lauss 11411177d99dSManuel Lauss if (host->flags & HOST_F_DBDMA) 1142c4223c2cSManuel Lauss au1xmmc_dbdma_shutdown(host); 11431177d99dSManuel Lauss 1144c4223c2cSManuel Lauss au1xmmc_set_power(host, 0); 1145c4223c2cSManuel Lauss 1146c4223c2cSManuel Lauss free_irq(host->irq, host); 1147c4223c2cSManuel Lauss iounmap((void *)host->iobase); 1148c4223c2cSManuel Lauss release_resource(host->ioarea); 1149c4223c2cSManuel Lauss kfree(host->ioarea); 1150c4223c2cSManuel Lauss 1151dd8572afSManuel Lauss mmc_free_host(host->mmc); 1152c4223c2cSManuel Lauss } 11531c6a0718SPierre Ossman return 0; 11541c6a0718SPierre Ossman } 11551c6a0718SPierre Ossman 1156dd8572afSManuel Lauss #ifdef CONFIG_PM 1157dd8572afSManuel Lauss static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state) 1158dd8572afSManuel Lauss { 1159dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1160dd8572afSManuel Lauss 1161dd8572afSManuel Lauss au_writel(0, HOST_CONFIG2(host)); 1162dd8572afSManuel Lauss au_writel(0, HOST_CONFIG(host)); 1163dd8572afSManuel Lauss au_writel(0xffffffff, HOST_STATUS(host)); 1164dd8572afSManuel Lauss au_writel(0, HOST_ENABLE(host)); 1165dd8572afSManuel Lauss au_sync(); 1166dd8572afSManuel Lauss 1167dd8572afSManuel Lauss return 0; 1168dd8572afSManuel Lauss } 1169dd8572afSManuel Lauss 1170dd8572afSManuel Lauss static int au1xmmc_resume(struct platform_device *pdev) 1171dd8572afSManuel Lauss { 1172dd8572afSManuel Lauss struct au1xmmc_host *host = platform_get_drvdata(pdev); 1173dd8572afSManuel Lauss 1174dd8572afSManuel Lauss au1xmmc_reset_controller(host); 1175dd8572afSManuel Lauss 11761e63d485SUlf Hansson return 0; 1177dd8572afSManuel Lauss } 1178dd8572afSManuel Lauss #else 1179dd8572afSManuel Lauss #define au1xmmc_suspend NULL 1180dd8572afSManuel Lauss #define au1xmmc_resume NULL 1181dd8572afSManuel Lauss #endif 1182dd8572afSManuel Lauss 11831c6a0718SPierre Ossman static struct platform_driver au1xmmc_driver = { 11841c6a0718SPierre Ossman .probe = au1xmmc_probe, 11851c6a0718SPierre Ossman .remove = au1xmmc_remove, 1186dd8572afSManuel Lauss .suspend = au1xmmc_suspend, 1187dd8572afSManuel Lauss .resume = au1xmmc_resume, 11881c6a0718SPierre Ossman .driver = { 11891c6a0718SPierre Ossman .name = DRIVER_NAME, 1190bc65c724SKay Sievers .owner = THIS_MODULE, 11911c6a0718SPierre Ossman }, 11921c6a0718SPierre Ossman }; 11931c6a0718SPierre Ossman 11941c6a0718SPierre Ossman static int __init au1xmmc_init(void) 11951c6a0718SPierre Ossman { 11961177d99dSManuel Lauss if (has_dbdma()) { 1197c4223c2cSManuel Lauss /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride 1198c4223c2cSManuel Lauss * of 8 bits. And since devices are shared, we need to create 1199c4223c2cSManuel Lauss * our own to avoid freaking out other devices. 1200c4223c2cSManuel Lauss */ 1201c4223c2cSManuel Lauss memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); 1202c4223c2cSManuel Lauss if (!memid) 1203d6748066SLinus Torvalds pr_err("au1xmmc: cannot add memory dbdma\n"); 12041177d99dSManuel Lauss } 12051c6a0718SPierre Ossman return platform_driver_register(&au1xmmc_driver); 12061c6a0718SPierre Ossman } 12071c6a0718SPierre Ossman 12081c6a0718SPierre Ossman static void __exit au1xmmc_exit(void) 12091c6a0718SPierre Ossman { 12101177d99dSManuel Lauss if (has_dbdma() && memid) 1211c4223c2cSManuel Lauss au1xxx_ddma_del_device(memid); 12121177d99dSManuel Lauss 12131c6a0718SPierre Ossman platform_driver_unregister(&au1xmmc_driver); 12141c6a0718SPierre Ossman } 12151c6a0718SPierre Ossman 12161c6a0718SPierre Ossman module_init(au1xmmc_init); 12171c6a0718SPierre Ossman module_exit(au1xmmc_exit); 12181c6a0718SPierre Ossman 12191c6a0718SPierre Ossman MODULE_AUTHOR("Advanced Micro Devices, Inc"); 12201c6a0718SPierre Ossman MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); 12211c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1222bc65c724SKay Sievers MODULE_ALIAS("platform:au1xxx-mmc"); 1223