1 /* 2 * Atmel MultiMedia Card Interface driver 3 * 4 * Copyright (C) 2004-2008 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/blkdev.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/device.h> 14 #include <linux/dmaengine.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/ioport.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_gpio.h> 26 #include <linux/platform_device.h> 27 #include <linux/scatterlist.h> 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <linux/stat.h> 31 #include <linux/types.h> 32 #include <linux/platform_data/atmel.h> 33 #include <linux/platform_data/mmc-atmel-mci.h> 34 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/sdio.h> 37 38 #include <linux/atmel-mci.h> 39 #include <linux/atmel_pdc.h> 40 #include <linux/pm.h> 41 #include <linux/pm_runtime.h> 42 43 #include <asm/cacheflush.h> 44 #include <asm/io.h> 45 #include <asm/unaligned.h> 46 47 #include "atmel-mci-regs.h" 48 49 #define AUTOSUSPEND_DELAY 50 50 51 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) 52 #define ATMCI_DMA_THRESHOLD 16 53 54 enum { 55 EVENT_CMD_RDY = 0, 56 EVENT_XFER_COMPLETE, 57 EVENT_NOTBUSY, 58 EVENT_DATA_ERROR, 59 }; 60 61 enum atmel_mci_state { 62 STATE_IDLE = 0, 63 STATE_SENDING_CMD, 64 STATE_DATA_XFER, 65 STATE_WAITING_NOTBUSY, 66 STATE_SENDING_STOP, 67 STATE_END_REQUEST, 68 }; 69 70 enum atmci_xfer_dir { 71 XFER_RECEIVE = 0, 72 XFER_TRANSMIT, 73 }; 74 75 enum atmci_pdc_buf { 76 PDC_FIRST_BUF = 0, 77 PDC_SECOND_BUF, 78 }; 79 80 struct atmel_mci_caps { 81 bool has_dma_conf_reg; 82 bool has_pdc; 83 bool has_cfg_reg; 84 bool has_cstor_reg; 85 bool has_highspeed; 86 bool has_rwproof; 87 bool has_odd_clk_div; 88 bool has_bad_data_ordering; 89 bool need_reset_after_xfer; 90 bool need_blksz_mul_4; 91 bool need_notbusy_for_read_ops; 92 }; 93 94 struct atmel_mci_dma { 95 struct dma_chan *chan; 96 struct dma_async_tx_descriptor *data_desc; 97 }; 98 99 /** 100 * struct atmel_mci - MMC controller state shared between all slots 101 * @lock: Spinlock protecting the queue and associated data. 102 * @regs: Pointer to MMIO registers. 103 * @sg: Scatterlist entry currently being processed by PIO or PDC code. 104 * @pio_offset: Offset into the current scatterlist entry. 105 * @buffer: Buffer used if we don't have the r/w proof capability. We 106 * don't have the time to switch pdc buffers so we have to use only 107 * one buffer for the full transaction. 108 * @buf_size: size of the buffer. 109 * @phys_buf_addr: buffer address needed for pdc. 110 * @cur_slot: The slot which is currently using the controller. 111 * @mrq: The request currently being processed on @cur_slot, 112 * or NULL if the controller is idle. 113 * @cmd: The command currently being sent to the card, or NULL. 114 * @data: The data currently being transferred, or NULL if no data 115 * transfer is in progress. 116 * @data_size: just data->blocks * data->blksz. 117 * @dma: DMA client state. 118 * @data_chan: DMA channel being used for the current data transfer. 119 * @cmd_status: Snapshot of SR taken upon completion of the current 120 * command. Only valid when EVENT_CMD_COMPLETE is pending. 121 * @data_status: Snapshot of SR taken upon completion of the current 122 * data transfer. Only valid when EVENT_DATA_COMPLETE or 123 * EVENT_DATA_ERROR is pending. 124 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 125 * to be sent. 126 * @tasklet: Tasklet running the request state machine. 127 * @pending_events: Bitmask of events flagged by the interrupt handler 128 * to be processed by the tasklet. 129 * @completed_events: Bitmask of events which the state machine has 130 * processed. 131 * @state: Tasklet state. 132 * @queue: List of slots waiting for access to the controller. 133 * @need_clock_update: Update the clock rate before the next request. 134 * @need_reset: Reset controller before next request. 135 * @timer: Timer to balance the data timeout error flag which cannot rise. 136 * @mode_reg: Value of the MR register. 137 * @cfg_reg: Value of the CFG register. 138 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 139 * rate and timeout calculations. 140 * @mapbase: Physical address of the MMIO registers. 141 * @mck: The peripheral bus clock hooked up to the MMC controller. 142 * @pdev: Platform device associated with the MMC controller. 143 * @slot: Slots sharing this MMC controller. 144 * @caps: MCI capabilities depending on MCI version. 145 * @prepare_data: function to setup MCI before data transfer which 146 * depends on MCI capabilities. 147 * @submit_data: function to start data transfer which depends on MCI 148 * capabilities. 149 * @stop_transfer: function to stop data transfer which depends on MCI 150 * capabilities. 151 * 152 * Locking 153 * ======= 154 * 155 * @lock is a softirq-safe spinlock protecting @queue as well as 156 * @cur_slot, @mrq and @state. These must always be updated 157 * at the same time while holding @lock. 158 * 159 * @lock also protects mode_reg and need_clock_update since these are 160 * used to synchronize mode register updates with the queue 161 * processing. 162 * 163 * The @mrq field of struct atmel_mci_slot is also protected by @lock, 164 * and must always be written at the same time as the slot is added to 165 * @queue. 166 * 167 * @pending_events and @completed_events are accessed using atomic bit 168 * operations, so they don't need any locking. 169 * 170 * None of the fields touched by the interrupt handler need any 171 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 172 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 173 * interrupts must be disabled and @data_status updated with a 174 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 175 * CMDRDY interrupt must be disabled and @cmd_status updated with a 176 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 177 * bytes_xfered field of @data must be written. This is ensured by 178 * using barriers. 179 */ 180 struct atmel_mci { 181 spinlock_t lock; 182 void __iomem *regs; 183 184 struct scatterlist *sg; 185 unsigned int sg_len; 186 unsigned int pio_offset; 187 unsigned int *buffer; 188 unsigned int buf_size; 189 dma_addr_t buf_phys_addr; 190 191 struct atmel_mci_slot *cur_slot; 192 struct mmc_request *mrq; 193 struct mmc_command *cmd; 194 struct mmc_data *data; 195 unsigned int data_size; 196 197 struct atmel_mci_dma dma; 198 struct dma_chan *data_chan; 199 struct dma_slave_config dma_conf; 200 201 u32 cmd_status; 202 u32 data_status; 203 u32 stop_cmdr; 204 205 struct tasklet_struct tasklet; 206 unsigned long pending_events; 207 unsigned long completed_events; 208 enum atmel_mci_state state; 209 struct list_head queue; 210 211 bool need_clock_update; 212 bool need_reset; 213 struct timer_list timer; 214 u32 mode_reg; 215 u32 cfg_reg; 216 unsigned long bus_hz; 217 unsigned long mapbase; 218 struct clk *mck; 219 struct platform_device *pdev; 220 221 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; 222 223 struct atmel_mci_caps caps; 224 225 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); 226 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); 227 void (*stop_transfer)(struct atmel_mci *host); 228 }; 229 230 /** 231 * struct atmel_mci_slot - MMC slot state 232 * @mmc: The mmc_host representing this slot. 233 * @host: The MMC controller this slot is using. 234 * @sdc_reg: Value of SDCR to be written before using this slot. 235 * @sdio_irq: SDIO irq mask for this slot. 236 * @mrq: mmc_request currently being processed or waiting to be 237 * processed, or NULL when the slot is idle. 238 * @queue_node: List node for placing this node in the @queue list of 239 * &struct atmel_mci. 240 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 241 * @flags: Random state bits associated with the slot. 242 * @detect_pin: GPIO pin used for card detection, or negative if not 243 * available. 244 * @wp_pin: GPIO pin used for card write protect sending, or negative 245 * if not available. 246 * @detect_is_active_high: The state of the detect pin when it is active. 247 * @detect_timer: Timer used for debouncing @detect_pin interrupts. 248 */ 249 struct atmel_mci_slot { 250 struct mmc_host *mmc; 251 struct atmel_mci *host; 252 253 u32 sdc_reg; 254 u32 sdio_irq; 255 256 struct mmc_request *mrq; 257 struct list_head queue_node; 258 259 unsigned int clock; 260 unsigned long flags; 261 #define ATMCI_CARD_PRESENT 0 262 #define ATMCI_CARD_NEED_INIT 1 263 #define ATMCI_SHUTDOWN 2 264 265 int detect_pin; 266 int wp_pin; 267 bool detect_is_active_high; 268 269 struct timer_list detect_timer; 270 }; 271 272 #define atmci_test_and_clear_pending(host, event) \ 273 test_and_clear_bit(event, &host->pending_events) 274 #define atmci_set_completed(host, event) \ 275 set_bit(event, &host->completed_events) 276 #define atmci_set_pending(host, event) \ 277 set_bit(event, &host->pending_events) 278 279 /* 280 * The debugfs stuff below is mostly optimized away when 281 * CONFIG_DEBUG_FS is not set. 282 */ 283 static int atmci_req_show(struct seq_file *s, void *v) 284 { 285 struct atmel_mci_slot *slot = s->private; 286 struct mmc_request *mrq; 287 struct mmc_command *cmd; 288 struct mmc_command *stop; 289 struct mmc_data *data; 290 291 /* Make sure we get a consistent snapshot */ 292 spin_lock_bh(&slot->host->lock); 293 mrq = slot->mrq; 294 295 if (mrq) { 296 cmd = mrq->cmd; 297 data = mrq->data; 298 stop = mrq->stop; 299 300 if (cmd) 301 seq_printf(s, 302 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 303 cmd->opcode, cmd->arg, cmd->flags, 304 cmd->resp[0], cmd->resp[1], cmd->resp[2], 305 cmd->resp[3], cmd->error); 306 if (data) 307 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 308 data->bytes_xfered, data->blocks, 309 data->blksz, data->flags, data->error); 310 if (stop) 311 seq_printf(s, 312 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 313 stop->opcode, stop->arg, stop->flags, 314 stop->resp[0], stop->resp[1], stop->resp[2], 315 stop->resp[3], stop->error); 316 } 317 318 spin_unlock_bh(&slot->host->lock); 319 320 return 0; 321 } 322 323 static int atmci_req_open(struct inode *inode, struct file *file) 324 { 325 return single_open(file, atmci_req_show, inode->i_private); 326 } 327 328 static const struct file_operations atmci_req_fops = { 329 .owner = THIS_MODULE, 330 .open = atmci_req_open, 331 .read = seq_read, 332 .llseek = seq_lseek, 333 .release = single_release, 334 }; 335 336 static void atmci_show_status_reg(struct seq_file *s, 337 const char *regname, u32 value) 338 { 339 static const char *sr_bit[] = { 340 [0] = "CMDRDY", 341 [1] = "RXRDY", 342 [2] = "TXRDY", 343 [3] = "BLKE", 344 [4] = "DTIP", 345 [5] = "NOTBUSY", 346 [6] = "ENDRX", 347 [7] = "ENDTX", 348 [8] = "SDIOIRQA", 349 [9] = "SDIOIRQB", 350 [12] = "SDIOWAIT", 351 [14] = "RXBUFF", 352 [15] = "TXBUFE", 353 [16] = "RINDE", 354 [17] = "RDIRE", 355 [18] = "RCRCE", 356 [19] = "RENDE", 357 [20] = "RTOE", 358 [21] = "DCRCE", 359 [22] = "DTOE", 360 [23] = "CSTOE", 361 [24] = "BLKOVRE", 362 [25] = "DMADONE", 363 [26] = "FIFOEMPTY", 364 [27] = "XFRDONE", 365 [30] = "OVRE", 366 [31] = "UNRE", 367 }; 368 unsigned int i; 369 370 seq_printf(s, "%s:\t0x%08x", regname, value); 371 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { 372 if (value & (1 << i)) { 373 if (sr_bit[i]) 374 seq_printf(s, " %s", sr_bit[i]); 375 else 376 seq_puts(s, " UNKNOWN"); 377 } 378 } 379 seq_putc(s, '\n'); 380 } 381 382 static int atmci_regs_show(struct seq_file *s, void *v) 383 { 384 struct atmel_mci *host = s->private; 385 u32 *buf; 386 int ret = 0; 387 388 389 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); 390 if (!buf) 391 return -ENOMEM; 392 393 pm_runtime_get_sync(&host->pdev->dev); 394 395 /* 396 * Grab a more or less consistent snapshot. Note that we're 397 * not disabling interrupts, so IMR and SR may not be 398 * consistent. 399 */ 400 spin_lock_bh(&host->lock); 401 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); 402 spin_unlock_bh(&host->lock); 403 404 pm_runtime_mark_last_busy(&host->pdev->dev); 405 pm_runtime_put_autosuspend(&host->pdev->dev); 406 407 seq_printf(s, "MR:\t0x%08x%s%s ", 408 buf[ATMCI_MR / 4], 409 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", 410 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : ""); 411 if (host->caps.has_odd_clk_div) 412 seq_printf(s, "{CLKDIV,CLKODD}=%u\n", 413 ((buf[ATMCI_MR / 4] & 0xff) << 1) 414 | ((buf[ATMCI_MR / 4] >> 16) & 1)); 415 else 416 seq_printf(s, "CLKDIV=%u\n", 417 (buf[ATMCI_MR / 4] & 0xff)); 418 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); 419 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); 420 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); 421 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", 422 buf[ATMCI_BLKR / 4], 423 buf[ATMCI_BLKR / 4] & 0xffff, 424 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); 425 if (host->caps.has_cstor_reg) 426 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); 427 428 /* Don't read RSPR and RDR; it will consume the data there */ 429 430 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); 431 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); 432 433 if (host->caps.has_dma_conf_reg) { 434 u32 val; 435 436 val = buf[ATMCI_DMA / 4]; 437 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", 438 val, val & 3, 439 ((val >> 4) & 3) ? 440 1 << (((val >> 4) & 3) + 1) : 1, 441 val & ATMCI_DMAEN ? " DMAEN" : ""); 442 } 443 if (host->caps.has_cfg_reg) { 444 u32 val; 445 446 val = buf[ATMCI_CFG / 4]; 447 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", 448 val, 449 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", 450 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", 451 val & ATMCI_CFG_HSMODE ? " HSMODE" : "", 452 val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); 453 } 454 455 kfree(buf); 456 457 return ret; 458 } 459 460 static int atmci_regs_open(struct inode *inode, struct file *file) 461 { 462 return single_open(file, atmci_regs_show, inode->i_private); 463 } 464 465 static const struct file_operations atmci_regs_fops = { 466 .owner = THIS_MODULE, 467 .open = atmci_regs_open, 468 .read = seq_read, 469 .llseek = seq_lseek, 470 .release = single_release, 471 }; 472 473 static void atmci_init_debugfs(struct atmel_mci_slot *slot) 474 { 475 struct mmc_host *mmc = slot->mmc; 476 struct atmel_mci *host = slot->host; 477 struct dentry *root; 478 struct dentry *node; 479 480 root = mmc->debugfs_root; 481 if (!root) 482 return; 483 484 node = debugfs_create_file("regs", S_IRUSR, root, host, 485 &atmci_regs_fops); 486 if (IS_ERR(node)) 487 return; 488 if (!node) 489 goto err; 490 491 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); 492 if (!node) 493 goto err; 494 495 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 496 if (!node) 497 goto err; 498 499 node = debugfs_create_x32("pending_events", S_IRUSR, root, 500 (u32 *)&host->pending_events); 501 if (!node) 502 goto err; 503 504 node = debugfs_create_x32("completed_events", S_IRUSR, root, 505 (u32 *)&host->completed_events); 506 if (!node) 507 goto err; 508 509 return; 510 511 err: 512 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 513 } 514 515 #if defined(CONFIG_OF) 516 static const struct of_device_id atmci_dt_ids[] = { 517 { .compatible = "atmel,hsmci" }, 518 { /* sentinel */ } 519 }; 520 521 MODULE_DEVICE_TABLE(of, atmci_dt_ids); 522 523 static struct mci_platform_data* 524 atmci_of_init(struct platform_device *pdev) 525 { 526 struct device_node *np = pdev->dev.of_node; 527 struct device_node *cnp; 528 struct mci_platform_data *pdata; 529 u32 slot_id; 530 531 if (!np) { 532 dev_err(&pdev->dev, "device node not found\n"); 533 return ERR_PTR(-EINVAL); 534 } 535 536 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 537 if (!pdata) { 538 dev_err(&pdev->dev, "could not allocate memory for pdata\n"); 539 return ERR_PTR(-ENOMEM); 540 } 541 542 for_each_child_of_node(np, cnp) { 543 if (of_property_read_u32(cnp, "reg", &slot_id)) { 544 dev_warn(&pdev->dev, "reg property is missing for %s\n", 545 cnp->full_name); 546 continue; 547 } 548 549 if (slot_id >= ATMCI_MAX_NR_SLOTS) { 550 dev_warn(&pdev->dev, "can't have more than %d slots\n", 551 ATMCI_MAX_NR_SLOTS); 552 break; 553 } 554 555 if (of_property_read_u32(cnp, "bus-width", 556 &pdata->slot[slot_id].bus_width)) 557 pdata->slot[slot_id].bus_width = 1; 558 559 pdata->slot[slot_id].detect_pin = 560 of_get_named_gpio(cnp, "cd-gpios", 0); 561 562 pdata->slot[slot_id].detect_is_active_high = 563 of_property_read_bool(cnp, "cd-inverted"); 564 565 pdata->slot[slot_id].non_removable = 566 of_property_read_bool(cnp, "non-removable"); 567 568 pdata->slot[slot_id].wp_pin = 569 of_get_named_gpio(cnp, "wp-gpios", 0); 570 } 571 572 return pdata; 573 } 574 #else /* CONFIG_OF */ 575 static inline struct mci_platform_data* 576 atmci_of_init(struct platform_device *dev) 577 { 578 return ERR_PTR(-EINVAL); 579 } 580 #endif 581 582 static inline unsigned int atmci_get_version(struct atmel_mci *host) 583 { 584 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; 585 } 586 587 static void atmci_timeout_timer(unsigned long data) 588 { 589 struct atmel_mci *host; 590 591 host = (struct atmel_mci *)data; 592 593 dev_dbg(&host->pdev->dev, "software timeout\n"); 594 595 if (host->mrq->cmd->data) { 596 host->mrq->cmd->data->error = -ETIMEDOUT; 597 host->data = NULL; 598 /* 599 * With some SDIO modules, sometimes DMA transfer hangs. If 600 * stop_transfer() is not called then the DMA request is not 601 * removed, following ones are queued and never computed. 602 */ 603 if (host->state == STATE_DATA_XFER) 604 host->stop_transfer(host); 605 } else { 606 host->mrq->cmd->error = -ETIMEDOUT; 607 host->cmd = NULL; 608 } 609 host->need_reset = 1; 610 host->state = STATE_END_REQUEST; 611 smp_wmb(); 612 tasklet_schedule(&host->tasklet); 613 } 614 615 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, 616 unsigned int ns) 617 { 618 /* 619 * It is easier here to use us instead of ns for the timeout, 620 * it prevents from overflows during calculation. 621 */ 622 unsigned int us = DIV_ROUND_UP(ns, 1000); 623 624 /* Maximum clock frequency is host->bus_hz/2 */ 625 return us * (DIV_ROUND_UP(host->bus_hz, 2000000)); 626 } 627 628 static void atmci_set_timeout(struct atmel_mci *host, 629 struct atmel_mci_slot *slot, struct mmc_data *data) 630 { 631 static unsigned dtomul_to_shift[] = { 632 0, 4, 7, 8, 10, 12, 16, 20 633 }; 634 unsigned timeout; 635 unsigned dtocyc; 636 unsigned dtomul; 637 638 timeout = atmci_ns_to_clocks(host, data->timeout_ns) 639 + data->timeout_clks; 640 641 for (dtomul = 0; dtomul < 8; dtomul++) { 642 unsigned shift = dtomul_to_shift[dtomul]; 643 dtocyc = (timeout + (1 << shift) - 1) >> shift; 644 if (dtocyc < 15) 645 break; 646 } 647 648 if (dtomul >= 8) { 649 dtomul = 7; 650 dtocyc = 15; 651 } 652 653 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 654 dtocyc << dtomul_to_shift[dtomul]); 655 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); 656 } 657 658 /* 659 * Return mask with command flags to be enabled for this command. 660 */ 661 static u32 atmci_prepare_command(struct mmc_host *mmc, 662 struct mmc_command *cmd) 663 { 664 struct mmc_data *data; 665 u32 cmdr; 666 667 cmd->error = -EINPROGRESS; 668 669 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); 670 671 if (cmd->flags & MMC_RSP_PRESENT) { 672 if (cmd->flags & MMC_RSP_136) 673 cmdr |= ATMCI_CMDR_RSPTYP_136BIT; 674 else 675 cmdr |= ATMCI_CMDR_RSPTYP_48BIT; 676 } 677 678 /* 679 * This should really be MAXLAT_5 for CMD2 and ACMD41, but 680 * it's too difficult to determine whether this is an ACMD or 681 * not. Better make it 64. 682 */ 683 cmdr |= ATMCI_CMDR_MAXLAT_64CYC; 684 685 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) 686 cmdr |= ATMCI_CMDR_OPDCMD; 687 688 data = cmd->data; 689 if (data) { 690 cmdr |= ATMCI_CMDR_START_XFER; 691 692 if (cmd->opcode == SD_IO_RW_EXTENDED) { 693 cmdr |= ATMCI_CMDR_SDIO_BLOCK; 694 } else { 695 if (data->flags & MMC_DATA_STREAM) 696 cmdr |= ATMCI_CMDR_STREAM; 697 else if (data->blocks > 1) 698 cmdr |= ATMCI_CMDR_MULTI_BLOCK; 699 else 700 cmdr |= ATMCI_CMDR_BLOCK; 701 } 702 703 if (data->flags & MMC_DATA_READ) 704 cmdr |= ATMCI_CMDR_TRDIR_READ; 705 } 706 707 return cmdr; 708 } 709 710 static void atmci_send_command(struct atmel_mci *host, 711 struct mmc_command *cmd, u32 cmd_flags) 712 { 713 WARN_ON(host->cmd); 714 host->cmd = cmd; 715 716 dev_vdbg(&host->pdev->dev, 717 "start command: ARGR=0x%08x CMDR=0x%08x\n", 718 cmd->arg, cmd_flags); 719 720 atmci_writel(host, ATMCI_ARGR, cmd->arg); 721 atmci_writel(host, ATMCI_CMDR, cmd_flags); 722 } 723 724 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 725 { 726 dev_dbg(&host->pdev->dev, "send stop command\n"); 727 atmci_send_command(host, data->stop, host->stop_cmdr); 728 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 729 } 730 731 /* 732 * Configure given PDC buffer taking care of alignement issues. 733 * Update host->data_size and host->sg. 734 */ 735 static void atmci_pdc_set_single_buf(struct atmel_mci *host, 736 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) 737 { 738 u32 pointer_reg, counter_reg; 739 unsigned int buf_size; 740 741 if (dir == XFER_RECEIVE) { 742 pointer_reg = ATMEL_PDC_RPR; 743 counter_reg = ATMEL_PDC_RCR; 744 } else { 745 pointer_reg = ATMEL_PDC_TPR; 746 counter_reg = ATMEL_PDC_TCR; 747 } 748 749 if (buf_nb == PDC_SECOND_BUF) { 750 pointer_reg += ATMEL_PDC_SCND_BUF_OFF; 751 counter_reg += ATMEL_PDC_SCND_BUF_OFF; 752 } 753 754 if (!host->caps.has_rwproof) { 755 buf_size = host->buf_size; 756 atmci_writel(host, pointer_reg, host->buf_phys_addr); 757 } else { 758 buf_size = sg_dma_len(host->sg); 759 atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); 760 } 761 762 if (host->data_size <= buf_size) { 763 if (host->data_size & 0x3) { 764 /* If size is different from modulo 4, transfer bytes */ 765 atmci_writel(host, counter_reg, host->data_size); 766 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); 767 } else { 768 /* Else transfer 32-bits words */ 769 atmci_writel(host, counter_reg, host->data_size / 4); 770 } 771 host->data_size = 0; 772 } else { 773 /* We assume the size of a page is 32-bits aligned */ 774 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); 775 host->data_size -= sg_dma_len(host->sg); 776 if (host->data_size) 777 host->sg = sg_next(host->sg); 778 } 779 } 780 781 /* 782 * Configure PDC buffer according to the data size ie configuring one or two 783 * buffers. Don't use this function if you want to configure only the second 784 * buffer. In this case, use atmci_pdc_set_single_buf. 785 */ 786 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) 787 { 788 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); 789 if (host->data_size) 790 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); 791 } 792 793 /* 794 * Unmap sg lists, called when transfer is finished. 795 */ 796 static void atmci_pdc_cleanup(struct atmel_mci *host) 797 { 798 struct mmc_data *data = host->data; 799 800 if (data) 801 dma_unmap_sg(&host->pdev->dev, 802 data->sg, data->sg_len, 803 ((data->flags & MMC_DATA_WRITE) 804 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 805 } 806 807 /* 808 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after 809 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY 810 * interrupt needed for both transfer directions. 811 */ 812 static void atmci_pdc_complete(struct atmel_mci *host) 813 { 814 int transfer_size = host->data->blocks * host->data->blksz; 815 int i; 816 817 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 818 819 if ((!host->caps.has_rwproof) 820 && (host->data->flags & MMC_DATA_READ)) { 821 if (host->caps.has_bad_data_ordering) 822 for (i = 0; i < transfer_size; i++) 823 host->buffer[i] = swab32(host->buffer[i]); 824 sg_copy_from_buffer(host->data->sg, host->data->sg_len, 825 host->buffer, transfer_size); 826 } 827 828 atmci_pdc_cleanup(host); 829 830 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__); 831 atmci_set_pending(host, EVENT_XFER_COMPLETE); 832 tasklet_schedule(&host->tasklet); 833 } 834 835 static void atmci_dma_cleanup(struct atmel_mci *host) 836 { 837 struct mmc_data *data = host->data; 838 839 if (data) 840 dma_unmap_sg(host->dma.chan->device->dev, 841 data->sg, data->sg_len, 842 ((data->flags & MMC_DATA_WRITE) 843 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 844 } 845 846 /* 847 * This function is called by the DMA driver from tasklet context. 848 */ 849 static void atmci_dma_complete(void *arg) 850 { 851 struct atmel_mci *host = arg; 852 struct mmc_data *data = host->data; 853 854 dev_vdbg(&host->pdev->dev, "DMA complete\n"); 855 856 if (host->caps.has_dma_conf_reg) 857 /* Disable DMA hardware handshaking on MCI */ 858 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); 859 860 atmci_dma_cleanup(host); 861 862 /* 863 * If the card was removed, data will be NULL. No point trying 864 * to send the stop command or waiting for NBUSY in this case. 865 */ 866 if (data) { 867 dev_dbg(&host->pdev->dev, 868 "(%s) set pending xfer complete\n", __func__); 869 atmci_set_pending(host, EVENT_XFER_COMPLETE); 870 tasklet_schedule(&host->tasklet); 871 872 /* 873 * Regardless of what the documentation says, we have 874 * to wait for NOTBUSY even after block read 875 * operations. 876 * 877 * When the DMA transfer is complete, the controller 878 * may still be reading the CRC from the card, i.e. 879 * the data transfer is still in progress and we 880 * haven't seen all the potential error bits yet. 881 * 882 * The interrupt handler will schedule a different 883 * tasklet to finish things up when the data transfer 884 * is completely done. 885 * 886 * We may not complete the mmc request here anyway 887 * because the mmc layer may call back and cause us to 888 * violate the "don't submit new operations from the 889 * completion callback" rule of the dma engine 890 * framework. 891 */ 892 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 893 } 894 } 895 896 /* 897 * Returns a mask of interrupt flags to be enabled after the whole 898 * request has been prepared. 899 */ 900 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) 901 { 902 u32 iflags; 903 904 data->error = -EINPROGRESS; 905 906 host->sg = data->sg; 907 host->sg_len = data->sg_len; 908 host->data = data; 909 host->data_chan = NULL; 910 911 iflags = ATMCI_DATA_ERROR_FLAGS; 912 913 /* 914 * Errata: MMC data write operation with less than 12 915 * bytes is impossible. 916 * 917 * Errata: MCI Transmit Data Register (TDR) FIFO 918 * corruption when length is not multiple of 4. 919 */ 920 if (data->blocks * data->blksz < 12 921 || (data->blocks * data->blksz) & 3) 922 host->need_reset = true; 923 924 host->pio_offset = 0; 925 if (data->flags & MMC_DATA_READ) 926 iflags |= ATMCI_RXRDY; 927 else 928 iflags |= ATMCI_TXRDY; 929 930 return iflags; 931 } 932 933 /* 934 * Set interrupt flags and set block length into the MCI mode register even 935 * if this value is also accessible in the MCI block register. It seems to be 936 * necessary before the High Speed MCI version. It also map sg and configure 937 * PDC registers. 938 */ 939 static u32 940 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) 941 { 942 u32 iflags, tmp; 943 unsigned int sg_len; 944 enum dma_data_direction dir; 945 int i; 946 947 data->error = -EINPROGRESS; 948 949 host->data = data; 950 host->sg = data->sg; 951 iflags = ATMCI_DATA_ERROR_FLAGS; 952 953 /* Enable pdc mode */ 954 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); 955 956 if (data->flags & MMC_DATA_READ) { 957 dir = DMA_FROM_DEVICE; 958 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; 959 } else { 960 dir = DMA_TO_DEVICE; 961 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE; 962 } 963 964 /* Set BLKLEN */ 965 tmp = atmci_readl(host, ATMCI_MR); 966 tmp &= 0x0000ffff; 967 tmp |= ATMCI_BLKLEN(data->blksz); 968 atmci_writel(host, ATMCI_MR, tmp); 969 970 /* Configure PDC */ 971 host->data_size = data->blocks * data->blksz; 972 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir); 973 974 if ((!host->caps.has_rwproof) 975 && (host->data->flags & MMC_DATA_WRITE)) { 976 sg_copy_to_buffer(host->data->sg, host->data->sg_len, 977 host->buffer, host->data_size); 978 if (host->caps.has_bad_data_ordering) 979 for (i = 0; i < host->data_size; i++) 980 host->buffer[i] = swab32(host->buffer[i]); 981 } 982 983 if (host->data_size) 984 atmci_pdc_set_both_buf(host, 985 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT)); 986 987 return iflags; 988 } 989 990 static u32 991 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) 992 { 993 struct dma_chan *chan; 994 struct dma_async_tx_descriptor *desc; 995 struct scatterlist *sg; 996 unsigned int i; 997 enum dma_data_direction direction; 998 enum dma_transfer_direction slave_dirn; 999 unsigned int sglen; 1000 u32 maxburst; 1001 u32 iflags; 1002 1003 data->error = -EINPROGRESS; 1004 1005 WARN_ON(host->data); 1006 host->sg = NULL; 1007 host->data = data; 1008 1009 iflags = ATMCI_DATA_ERROR_FLAGS; 1010 1011 /* 1012 * We don't do DMA on "complex" transfers, i.e. with 1013 * non-word-aligned buffers or lengths. Also, we don't bother 1014 * with all the DMA setup overhead for short transfers. 1015 */ 1016 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 1017 return atmci_prepare_data(host, data); 1018 if (data->blksz & 3) 1019 return atmci_prepare_data(host, data); 1020 1021 for_each_sg(data->sg, sg, data->sg_len, i) { 1022 if (sg->offset & 3 || sg->length & 3) 1023 return atmci_prepare_data(host, data); 1024 } 1025 1026 /* If we don't have a channel, we can't do DMA */ 1027 chan = host->dma.chan; 1028 if (chan) 1029 host->data_chan = chan; 1030 1031 if (!chan) 1032 return -ENODEV; 1033 1034 if (data->flags & MMC_DATA_READ) { 1035 direction = DMA_FROM_DEVICE; 1036 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM; 1037 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst); 1038 } else { 1039 direction = DMA_TO_DEVICE; 1040 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV; 1041 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst); 1042 } 1043 1044 if (host->caps.has_dma_conf_reg) 1045 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | 1046 ATMCI_DMAEN); 1047 1048 sglen = dma_map_sg(chan->device->dev, data->sg, 1049 data->sg_len, direction); 1050 1051 dmaengine_slave_config(chan, &host->dma_conf); 1052 desc = dmaengine_prep_slave_sg(chan, 1053 data->sg, sglen, slave_dirn, 1054 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1055 if (!desc) 1056 goto unmap_exit; 1057 1058 host->dma.data_desc = desc; 1059 desc->callback = atmci_dma_complete; 1060 desc->callback_param = host; 1061 1062 return iflags; 1063 unmap_exit: 1064 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction); 1065 return -ENOMEM; 1066 } 1067 1068 static void 1069 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) 1070 { 1071 return; 1072 } 1073 1074 /* 1075 * Start PDC according to transfer direction. 1076 */ 1077 static void 1078 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) 1079 { 1080 if (data->flags & MMC_DATA_READ) 1081 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1082 else 1083 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1084 } 1085 1086 static void 1087 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) 1088 { 1089 struct dma_chan *chan = host->data_chan; 1090 struct dma_async_tx_descriptor *desc = host->dma.data_desc; 1091 1092 if (chan) { 1093 dmaengine_submit(desc); 1094 dma_async_issue_pending(chan); 1095 } 1096 } 1097 1098 static void atmci_stop_transfer(struct atmel_mci *host) 1099 { 1100 dev_dbg(&host->pdev->dev, 1101 "(%s) set pending xfer complete\n", __func__); 1102 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1103 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1104 } 1105 1106 /* 1107 * Stop data transfer because error(s) occurred. 1108 */ 1109 static void atmci_stop_transfer_pdc(struct atmel_mci *host) 1110 { 1111 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 1112 } 1113 1114 static void atmci_stop_transfer_dma(struct atmel_mci *host) 1115 { 1116 struct dma_chan *chan = host->data_chan; 1117 1118 if (chan) { 1119 dmaengine_terminate_all(chan); 1120 atmci_dma_cleanup(host); 1121 } else { 1122 /* Data transfer was stopped by the interrupt handler */ 1123 dev_dbg(&host->pdev->dev, 1124 "(%s) set pending xfer complete\n", __func__); 1125 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1126 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1127 } 1128 } 1129 1130 /* 1131 * Start a request: prepare data if needed, prepare the command and activate 1132 * interrupts. 1133 */ 1134 static void atmci_start_request(struct atmel_mci *host, 1135 struct atmel_mci_slot *slot) 1136 { 1137 struct mmc_request *mrq; 1138 struct mmc_command *cmd; 1139 struct mmc_data *data; 1140 u32 iflags; 1141 u32 cmdflags; 1142 1143 mrq = slot->mrq; 1144 host->cur_slot = slot; 1145 host->mrq = mrq; 1146 1147 host->pending_events = 0; 1148 host->completed_events = 0; 1149 host->cmd_status = 0; 1150 host->data_status = 0; 1151 1152 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode); 1153 1154 if (host->need_reset || host->caps.need_reset_after_xfer) { 1155 iflags = atmci_readl(host, ATMCI_IMR); 1156 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB); 1157 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1158 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1159 atmci_writel(host, ATMCI_MR, host->mode_reg); 1160 if (host->caps.has_cfg_reg) 1161 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1162 atmci_writel(host, ATMCI_IER, iflags); 1163 host->need_reset = false; 1164 } 1165 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); 1166 1167 iflags = atmci_readl(host, ATMCI_IMR); 1168 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 1169 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 1170 iflags); 1171 1172 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 1173 /* Send init sequence (74 clock cycles) */ 1174 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); 1175 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) 1176 cpu_relax(); 1177 } 1178 iflags = 0; 1179 data = mrq->data; 1180 if (data) { 1181 atmci_set_timeout(host, slot, data); 1182 1183 /* Must set block count/size before sending command */ 1184 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) 1185 | ATMCI_BLKLEN(data->blksz)); 1186 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 1187 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); 1188 1189 iflags |= host->prepare_data(host, data); 1190 } 1191 1192 iflags |= ATMCI_CMDRDY; 1193 cmd = mrq->cmd; 1194 cmdflags = atmci_prepare_command(slot->mmc, cmd); 1195 1196 /* 1197 * DMA transfer should be started before sending the command to avoid 1198 * unexpected errors especially for read operations in SDIO mode. 1199 * Unfortunately, in PDC mode, command has to be sent before starting 1200 * the transfer. 1201 */ 1202 if (host->submit_data != &atmci_submit_data_dma) 1203 atmci_send_command(host, cmd, cmdflags); 1204 1205 if (data) 1206 host->submit_data(host, data); 1207 1208 if (host->submit_data == &atmci_submit_data_dma) 1209 atmci_send_command(host, cmd, cmdflags); 1210 1211 if (mrq->stop) { 1212 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 1213 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; 1214 if (!(data->flags & MMC_DATA_WRITE)) 1215 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; 1216 if (data->flags & MMC_DATA_STREAM) 1217 host->stop_cmdr |= ATMCI_CMDR_STREAM; 1218 else 1219 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; 1220 } 1221 1222 /* 1223 * We could have enabled interrupts earlier, but I suspect 1224 * that would open up a nice can of interesting race 1225 * conditions (e.g. command and data complete, but stop not 1226 * prepared yet.) 1227 */ 1228 atmci_writel(host, ATMCI_IER, iflags); 1229 1230 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); 1231 } 1232 1233 static void atmci_queue_request(struct atmel_mci *host, 1234 struct atmel_mci_slot *slot, struct mmc_request *mrq) 1235 { 1236 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1237 host->state); 1238 1239 spin_lock_bh(&host->lock); 1240 slot->mrq = mrq; 1241 if (host->state == STATE_IDLE) { 1242 host->state = STATE_SENDING_CMD; 1243 atmci_start_request(host, slot); 1244 } else { 1245 dev_dbg(&host->pdev->dev, "queue request\n"); 1246 list_add_tail(&slot->queue_node, &host->queue); 1247 } 1248 spin_unlock_bh(&host->lock); 1249 } 1250 1251 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1252 { 1253 struct atmel_mci_slot *slot = mmc_priv(mmc); 1254 struct atmel_mci *host = slot->host; 1255 struct mmc_data *data; 1256 1257 WARN_ON(slot->mrq); 1258 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode); 1259 1260 pm_runtime_get_sync(&host->pdev->dev); 1261 1262 /* 1263 * We may "know" the card is gone even though there's still an 1264 * electrical connection. If so, we really need to communicate 1265 * this to the MMC core since there won't be any more 1266 * interrupts as the card is completely removed. Otherwise, 1267 * the MMC core might believe the card is still there even 1268 * though the card was just removed very slowly. 1269 */ 1270 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { 1271 mrq->cmd->error = -ENOMEDIUM; 1272 mmc_request_done(mmc, mrq); 1273 return; 1274 } 1275 1276 /* We don't support multiple blocks of weird lengths. */ 1277 data = mrq->data; 1278 if (data && data->blocks > 1 && data->blksz & 3) { 1279 mrq->cmd->error = -EINVAL; 1280 mmc_request_done(mmc, mrq); 1281 } 1282 1283 atmci_queue_request(host, slot, mrq); 1284 } 1285 1286 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1287 { 1288 struct atmel_mci_slot *slot = mmc_priv(mmc); 1289 struct atmel_mci *host = slot->host; 1290 unsigned int i; 1291 1292 pm_runtime_get_sync(&host->pdev->dev); 1293 1294 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; 1295 switch (ios->bus_width) { 1296 case MMC_BUS_WIDTH_1: 1297 slot->sdc_reg |= ATMCI_SDCBUS_1BIT; 1298 break; 1299 case MMC_BUS_WIDTH_4: 1300 slot->sdc_reg |= ATMCI_SDCBUS_4BIT; 1301 break; 1302 } 1303 1304 if (ios->clock) { 1305 unsigned int clock_min = ~0U; 1306 u32 clkdiv; 1307 1308 spin_lock_bh(&host->lock); 1309 if (!host->mode_reg) { 1310 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1311 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1312 if (host->caps.has_cfg_reg) 1313 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1314 } 1315 1316 /* 1317 * Use mirror of ios->clock to prevent race with mmc 1318 * core ios update when finding the minimum. 1319 */ 1320 slot->clock = ios->clock; 1321 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1322 if (host->slot[i] && host->slot[i]->clock 1323 && host->slot[i]->clock < clock_min) 1324 clock_min = host->slot[i]->clock; 1325 } 1326 1327 /* Calculate clock divider */ 1328 if (host->caps.has_odd_clk_div) { 1329 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; 1330 if (clkdiv > 511) { 1331 dev_warn(&mmc->class_dev, 1332 "clock %u too slow; using %lu\n", 1333 clock_min, host->bus_hz / (511 + 2)); 1334 clkdiv = 511; 1335 } 1336 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) 1337 | ATMCI_MR_CLKODD(clkdiv & 1); 1338 } else { 1339 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; 1340 if (clkdiv > 255) { 1341 dev_warn(&mmc->class_dev, 1342 "clock %u too slow; using %lu\n", 1343 clock_min, host->bus_hz / (2 * 256)); 1344 clkdiv = 255; 1345 } 1346 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); 1347 } 1348 1349 /* 1350 * WRPROOF and RDPROOF prevent overruns/underruns by 1351 * stopping the clock when the FIFO is full/empty. 1352 * This state is not expected to last for long. 1353 */ 1354 if (host->caps.has_rwproof) 1355 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); 1356 1357 if (host->caps.has_cfg_reg) { 1358 /* setup High Speed mode in relation with card capacity */ 1359 if (ios->timing == MMC_TIMING_SD_HS) 1360 host->cfg_reg |= ATMCI_CFG_HSMODE; 1361 else 1362 host->cfg_reg &= ~ATMCI_CFG_HSMODE; 1363 } 1364 1365 if (list_empty(&host->queue)) { 1366 atmci_writel(host, ATMCI_MR, host->mode_reg); 1367 if (host->caps.has_cfg_reg) 1368 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1369 } else { 1370 host->need_clock_update = true; 1371 } 1372 1373 spin_unlock_bh(&host->lock); 1374 } else { 1375 bool any_slot_active = false; 1376 1377 spin_lock_bh(&host->lock); 1378 slot->clock = 0; 1379 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1380 if (host->slot[i] && host->slot[i]->clock) { 1381 any_slot_active = true; 1382 break; 1383 } 1384 } 1385 if (!any_slot_active) { 1386 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 1387 if (host->mode_reg) { 1388 atmci_readl(host, ATMCI_MR); 1389 } 1390 host->mode_reg = 0; 1391 } 1392 spin_unlock_bh(&host->lock); 1393 } 1394 1395 switch (ios->power_mode) { 1396 case MMC_POWER_OFF: 1397 if (!IS_ERR(mmc->supply.vmmc)) 1398 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1399 break; 1400 case MMC_POWER_UP: 1401 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); 1402 if (!IS_ERR(mmc->supply.vmmc)) 1403 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1404 break; 1405 default: 1406 /* 1407 * TODO: None of the currently available AVR32-based 1408 * boards allow MMC power to be turned off. Implement 1409 * power control when this can be tested properly. 1410 * 1411 * We also need to hook this into the clock management 1412 * somehow so that newly inserted cards aren't 1413 * subjected to a fast clock before we have a chance 1414 * to figure out what the maximum rate is. Currently, 1415 * there's no way to avoid this, and there never will 1416 * be for boards that don't support power control. 1417 */ 1418 break; 1419 } 1420 1421 pm_runtime_mark_last_busy(&host->pdev->dev); 1422 pm_runtime_put_autosuspend(&host->pdev->dev); 1423 } 1424 1425 static int atmci_get_ro(struct mmc_host *mmc) 1426 { 1427 int read_only = -ENOSYS; 1428 struct atmel_mci_slot *slot = mmc_priv(mmc); 1429 1430 if (gpio_is_valid(slot->wp_pin)) { 1431 read_only = gpio_get_value(slot->wp_pin); 1432 dev_dbg(&mmc->class_dev, "card is %s\n", 1433 read_only ? "read-only" : "read-write"); 1434 } 1435 1436 return read_only; 1437 } 1438 1439 static int atmci_get_cd(struct mmc_host *mmc) 1440 { 1441 int present = -ENOSYS; 1442 struct atmel_mci_slot *slot = mmc_priv(mmc); 1443 1444 if (gpio_is_valid(slot->detect_pin)) { 1445 present = !(gpio_get_value(slot->detect_pin) ^ 1446 slot->detect_is_active_high); 1447 dev_dbg(&mmc->class_dev, "card is %spresent\n", 1448 present ? "" : "not "); 1449 } 1450 1451 return present; 1452 } 1453 1454 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1455 { 1456 struct atmel_mci_slot *slot = mmc_priv(mmc); 1457 struct atmel_mci *host = slot->host; 1458 1459 if (enable) 1460 atmci_writel(host, ATMCI_IER, slot->sdio_irq); 1461 else 1462 atmci_writel(host, ATMCI_IDR, slot->sdio_irq); 1463 } 1464 1465 static const struct mmc_host_ops atmci_ops = { 1466 .request = atmci_request, 1467 .set_ios = atmci_set_ios, 1468 .get_ro = atmci_get_ro, 1469 .get_cd = atmci_get_cd, 1470 .enable_sdio_irq = atmci_enable_sdio_irq, 1471 }; 1472 1473 /* Called with host->lock held */ 1474 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) 1475 __releases(&host->lock) 1476 __acquires(&host->lock) 1477 { 1478 struct atmel_mci_slot *slot = NULL; 1479 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1480 1481 WARN_ON(host->cmd || host->data); 1482 1483 /* 1484 * Update the MMC clock rate if necessary. This may be 1485 * necessary if set_ios() is called when a different slot is 1486 * busy transferring data. 1487 */ 1488 if (host->need_clock_update) { 1489 atmci_writel(host, ATMCI_MR, host->mode_reg); 1490 if (host->caps.has_cfg_reg) 1491 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1492 } 1493 1494 host->cur_slot->mrq = NULL; 1495 host->mrq = NULL; 1496 if (!list_empty(&host->queue)) { 1497 slot = list_entry(host->queue.next, 1498 struct atmel_mci_slot, queue_node); 1499 list_del(&slot->queue_node); 1500 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 1501 mmc_hostname(slot->mmc)); 1502 host->state = STATE_SENDING_CMD; 1503 atmci_start_request(host, slot); 1504 } else { 1505 dev_vdbg(&host->pdev->dev, "list empty\n"); 1506 host->state = STATE_IDLE; 1507 } 1508 1509 del_timer(&host->timer); 1510 1511 spin_unlock(&host->lock); 1512 mmc_request_done(prev_mmc, mrq); 1513 spin_lock(&host->lock); 1514 1515 pm_runtime_mark_last_busy(&host->pdev->dev); 1516 pm_runtime_put_autosuspend(&host->pdev->dev); 1517 } 1518 1519 static void atmci_command_complete(struct atmel_mci *host, 1520 struct mmc_command *cmd) 1521 { 1522 u32 status = host->cmd_status; 1523 1524 /* Read the response from the card (up to 16 bytes) */ 1525 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); 1526 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); 1527 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); 1528 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); 1529 1530 if (status & ATMCI_RTOE) 1531 cmd->error = -ETIMEDOUT; 1532 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) 1533 cmd->error = -EILSEQ; 1534 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) 1535 cmd->error = -EIO; 1536 else if (host->mrq->data && (host->mrq->data->blksz & 3)) { 1537 if (host->caps.need_blksz_mul_4) { 1538 cmd->error = -EINVAL; 1539 host->need_reset = 1; 1540 } 1541 } else 1542 cmd->error = 0; 1543 } 1544 1545 static void atmci_detect_change(unsigned long data) 1546 { 1547 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; 1548 bool present; 1549 bool present_old; 1550 1551 /* 1552 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before 1553 * freeing the interrupt. We must not re-enable the interrupt 1554 * if it has been freed, and if we're shutting down, it 1555 * doesn't really matter whether the card is present or not. 1556 */ 1557 smp_rmb(); 1558 if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) 1559 return; 1560 1561 enable_irq(gpio_to_irq(slot->detect_pin)); 1562 present = !(gpio_get_value(slot->detect_pin) ^ 1563 slot->detect_is_active_high); 1564 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1565 1566 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 1567 present, present_old); 1568 1569 if (present != present_old) { 1570 struct atmel_mci *host = slot->host; 1571 struct mmc_request *mrq; 1572 1573 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1574 present ? "inserted" : "removed"); 1575 1576 spin_lock(&host->lock); 1577 1578 if (!present) 1579 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1580 else 1581 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1582 1583 /* Clean up queue if present */ 1584 mrq = slot->mrq; 1585 if (mrq) { 1586 if (mrq == host->mrq) { 1587 /* 1588 * Reset controller to terminate any ongoing 1589 * commands or data transfers. 1590 */ 1591 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1592 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1593 atmci_writel(host, ATMCI_MR, host->mode_reg); 1594 if (host->caps.has_cfg_reg) 1595 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1596 1597 host->data = NULL; 1598 host->cmd = NULL; 1599 1600 switch (host->state) { 1601 case STATE_IDLE: 1602 break; 1603 case STATE_SENDING_CMD: 1604 mrq->cmd->error = -ENOMEDIUM; 1605 if (mrq->data) 1606 host->stop_transfer(host); 1607 break; 1608 case STATE_DATA_XFER: 1609 mrq->data->error = -ENOMEDIUM; 1610 host->stop_transfer(host); 1611 break; 1612 case STATE_WAITING_NOTBUSY: 1613 mrq->data->error = -ENOMEDIUM; 1614 break; 1615 case STATE_SENDING_STOP: 1616 mrq->stop->error = -ENOMEDIUM; 1617 break; 1618 case STATE_END_REQUEST: 1619 break; 1620 } 1621 1622 atmci_request_end(host, mrq); 1623 } else { 1624 list_del(&slot->queue_node); 1625 mrq->cmd->error = -ENOMEDIUM; 1626 if (mrq->data) 1627 mrq->data->error = -ENOMEDIUM; 1628 if (mrq->stop) 1629 mrq->stop->error = -ENOMEDIUM; 1630 1631 spin_unlock(&host->lock); 1632 mmc_request_done(slot->mmc, mrq); 1633 spin_lock(&host->lock); 1634 } 1635 } 1636 spin_unlock(&host->lock); 1637 1638 mmc_detect_change(slot->mmc, 0); 1639 } 1640 } 1641 1642 static void atmci_tasklet_func(unsigned long priv) 1643 { 1644 struct atmel_mci *host = (struct atmel_mci *)priv; 1645 struct mmc_request *mrq = host->mrq; 1646 struct mmc_data *data = host->data; 1647 enum atmel_mci_state state = host->state; 1648 enum atmel_mci_state prev_state; 1649 u32 status; 1650 1651 spin_lock(&host->lock); 1652 1653 state = host->state; 1654 1655 dev_vdbg(&host->pdev->dev, 1656 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1657 state, host->pending_events, host->completed_events, 1658 atmci_readl(host, ATMCI_IMR)); 1659 1660 do { 1661 prev_state = state; 1662 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state); 1663 1664 switch (state) { 1665 case STATE_IDLE: 1666 break; 1667 1668 case STATE_SENDING_CMD: 1669 /* 1670 * Command has been sent, we are waiting for command 1671 * ready. Then we have three next states possible: 1672 * END_REQUEST by default, WAITING_NOTBUSY if it's a 1673 * command needing it or DATA_XFER if there is data. 1674 */ 1675 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1676 if (!atmci_test_and_clear_pending(host, 1677 EVENT_CMD_RDY)) 1678 break; 1679 1680 dev_dbg(&host->pdev->dev, "set completed cmd ready\n"); 1681 host->cmd = NULL; 1682 atmci_set_completed(host, EVENT_CMD_RDY); 1683 atmci_command_complete(host, mrq->cmd); 1684 if (mrq->data) { 1685 dev_dbg(&host->pdev->dev, 1686 "command with data transfer"); 1687 /* 1688 * If there is a command error don't start 1689 * data transfer. 1690 */ 1691 if (mrq->cmd->error) { 1692 host->stop_transfer(host); 1693 host->data = NULL; 1694 atmci_writel(host, ATMCI_IDR, 1695 ATMCI_TXRDY | ATMCI_RXRDY 1696 | ATMCI_DATA_ERROR_FLAGS); 1697 state = STATE_END_REQUEST; 1698 } else 1699 state = STATE_DATA_XFER; 1700 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) { 1701 dev_dbg(&host->pdev->dev, 1702 "command response need waiting notbusy"); 1703 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1704 state = STATE_WAITING_NOTBUSY; 1705 } else 1706 state = STATE_END_REQUEST; 1707 1708 break; 1709 1710 case STATE_DATA_XFER: 1711 if (atmci_test_and_clear_pending(host, 1712 EVENT_DATA_ERROR)) { 1713 dev_dbg(&host->pdev->dev, "set completed data error\n"); 1714 atmci_set_completed(host, EVENT_DATA_ERROR); 1715 state = STATE_END_REQUEST; 1716 break; 1717 } 1718 1719 /* 1720 * A data transfer is in progress. The event expected 1721 * to move to the next state depends of data transfer 1722 * type (PDC or DMA). Once transfer done we can move 1723 * to the next step which is WAITING_NOTBUSY in write 1724 * case and directly SENDING_STOP in read case. 1725 */ 1726 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n"); 1727 if (!atmci_test_and_clear_pending(host, 1728 EVENT_XFER_COMPLETE)) 1729 break; 1730 1731 dev_dbg(&host->pdev->dev, 1732 "(%s) set completed xfer complete\n", 1733 __func__); 1734 atmci_set_completed(host, EVENT_XFER_COMPLETE); 1735 1736 if (host->caps.need_notbusy_for_read_ops || 1737 (host->data->flags & MMC_DATA_WRITE)) { 1738 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1739 state = STATE_WAITING_NOTBUSY; 1740 } else if (host->mrq->stop) { 1741 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 1742 atmci_send_stop_cmd(host, data); 1743 state = STATE_SENDING_STOP; 1744 } else { 1745 host->data = NULL; 1746 data->bytes_xfered = data->blocks * data->blksz; 1747 data->error = 0; 1748 state = STATE_END_REQUEST; 1749 } 1750 break; 1751 1752 case STATE_WAITING_NOTBUSY: 1753 /* 1754 * We can be in the state for two reasons: a command 1755 * requiring waiting not busy signal (stop command 1756 * included) or a write operation. In the latest case, 1757 * we need to send a stop command. 1758 */ 1759 dev_dbg(&host->pdev->dev, "FSM: not busy?\n"); 1760 if (!atmci_test_and_clear_pending(host, 1761 EVENT_NOTBUSY)) 1762 break; 1763 1764 dev_dbg(&host->pdev->dev, "set completed not busy\n"); 1765 atmci_set_completed(host, EVENT_NOTBUSY); 1766 1767 if (host->data) { 1768 /* 1769 * For some commands such as CMD53, even if 1770 * there is data transfer, there is no stop 1771 * command to send. 1772 */ 1773 if (host->mrq->stop) { 1774 atmci_writel(host, ATMCI_IER, 1775 ATMCI_CMDRDY); 1776 atmci_send_stop_cmd(host, data); 1777 state = STATE_SENDING_STOP; 1778 } else { 1779 host->data = NULL; 1780 data->bytes_xfered = data->blocks 1781 * data->blksz; 1782 data->error = 0; 1783 state = STATE_END_REQUEST; 1784 } 1785 } else 1786 state = STATE_END_REQUEST; 1787 break; 1788 1789 case STATE_SENDING_STOP: 1790 /* 1791 * In this state, it is important to set host->data to 1792 * NULL (which is tested in the waiting notbusy state) 1793 * in order to go to the end request state instead of 1794 * sending stop again. 1795 */ 1796 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1797 if (!atmci_test_and_clear_pending(host, 1798 EVENT_CMD_RDY)) 1799 break; 1800 1801 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n"); 1802 host->cmd = NULL; 1803 data->bytes_xfered = data->blocks * data->blksz; 1804 data->error = 0; 1805 atmci_command_complete(host, mrq->stop); 1806 if (mrq->stop->error) { 1807 host->stop_transfer(host); 1808 atmci_writel(host, ATMCI_IDR, 1809 ATMCI_TXRDY | ATMCI_RXRDY 1810 | ATMCI_DATA_ERROR_FLAGS); 1811 state = STATE_END_REQUEST; 1812 } else { 1813 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1814 state = STATE_WAITING_NOTBUSY; 1815 } 1816 host->data = NULL; 1817 break; 1818 1819 case STATE_END_REQUEST: 1820 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY 1821 | ATMCI_DATA_ERROR_FLAGS); 1822 status = host->data_status; 1823 if (unlikely(status)) { 1824 host->stop_transfer(host); 1825 host->data = NULL; 1826 if (data) { 1827 if (status & ATMCI_DTOE) { 1828 data->error = -ETIMEDOUT; 1829 } else if (status & ATMCI_DCRCE) { 1830 data->error = -EILSEQ; 1831 } else { 1832 data->error = -EIO; 1833 } 1834 } 1835 } 1836 1837 atmci_request_end(host, host->mrq); 1838 state = STATE_IDLE; 1839 break; 1840 } 1841 } while (state != prev_state); 1842 1843 host->state = state; 1844 1845 spin_unlock(&host->lock); 1846 } 1847 1848 static void atmci_read_data_pio(struct atmel_mci *host) 1849 { 1850 struct scatterlist *sg = host->sg; 1851 void *buf = sg_virt(sg); 1852 unsigned int offset = host->pio_offset; 1853 struct mmc_data *data = host->data; 1854 u32 value; 1855 u32 status; 1856 unsigned int nbytes = 0; 1857 1858 do { 1859 value = atmci_readl(host, ATMCI_RDR); 1860 if (likely(offset + 4 <= sg->length)) { 1861 put_unaligned(value, (u32 *)(buf + offset)); 1862 1863 offset += 4; 1864 nbytes += 4; 1865 1866 if (offset == sg->length) { 1867 flush_dcache_page(sg_page(sg)); 1868 host->sg = sg = sg_next(sg); 1869 host->sg_len--; 1870 if (!sg || !host->sg_len) 1871 goto done; 1872 1873 offset = 0; 1874 buf = sg_virt(sg); 1875 } 1876 } else { 1877 unsigned int remaining = sg->length - offset; 1878 memcpy(buf + offset, &value, remaining); 1879 nbytes += remaining; 1880 1881 flush_dcache_page(sg_page(sg)); 1882 host->sg = sg = sg_next(sg); 1883 host->sg_len--; 1884 if (!sg || !host->sg_len) 1885 goto done; 1886 1887 offset = 4 - remaining; 1888 buf = sg_virt(sg); 1889 memcpy(buf, (u8 *)&value + remaining, offset); 1890 nbytes += offset; 1891 } 1892 1893 status = atmci_readl(host, ATMCI_SR); 1894 if (status & ATMCI_DATA_ERROR_FLAGS) { 1895 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY 1896 | ATMCI_DATA_ERROR_FLAGS)); 1897 host->data_status = status; 1898 data->bytes_xfered += nbytes; 1899 return; 1900 } 1901 } while (status & ATMCI_RXRDY); 1902 1903 host->pio_offset = offset; 1904 data->bytes_xfered += nbytes; 1905 1906 return; 1907 1908 done: 1909 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); 1910 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1911 data->bytes_xfered += nbytes; 1912 smp_wmb(); 1913 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1914 } 1915 1916 static void atmci_write_data_pio(struct atmel_mci *host) 1917 { 1918 struct scatterlist *sg = host->sg; 1919 void *buf = sg_virt(sg); 1920 unsigned int offset = host->pio_offset; 1921 struct mmc_data *data = host->data; 1922 u32 value; 1923 u32 status; 1924 unsigned int nbytes = 0; 1925 1926 do { 1927 if (likely(offset + 4 <= sg->length)) { 1928 value = get_unaligned((u32 *)(buf + offset)); 1929 atmci_writel(host, ATMCI_TDR, value); 1930 1931 offset += 4; 1932 nbytes += 4; 1933 if (offset == sg->length) { 1934 host->sg = sg = sg_next(sg); 1935 host->sg_len--; 1936 if (!sg || !host->sg_len) 1937 goto done; 1938 1939 offset = 0; 1940 buf = sg_virt(sg); 1941 } 1942 } else { 1943 unsigned int remaining = sg->length - offset; 1944 1945 value = 0; 1946 memcpy(&value, buf + offset, remaining); 1947 nbytes += remaining; 1948 1949 host->sg = sg = sg_next(sg); 1950 host->sg_len--; 1951 if (!sg || !host->sg_len) { 1952 atmci_writel(host, ATMCI_TDR, value); 1953 goto done; 1954 } 1955 1956 offset = 4 - remaining; 1957 buf = sg_virt(sg); 1958 memcpy((u8 *)&value + remaining, buf, offset); 1959 atmci_writel(host, ATMCI_TDR, value); 1960 nbytes += offset; 1961 } 1962 1963 status = atmci_readl(host, ATMCI_SR); 1964 if (status & ATMCI_DATA_ERROR_FLAGS) { 1965 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY 1966 | ATMCI_DATA_ERROR_FLAGS)); 1967 host->data_status = status; 1968 data->bytes_xfered += nbytes; 1969 return; 1970 } 1971 } while (status & ATMCI_TXRDY); 1972 1973 host->pio_offset = offset; 1974 data->bytes_xfered += nbytes; 1975 1976 return; 1977 1978 done: 1979 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); 1980 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1981 data->bytes_xfered += nbytes; 1982 smp_wmb(); 1983 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1984 } 1985 1986 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) 1987 { 1988 int i; 1989 1990 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1991 struct atmel_mci_slot *slot = host->slot[i]; 1992 if (slot && (status & slot->sdio_irq)) { 1993 mmc_signal_sdio_irq(slot->mmc); 1994 } 1995 } 1996 } 1997 1998 1999 static irqreturn_t atmci_interrupt(int irq, void *dev_id) 2000 { 2001 struct atmel_mci *host = dev_id; 2002 u32 status, mask, pending; 2003 unsigned int pass_count = 0; 2004 2005 do { 2006 status = atmci_readl(host, ATMCI_SR); 2007 mask = atmci_readl(host, ATMCI_IMR); 2008 pending = status & mask; 2009 if (!pending) 2010 break; 2011 2012 if (pending & ATMCI_DATA_ERROR_FLAGS) { 2013 dev_dbg(&host->pdev->dev, "IRQ: data error\n"); 2014 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS 2015 | ATMCI_RXRDY | ATMCI_TXRDY 2016 | ATMCI_ENDRX | ATMCI_ENDTX 2017 | ATMCI_RXBUFF | ATMCI_TXBUFE); 2018 2019 host->data_status = status; 2020 dev_dbg(&host->pdev->dev, "set pending data error\n"); 2021 smp_wmb(); 2022 atmci_set_pending(host, EVENT_DATA_ERROR); 2023 tasklet_schedule(&host->tasklet); 2024 } 2025 2026 if (pending & ATMCI_TXBUFE) { 2027 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n"); 2028 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); 2029 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2030 /* 2031 * We can receive this interruption before having configured 2032 * the second pdc buffer, so we need to reconfigure first and 2033 * second buffers again 2034 */ 2035 if (host->data_size) { 2036 atmci_pdc_set_both_buf(host, XFER_TRANSMIT); 2037 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2038 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); 2039 } else { 2040 atmci_pdc_complete(host); 2041 } 2042 } else if (pending & ATMCI_ENDTX) { 2043 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n"); 2044 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2045 2046 if (host->data_size) { 2047 atmci_pdc_set_single_buf(host, 2048 XFER_TRANSMIT, PDC_SECOND_BUF); 2049 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2050 } 2051 } 2052 2053 if (pending & ATMCI_RXBUFF) { 2054 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n"); 2055 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); 2056 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2057 /* 2058 * We can receive this interruption before having configured 2059 * the second pdc buffer, so we need to reconfigure first and 2060 * second buffers again 2061 */ 2062 if (host->data_size) { 2063 atmci_pdc_set_both_buf(host, XFER_RECEIVE); 2064 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2065 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); 2066 } else { 2067 atmci_pdc_complete(host); 2068 } 2069 } else if (pending & ATMCI_ENDRX) { 2070 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n"); 2071 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2072 2073 if (host->data_size) { 2074 atmci_pdc_set_single_buf(host, 2075 XFER_RECEIVE, PDC_SECOND_BUF); 2076 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2077 } 2078 } 2079 2080 /* 2081 * First mci IPs, so mainly the ones having pdc, have some 2082 * issues with the notbusy signal. You can't get it after 2083 * data transmission if you have not sent a stop command. 2084 * The appropriate workaround is to use the BLKE signal. 2085 */ 2086 if (pending & ATMCI_BLKE) { 2087 dev_dbg(&host->pdev->dev, "IRQ: blke\n"); 2088 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE); 2089 smp_wmb(); 2090 dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2091 atmci_set_pending(host, EVENT_NOTBUSY); 2092 tasklet_schedule(&host->tasklet); 2093 } 2094 2095 if (pending & ATMCI_NOTBUSY) { 2096 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n"); 2097 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY); 2098 smp_wmb(); 2099 dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2100 atmci_set_pending(host, EVENT_NOTBUSY); 2101 tasklet_schedule(&host->tasklet); 2102 } 2103 2104 if (pending & ATMCI_RXRDY) 2105 atmci_read_data_pio(host); 2106 if (pending & ATMCI_TXRDY) 2107 atmci_write_data_pio(host); 2108 2109 if (pending & ATMCI_CMDRDY) { 2110 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n"); 2111 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); 2112 host->cmd_status = status; 2113 smp_wmb(); 2114 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n"); 2115 atmci_set_pending(host, EVENT_CMD_RDY); 2116 tasklet_schedule(&host->tasklet); 2117 } 2118 2119 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 2120 atmci_sdio_interrupt(host, status); 2121 2122 } while (pass_count++ < 5); 2123 2124 return pass_count ? IRQ_HANDLED : IRQ_NONE; 2125 } 2126 2127 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) 2128 { 2129 struct atmel_mci_slot *slot = dev_id; 2130 2131 /* 2132 * Disable interrupts until the pin has stabilized and check 2133 * the state then. Use mod_timer() since we may be in the 2134 * middle of the timer routine when this interrupt triggers. 2135 */ 2136 disable_irq_nosync(irq); 2137 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); 2138 2139 return IRQ_HANDLED; 2140 } 2141 2142 static int __init atmci_init_slot(struct atmel_mci *host, 2143 struct mci_slot_pdata *slot_data, unsigned int id, 2144 u32 sdc_reg, u32 sdio_irq) 2145 { 2146 struct mmc_host *mmc; 2147 struct atmel_mci_slot *slot; 2148 2149 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 2150 if (!mmc) 2151 return -ENOMEM; 2152 2153 slot = mmc_priv(mmc); 2154 slot->mmc = mmc; 2155 slot->host = host; 2156 slot->detect_pin = slot_data->detect_pin; 2157 slot->wp_pin = slot_data->wp_pin; 2158 slot->detect_is_active_high = slot_data->detect_is_active_high; 2159 slot->sdc_reg = sdc_reg; 2160 slot->sdio_irq = sdio_irq; 2161 2162 dev_dbg(&mmc->class_dev, 2163 "slot[%u]: bus_width=%u, detect_pin=%d, " 2164 "detect_is_active_high=%s, wp_pin=%d\n", 2165 id, slot_data->bus_width, slot_data->detect_pin, 2166 slot_data->detect_is_active_high ? "true" : "false", 2167 slot_data->wp_pin); 2168 2169 mmc->ops = &atmci_ops; 2170 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); 2171 mmc->f_max = host->bus_hz / 2; 2172 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2173 if (sdio_irq) 2174 mmc->caps |= MMC_CAP_SDIO_IRQ; 2175 if (host->caps.has_highspeed) 2176 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2177 /* 2178 * Without the read/write proof capability, it is strongly suggested to 2179 * use only one bit for data to prevent fifo underruns and overruns 2180 * which will corrupt data. 2181 */ 2182 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) 2183 mmc->caps |= MMC_CAP_4_BIT_DATA; 2184 2185 if (atmci_get_version(host) < 0x200) { 2186 mmc->max_segs = 256; 2187 mmc->max_blk_size = 4095; 2188 mmc->max_blk_count = 256; 2189 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2190 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs; 2191 } else { 2192 mmc->max_segs = 64; 2193 mmc->max_req_size = 32768 * 512; 2194 mmc->max_blk_size = 32768; 2195 mmc->max_blk_count = 512; 2196 } 2197 2198 /* Assume card is present initially */ 2199 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 2200 if (gpio_is_valid(slot->detect_pin)) { 2201 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin, 2202 "mmc_detect")) { 2203 dev_dbg(&mmc->class_dev, "no detect pin available\n"); 2204 slot->detect_pin = -EBUSY; 2205 } else if (gpio_get_value(slot->detect_pin) ^ 2206 slot->detect_is_active_high) { 2207 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 2208 } 2209 } 2210 2211 if (!gpio_is_valid(slot->detect_pin)) { 2212 if (slot_data->non_removable) 2213 mmc->caps |= MMC_CAP_NONREMOVABLE; 2214 else 2215 mmc->caps |= MMC_CAP_NEEDS_POLL; 2216 } 2217 2218 if (gpio_is_valid(slot->wp_pin)) { 2219 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin, 2220 "mmc_wp")) { 2221 dev_dbg(&mmc->class_dev, "no WP pin available\n"); 2222 slot->wp_pin = -EBUSY; 2223 } 2224 } 2225 2226 host->slot[id] = slot; 2227 mmc_regulator_get_supply(mmc); 2228 mmc_add_host(mmc); 2229 2230 if (gpio_is_valid(slot->detect_pin)) { 2231 int ret; 2232 2233 setup_timer(&slot->detect_timer, atmci_detect_change, 2234 (unsigned long)slot); 2235 2236 ret = request_irq(gpio_to_irq(slot->detect_pin), 2237 atmci_detect_interrupt, 2238 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 2239 "mmc-detect", slot); 2240 if (ret) { 2241 dev_dbg(&mmc->class_dev, 2242 "could not request IRQ %d for detect pin\n", 2243 gpio_to_irq(slot->detect_pin)); 2244 slot->detect_pin = -EBUSY; 2245 } 2246 } 2247 2248 atmci_init_debugfs(slot); 2249 2250 return 0; 2251 } 2252 2253 static void atmci_cleanup_slot(struct atmel_mci_slot *slot, 2254 unsigned int id) 2255 { 2256 /* Debugfs stuff is cleaned up by mmc core */ 2257 2258 set_bit(ATMCI_SHUTDOWN, &slot->flags); 2259 smp_wmb(); 2260 2261 mmc_remove_host(slot->mmc); 2262 2263 if (gpio_is_valid(slot->detect_pin)) { 2264 int pin = slot->detect_pin; 2265 2266 free_irq(gpio_to_irq(pin), slot); 2267 del_timer_sync(&slot->detect_timer); 2268 } 2269 2270 slot->host->slot[id] = NULL; 2271 mmc_free_host(slot->mmc); 2272 } 2273 2274 static bool atmci_filter(struct dma_chan *chan, void *pdata) 2275 { 2276 struct mci_platform_data *sl_pdata = pdata; 2277 struct mci_dma_data *sl; 2278 2279 if (!sl_pdata) 2280 return false; 2281 2282 sl = sl_pdata->dma_slave; 2283 if (sl && find_slave_dev(sl) == chan->device->dev) { 2284 chan->private = slave_data_ptr(sl); 2285 return true; 2286 } else { 2287 return false; 2288 } 2289 } 2290 2291 static bool atmci_configure_dma(struct atmel_mci *host) 2292 { 2293 struct mci_platform_data *pdata; 2294 dma_cap_mask_t mask; 2295 2296 if (host == NULL) 2297 return false; 2298 2299 pdata = host->pdev->dev.platform_data; 2300 2301 dma_cap_zero(mask); 2302 dma_cap_set(DMA_SLAVE, mask); 2303 2304 host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata, 2305 &host->pdev->dev, "rxtx"); 2306 if (!host->dma.chan) { 2307 dev_warn(&host->pdev->dev, "no DMA channel available\n"); 2308 return false; 2309 } else { 2310 dev_info(&host->pdev->dev, 2311 "using %s for DMA transfers\n", 2312 dma_chan_name(host->dma.chan)); 2313 2314 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR; 2315 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2316 host->dma_conf.src_maxburst = 1; 2317 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR; 2318 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2319 host->dma_conf.dst_maxburst = 1; 2320 host->dma_conf.device_fc = false; 2321 return true; 2322 } 2323 } 2324 2325 /* 2326 * HSMCI (High Speed MCI) module is not fully compatible with MCI module. 2327 * HSMCI provides DMA support and a new config register but no more supports 2328 * PDC. 2329 */ 2330 static void __init atmci_get_cap(struct atmel_mci *host) 2331 { 2332 unsigned int version; 2333 2334 version = atmci_get_version(host); 2335 dev_info(&host->pdev->dev, 2336 "version: 0x%x\n", version); 2337 2338 host->caps.has_dma_conf_reg = 0; 2339 host->caps.has_pdc = ATMCI_PDC_CONNECTED; 2340 host->caps.has_cfg_reg = 0; 2341 host->caps.has_cstor_reg = 0; 2342 host->caps.has_highspeed = 0; 2343 host->caps.has_rwproof = 0; 2344 host->caps.has_odd_clk_div = 0; 2345 host->caps.has_bad_data_ordering = 1; 2346 host->caps.need_reset_after_xfer = 1; 2347 host->caps.need_blksz_mul_4 = 1; 2348 host->caps.need_notbusy_for_read_ops = 0; 2349 2350 /* keep only major version number */ 2351 switch (version & 0xf00) { 2352 case 0x600: 2353 case 0x500: 2354 host->caps.has_odd_clk_div = 1; 2355 case 0x400: 2356 case 0x300: 2357 host->caps.has_dma_conf_reg = 1; 2358 host->caps.has_pdc = 0; 2359 host->caps.has_cfg_reg = 1; 2360 host->caps.has_cstor_reg = 1; 2361 host->caps.has_highspeed = 1; 2362 case 0x200: 2363 host->caps.has_rwproof = 1; 2364 host->caps.need_blksz_mul_4 = 0; 2365 host->caps.need_notbusy_for_read_ops = 1; 2366 case 0x100: 2367 host->caps.has_bad_data_ordering = 0; 2368 host->caps.need_reset_after_xfer = 0; 2369 case 0x0: 2370 break; 2371 default: 2372 host->caps.has_pdc = 0; 2373 dev_warn(&host->pdev->dev, 2374 "Unmanaged mci version, set minimum capabilities\n"); 2375 break; 2376 } 2377 } 2378 2379 static int __init atmci_probe(struct platform_device *pdev) 2380 { 2381 struct mci_platform_data *pdata; 2382 struct atmel_mci *host; 2383 struct resource *regs; 2384 unsigned int nr_slots; 2385 int irq; 2386 int ret, i; 2387 2388 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2389 if (!regs) 2390 return -ENXIO; 2391 pdata = pdev->dev.platform_data; 2392 if (!pdata) { 2393 pdata = atmci_of_init(pdev); 2394 if (IS_ERR(pdata)) { 2395 dev_err(&pdev->dev, "platform data not available\n"); 2396 return PTR_ERR(pdata); 2397 } 2398 } 2399 2400 irq = platform_get_irq(pdev, 0); 2401 if (irq < 0) 2402 return irq; 2403 2404 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 2405 if (!host) 2406 return -ENOMEM; 2407 2408 host->pdev = pdev; 2409 spin_lock_init(&host->lock); 2410 INIT_LIST_HEAD(&host->queue); 2411 2412 host->mck = devm_clk_get(&pdev->dev, "mci_clk"); 2413 if (IS_ERR(host->mck)) 2414 return PTR_ERR(host->mck); 2415 2416 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); 2417 if (!host->regs) 2418 return -ENOMEM; 2419 2420 ret = clk_prepare_enable(host->mck); 2421 if (ret) 2422 return ret; 2423 2424 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 2425 host->bus_hz = clk_get_rate(host->mck); 2426 2427 host->mapbase = regs->start; 2428 2429 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); 2430 2431 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); 2432 if (ret) { 2433 clk_disable_unprepare(host->mck); 2434 return ret; 2435 } 2436 2437 /* Get MCI capabilities and set operations according to it */ 2438 atmci_get_cap(host); 2439 if (atmci_configure_dma(host)) { 2440 host->prepare_data = &atmci_prepare_data_dma; 2441 host->submit_data = &atmci_submit_data_dma; 2442 host->stop_transfer = &atmci_stop_transfer_dma; 2443 } else if (host->caps.has_pdc) { 2444 dev_info(&pdev->dev, "using PDC\n"); 2445 host->prepare_data = &atmci_prepare_data_pdc; 2446 host->submit_data = &atmci_submit_data_pdc; 2447 host->stop_transfer = &atmci_stop_transfer_pdc; 2448 } else { 2449 dev_info(&pdev->dev, "using PIO\n"); 2450 host->prepare_data = &atmci_prepare_data; 2451 host->submit_data = &atmci_submit_data; 2452 host->stop_transfer = &atmci_stop_transfer; 2453 } 2454 2455 platform_set_drvdata(pdev, host); 2456 2457 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host); 2458 2459 pm_runtime_get_noresume(&pdev->dev); 2460 pm_runtime_set_active(&pdev->dev); 2461 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY); 2462 pm_runtime_use_autosuspend(&pdev->dev); 2463 pm_runtime_enable(&pdev->dev); 2464 2465 /* We need at least one slot to succeed */ 2466 nr_slots = 0; 2467 ret = -ENODEV; 2468 if (pdata->slot[0].bus_width) { 2469 ret = atmci_init_slot(host, &pdata->slot[0], 2470 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); 2471 if (!ret) { 2472 nr_slots++; 2473 host->buf_size = host->slot[0]->mmc->max_req_size; 2474 } 2475 } 2476 if (pdata->slot[1].bus_width) { 2477 ret = atmci_init_slot(host, &pdata->slot[1], 2478 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); 2479 if (!ret) { 2480 nr_slots++; 2481 if (host->slot[1]->mmc->max_req_size > host->buf_size) 2482 host->buf_size = 2483 host->slot[1]->mmc->max_req_size; 2484 } 2485 } 2486 2487 if (!nr_slots) { 2488 dev_err(&pdev->dev, "init failed: no slot defined\n"); 2489 goto err_init_slot; 2490 } 2491 2492 if (!host->caps.has_rwproof) { 2493 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size, 2494 &host->buf_phys_addr, 2495 GFP_KERNEL); 2496 if (!host->buffer) { 2497 ret = -ENOMEM; 2498 dev_err(&pdev->dev, "buffer allocation failed\n"); 2499 goto err_dma_alloc; 2500 } 2501 } 2502 2503 dev_info(&pdev->dev, 2504 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2505 host->mapbase, irq, nr_slots); 2506 2507 pm_runtime_mark_last_busy(&host->pdev->dev); 2508 pm_runtime_put_autosuspend(&pdev->dev); 2509 2510 return 0; 2511 2512 err_dma_alloc: 2513 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2514 if (host->slot[i]) 2515 atmci_cleanup_slot(host->slot[i], i); 2516 } 2517 err_init_slot: 2518 clk_disable_unprepare(host->mck); 2519 2520 pm_runtime_disable(&pdev->dev); 2521 pm_runtime_put_noidle(&pdev->dev); 2522 2523 del_timer_sync(&host->timer); 2524 if (host->dma.chan) 2525 dma_release_channel(host->dma.chan); 2526 free_irq(irq, host); 2527 return ret; 2528 } 2529 2530 static int __exit atmci_remove(struct platform_device *pdev) 2531 { 2532 struct atmel_mci *host = platform_get_drvdata(pdev); 2533 unsigned int i; 2534 2535 pm_runtime_get_sync(&pdev->dev); 2536 2537 if (host->buffer) 2538 dma_free_coherent(&pdev->dev, host->buf_size, 2539 host->buffer, host->buf_phys_addr); 2540 2541 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2542 if (host->slot[i]) 2543 atmci_cleanup_slot(host->slot[i], i); 2544 } 2545 2546 atmci_writel(host, ATMCI_IDR, ~0UL); 2547 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 2548 atmci_readl(host, ATMCI_SR); 2549 2550 del_timer_sync(&host->timer); 2551 if (host->dma.chan) 2552 dma_release_channel(host->dma.chan); 2553 2554 free_irq(platform_get_irq(pdev, 0), host); 2555 2556 clk_disable_unprepare(host->mck); 2557 2558 pm_runtime_disable(&pdev->dev); 2559 pm_runtime_put_noidle(&pdev->dev); 2560 2561 return 0; 2562 } 2563 2564 #ifdef CONFIG_PM 2565 static int atmci_runtime_suspend(struct device *dev) 2566 { 2567 struct atmel_mci *host = dev_get_drvdata(dev); 2568 2569 clk_disable_unprepare(host->mck); 2570 2571 return 0; 2572 } 2573 2574 static int atmci_runtime_resume(struct device *dev) 2575 { 2576 struct atmel_mci *host = dev_get_drvdata(dev); 2577 2578 return clk_prepare_enable(host->mck); 2579 } 2580 #endif 2581 2582 static const struct dev_pm_ops atmci_dev_pm_ops = { 2583 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2584 pm_runtime_force_resume) 2585 SET_PM_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL) 2586 }; 2587 2588 static struct platform_driver atmci_driver = { 2589 .remove = __exit_p(atmci_remove), 2590 .driver = { 2591 .name = "atmel_mci", 2592 .of_match_table = of_match_ptr(atmci_dt_ids), 2593 .pm = &atmci_dev_pm_ops, 2594 }, 2595 }; 2596 2597 static int __init atmci_init(void) 2598 { 2599 return platform_driver_probe(&atmci_driver, atmci_probe); 2600 } 2601 2602 static void __exit atmci_exit(void) 2603 { 2604 platform_driver_unregister(&atmci_driver); 2605 } 2606 2607 late_initcall(atmci_init); /* try to load after dma driver when built-in */ 2608 module_exit(atmci_exit); 2609 2610 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); 2611 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2612 MODULE_LICENSE("GPL v2"); 2613