1 /* 2 * Atmel MultiMedia Card Interface driver 3 * 4 * Copyright (C) 2004-2008 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/blkdev.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/device.h> 14 #include <linux/dmaengine.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_gpio.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/seq_file.h> 28 #include <linux/slab.h> 29 #include <linux/stat.h> 30 #include <linux/types.h> 31 #include <linux/platform_data/atmel.h> 32 33 #include <linux/mmc/host.h> 34 #include <linux/mmc/sdio.h> 35 36 #include <mach/atmel-mci.h> 37 #include <linux/atmel-mci.h> 38 #include <linux/atmel_pdc.h> 39 40 #include <asm/io.h> 41 #include <asm/unaligned.h> 42 43 #include "atmel-mci-regs.h" 44 45 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) 46 #define ATMCI_DMA_THRESHOLD 16 47 48 enum { 49 EVENT_CMD_RDY = 0, 50 EVENT_XFER_COMPLETE, 51 EVENT_NOTBUSY, 52 EVENT_DATA_ERROR, 53 }; 54 55 enum atmel_mci_state { 56 STATE_IDLE = 0, 57 STATE_SENDING_CMD, 58 STATE_DATA_XFER, 59 STATE_WAITING_NOTBUSY, 60 STATE_SENDING_STOP, 61 STATE_END_REQUEST, 62 }; 63 64 enum atmci_xfer_dir { 65 XFER_RECEIVE = 0, 66 XFER_TRANSMIT, 67 }; 68 69 enum atmci_pdc_buf { 70 PDC_FIRST_BUF = 0, 71 PDC_SECOND_BUF, 72 }; 73 74 struct atmel_mci_caps { 75 bool has_dma_conf_reg; 76 bool has_pdc; 77 bool has_cfg_reg; 78 bool has_cstor_reg; 79 bool has_highspeed; 80 bool has_rwproof; 81 bool has_odd_clk_div; 82 bool has_bad_data_ordering; 83 bool need_reset_after_xfer; 84 bool need_blksz_mul_4; 85 bool need_notbusy_for_read_ops; 86 }; 87 88 struct atmel_mci_dma { 89 struct dma_chan *chan; 90 struct dma_async_tx_descriptor *data_desc; 91 }; 92 93 /** 94 * struct atmel_mci - MMC controller state shared between all slots 95 * @lock: Spinlock protecting the queue and associated data. 96 * @regs: Pointer to MMIO registers. 97 * @sg: Scatterlist entry currently being processed by PIO or PDC code. 98 * @pio_offset: Offset into the current scatterlist entry. 99 * @buffer: Buffer used if we don't have the r/w proof capability. We 100 * don't have the time to switch pdc buffers so we have to use only 101 * one buffer for the full transaction. 102 * @buf_size: size of the buffer. 103 * @phys_buf_addr: buffer address needed for pdc. 104 * @cur_slot: The slot which is currently using the controller. 105 * @mrq: The request currently being processed on @cur_slot, 106 * or NULL if the controller is idle. 107 * @cmd: The command currently being sent to the card, or NULL. 108 * @data: The data currently being transferred, or NULL if no data 109 * transfer is in progress. 110 * @data_size: just data->blocks * data->blksz. 111 * @dma: DMA client state. 112 * @data_chan: DMA channel being used for the current data transfer. 113 * @cmd_status: Snapshot of SR taken upon completion of the current 114 * command. Only valid when EVENT_CMD_COMPLETE is pending. 115 * @data_status: Snapshot of SR taken upon completion of the current 116 * data transfer. Only valid when EVENT_DATA_COMPLETE or 117 * EVENT_DATA_ERROR is pending. 118 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 119 * to be sent. 120 * @tasklet: Tasklet running the request state machine. 121 * @pending_events: Bitmask of events flagged by the interrupt handler 122 * to be processed by the tasklet. 123 * @completed_events: Bitmask of events which the state machine has 124 * processed. 125 * @state: Tasklet state. 126 * @queue: List of slots waiting for access to the controller. 127 * @need_clock_update: Update the clock rate before the next request. 128 * @need_reset: Reset controller before next request. 129 * @timer: Timer to balance the data timeout error flag which cannot rise. 130 * @mode_reg: Value of the MR register. 131 * @cfg_reg: Value of the CFG register. 132 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 133 * rate and timeout calculations. 134 * @mapbase: Physical address of the MMIO registers. 135 * @mck: The peripheral bus clock hooked up to the MMC controller. 136 * @pdev: Platform device associated with the MMC controller. 137 * @slot: Slots sharing this MMC controller. 138 * @caps: MCI capabilities depending on MCI version. 139 * @prepare_data: function to setup MCI before data transfer which 140 * depends on MCI capabilities. 141 * @submit_data: function to start data transfer which depends on MCI 142 * capabilities. 143 * @stop_transfer: function to stop data transfer which depends on MCI 144 * capabilities. 145 * 146 * Locking 147 * ======= 148 * 149 * @lock is a softirq-safe spinlock protecting @queue as well as 150 * @cur_slot, @mrq and @state. These must always be updated 151 * at the same time while holding @lock. 152 * 153 * @lock also protects mode_reg and need_clock_update since these are 154 * used to synchronize mode register updates with the queue 155 * processing. 156 * 157 * The @mrq field of struct atmel_mci_slot is also protected by @lock, 158 * and must always be written at the same time as the slot is added to 159 * @queue. 160 * 161 * @pending_events and @completed_events are accessed using atomic bit 162 * operations, so they don't need any locking. 163 * 164 * None of the fields touched by the interrupt handler need any 165 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 166 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 167 * interrupts must be disabled and @data_status updated with a 168 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 169 * CMDRDY interrupt must be disabled and @cmd_status updated with a 170 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 171 * bytes_xfered field of @data must be written. This is ensured by 172 * using barriers. 173 */ 174 struct atmel_mci { 175 spinlock_t lock; 176 void __iomem *regs; 177 178 struct scatterlist *sg; 179 unsigned int sg_len; 180 unsigned int pio_offset; 181 unsigned int *buffer; 182 unsigned int buf_size; 183 dma_addr_t buf_phys_addr; 184 185 struct atmel_mci_slot *cur_slot; 186 struct mmc_request *mrq; 187 struct mmc_command *cmd; 188 struct mmc_data *data; 189 unsigned int data_size; 190 191 struct atmel_mci_dma dma; 192 struct dma_chan *data_chan; 193 struct dma_slave_config dma_conf; 194 195 u32 cmd_status; 196 u32 data_status; 197 u32 stop_cmdr; 198 199 struct tasklet_struct tasklet; 200 unsigned long pending_events; 201 unsigned long completed_events; 202 enum atmel_mci_state state; 203 struct list_head queue; 204 205 bool need_clock_update; 206 bool need_reset; 207 struct timer_list timer; 208 u32 mode_reg; 209 u32 cfg_reg; 210 unsigned long bus_hz; 211 unsigned long mapbase; 212 struct clk *mck; 213 struct platform_device *pdev; 214 215 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; 216 217 struct atmel_mci_caps caps; 218 219 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); 220 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); 221 void (*stop_transfer)(struct atmel_mci *host); 222 }; 223 224 /** 225 * struct atmel_mci_slot - MMC slot state 226 * @mmc: The mmc_host representing this slot. 227 * @host: The MMC controller this slot is using. 228 * @sdc_reg: Value of SDCR to be written before using this slot. 229 * @sdio_irq: SDIO irq mask for this slot. 230 * @mrq: mmc_request currently being processed or waiting to be 231 * processed, or NULL when the slot is idle. 232 * @queue_node: List node for placing this node in the @queue list of 233 * &struct atmel_mci. 234 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 235 * @flags: Random state bits associated with the slot. 236 * @detect_pin: GPIO pin used for card detection, or negative if not 237 * available. 238 * @wp_pin: GPIO pin used for card write protect sending, or negative 239 * if not available. 240 * @detect_is_active_high: The state of the detect pin when it is active. 241 * @detect_timer: Timer used for debouncing @detect_pin interrupts. 242 */ 243 struct atmel_mci_slot { 244 struct mmc_host *mmc; 245 struct atmel_mci *host; 246 247 u32 sdc_reg; 248 u32 sdio_irq; 249 250 struct mmc_request *mrq; 251 struct list_head queue_node; 252 253 unsigned int clock; 254 unsigned long flags; 255 #define ATMCI_CARD_PRESENT 0 256 #define ATMCI_CARD_NEED_INIT 1 257 #define ATMCI_SHUTDOWN 2 258 259 int detect_pin; 260 int wp_pin; 261 bool detect_is_active_high; 262 263 struct timer_list detect_timer; 264 }; 265 266 #define atmci_test_and_clear_pending(host, event) \ 267 test_and_clear_bit(event, &host->pending_events) 268 #define atmci_set_completed(host, event) \ 269 set_bit(event, &host->completed_events) 270 #define atmci_set_pending(host, event) \ 271 set_bit(event, &host->pending_events) 272 273 /* 274 * The debugfs stuff below is mostly optimized away when 275 * CONFIG_DEBUG_FS is not set. 276 */ 277 static int atmci_req_show(struct seq_file *s, void *v) 278 { 279 struct atmel_mci_slot *slot = s->private; 280 struct mmc_request *mrq; 281 struct mmc_command *cmd; 282 struct mmc_command *stop; 283 struct mmc_data *data; 284 285 /* Make sure we get a consistent snapshot */ 286 spin_lock_bh(&slot->host->lock); 287 mrq = slot->mrq; 288 289 if (mrq) { 290 cmd = mrq->cmd; 291 data = mrq->data; 292 stop = mrq->stop; 293 294 if (cmd) 295 seq_printf(s, 296 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 297 cmd->opcode, cmd->arg, cmd->flags, 298 cmd->resp[0], cmd->resp[1], cmd->resp[2], 299 cmd->resp[3], cmd->error); 300 if (data) 301 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 302 data->bytes_xfered, data->blocks, 303 data->blksz, data->flags, data->error); 304 if (stop) 305 seq_printf(s, 306 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 307 stop->opcode, stop->arg, stop->flags, 308 stop->resp[0], stop->resp[1], stop->resp[2], 309 stop->resp[3], stop->error); 310 } 311 312 spin_unlock_bh(&slot->host->lock); 313 314 return 0; 315 } 316 317 static int atmci_req_open(struct inode *inode, struct file *file) 318 { 319 return single_open(file, atmci_req_show, inode->i_private); 320 } 321 322 static const struct file_operations atmci_req_fops = { 323 .owner = THIS_MODULE, 324 .open = atmci_req_open, 325 .read = seq_read, 326 .llseek = seq_lseek, 327 .release = single_release, 328 }; 329 330 static void atmci_show_status_reg(struct seq_file *s, 331 const char *regname, u32 value) 332 { 333 static const char *sr_bit[] = { 334 [0] = "CMDRDY", 335 [1] = "RXRDY", 336 [2] = "TXRDY", 337 [3] = "BLKE", 338 [4] = "DTIP", 339 [5] = "NOTBUSY", 340 [6] = "ENDRX", 341 [7] = "ENDTX", 342 [8] = "SDIOIRQA", 343 [9] = "SDIOIRQB", 344 [12] = "SDIOWAIT", 345 [14] = "RXBUFF", 346 [15] = "TXBUFE", 347 [16] = "RINDE", 348 [17] = "RDIRE", 349 [18] = "RCRCE", 350 [19] = "RENDE", 351 [20] = "RTOE", 352 [21] = "DCRCE", 353 [22] = "DTOE", 354 [23] = "CSTOE", 355 [24] = "BLKOVRE", 356 [25] = "DMADONE", 357 [26] = "FIFOEMPTY", 358 [27] = "XFRDONE", 359 [30] = "OVRE", 360 [31] = "UNRE", 361 }; 362 unsigned int i; 363 364 seq_printf(s, "%s:\t0x%08x", regname, value); 365 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { 366 if (value & (1 << i)) { 367 if (sr_bit[i]) 368 seq_printf(s, " %s", sr_bit[i]); 369 else 370 seq_puts(s, " UNKNOWN"); 371 } 372 } 373 seq_putc(s, '\n'); 374 } 375 376 static int atmci_regs_show(struct seq_file *s, void *v) 377 { 378 struct atmel_mci *host = s->private; 379 u32 *buf; 380 int ret = 0; 381 382 383 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); 384 if (!buf) 385 return -ENOMEM; 386 387 /* 388 * Grab a more or less consistent snapshot. Note that we're 389 * not disabling interrupts, so IMR and SR may not be 390 * consistent. 391 */ 392 ret = clk_prepare_enable(host->mck); 393 if (ret) 394 goto out; 395 396 spin_lock_bh(&host->lock); 397 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); 398 spin_unlock_bh(&host->lock); 399 400 clk_disable_unprepare(host->mck); 401 402 seq_printf(s, "MR:\t0x%08x%s%s ", 403 buf[ATMCI_MR / 4], 404 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", 405 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : ""); 406 if (host->caps.has_odd_clk_div) 407 seq_printf(s, "{CLKDIV,CLKODD}=%u\n", 408 ((buf[ATMCI_MR / 4] & 0xff) << 1) 409 | ((buf[ATMCI_MR / 4] >> 16) & 1)); 410 else 411 seq_printf(s, "CLKDIV=%u\n", 412 (buf[ATMCI_MR / 4] & 0xff)); 413 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); 414 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); 415 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); 416 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", 417 buf[ATMCI_BLKR / 4], 418 buf[ATMCI_BLKR / 4] & 0xffff, 419 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); 420 if (host->caps.has_cstor_reg) 421 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); 422 423 /* Don't read RSPR and RDR; it will consume the data there */ 424 425 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); 426 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); 427 428 if (host->caps.has_dma_conf_reg) { 429 u32 val; 430 431 val = buf[ATMCI_DMA / 4]; 432 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", 433 val, val & 3, 434 ((val >> 4) & 3) ? 435 1 << (((val >> 4) & 3) + 1) : 1, 436 val & ATMCI_DMAEN ? " DMAEN" : ""); 437 } 438 if (host->caps.has_cfg_reg) { 439 u32 val; 440 441 val = buf[ATMCI_CFG / 4]; 442 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", 443 val, 444 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", 445 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", 446 val & ATMCI_CFG_HSMODE ? " HSMODE" : "", 447 val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); 448 } 449 450 out: 451 kfree(buf); 452 453 return ret; 454 } 455 456 static int atmci_regs_open(struct inode *inode, struct file *file) 457 { 458 return single_open(file, atmci_regs_show, inode->i_private); 459 } 460 461 static const struct file_operations atmci_regs_fops = { 462 .owner = THIS_MODULE, 463 .open = atmci_regs_open, 464 .read = seq_read, 465 .llseek = seq_lseek, 466 .release = single_release, 467 }; 468 469 static void atmci_init_debugfs(struct atmel_mci_slot *slot) 470 { 471 struct mmc_host *mmc = slot->mmc; 472 struct atmel_mci *host = slot->host; 473 struct dentry *root; 474 struct dentry *node; 475 476 root = mmc->debugfs_root; 477 if (!root) 478 return; 479 480 node = debugfs_create_file("regs", S_IRUSR, root, host, 481 &atmci_regs_fops); 482 if (IS_ERR(node)) 483 return; 484 if (!node) 485 goto err; 486 487 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); 488 if (!node) 489 goto err; 490 491 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 492 if (!node) 493 goto err; 494 495 node = debugfs_create_x32("pending_events", S_IRUSR, root, 496 (u32 *)&host->pending_events); 497 if (!node) 498 goto err; 499 500 node = debugfs_create_x32("completed_events", S_IRUSR, root, 501 (u32 *)&host->completed_events); 502 if (!node) 503 goto err; 504 505 return; 506 507 err: 508 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 509 } 510 511 #if defined(CONFIG_OF) 512 static const struct of_device_id atmci_dt_ids[] = { 513 { .compatible = "atmel,hsmci" }, 514 { /* sentinel */ } 515 }; 516 517 MODULE_DEVICE_TABLE(of, atmci_dt_ids); 518 519 static struct mci_platform_data* 520 atmci_of_init(struct platform_device *pdev) 521 { 522 struct device_node *np = pdev->dev.of_node; 523 struct device_node *cnp; 524 struct mci_platform_data *pdata; 525 u32 slot_id; 526 527 if (!np) { 528 dev_err(&pdev->dev, "device node not found\n"); 529 return ERR_PTR(-EINVAL); 530 } 531 532 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 533 if (!pdata) { 534 dev_err(&pdev->dev, "could not allocate memory for pdata\n"); 535 return ERR_PTR(-ENOMEM); 536 } 537 538 for_each_child_of_node(np, cnp) { 539 if (of_property_read_u32(cnp, "reg", &slot_id)) { 540 dev_warn(&pdev->dev, "reg property is missing for %s\n", 541 cnp->full_name); 542 continue; 543 } 544 545 if (slot_id >= ATMCI_MAX_NR_SLOTS) { 546 dev_warn(&pdev->dev, "can't have more than %d slots\n", 547 ATMCI_MAX_NR_SLOTS); 548 break; 549 } 550 551 if (of_property_read_u32(cnp, "bus-width", 552 &pdata->slot[slot_id].bus_width)) 553 pdata->slot[slot_id].bus_width = 1; 554 555 pdata->slot[slot_id].detect_pin = 556 of_get_named_gpio(cnp, "cd-gpios", 0); 557 558 pdata->slot[slot_id].detect_is_active_high = 559 of_property_read_bool(cnp, "cd-inverted"); 560 561 pdata->slot[slot_id].wp_pin = 562 of_get_named_gpio(cnp, "wp-gpios", 0); 563 } 564 565 return pdata; 566 } 567 #else /* CONFIG_OF */ 568 static inline struct mci_platform_data* 569 atmci_of_init(struct platform_device *dev) 570 { 571 return ERR_PTR(-EINVAL); 572 } 573 #endif 574 575 static inline unsigned int atmci_get_version(struct atmel_mci *host) 576 { 577 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; 578 } 579 580 static void atmci_timeout_timer(unsigned long data) 581 { 582 struct atmel_mci *host; 583 584 host = (struct atmel_mci *)data; 585 586 dev_dbg(&host->pdev->dev, "software timeout\n"); 587 588 if (host->mrq->cmd->data) { 589 host->mrq->cmd->data->error = -ETIMEDOUT; 590 host->data = NULL; 591 /* 592 * With some SDIO modules, sometimes DMA transfer hangs. If 593 * stop_transfer() is not called then the DMA request is not 594 * removed, following ones are queued and never computed. 595 */ 596 if (host->state == STATE_DATA_XFER) 597 host->stop_transfer(host); 598 } else { 599 host->mrq->cmd->error = -ETIMEDOUT; 600 host->cmd = NULL; 601 } 602 host->need_reset = 1; 603 host->state = STATE_END_REQUEST; 604 smp_wmb(); 605 tasklet_schedule(&host->tasklet); 606 } 607 608 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, 609 unsigned int ns) 610 { 611 /* 612 * It is easier here to use us instead of ns for the timeout, 613 * it prevents from overflows during calculation. 614 */ 615 unsigned int us = DIV_ROUND_UP(ns, 1000); 616 617 /* Maximum clock frequency is host->bus_hz/2 */ 618 return us * (DIV_ROUND_UP(host->bus_hz, 2000000)); 619 } 620 621 static void atmci_set_timeout(struct atmel_mci *host, 622 struct atmel_mci_slot *slot, struct mmc_data *data) 623 { 624 static unsigned dtomul_to_shift[] = { 625 0, 4, 7, 8, 10, 12, 16, 20 626 }; 627 unsigned timeout; 628 unsigned dtocyc; 629 unsigned dtomul; 630 631 timeout = atmci_ns_to_clocks(host, data->timeout_ns) 632 + data->timeout_clks; 633 634 for (dtomul = 0; dtomul < 8; dtomul++) { 635 unsigned shift = dtomul_to_shift[dtomul]; 636 dtocyc = (timeout + (1 << shift) - 1) >> shift; 637 if (dtocyc < 15) 638 break; 639 } 640 641 if (dtomul >= 8) { 642 dtomul = 7; 643 dtocyc = 15; 644 } 645 646 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 647 dtocyc << dtomul_to_shift[dtomul]); 648 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); 649 } 650 651 /* 652 * Return mask with command flags to be enabled for this command. 653 */ 654 static u32 atmci_prepare_command(struct mmc_host *mmc, 655 struct mmc_command *cmd) 656 { 657 struct mmc_data *data; 658 u32 cmdr; 659 660 cmd->error = -EINPROGRESS; 661 662 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); 663 664 if (cmd->flags & MMC_RSP_PRESENT) { 665 if (cmd->flags & MMC_RSP_136) 666 cmdr |= ATMCI_CMDR_RSPTYP_136BIT; 667 else 668 cmdr |= ATMCI_CMDR_RSPTYP_48BIT; 669 } 670 671 /* 672 * This should really be MAXLAT_5 for CMD2 and ACMD41, but 673 * it's too difficult to determine whether this is an ACMD or 674 * not. Better make it 64. 675 */ 676 cmdr |= ATMCI_CMDR_MAXLAT_64CYC; 677 678 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) 679 cmdr |= ATMCI_CMDR_OPDCMD; 680 681 data = cmd->data; 682 if (data) { 683 cmdr |= ATMCI_CMDR_START_XFER; 684 685 if (cmd->opcode == SD_IO_RW_EXTENDED) { 686 cmdr |= ATMCI_CMDR_SDIO_BLOCK; 687 } else { 688 if (data->flags & MMC_DATA_STREAM) 689 cmdr |= ATMCI_CMDR_STREAM; 690 else if (data->blocks > 1) 691 cmdr |= ATMCI_CMDR_MULTI_BLOCK; 692 else 693 cmdr |= ATMCI_CMDR_BLOCK; 694 } 695 696 if (data->flags & MMC_DATA_READ) 697 cmdr |= ATMCI_CMDR_TRDIR_READ; 698 } 699 700 return cmdr; 701 } 702 703 static void atmci_send_command(struct atmel_mci *host, 704 struct mmc_command *cmd, u32 cmd_flags) 705 { 706 WARN_ON(host->cmd); 707 host->cmd = cmd; 708 709 dev_vdbg(&host->pdev->dev, 710 "start command: ARGR=0x%08x CMDR=0x%08x\n", 711 cmd->arg, cmd_flags); 712 713 atmci_writel(host, ATMCI_ARGR, cmd->arg); 714 atmci_writel(host, ATMCI_CMDR, cmd_flags); 715 } 716 717 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 718 { 719 dev_dbg(&host->pdev->dev, "send stop command\n"); 720 atmci_send_command(host, data->stop, host->stop_cmdr); 721 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 722 } 723 724 /* 725 * Configure given PDC buffer taking care of alignement issues. 726 * Update host->data_size and host->sg. 727 */ 728 static void atmci_pdc_set_single_buf(struct atmel_mci *host, 729 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) 730 { 731 u32 pointer_reg, counter_reg; 732 unsigned int buf_size; 733 734 if (dir == XFER_RECEIVE) { 735 pointer_reg = ATMEL_PDC_RPR; 736 counter_reg = ATMEL_PDC_RCR; 737 } else { 738 pointer_reg = ATMEL_PDC_TPR; 739 counter_reg = ATMEL_PDC_TCR; 740 } 741 742 if (buf_nb == PDC_SECOND_BUF) { 743 pointer_reg += ATMEL_PDC_SCND_BUF_OFF; 744 counter_reg += ATMEL_PDC_SCND_BUF_OFF; 745 } 746 747 if (!host->caps.has_rwproof) { 748 buf_size = host->buf_size; 749 atmci_writel(host, pointer_reg, host->buf_phys_addr); 750 } else { 751 buf_size = sg_dma_len(host->sg); 752 atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); 753 } 754 755 if (host->data_size <= buf_size) { 756 if (host->data_size & 0x3) { 757 /* If size is different from modulo 4, transfer bytes */ 758 atmci_writel(host, counter_reg, host->data_size); 759 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); 760 } else { 761 /* Else transfer 32-bits words */ 762 atmci_writel(host, counter_reg, host->data_size / 4); 763 } 764 host->data_size = 0; 765 } else { 766 /* We assume the size of a page is 32-bits aligned */ 767 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); 768 host->data_size -= sg_dma_len(host->sg); 769 if (host->data_size) 770 host->sg = sg_next(host->sg); 771 } 772 } 773 774 /* 775 * Configure PDC buffer according to the data size ie configuring one or two 776 * buffers. Don't use this function if you want to configure only the second 777 * buffer. In this case, use atmci_pdc_set_single_buf. 778 */ 779 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) 780 { 781 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); 782 if (host->data_size) 783 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); 784 } 785 786 /* 787 * Unmap sg lists, called when transfer is finished. 788 */ 789 static void atmci_pdc_cleanup(struct atmel_mci *host) 790 { 791 struct mmc_data *data = host->data; 792 793 if (data) 794 dma_unmap_sg(&host->pdev->dev, 795 data->sg, data->sg_len, 796 ((data->flags & MMC_DATA_WRITE) 797 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 798 } 799 800 /* 801 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after 802 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY 803 * interrupt needed for both transfer directions. 804 */ 805 static void atmci_pdc_complete(struct atmel_mci *host) 806 { 807 int transfer_size = host->data->blocks * host->data->blksz; 808 int i; 809 810 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 811 812 if ((!host->caps.has_rwproof) 813 && (host->data->flags & MMC_DATA_READ)) { 814 if (host->caps.has_bad_data_ordering) 815 for (i = 0; i < transfer_size; i++) 816 host->buffer[i] = swab32(host->buffer[i]); 817 sg_copy_from_buffer(host->data->sg, host->data->sg_len, 818 host->buffer, transfer_size); 819 } 820 821 atmci_pdc_cleanup(host); 822 823 /* 824 * If the card was removed, data will be NULL. No point trying 825 * to send the stop command or waiting for NBUSY in this case. 826 */ 827 if (host->data) { 828 dev_dbg(&host->pdev->dev, 829 "(%s) set pending xfer complete\n", __func__); 830 atmci_set_pending(host, EVENT_XFER_COMPLETE); 831 tasklet_schedule(&host->tasklet); 832 } 833 } 834 835 static void atmci_dma_cleanup(struct atmel_mci *host) 836 { 837 struct mmc_data *data = host->data; 838 839 if (data) 840 dma_unmap_sg(host->dma.chan->device->dev, 841 data->sg, data->sg_len, 842 ((data->flags & MMC_DATA_WRITE) 843 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 844 } 845 846 /* 847 * This function is called by the DMA driver from tasklet context. 848 */ 849 static void atmci_dma_complete(void *arg) 850 { 851 struct atmel_mci *host = arg; 852 struct mmc_data *data = host->data; 853 854 dev_vdbg(&host->pdev->dev, "DMA complete\n"); 855 856 if (host->caps.has_dma_conf_reg) 857 /* Disable DMA hardware handshaking on MCI */ 858 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); 859 860 atmci_dma_cleanup(host); 861 862 /* 863 * If the card was removed, data will be NULL. No point trying 864 * to send the stop command or waiting for NBUSY in this case. 865 */ 866 if (data) { 867 dev_dbg(&host->pdev->dev, 868 "(%s) set pending xfer complete\n", __func__); 869 atmci_set_pending(host, EVENT_XFER_COMPLETE); 870 tasklet_schedule(&host->tasklet); 871 872 /* 873 * Regardless of what the documentation says, we have 874 * to wait for NOTBUSY even after block read 875 * operations. 876 * 877 * When the DMA transfer is complete, the controller 878 * may still be reading the CRC from the card, i.e. 879 * the data transfer is still in progress and we 880 * haven't seen all the potential error bits yet. 881 * 882 * The interrupt handler will schedule a different 883 * tasklet to finish things up when the data transfer 884 * is completely done. 885 * 886 * We may not complete the mmc request here anyway 887 * because the mmc layer may call back and cause us to 888 * violate the "don't submit new operations from the 889 * completion callback" rule of the dma engine 890 * framework. 891 */ 892 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 893 } 894 } 895 896 /* 897 * Returns a mask of interrupt flags to be enabled after the whole 898 * request has been prepared. 899 */ 900 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) 901 { 902 u32 iflags; 903 904 data->error = -EINPROGRESS; 905 906 host->sg = data->sg; 907 host->sg_len = data->sg_len; 908 host->data = data; 909 host->data_chan = NULL; 910 911 iflags = ATMCI_DATA_ERROR_FLAGS; 912 913 /* 914 * Errata: MMC data write operation with less than 12 915 * bytes is impossible. 916 * 917 * Errata: MCI Transmit Data Register (TDR) FIFO 918 * corruption when length is not multiple of 4. 919 */ 920 if (data->blocks * data->blksz < 12 921 || (data->blocks * data->blksz) & 3) 922 host->need_reset = true; 923 924 host->pio_offset = 0; 925 if (data->flags & MMC_DATA_READ) 926 iflags |= ATMCI_RXRDY; 927 else 928 iflags |= ATMCI_TXRDY; 929 930 return iflags; 931 } 932 933 /* 934 * Set interrupt flags and set block length into the MCI mode register even 935 * if this value is also accessible in the MCI block register. It seems to be 936 * necessary before the High Speed MCI version. It also map sg and configure 937 * PDC registers. 938 */ 939 static u32 940 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) 941 { 942 u32 iflags, tmp; 943 unsigned int sg_len; 944 enum dma_data_direction dir; 945 int i; 946 947 data->error = -EINPROGRESS; 948 949 host->data = data; 950 host->sg = data->sg; 951 iflags = ATMCI_DATA_ERROR_FLAGS; 952 953 /* Enable pdc mode */ 954 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); 955 956 if (data->flags & MMC_DATA_READ) { 957 dir = DMA_FROM_DEVICE; 958 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; 959 } else { 960 dir = DMA_TO_DEVICE; 961 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE; 962 } 963 964 /* Set BLKLEN */ 965 tmp = atmci_readl(host, ATMCI_MR); 966 tmp &= 0x0000ffff; 967 tmp |= ATMCI_BLKLEN(data->blksz); 968 atmci_writel(host, ATMCI_MR, tmp); 969 970 /* Configure PDC */ 971 host->data_size = data->blocks * data->blksz; 972 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir); 973 974 if ((!host->caps.has_rwproof) 975 && (host->data->flags & MMC_DATA_WRITE)) { 976 sg_copy_to_buffer(host->data->sg, host->data->sg_len, 977 host->buffer, host->data_size); 978 if (host->caps.has_bad_data_ordering) 979 for (i = 0; i < host->data_size; i++) 980 host->buffer[i] = swab32(host->buffer[i]); 981 } 982 983 if (host->data_size) 984 atmci_pdc_set_both_buf(host, 985 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT)); 986 987 return iflags; 988 } 989 990 static u32 991 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) 992 { 993 struct dma_chan *chan; 994 struct dma_async_tx_descriptor *desc; 995 struct scatterlist *sg; 996 unsigned int i; 997 enum dma_data_direction direction; 998 enum dma_transfer_direction slave_dirn; 999 unsigned int sglen; 1000 u32 maxburst; 1001 u32 iflags; 1002 1003 data->error = -EINPROGRESS; 1004 1005 WARN_ON(host->data); 1006 host->sg = NULL; 1007 host->data = data; 1008 1009 iflags = ATMCI_DATA_ERROR_FLAGS; 1010 1011 /* 1012 * We don't do DMA on "complex" transfers, i.e. with 1013 * non-word-aligned buffers or lengths. Also, we don't bother 1014 * with all the DMA setup overhead for short transfers. 1015 */ 1016 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 1017 return atmci_prepare_data(host, data); 1018 if (data->blksz & 3) 1019 return atmci_prepare_data(host, data); 1020 1021 for_each_sg(data->sg, sg, data->sg_len, i) { 1022 if (sg->offset & 3 || sg->length & 3) 1023 return atmci_prepare_data(host, data); 1024 } 1025 1026 /* If we don't have a channel, we can't do DMA */ 1027 chan = host->dma.chan; 1028 if (chan) 1029 host->data_chan = chan; 1030 1031 if (!chan) 1032 return -ENODEV; 1033 1034 if (data->flags & MMC_DATA_READ) { 1035 direction = DMA_FROM_DEVICE; 1036 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM; 1037 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst); 1038 } else { 1039 direction = DMA_TO_DEVICE; 1040 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV; 1041 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst); 1042 } 1043 1044 if (host->caps.has_dma_conf_reg) 1045 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | 1046 ATMCI_DMAEN); 1047 1048 sglen = dma_map_sg(chan->device->dev, data->sg, 1049 data->sg_len, direction); 1050 1051 dmaengine_slave_config(chan, &host->dma_conf); 1052 desc = dmaengine_prep_slave_sg(chan, 1053 data->sg, sglen, slave_dirn, 1054 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1055 if (!desc) 1056 goto unmap_exit; 1057 1058 host->dma.data_desc = desc; 1059 desc->callback = atmci_dma_complete; 1060 desc->callback_param = host; 1061 1062 return iflags; 1063 unmap_exit: 1064 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction); 1065 return -ENOMEM; 1066 } 1067 1068 static void 1069 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) 1070 { 1071 return; 1072 } 1073 1074 /* 1075 * Start PDC according to transfer direction. 1076 */ 1077 static void 1078 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) 1079 { 1080 if (data->flags & MMC_DATA_READ) 1081 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1082 else 1083 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1084 } 1085 1086 static void 1087 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) 1088 { 1089 struct dma_chan *chan = host->data_chan; 1090 struct dma_async_tx_descriptor *desc = host->dma.data_desc; 1091 1092 if (chan) { 1093 dmaengine_submit(desc); 1094 dma_async_issue_pending(chan); 1095 } 1096 } 1097 1098 static void atmci_stop_transfer(struct atmel_mci *host) 1099 { 1100 dev_dbg(&host->pdev->dev, 1101 "(%s) set pending xfer complete\n", __func__); 1102 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1103 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1104 } 1105 1106 /* 1107 * Stop data transfer because error(s) occurred. 1108 */ 1109 static void atmci_stop_transfer_pdc(struct atmel_mci *host) 1110 { 1111 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 1112 } 1113 1114 static void atmci_stop_transfer_dma(struct atmel_mci *host) 1115 { 1116 struct dma_chan *chan = host->data_chan; 1117 1118 if (chan) { 1119 dmaengine_terminate_all(chan); 1120 atmci_dma_cleanup(host); 1121 } else { 1122 /* Data transfer was stopped by the interrupt handler */ 1123 dev_dbg(&host->pdev->dev, 1124 "(%s) set pending xfer complete\n", __func__); 1125 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1126 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1127 } 1128 } 1129 1130 /* 1131 * Start a request: prepare data if needed, prepare the command and activate 1132 * interrupts. 1133 */ 1134 static void atmci_start_request(struct atmel_mci *host, 1135 struct atmel_mci_slot *slot) 1136 { 1137 struct mmc_request *mrq; 1138 struct mmc_command *cmd; 1139 struct mmc_data *data; 1140 u32 iflags; 1141 u32 cmdflags; 1142 1143 mrq = slot->mrq; 1144 host->cur_slot = slot; 1145 host->mrq = mrq; 1146 1147 host->pending_events = 0; 1148 host->completed_events = 0; 1149 host->cmd_status = 0; 1150 host->data_status = 0; 1151 1152 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode); 1153 1154 if (host->need_reset || host->caps.need_reset_after_xfer) { 1155 iflags = atmci_readl(host, ATMCI_IMR); 1156 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB); 1157 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1158 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1159 atmci_writel(host, ATMCI_MR, host->mode_reg); 1160 if (host->caps.has_cfg_reg) 1161 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1162 atmci_writel(host, ATMCI_IER, iflags); 1163 host->need_reset = false; 1164 } 1165 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); 1166 1167 iflags = atmci_readl(host, ATMCI_IMR); 1168 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 1169 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 1170 iflags); 1171 1172 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 1173 /* Send init sequence (74 clock cycles) */ 1174 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); 1175 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) 1176 cpu_relax(); 1177 } 1178 iflags = 0; 1179 data = mrq->data; 1180 if (data) { 1181 atmci_set_timeout(host, slot, data); 1182 1183 /* Must set block count/size before sending command */ 1184 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) 1185 | ATMCI_BLKLEN(data->blksz)); 1186 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 1187 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); 1188 1189 iflags |= host->prepare_data(host, data); 1190 } 1191 1192 iflags |= ATMCI_CMDRDY; 1193 cmd = mrq->cmd; 1194 cmdflags = atmci_prepare_command(slot->mmc, cmd); 1195 atmci_send_command(host, cmd, cmdflags); 1196 1197 if (data) 1198 host->submit_data(host, data); 1199 1200 if (mrq->stop) { 1201 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 1202 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; 1203 if (!(data->flags & MMC_DATA_WRITE)) 1204 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; 1205 if (data->flags & MMC_DATA_STREAM) 1206 host->stop_cmdr |= ATMCI_CMDR_STREAM; 1207 else 1208 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; 1209 } 1210 1211 /* 1212 * We could have enabled interrupts earlier, but I suspect 1213 * that would open up a nice can of interesting race 1214 * conditions (e.g. command and data complete, but stop not 1215 * prepared yet.) 1216 */ 1217 atmci_writel(host, ATMCI_IER, iflags); 1218 1219 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); 1220 } 1221 1222 static void atmci_queue_request(struct atmel_mci *host, 1223 struct atmel_mci_slot *slot, struct mmc_request *mrq) 1224 { 1225 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1226 host->state); 1227 1228 spin_lock_bh(&host->lock); 1229 slot->mrq = mrq; 1230 if (host->state == STATE_IDLE) { 1231 host->state = STATE_SENDING_CMD; 1232 atmci_start_request(host, slot); 1233 } else { 1234 dev_dbg(&host->pdev->dev, "queue request\n"); 1235 list_add_tail(&slot->queue_node, &host->queue); 1236 } 1237 spin_unlock_bh(&host->lock); 1238 } 1239 1240 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1241 { 1242 struct atmel_mci_slot *slot = mmc_priv(mmc); 1243 struct atmel_mci *host = slot->host; 1244 struct mmc_data *data; 1245 1246 WARN_ON(slot->mrq); 1247 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode); 1248 1249 /* 1250 * We may "know" the card is gone even though there's still an 1251 * electrical connection. If so, we really need to communicate 1252 * this to the MMC core since there won't be any more 1253 * interrupts as the card is completely removed. Otherwise, 1254 * the MMC core might believe the card is still there even 1255 * though the card was just removed very slowly. 1256 */ 1257 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { 1258 mrq->cmd->error = -ENOMEDIUM; 1259 mmc_request_done(mmc, mrq); 1260 return; 1261 } 1262 1263 /* We don't support multiple blocks of weird lengths. */ 1264 data = mrq->data; 1265 if (data && data->blocks > 1 && data->blksz & 3) { 1266 mrq->cmd->error = -EINVAL; 1267 mmc_request_done(mmc, mrq); 1268 } 1269 1270 atmci_queue_request(host, slot, mrq); 1271 } 1272 1273 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1274 { 1275 struct atmel_mci_slot *slot = mmc_priv(mmc); 1276 struct atmel_mci *host = slot->host; 1277 unsigned int i; 1278 bool unprepare_clk; 1279 1280 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; 1281 switch (ios->bus_width) { 1282 case MMC_BUS_WIDTH_1: 1283 slot->sdc_reg |= ATMCI_SDCBUS_1BIT; 1284 break; 1285 case MMC_BUS_WIDTH_4: 1286 slot->sdc_reg |= ATMCI_SDCBUS_4BIT; 1287 break; 1288 } 1289 1290 if (ios->clock) { 1291 unsigned int clock_min = ~0U; 1292 u32 clkdiv; 1293 1294 clk_prepare(host->mck); 1295 unprepare_clk = true; 1296 1297 spin_lock_bh(&host->lock); 1298 if (!host->mode_reg) { 1299 clk_enable(host->mck); 1300 unprepare_clk = false; 1301 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1302 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1303 if (host->caps.has_cfg_reg) 1304 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1305 } 1306 1307 /* 1308 * Use mirror of ios->clock to prevent race with mmc 1309 * core ios update when finding the minimum. 1310 */ 1311 slot->clock = ios->clock; 1312 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1313 if (host->slot[i] && host->slot[i]->clock 1314 && host->slot[i]->clock < clock_min) 1315 clock_min = host->slot[i]->clock; 1316 } 1317 1318 /* Calculate clock divider */ 1319 if (host->caps.has_odd_clk_div) { 1320 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; 1321 if (clkdiv > 511) { 1322 dev_warn(&mmc->class_dev, 1323 "clock %u too slow; using %lu\n", 1324 clock_min, host->bus_hz / (511 + 2)); 1325 clkdiv = 511; 1326 } 1327 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) 1328 | ATMCI_MR_CLKODD(clkdiv & 1); 1329 } else { 1330 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; 1331 if (clkdiv > 255) { 1332 dev_warn(&mmc->class_dev, 1333 "clock %u too slow; using %lu\n", 1334 clock_min, host->bus_hz / (2 * 256)); 1335 clkdiv = 255; 1336 } 1337 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); 1338 } 1339 1340 /* 1341 * WRPROOF and RDPROOF prevent overruns/underruns by 1342 * stopping the clock when the FIFO is full/empty. 1343 * This state is not expected to last for long. 1344 */ 1345 if (host->caps.has_rwproof) 1346 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); 1347 1348 if (host->caps.has_cfg_reg) { 1349 /* setup High Speed mode in relation with card capacity */ 1350 if (ios->timing == MMC_TIMING_SD_HS) 1351 host->cfg_reg |= ATMCI_CFG_HSMODE; 1352 else 1353 host->cfg_reg &= ~ATMCI_CFG_HSMODE; 1354 } 1355 1356 if (list_empty(&host->queue)) { 1357 atmci_writel(host, ATMCI_MR, host->mode_reg); 1358 if (host->caps.has_cfg_reg) 1359 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1360 } else { 1361 host->need_clock_update = true; 1362 } 1363 1364 spin_unlock_bh(&host->lock); 1365 } else { 1366 bool any_slot_active = false; 1367 1368 unprepare_clk = false; 1369 1370 spin_lock_bh(&host->lock); 1371 slot->clock = 0; 1372 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1373 if (host->slot[i] && host->slot[i]->clock) { 1374 any_slot_active = true; 1375 break; 1376 } 1377 } 1378 if (!any_slot_active) { 1379 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 1380 if (host->mode_reg) { 1381 atmci_readl(host, ATMCI_MR); 1382 clk_disable(host->mck); 1383 unprepare_clk = true; 1384 } 1385 host->mode_reg = 0; 1386 } 1387 spin_unlock_bh(&host->lock); 1388 } 1389 1390 if (unprepare_clk) 1391 clk_unprepare(host->mck); 1392 1393 switch (ios->power_mode) { 1394 case MMC_POWER_UP: 1395 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); 1396 break; 1397 default: 1398 /* 1399 * TODO: None of the currently available AVR32-based 1400 * boards allow MMC power to be turned off. Implement 1401 * power control when this can be tested properly. 1402 * 1403 * We also need to hook this into the clock management 1404 * somehow so that newly inserted cards aren't 1405 * subjected to a fast clock before we have a chance 1406 * to figure out what the maximum rate is. Currently, 1407 * there's no way to avoid this, and there never will 1408 * be for boards that don't support power control. 1409 */ 1410 break; 1411 } 1412 } 1413 1414 static int atmci_get_ro(struct mmc_host *mmc) 1415 { 1416 int read_only = -ENOSYS; 1417 struct atmel_mci_slot *slot = mmc_priv(mmc); 1418 1419 if (gpio_is_valid(slot->wp_pin)) { 1420 read_only = gpio_get_value(slot->wp_pin); 1421 dev_dbg(&mmc->class_dev, "card is %s\n", 1422 read_only ? "read-only" : "read-write"); 1423 } 1424 1425 return read_only; 1426 } 1427 1428 static int atmci_get_cd(struct mmc_host *mmc) 1429 { 1430 int present = -ENOSYS; 1431 struct atmel_mci_slot *slot = mmc_priv(mmc); 1432 1433 if (gpio_is_valid(slot->detect_pin)) { 1434 present = !(gpio_get_value(slot->detect_pin) ^ 1435 slot->detect_is_active_high); 1436 dev_dbg(&mmc->class_dev, "card is %spresent\n", 1437 present ? "" : "not "); 1438 } 1439 1440 return present; 1441 } 1442 1443 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1444 { 1445 struct atmel_mci_slot *slot = mmc_priv(mmc); 1446 struct atmel_mci *host = slot->host; 1447 1448 if (enable) 1449 atmci_writel(host, ATMCI_IER, slot->sdio_irq); 1450 else 1451 atmci_writel(host, ATMCI_IDR, slot->sdio_irq); 1452 } 1453 1454 static const struct mmc_host_ops atmci_ops = { 1455 .request = atmci_request, 1456 .set_ios = atmci_set_ios, 1457 .get_ro = atmci_get_ro, 1458 .get_cd = atmci_get_cd, 1459 .enable_sdio_irq = atmci_enable_sdio_irq, 1460 }; 1461 1462 /* Called with host->lock held */ 1463 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) 1464 __releases(&host->lock) 1465 __acquires(&host->lock) 1466 { 1467 struct atmel_mci_slot *slot = NULL; 1468 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1469 1470 WARN_ON(host->cmd || host->data); 1471 1472 /* 1473 * Update the MMC clock rate if necessary. This may be 1474 * necessary if set_ios() is called when a different slot is 1475 * busy transferring data. 1476 */ 1477 if (host->need_clock_update) { 1478 atmci_writel(host, ATMCI_MR, host->mode_reg); 1479 if (host->caps.has_cfg_reg) 1480 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1481 } 1482 1483 host->cur_slot->mrq = NULL; 1484 host->mrq = NULL; 1485 if (!list_empty(&host->queue)) { 1486 slot = list_entry(host->queue.next, 1487 struct atmel_mci_slot, queue_node); 1488 list_del(&slot->queue_node); 1489 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 1490 mmc_hostname(slot->mmc)); 1491 host->state = STATE_SENDING_CMD; 1492 atmci_start_request(host, slot); 1493 } else { 1494 dev_vdbg(&host->pdev->dev, "list empty\n"); 1495 host->state = STATE_IDLE; 1496 } 1497 1498 del_timer(&host->timer); 1499 1500 spin_unlock(&host->lock); 1501 mmc_request_done(prev_mmc, mrq); 1502 spin_lock(&host->lock); 1503 } 1504 1505 static void atmci_command_complete(struct atmel_mci *host, 1506 struct mmc_command *cmd) 1507 { 1508 u32 status = host->cmd_status; 1509 1510 /* Read the response from the card (up to 16 bytes) */ 1511 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); 1512 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); 1513 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); 1514 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); 1515 1516 if (status & ATMCI_RTOE) 1517 cmd->error = -ETIMEDOUT; 1518 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) 1519 cmd->error = -EILSEQ; 1520 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) 1521 cmd->error = -EIO; 1522 else if (host->mrq->data && (host->mrq->data->blksz & 3)) { 1523 if (host->caps.need_blksz_mul_4) { 1524 cmd->error = -EINVAL; 1525 host->need_reset = 1; 1526 } 1527 } else 1528 cmd->error = 0; 1529 } 1530 1531 static void atmci_detect_change(unsigned long data) 1532 { 1533 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; 1534 bool present; 1535 bool present_old; 1536 1537 /* 1538 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before 1539 * freeing the interrupt. We must not re-enable the interrupt 1540 * if it has been freed, and if we're shutting down, it 1541 * doesn't really matter whether the card is present or not. 1542 */ 1543 smp_rmb(); 1544 if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) 1545 return; 1546 1547 enable_irq(gpio_to_irq(slot->detect_pin)); 1548 present = !(gpio_get_value(slot->detect_pin) ^ 1549 slot->detect_is_active_high); 1550 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1551 1552 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 1553 present, present_old); 1554 1555 if (present != present_old) { 1556 struct atmel_mci *host = slot->host; 1557 struct mmc_request *mrq; 1558 1559 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1560 present ? "inserted" : "removed"); 1561 1562 spin_lock(&host->lock); 1563 1564 if (!present) 1565 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1566 else 1567 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1568 1569 /* Clean up queue if present */ 1570 mrq = slot->mrq; 1571 if (mrq) { 1572 if (mrq == host->mrq) { 1573 /* 1574 * Reset controller to terminate any ongoing 1575 * commands or data transfers. 1576 */ 1577 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1578 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1579 atmci_writel(host, ATMCI_MR, host->mode_reg); 1580 if (host->caps.has_cfg_reg) 1581 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1582 1583 host->data = NULL; 1584 host->cmd = NULL; 1585 1586 switch (host->state) { 1587 case STATE_IDLE: 1588 break; 1589 case STATE_SENDING_CMD: 1590 mrq->cmd->error = -ENOMEDIUM; 1591 if (mrq->data) 1592 host->stop_transfer(host); 1593 break; 1594 case STATE_DATA_XFER: 1595 mrq->data->error = -ENOMEDIUM; 1596 host->stop_transfer(host); 1597 break; 1598 case STATE_WAITING_NOTBUSY: 1599 mrq->data->error = -ENOMEDIUM; 1600 break; 1601 case STATE_SENDING_STOP: 1602 mrq->stop->error = -ENOMEDIUM; 1603 break; 1604 case STATE_END_REQUEST: 1605 break; 1606 } 1607 1608 atmci_request_end(host, mrq); 1609 } else { 1610 list_del(&slot->queue_node); 1611 mrq->cmd->error = -ENOMEDIUM; 1612 if (mrq->data) 1613 mrq->data->error = -ENOMEDIUM; 1614 if (mrq->stop) 1615 mrq->stop->error = -ENOMEDIUM; 1616 1617 spin_unlock(&host->lock); 1618 mmc_request_done(slot->mmc, mrq); 1619 spin_lock(&host->lock); 1620 } 1621 } 1622 spin_unlock(&host->lock); 1623 1624 mmc_detect_change(slot->mmc, 0); 1625 } 1626 } 1627 1628 static void atmci_tasklet_func(unsigned long priv) 1629 { 1630 struct atmel_mci *host = (struct atmel_mci *)priv; 1631 struct mmc_request *mrq = host->mrq; 1632 struct mmc_data *data = host->data; 1633 enum atmel_mci_state state = host->state; 1634 enum atmel_mci_state prev_state; 1635 u32 status; 1636 1637 spin_lock(&host->lock); 1638 1639 state = host->state; 1640 1641 dev_vdbg(&host->pdev->dev, 1642 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1643 state, host->pending_events, host->completed_events, 1644 atmci_readl(host, ATMCI_IMR)); 1645 1646 do { 1647 prev_state = state; 1648 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state); 1649 1650 switch (state) { 1651 case STATE_IDLE: 1652 break; 1653 1654 case STATE_SENDING_CMD: 1655 /* 1656 * Command has been sent, we are waiting for command 1657 * ready. Then we have three next states possible: 1658 * END_REQUEST by default, WAITING_NOTBUSY if it's a 1659 * command needing it or DATA_XFER if there is data. 1660 */ 1661 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1662 if (!atmci_test_and_clear_pending(host, 1663 EVENT_CMD_RDY)) 1664 break; 1665 1666 dev_dbg(&host->pdev->dev, "set completed cmd ready\n"); 1667 host->cmd = NULL; 1668 atmci_set_completed(host, EVENT_CMD_RDY); 1669 atmci_command_complete(host, mrq->cmd); 1670 if (mrq->data) { 1671 dev_dbg(&host->pdev->dev, 1672 "command with data transfer"); 1673 /* 1674 * If there is a command error don't start 1675 * data transfer. 1676 */ 1677 if (mrq->cmd->error) { 1678 host->stop_transfer(host); 1679 host->data = NULL; 1680 atmci_writel(host, ATMCI_IDR, 1681 ATMCI_TXRDY | ATMCI_RXRDY 1682 | ATMCI_DATA_ERROR_FLAGS); 1683 state = STATE_END_REQUEST; 1684 } else 1685 state = STATE_DATA_XFER; 1686 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) { 1687 dev_dbg(&host->pdev->dev, 1688 "command response need waiting notbusy"); 1689 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1690 state = STATE_WAITING_NOTBUSY; 1691 } else 1692 state = STATE_END_REQUEST; 1693 1694 break; 1695 1696 case STATE_DATA_XFER: 1697 if (atmci_test_and_clear_pending(host, 1698 EVENT_DATA_ERROR)) { 1699 dev_dbg(&host->pdev->dev, "set completed data error\n"); 1700 atmci_set_completed(host, EVENT_DATA_ERROR); 1701 state = STATE_END_REQUEST; 1702 break; 1703 } 1704 1705 /* 1706 * A data transfer is in progress. The event expected 1707 * to move to the next state depends of data transfer 1708 * type (PDC or DMA). Once transfer done we can move 1709 * to the next step which is WAITING_NOTBUSY in write 1710 * case and directly SENDING_STOP in read case. 1711 */ 1712 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n"); 1713 if (!atmci_test_and_clear_pending(host, 1714 EVENT_XFER_COMPLETE)) 1715 break; 1716 1717 dev_dbg(&host->pdev->dev, 1718 "(%s) set completed xfer complete\n", 1719 __func__); 1720 atmci_set_completed(host, EVENT_XFER_COMPLETE); 1721 1722 if (host->caps.need_notbusy_for_read_ops || 1723 (host->data->flags & MMC_DATA_WRITE)) { 1724 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1725 state = STATE_WAITING_NOTBUSY; 1726 } else if (host->mrq->stop) { 1727 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 1728 atmci_send_stop_cmd(host, data); 1729 state = STATE_SENDING_STOP; 1730 } else { 1731 host->data = NULL; 1732 data->bytes_xfered = data->blocks * data->blksz; 1733 data->error = 0; 1734 state = STATE_END_REQUEST; 1735 } 1736 break; 1737 1738 case STATE_WAITING_NOTBUSY: 1739 /* 1740 * We can be in the state for two reasons: a command 1741 * requiring waiting not busy signal (stop command 1742 * included) or a write operation. In the latest case, 1743 * we need to send a stop command. 1744 */ 1745 dev_dbg(&host->pdev->dev, "FSM: not busy?\n"); 1746 if (!atmci_test_and_clear_pending(host, 1747 EVENT_NOTBUSY)) 1748 break; 1749 1750 dev_dbg(&host->pdev->dev, "set completed not busy\n"); 1751 atmci_set_completed(host, EVENT_NOTBUSY); 1752 1753 if (host->data) { 1754 /* 1755 * For some commands such as CMD53, even if 1756 * there is data transfer, there is no stop 1757 * command to send. 1758 */ 1759 if (host->mrq->stop) { 1760 atmci_writel(host, ATMCI_IER, 1761 ATMCI_CMDRDY); 1762 atmci_send_stop_cmd(host, data); 1763 state = STATE_SENDING_STOP; 1764 } else { 1765 host->data = NULL; 1766 data->bytes_xfered = data->blocks 1767 * data->blksz; 1768 data->error = 0; 1769 state = STATE_END_REQUEST; 1770 } 1771 } else 1772 state = STATE_END_REQUEST; 1773 break; 1774 1775 case STATE_SENDING_STOP: 1776 /* 1777 * In this state, it is important to set host->data to 1778 * NULL (which is tested in the waiting notbusy state) 1779 * in order to go to the end request state instead of 1780 * sending stop again. 1781 */ 1782 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1783 if (!atmci_test_and_clear_pending(host, 1784 EVENT_CMD_RDY)) 1785 break; 1786 1787 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n"); 1788 host->cmd = NULL; 1789 data->bytes_xfered = data->blocks * data->blksz; 1790 data->error = 0; 1791 atmci_command_complete(host, mrq->stop); 1792 if (mrq->stop->error) { 1793 host->stop_transfer(host); 1794 atmci_writel(host, ATMCI_IDR, 1795 ATMCI_TXRDY | ATMCI_RXRDY 1796 | ATMCI_DATA_ERROR_FLAGS); 1797 state = STATE_END_REQUEST; 1798 } else { 1799 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1800 state = STATE_WAITING_NOTBUSY; 1801 } 1802 host->data = NULL; 1803 break; 1804 1805 case STATE_END_REQUEST: 1806 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY 1807 | ATMCI_DATA_ERROR_FLAGS); 1808 status = host->data_status; 1809 if (unlikely(status)) { 1810 host->stop_transfer(host); 1811 host->data = NULL; 1812 if (data) { 1813 if (status & ATMCI_DTOE) { 1814 data->error = -ETIMEDOUT; 1815 } else if (status & ATMCI_DCRCE) { 1816 data->error = -EILSEQ; 1817 } else { 1818 data->error = -EIO; 1819 } 1820 } 1821 } 1822 1823 atmci_request_end(host, host->mrq); 1824 state = STATE_IDLE; 1825 break; 1826 } 1827 } while (state != prev_state); 1828 1829 host->state = state; 1830 1831 spin_unlock(&host->lock); 1832 } 1833 1834 static void atmci_read_data_pio(struct atmel_mci *host) 1835 { 1836 struct scatterlist *sg = host->sg; 1837 void *buf = sg_virt(sg); 1838 unsigned int offset = host->pio_offset; 1839 struct mmc_data *data = host->data; 1840 u32 value; 1841 u32 status; 1842 unsigned int nbytes = 0; 1843 1844 do { 1845 value = atmci_readl(host, ATMCI_RDR); 1846 if (likely(offset + 4 <= sg->length)) { 1847 put_unaligned(value, (u32 *)(buf + offset)); 1848 1849 offset += 4; 1850 nbytes += 4; 1851 1852 if (offset == sg->length) { 1853 flush_dcache_page(sg_page(sg)); 1854 host->sg = sg = sg_next(sg); 1855 host->sg_len--; 1856 if (!sg || !host->sg_len) 1857 goto done; 1858 1859 offset = 0; 1860 buf = sg_virt(sg); 1861 } 1862 } else { 1863 unsigned int remaining = sg->length - offset; 1864 memcpy(buf + offset, &value, remaining); 1865 nbytes += remaining; 1866 1867 flush_dcache_page(sg_page(sg)); 1868 host->sg = sg = sg_next(sg); 1869 host->sg_len--; 1870 if (!sg || !host->sg_len) 1871 goto done; 1872 1873 offset = 4 - remaining; 1874 buf = sg_virt(sg); 1875 memcpy(buf, (u8 *)&value + remaining, offset); 1876 nbytes += offset; 1877 } 1878 1879 status = atmci_readl(host, ATMCI_SR); 1880 if (status & ATMCI_DATA_ERROR_FLAGS) { 1881 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY 1882 | ATMCI_DATA_ERROR_FLAGS)); 1883 host->data_status = status; 1884 data->bytes_xfered += nbytes; 1885 return; 1886 } 1887 } while (status & ATMCI_RXRDY); 1888 1889 host->pio_offset = offset; 1890 data->bytes_xfered += nbytes; 1891 1892 return; 1893 1894 done: 1895 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); 1896 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1897 data->bytes_xfered += nbytes; 1898 smp_wmb(); 1899 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1900 } 1901 1902 static void atmci_write_data_pio(struct atmel_mci *host) 1903 { 1904 struct scatterlist *sg = host->sg; 1905 void *buf = sg_virt(sg); 1906 unsigned int offset = host->pio_offset; 1907 struct mmc_data *data = host->data; 1908 u32 value; 1909 u32 status; 1910 unsigned int nbytes = 0; 1911 1912 do { 1913 if (likely(offset + 4 <= sg->length)) { 1914 value = get_unaligned((u32 *)(buf + offset)); 1915 atmci_writel(host, ATMCI_TDR, value); 1916 1917 offset += 4; 1918 nbytes += 4; 1919 if (offset == sg->length) { 1920 host->sg = sg = sg_next(sg); 1921 host->sg_len--; 1922 if (!sg || !host->sg_len) 1923 goto done; 1924 1925 offset = 0; 1926 buf = sg_virt(sg); 1927 } 1928 } else { 1929 unsigned int remaining = sg->length - offset; 1930 1931 value = 0; 1932 memcpy(&value, buf + offset, remaining); 1933 nbytes += remaining; 1934 1935 host->sg = sg = sg_next(sg); 1936 host->sg_len--; 1937 if (!sg || !host->sg_len) { 1938 atmci_writel(host, ATMCI_TDR, value); 1939 goto done; 1940 } 1941 1942 offset = 4 - remaining; 1943 buf = sg_virt(sg); 1944 memcpy((u8 *)&value + remaining, buf, offset); 1945 atmci_writel(host, ATMCI_TDR, value); 1946 nbytes += offset; 1947 } 1948 1949 status = atmci_readl(host, ATMCI_SR); 1950 if (status & ATMCI_DATA_ERROR_FLAGS) { 1951 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY 1952 | ATMCI_DATA_ERROR_FLAGS)); 1953 host->data_status = status; 1954 data->bytes_xfered += nbytes; 1955 return; 1956 } 1957 } while (status & ATMCI_TXRDY); 1958 1959 host->pio_offset = offset; 1960 data->bytes_xfered += nbytes; 1961 1962 return; 1963 1964 done: 1965 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); 1966 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1967 data->bytes_xfered += nbytes; 1968 smp_wmb(); 1969 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1970 } 1971 1972 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) 1973 { 1974 int i; 1975 1976 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1977 struct atmel_mci_slot *slot = host->slot[i]; 1978 if (slot && (status & slot->sdio_irq)) { 1979 mmc_signal_sdio_irq(slot->mmc); 1980 } 1981 } 1982 } 1983 1984 1985 static irqreturn_t atmci_interrupt(int irq, void *dev_id) 1986 { 1987 struct atmel_mci *host = dev_id; 1988 u32 status, mask, pending; 1989 unsigned int pass_count = 0; 1990 1991 do { 1992 status = atmci_readl(host, ATMCI_SR); 1993 mask = atmci_readl(host, ATMCI_IMR); 1994 pending = status & mask; 1995 if (!pending) 1996 break; 1997 1998 if (pending & ATMCI_DATA_ERROR_FLAGS) { 1999 dev_dbg(&host->pdev->dev, "IRQ: data error\n"); 2000 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS 2001 | ATMCI_RXRDY | ATMCI_TXRDY 2002 | ATMCI_ENDRX | ATMCI_ENDTX 2003 | ATMCI_RXBUFF | ATMCI_TXBUFE); 2004 2005 host->data_status = status; 2006 dev_dbg(&host->pdev->dev, "set pending data error\n"); 2007 smp_wmb(); 2008 atmci_set_pending(host, EVENT_DATA_ERROR); 2009 tasklet_schedule(&host->tasklet); 2010 } 2011 2012 if (pending & ATMCI_TXBUFE) { 2013 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n"); 2014 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); 2015 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2016 /* 2017 * We can receive this interruption before having configured 2018 * the second pdc buffer, so we need to reconfigure first and 2019 * second buffers again 2020 */ 2021 if (host->data_size) { 2022 atmci_pdc_set_both_buf(host, XFER_TRANSMIT); 2023 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2024 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); 2025 } else { 2026 atmci_pdc_complete(host); 2027 } 2028 } else if (pending & ATMCI_ENDTX) { 2029 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n"); 2030 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2031 2032 if (host->data_size) { 2033 atmci_pdc_set_single_buf(host, 2034 XFER_TRANSMIT, PDC_SECOND_BUF); 2035 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2036 } 2037 } 2038 2039 if (pending & ATMCI_RXBUFF) { 2040 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n"); 2041 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); 2042 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2043 /* 2044 * We can receive this interruption before having configured 2045 * the second pdc buffer, so we need to reconfigure first and 2046 * second buffers again 2047 */ 2048 if (host->data_size) { 2049 atmci_pdc_set_both_buf(host, XFER_RECEIVE); 2050 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2051 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); 2052 } else { 2053 atmci_pdc_complete(host); 2054 } 2055 } else if (pending & ATMCI_ENDRX) { 2056 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n"); 2057 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2058 2059 if (host->data_size) { 2060 atmci_pdc_set_single_buf(host, 2061 XFER_RECEIVE, PDC_SECOND_BUF); 2062 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2063 } 2064 } 2065 2066 /* 2067 * First mci IPs, so mainly the ones having pdc, have some 2068 * issues with the notbusy signal. You can't get it after 2069 * data transmission if you have not sent a stop command. 2070 * The appropriate workaround is to use the BLKE signal. 2071 */ 2072 if (pending & ATMCI_BLKE) { 2073 dev_dbg(&host->pdev->dev, "IRQ: blke\n"); 2074 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE); 2075 smp_wmb(); 2076 dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2077 atmci_set_pending(host, EVENT_NOTBUSY); 2078 tasklet_schedule(&host->tasklet); 2079 } 2080 2081 if (pending & ATMCI_NOTBUSY) { 2082 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n"); 2083 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY); 2084 smp_wmb(); 2085 dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2086 atmci_set_pending(host, EVENT_NOTBUSY); 2087 tasklet_schedule(&host->tasklet); 2088 } 2089 2090 if (pending & ATMCI_RXRDY) 2091 atmci_read_data_pio(host); 2092 if (pending & ATMCI_TXRDY) 2093 atmci_write_data_pio(host); 2094 2095 if (pending & ATMCI_CMDRDY) { 2096 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n"); 2097 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); 2098 host->cmd_status = status; 2099 smp_wmb(); 2100 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n"); 2101 atmci_set_pending(host, EVENT_CMD_RDY); 2102 tasklet_schedule(&host->tasklet); 2103 } 2104 2105 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 2106 atmci_sdio_interrupt(host, status); 2107 2108 } while (pass_count++ < 5); 2109 2110 return pass_count ? IRQ_HANDLED : IRQ_NONE; 2111 } 2112 2113 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) 2114 { 2115 struct atmel_mci_slot *slot = dev_id; 2116 2117 /* 2118 * Disable interrupts until the pin has stabilized and check 2119 * the state then. Use mod_timer() since we may be in the 2120 * middle of the timer routine when this interrupt triggers. 2121 */ 2122 disable_irq_nosync(irq); 2123 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); 2124 2125 return IRQ_HANDLED; 2126 } 2127 2128 static int __init atmci_init_slot(struct atmel_mci *host, 2129 struct mci_slot_pdata *slot_data, unsigned int id, 2130 u32 sdc_reg, u32 sdio_irq) 2131 { 2132 struct mmc_host *mmc; 2133 struct atmel_mci_slot *slot; 2134 2135 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 2136 if (!mmc) 2137 return -ENOMEM; 2138 2139 slot = mmc_priv(mmc); 2140 slot->mmc = mmc; 2141 slot->host = host; 2142 slot->detect_pin = slot_data->detect_pin; 2143 slot->wp_pin = slot_data->wp_pin; 2144 slot->detect_is_active_high = slot_data->detect_is_active_high; 2145 slot->sdc_reg = sdc_reg; 2146 slot->sdio_irq = sdio_irq; 2147 2148 dev_dbg(&mmc->class_dev, 2149 "slot[%u]: bus_width=%u, detect_pin=%d, " 2150 "detect_is_active_high=%s, wp_pin=%d\n", 2151 id, slot_data->bus_width, slot_data->detect_pin, 2152 slot_data->detect_is_active_high ? "true" : "false", 2153 slot_data->wp_pin); 2154 2155 mmc->ops = &atmci_ops; 2156 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); 2157 mmc->f_max = host->bus_hz / 2; 2158 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2159 if (sdio_irq) 2160 mmc->caps |= MMC_CAP_SDIO_IRQ; 2161 if (host->caps.has_highspeed) 2162 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2163 /* 2164 * Without the read/write proof capability, it is strongly suggested to 2165 * use only one bit for data to prevent fifo underruns and overruns 2166 * which will corrupt data. 2167 */ 2168 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) 2169 mmc->caps |= MMC_CAP_4_BIT_DATA; 2170 2171 if (atmci_get_version(host) < 0x200) { 2172 mmc->max_segs = 256; 2173 mmc->max_blk_size = 4095; 2174 mmc->max_blk_count = 256; 2175 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2176 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs; 2177 } else { 2178 mmc->max_segs = 64; 2179 mmc->max_req_size = 32768 * 512; 2180 mmc->max_blk_size = 32768; 2181 mmc->max_blk_count = 512; 2182 } 2183 2184 /* Assume card is present initially */ 2185 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 2186 if (gpio_is_valid(slot->detect_pin)) { 2187 if (gpio_request(slot->detect_pin, "mmc_detect")) { 2188 dev_dbg(&mmc->class_dev, "no detect pin available\n"); 2189 slot->detect_pin = -EBUSY; 2190 } else if (gpio_get_value(slot->detect_pin) ^ 2191 slot->detect_is_active_high) { 2192 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 2193 } 2194 } 2195 2196 if (!gpio_is_valid(slot->detect_pin)) 2197 mmc->caps |= MMC_CAP_NEEDS_POLL; 2198 2199 if (gpio_is_valid(slot->wp_pin)) { 2200 if (gpio_request(slot->wp_pin, "mmc_wp")) { 2201 dev_dbg(&mmc->class_dev, "no WP pin available\n"); 2202 slot->wp_pin = -EBUSY; 2203 } 2204 } 2205 2206 host->slot[id] = slot; 2207 mmc_add_host(mmc); 2208 2209 if (gpio_is_valid(slot->detect_pin)) { 2210 int ret; 2211 2212 setup_timer(&slot->detect_timer, atmci_detect_change, 2213 (unsigned long)slot); 2214 2215 ret = request_irq(gpio_to_irq(slot->detect_pin), 2216 atmci_detect_interrupt, 2217 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 2218 "mmc-detect", slot); 2219 if (ret) { 2220 dev_dbg(&mmc->class_dev, 2221 "could not request IRQ %d for detect pin\n", 2222 gpio_to_irq(slot->detect_pin)); 2223 gpio_free(slot->detect_pin); 2224 slot->detect_pin = -EBUSY; 2225 } 2226 } 2227 2228 atmci_init_debugfs(slot); 2229 2230 return 0; 2231 } 2232 2233 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot, 2234 unsigned int id) 2235 { 2236 /* Debugfs stuff is cleaned up by mmc core */ 2237 2238 set_bit(ATMCI_SHUTDOWN, &slot->flags); 2239 smp_wmb(); 2240 2241 mmc_remove_host(slot->mmc); 2242 2243 if (gpio_is_valid(slot->detect_pin)) { 2244 int pin = slot->detect_pin; 2245 2246 free_irq(gpio_to_irq(pin), slot); 2247 del_timer_sync(&slot->detect_timer); 2248 gpio_free(pin); 2249 } 2250 if (gpio_is_valid(slot->wp_pin)) 2251 gpio_free(slot->wp_pin); 2252 2253 slot->host->slot[id] = NULL; 2254 mmc_free_host(slot->mmc); 2255 } 2256 2257 static bool atmci_filter(struct dma_chan *chan, void *pdata) 2258 { 2259 struct mci_platform_data *sl_pdata = pdata; 2260 struct mci_dma_data *sl; 2261 2262 if (!sl_pdata) 2263 return false; 2264 2265 sl = sl_pdata->dma_slave; 2266 if (sl && find_slave_dev(sl) == chan->device->dev) { 2267 chan->private = slave_data_ptr(sl); 2268 return true; 2269 } else { 2270 return false; 2271 } 2272 } 2273 2274 static bool atmci_configure_dma(struct atmel_mci *host) 2275 { 2276 struct mci_platform_data *pdata; 2277 dma_cap_mask_t mask; 2278 2279 if (host == NULL) 2280 return false; 2281 2282 pdata = host->pdev->dev.platform_data; 2283 2284 dma_cap_zero(mask); 2285 dma_cap_set(DMA_SLAVE, mask); 2286 2287 host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata, 2288 &host->pdev->dev, "rxtx"); 2289 if (!host->dma.chan) { 2290 dev_warn(&host->pdev->dev, "no DMA channel available\n"); 2291 return false; 2292 } else { 2293 dev_info(&host->pdev->dev, 2294 "using %s for DMA transfers\n", 2295 dma_chan_name(host->dma.chan)); 2296 2297 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR; 2298 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2299 host->dma_conf.src_maxburst = 1; 2300 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR; 2301 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2302 host->dma_conf.dst_maxburst = 1; 2303 host->dma_conf.device_fc = false; 2304 return true; 2305 } 2306 } 2307 2308 /* 2309 * HSMCI (High Speed MCI) module is not fully compatible with MCI module. 2310 * HSMCI provides DMA support and a new config register but no more supports 2311 * PDC. 2312 */ 2313 static void __init atmci_get_cap(struct atmel_mci *host) 2314 { 2315 unsigned int version; 2316 2317 version = atmci_get_version(host); 2318 dev_info(&host->pdev->dev, 2319 "version: 0x%x\n", version); 2320 2321 host->caps.has_dma_conf_reg = 0; 2322 host->caps.has_pdc = ATMCI_PDC_CONNECTED; 2323 host->caps.has_cfg_reg = 0; 2324 host->caps.has_cstor_reg = 0; 2325 host->caps.has_highspeed = 0; 2326 host->caps.has_rwproof = 0; 2327 host->caps.has_odd_clk_div = 0; 2328 host->caps.has_bad_data_ordering = 1; 2329 host->caps.need_reset_after_xfer = 1; 2330 host->caps.need_blksz_mul_4 = 1; 2331 host->caps.need_notbusy_for_read_ops = 0; 2332 2333 /* keep only major version number */ 2334 switch (version & 0xf00) { 2335 case 0x500: 2336 host->caps.has_odd_clk_div = 1; 2337 case 0x400: 2338 case 0x300: 2339 host->caps.has_dma_conf_reg = 1; 2340 host->caps.has_pdc = 0; 2341 host->caps.has_cfg_reg = 1; 2342 host->caps.has_cstor_reg = 1; 2343 host->caps.has_highspeed = 1; 2344 case 0x200: 2345 host->caps.has_rwproof = 1; 2346 host->caps.need_blksz_mul_4 = 0; 2347 host->caps.need_notbusy_for_read_ops = 1; 2348 case 0x100: 2349 host->caps.has_bad_data_ordering = 0; 2350 host->caps.need_reset_after_xfer = 0; 2351 case 0x0: 2352 break; 2353 default: 2354 host->caps.has_pdc = 0; 2355 dev_warn(&host->pdev->dev, 2356 "Unmanaged mci version, set minimum capabilities\n"); 2357 break; 2358 } 2359 } 2360 2361 static int __init atmci_probe(struct platform_device *pdev) 2362 { 2363 struct mci_platform_data *pdata; 2364 struct atmel_mci *host; 2365 struct resource *regs; 2366 unsigned int nr_slots; 2367 int irq; 2368 int ret; 2369 2370 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2371 if (!regs) 2372 return -ENXIO; 2373 pdata = pdev->dev.platform_data; 2374 if (!pdata) { 2375 pdata = atmci_of_init(pdev); 2376 if (IS_ERR(pdata)) { 2377 dev_err(&pdev->dev, "platform data not available\n"); 2378 return PTR_ERR(pdata); 2379 } 2380 } 2381 2382 irq = platform_get_irq(pdev, 0); 2383 if (irq < 0) 2384 return irq; 2385 2386 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL); 2387 if (!host) 2388 return -ENOMEM; 2389 2390 host->pdev = pdev; 2391 spin_lock_init(&host->lock); 2392 INIT_LIST_HEAD(&host->queue); 2393 2394 host->mck = clk_get(&pdev->dev, "mci_clk"); 2395 if (IS_ERR(host->mck)) { 2396 ret = PTR_ERR(host->mck); 2397 goto err_clk_get; 2398 } 2399 2400 ret = -ENOMEM; 2401 host->regs = ioremap(regs->start, resource_size(regs)); 2402 if (!host->regs) 2403 goto err_ioremap; 2404 2405 ret = clk_prepare_enable(host->mck); 2406 if (ret) 2407 goto err_request_irq; 2408 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 2409 host->bus_hz = clk_get_rate(host->mck); 2410 clk_disable_unprepare(host->mck); 2411 2412 host->mapbase = regs->start; 2413 2414 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); 2415 2416 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); 2417 if (ret) 2418 goto err_request_irq; 2419 2420 /* Get MCI capabilities and set operations according to it */ 2421 atmci_get_cap(host); 2422 if (atmci_configure_dma(host)) { 2423 host->prepare_data = &atmci_prepare_data_dma; 2424 host->submit_data = &atmci_submit_data_dma; 2425 host->stop_transfer = &atmci_stop_transfer_dma; 2426 } else if (host->caps.has_pdc) { 2427 dev_info(&pdev->dev, "using PDC\n"); 2428 host->prepare_data = &atmci_prepare_data_pdc; 2429 host->submit_data = &atmci_submit_data_pdc; 2430 host->stop_transfer = &atmci_stop_transfer_pdc; 2431 } else { 2432 dev_info(&pdev->dev, "using PIO\n"); 2433 host->prepare_data = &atmci_prepare_data; 2434 host->submit_data = &atmci_submit_data; 2435 host->stop_transfer = &atmci_stop_transfer; 2436 } 2437 2438 platform_set_drvdata(pdev, host); 2439 2440 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host); 2441 2442 /* We need at least one slot to succeed */ 2443 nr_slots = 0; 2444 ret = -ENODEV; 2445 if (pdata->slot[0].bus_width) { 2446 ret = atmci_init_slot(host, &pdata->slot[0], 2447 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); 2448 if (!ret) { 2449 nr_slots++; 2450 host->buf_size = host->slot[0]->mmc->max_req_size; 2451 } 2452 } 2453 if (pdata->slot[1].bus_width) { 2454 ret = atmci_init_slot(host, &pdata->slot[1], 2455 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); 2456 if (!ret) { 2457 nr_slots++; 2458 if (host->slot[1]->mmc->max_req_size > host->buf_size) 2459 host->buf_size = 2460 host->slot[1]->mmc->max_req_size; 2461 } 2462 } 2463 2464 if (!nr_slots) { 2465 dev_err(&pdev->dev, "init failed: no slot defined\n"); 2466 goto err_init_slot; 2467 } 2468 2469 if (!host->caps.has_rwproof) { 2470 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size, 2471 &host->buf_phys_addr, 2472 GFP_KERNEL); 2473 if (!host->buffer) { 2474 ret = -ENOMEM; 2475 dev_err(&pdev->dev, "buffer allocation failed\n"); 2476 goto err_init_slot; 2477 } 2478 } 2479 2480 dev_info(&pdev->dev, 2481 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2482 host->mapbase, irq, nr_slots); 2483 2484 return 0; 2485 2486 err_init_slot: 2487 if (host->dma.chan) 2488 dma_release_channel(host->dma.chan); 2489 free_irq(irq, host); 2490 err_request_irq: 2491 iounmap(host->regs); 2492 err_ioremap: 2493 clk_put(host->mck); 2494 err_clk_get: 2495 kfree(host); 2496 return ret; 2497 } 2498 2499 static int __exit atmci_remove(struct platform_device *pdev) 2500 { 2501 struct atmel_mci *host = platform_get_drvdata(pdev); 2502 unsigned int i; 2503 2504 if (host->buffer) 2505 dma_free_coherent(&pdev->dev, host->buf_size, 2506 host->buffer, host->buf_phys_addr); 2507 2508 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2509 if (host->slot[i]) 2510 atmci_cleanup_slot(host->slot[i], i); 2511 } 2512 2513 clk_prepare_enable(host->mck); 2514 atmci_writel(host, ATMCI_IDR, ~0UL); 2515 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 2516 atmci_readl(host, ATMCI_SR); 2517 clk_disable_unprepare(host->mck); 2518 2519 if (host->dma.chan) 2520 dma_release_channel(host->dma.chan); 2521 2522 free_irq(platform_get_irq(pdev, 0), host); 2523 iounmap(host->regs); 2524 2525 clk_put(host->mck); 2526 kfree(host); 2527 2528 return 0; 2529 } 2530 2531 static struct platform_driver atmci_driver = { 2532 .remove = __exit_p(atmci_remove), 2533 .driver = { 2534 .name = "atmel_mci", 2535 .of_match_table = of_match_ptr(atmci_dt_ids), 2536 }, 2537 }; 2538 2539 static int __init atmci_init(void) 2540 { 2541 return platform_driver_probe(&atmci_driver, atmci_probe); 2542 } 2543 2544 static void __exit atmci_exit(void) 2545 { 2546 platform_driver_unregister(&atmci_driver); 2547 } 2548 2549 late_initcall(atmci_init); /* try to load after dma driver when built-in */ 2550 module_exit(atmci_exit); 2551 2552 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); 2553 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2554 MODULE_LICENSE("GPL v2"); 2555