1 /* 2 * Atmel MultiMedia Card Interface driver 3 * 4 * Copyright (C) 2004-2008 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/blkdev.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/device.h> 14 #include <linux/dmaengine.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/ioport.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_gpio.h> 26 #include <linux/platform_device.h> 27 #include <linux/scatterlist.h> 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <linux/stat.h> 31 #include <linux/types.h> 32 #include <linux/platform_data/atmel.h> 33 #include <linux/platform_data/mmc-atmel-mci.h> 34 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/sdio.h> 37 38 #include <linux/atmel-mci.h> 39 #include <linux/atmel_pdc.h> 40 41 #include <asm/cacheflush.h> 42 #include <asm/io.h> 43 #include <asm/unaligned.h> 44 45 #include "atmel-mci-regs.h" 46 47 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) 48 #define ATMCI_DMA_THRESHOLD 16 49 50 enum { 51 EVENT_CMD_RDY = 0, 52 EVENT_XFER_COMPLETE, 53 EVENT_NOTBUSY, 54 EVENT_DATA_ERROR, 55 }; 56 57 enum atmel_mci_state { 58 STATE_IDLE = 0, 59 STATE_SENDING_CMD, 60 STATE_DATA_XFER, 61 STATE_WAITING_NOTBUSY, 62 STATE_SENDING_STOP, 63 STATE_END_REQUEST, 64 }; 65 66 enum atmci_xfer_dir { 67 XFER_RECEIVE = 0, 68 XFER_TRANSMIT, 69 }; 70 71 enum atmci_pdc_buf { 72 PDC_FIRST_BUF = 0, 73 PDC_SECOND_BUF, 74 }; 75 76 struct atmel_mci_caps { 77 bool has_dma_conf_reg; 78 bool has_pdc; 79 bool has_cfg_reg; 80 bool has_cstor_reg; 81 bool has_highspeed; 82 bool has_rwproof; 83 bool has_odd_clk_div; 84 bool has_bad_data_ordering; 85 bool need_reset_after_xfer; 86 bool need_blksz_mul_4; 87 bool need_notbusy_for_read_ops; 88 }; 89 90 struct atmel_mci_dma { 91 struct dma_chan *chan; 92 struct dma_async_tx_descriptor *data_desc; 93 }; 94 95 /** 96 * struct atmel_mci - MMC controller state shared between all slots 97 * @lock: Spinlock protecting the queue and associated data. 98 * @regs: Pointer to MMIO registers. 99 * @sg: Scatterlist entry currently being processed by PIO or PDC code. 100 * @pio_offset: Offset into the current scatterlist entry. 101 * @buffer: Buffer used if we don't have the r/w proof capability. We 102 * don't have the time to switch pdc buffers so we have to use only 103 * one buffer for the full transaction. 104 * @buf_size: size of the buffer. 105 * @phys_buf_addr: buffer address needed for pdc. 106 * @cur_slot: The slot which is currently using the controller. 107 * @mrq: The request currently being processed on @cur_slot, 108 * or NULL if the controller is idle. 109 * @cmd: The command currently being sent to the card, or NULL. 110 * @data: The data currently being transferred, or NULL if no data 111 * transfer is in progress. 112 * @data_size: just data->blocks * data->blksz. 113 * @dma: DMA client state. 114 * @data_chan: DMA channel being used for the current data transfer. 115 * @cmd_status: Snapshot of SR taken upon completion of the current 116 * command. Only valid when EVENT_CMD_COMPLETE is pending. 117 * @data_status: Snapshot of SR taken upon completion of the current 118 * data transfer. Only valid when EVENT_DATA_COMPLETE or 119 * EVENT_DATA_ERROR is pending. 120 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 121 * to be sent. 122 * @tasklet: Tasklet running the request state machine. 123 * @pending_events: Bitmask of events flagged by the interrupt handler 124 * to be processed by the tasklet. 125 * @completed_events: Bitmask of events which the state machine has 126 * processed. 127 * @state: Tasklet state. 128 * @queue: List of slots waiting for access to the controller. 129 * @need_clock_update: Update the clock rate before the next request. 130 * @need_reset: Reset controller before next request. 131 * @timer: Timer to balance the data timeout error flag which cannot rise. 132 * @mode_reg: Value of the MR register. 133 * @cfg_reg: Value of the CFG register. 134 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 135 * rate and timeout calculations. 136 * @mapbase: Physical address of the MMIO registers. 137 * @mck: The peripheral bus clock hooked up to the MMC controller. 138 * @pdev: Platform device associated with the MMC controller. 139 * @slot: Slots sharing this MMC controller. 140 * @caps: MCI capabilities depending on MCI version. 141 * @prepare_data: function to setup MCI before data transfer which 142 * depends on MCI capabilities. 143 * @submit_data: function to start data transfer which depends on MCI 144 * capabilities. 145 * @stop_transfer: function to stop data transfer which depends on MCI 146 * capabilities. 147 * 148 * Locking 149 * ======= 150 * 151 * @lock is a softirq-safe spinlock protecting @queue as well as 152 * @cur_slot, @mrq and @state. These must always be updated 153 * at the same time while holding @lock. 154 * 155 * @lock also protects mode_reg and need_clock_update since these are 156 * used to synchronize mode register updates with the queue 157 * processing. 158 * 159 * The @mrq field of struct atmel_mci_slot is also protected by @lock, 160 * and must always be written at the same time as the slot is added to 161 * @queue. 162 * 163 * @pending_events and @completed_events are accessed using atomic bit 164 * operations, so they don't need any locking. 165 * 166 * None of the fields touched by the interrupt handler need any 167 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 168 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 169 * interrupts must be disabled and @data_status updated with a 170 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 171 * CMDRDY interrupt must be disabled and @cmd_status updated with a 172 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 173 * bytes_xfered field of @data must be written. This is ensured by 174 * using barriers. 175 */ 176 struct atmel_mci { 177 spinlock_t lock; 178 void __iomem *regs; 179 180 struct scatterlist *sg; 181 unsigned int sg_len; 182 unsigned int pio_offset; 183 unsigned int *buffer; 184 unsigned int buf_size; 185 dma_addr_t buf_phys_addr; 186 187 struct atmel_mci_slot *cur_slot; 188 struct mmc_request *mrq; 189 struct mmc_command *cmd; 190 struct mmc_data *data; 191 unsigned int data_size; 192 193 struct atmel_mci_dma dma; 194 struct dma_chan *data_chan; 195 struct dma_slave_config dma_conf; 196 197 u32 cmd_status; 198 u32 data_status; 199 u32 stop_cmdr; 200 201 struct tasklet_struct tasklet; 202 unsigned long pending_events; 203 unsigned long completed_events; 204 enum atmel_mci_state state; 205 struct list_head queue; 206 207 bool need_clock_update; 208 bool need_reset; 209 struct timer_list timer; 210 u32 mode_reg; 211 u32 cfg_reg; 212 unsigned long bus_hz; 213 unsigned long mapbase; 214 struct clk *mck; 215 struct platform_device *pdev; 216 217 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; 218 219 struct atmel_mci_caps caps; 220 221 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); 222 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); 223 void (*stop_transfer)(struct atmel_mci *host); 224 }; 225 226 /** 227 * struct atmel_mci_slot - MMC slot state 228 * @mmc: The mmc_host representing this slot. 229 * @host: The MMC controller this slot is using. 230 * @sdc_reg: Value of SDCR to be written before using this slot. 231 * @sdio_irq: SDIO irq mask for this slot. 232 * @mrq: mmc_request currently being processed or waiting to be 233 * processed, or NULL when the slot is idle. 234 * @queue_node: List node for placing this node in the @queue list of 235 * &struct atmel_mci. 236 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 237 * @flags: Random state bits associated with the slot. 238 * @detect_pin: GPIO pin used for card detection, or negative if not 239 * available. 240 * @wp_pin: GPIO pin used for card write protect sending, or negative 241 * if not available. 242 * @detect_is_active_high: The state of the detect pin when it is active. 243 * @detect_timer: Timer used for debouncing @detect_pin interrupts. 244 */ 245 struct atmel_mci_slot { 246 struct mmc_host *mmc; 247 struct atmel_mci *host; 248 249 u32 sdc_reg; 250 u32 sdio_irq; 251 252 struct mmc_request *mrq; 253 struct list_head queue_node; 254 255 unsigned int clock; 256 unsigned long flags; 257 #define ATMCI_CARD_PRESENT 0 258 #define ATMCI_CARD_NEED_INIT 1 259 #define ATMCI_SHUTDOWN 2 260 261 int detect_pin; 262 int wp_pin; 263 bool detect_is_active_high; 264 265 struct timer_list detect_timer; 266 }; 267 268 #define atmci_test_and_clear_pending(host, event) \ 269 test_and_clear_bit(event, &host->pending_events) 270 #define atmci_set_completed(host, event) \ 271 set_bit(event, &host->completed_events) 272 #define atmci_set_pending(host, event) \ 273 set_bit(event, &host->pending_events) 274 275 /* 276 * The debugfs stuff below is mostly optimized away when 277 * CONFIG_DEBUG_FS is not set. 278 */ 279 static int atmci_req_show(struct seq_file *s, void *v) 280 { 281 struct atmel_mci_slot *slot = s->private; 282 struct mmc_request *mrq; 283 struct mmc_command *cmd; 284 struct mmc_command *stop; 285 struct mmc_data *data; 286 287 /* Make sure we get a consistent snapshot */ 288 spin_lock_bh(&slot->host->lock); 289 mrq = slot->mrq; 290 291 if (mrq) { 292 cmd = mrq->cmd; 293 data = mrq->data; 294 stop = mrq->stop; 295 296 if (cmd) 297 seq_printf(s, 298 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 299 cmd->opcode, cmd->arg, cmd->flags, 300 cmd->resp[0], cmd->resp[1], cmd->resp[2], 301 cmd->resp[3], cmd->error); 302 if (data) 303 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 304 data->bytes_xfered, data->blocks, 305 data->blksz, data->flags, data->error); 306 if (stop) 307 seq_printf(s, 308 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 309 stop->opcode, stop->arg, stop->flags, 310 stop->resp[0], stop->resp[1], stop->resp[2], 311 stop->resp[3], stop->error); 312 } 313 314 spin_unlock_bh(&slot->host->lock); 315 316 return 0; 317 } 318 319 static int atmci_req_open(struct inode *inode, struct file *file) 320 { 321 return single_open(file, atmci_req_show, inode->i_private); 322 } 323 324 static const struct file_operations atmci_req_fops = { 325 .owner = THIS_MODULE, 326 .open = atmci_req_open, 327 .read = seq_read, 328 .llseek = seq_lseek, 329 .release = single_release, 330 }; 331 332 static void atmci_show_status_reg(struct seq_file *s, 333 const char *regname, u32 value) 334 { 335 static const char *sr_bit[] = { 336 [0] = "CMDRDY", 337 [1] = "RXRDY", 338 [2] = "TXRDY", 339 [3] = "BLKE", 340 [4] = "DTIP", 341 [5] = "NOTBUSY", 342 [6] = "ENDRX", 343 [7] = "ENDTX", 344 [8] = "SDIOIRQA", 345 [9] = "SDIOIRQB", 346 [12] = "SDIOWAIT", 347 [14] = "RXBUFF", 348 [15] = "TXBUFE", 349 [16] = "RINDE", 350 [17] = "RDIRE", 351 [18] = "RCRCE", 352 [19] = "RENDE", 353 [20] = "RTOE", 354 [21] = "DCRCE", 355 [22] = "DTOE", 356 [23] = "CSTOE", 357 [24] = "BLKOVRE", 358 [25] = "DMADONE", 359 [26] = "FIFOEMPTY", 360 [27] = "XFRDONE", 361 [30] = "OVRE", 362 [31] = "UNRE", 363 }; 364 unsigned int i; 365 366 seq_printf(s, "%s:\t0x%08x", regname, value); 367 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { 368 if (value & (1 << i)) { 369 if (sr_bit[i]) 370 seq_printf(s, " %s", sr_bit[i]); 371 else 372 seq_puts(s, " UNKNOWN"); 373 } 374 } 375 seq_putc(s, '\n'); 376 } 377 378 static int atmci_regs_show(struct seq_file *s, void *v) 379 { 380 struct atmel_mci *host = s->private; 381 u32 *buf; 382 int ret = 0; 383 384 385 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); 386 if (!buf) 387 return -ENOMEM; 388 389 /* 390 * Grab a more or less consistent snapshot. Note that we're 391 * not disabling interrupts, so IMR and SR may not be 392 * consistent. 393 */ 394 ret = clk_prepare_enable(host->mck); 395 if (ret) 396 goto out; 397 398 spin_lock_bh(&host->lock); 399 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); 400 spin_unlock_bh(&host->lock); 401 402 clk_disable_unprepare(host->mck); 403 404 seq_printf(s, "MR:\t0x%08x%s%s ", 405 buf[ATMCI_MR / 4], 406 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", 407 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : ""); 408 if (host->caps.has_odd_clk_div) 409 seq_printf(s, "{CLKDIV,CLKODD}=%u\n", 410 ((buf[ATMCI_MR / 4] & 0xff) << 1) 411 | ((buf[ATMCI_MR / 4] >> 16) & 1)); 412 else 413 seq_printf(s, "CLKDIV=%u\n", 414 (buf[ATMCI_MR / 4] & 0xff)); 415 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); 416 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); 417 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); 418 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", 419 buf[ATMCI_BLKR / 4], 420 buf[ATMCI_BLKR / 4] & 0xffff, 421 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); 422 if (host->caps.has_cstor_reg) 423 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); 424 425 /* Don't read RSPR and RDR; it will consume the data there */ 426 427 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); 428 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); 429 430 if (host->caps.has_dma_conf_reg) { 431 u32 val; 432 433 val = buf[ATMCI_DMA / 4]; 434 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", 435 val, val & 3, 436 ((val >> 4) & 3) ? 437 1 << (((val >> 4) & 3) + 1) : 1, 438 val & ATMCI_DMAEN ? " DMAEN" : ""); 439 } 440 if (host->caps.has_cfg_reg) { 441 u32 val; 442 443 val = buf[ATMCI_CFG / 4]; 444 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", 445 val, 446 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", 447 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", 448 val & ATMCI_CFG_HSMODE ? " HSMODE" : "", 449 val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); 450 } 451 452 out: 453 kfree(buf); 454 455 return ret; 456 } 457 458 static int atmci_regs_open(struct inode *inode, struct file *file) 459 { 460 return single_open(file, atmci_regs_show, inode->i_private); 461 } 462 463 static const struct file_operations atmci_regs_fops = { 464 .owner = THIS_MODULE, 465 .open = atmci_regs_open, 466 .read = seq_read, 467 .llseek = seq_lseek, 468 .release = single_release, 469 }; 470 471 static void atmci_init_debugfs(struct atmel_mci_slot *slot) 472 { 473 struct mmc_host *mmc = slot->mmc; 474 struct atmel_mci *host = slot->host; 475 struct dentry *root; 476 struct dentry *node; 477 478 root = mmc->debugfs_root; 479 if (!root) 480 return; 481 482 node = debugfs_create_file("regs", S_IRUSR, root, host, 483 &atmci_regs_fops); 484 if (IS_ERR(node)) 485 return; 486 if (!node) 487 goto err; 488 489 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); 490 if (!node) 491 goto err; 492 493 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 494 if (!node) 495 goto err; 496 497 node = debugfs_create_x32("pending_events", S_IRUSR, root, 498 (u32 *)&host->pending_events); 499 if (!node) 500 goto err; 501 502 node = debugfs_create_x32("completed_events", S_IRUSR, root, 503 (u32 *)&host->completed_events); 504 if (!node) 505 goto err; 506 507 return; 508 509 err: 510 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 511 } 512 513 #if defined(CONFIG_OF) 514 static const struct of_device_id atmci_dt_ids[] = { 515 { .compatible = "atmel,hsmci" }, 516 { /* sentinel */ } 517 }; 518 519 MODULE_DEVICE_TABLE(of, atmci_dt_ids); 520 521 static struct mci_platform_data* 522 atmci_of_init(struct platform_device *pdev) 523 { 524 struct device_node *np = pdev->dev.of_node; 525 struct device_node *cnp; 526 struct mci_platform_data *pdata; 527 u32 slot_id; 528 529 if (!np) { 530 dev_err(&pdev->dev, "device node not found\n"); 531 return ERR_PTR(-EINVAL); 532 } 533 534 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 535 if (!pdata) { 536 dev_err(&pdev->dev, "could not allocate memory for pdata\n"); 537 return ERR_PTR(-ENOMEM); 538 } 539 540 for_each_child_of_node(np, cnp) { 541 if (of_property_read_u32(cnp, "reg", &slot_id)) { 542 dev_warn(&pdev->dev, "reg property is missing for %s\n", 543 cnp->full_name); 544 continue; 545 } 546 547 if (slot_id >= ATMCI_MAX_NR_SLOTS) { 548 dev_warn(&pdev->dev, "can't have more than %d slots\n", 549 ATMCI_MAX_NR_SLOTS); 550 break; 551 } 552 553 if (of_property_read_u32(cnp, "bus-width", 554 &pdata->slot[slot_id].bus_width)) 555 pdata->slot[slot_id].bus_width = 1; 556 557 pdata->slot[slot_id].detect_pin = 558 of_get_named_gpio(cnp, "cd-gpios", 0); 559 560 pdata->slot[slot_id].detect_is_active_high = 561 of_property_read_bool(cnp, "cd-inverted"); 562 563 pdata->slot[slot_id].non_removable = 564 of_property_read_bool(cnp, "non-removable"); 565 566 pdata->slot[slot_id].wp_pin = 567 of_get_named_gpio(cnp, "wp-gpios", 0); 568 } 569 570 return pdata; 571 } 572 #else /* CONFIG_OF */ 573 static inline struct mci_platform_data* 574 atmci_of_init(struct platform_device *dev) 575 { 576 return ERR_PTR(-EINVAL); 577 } 578 #endif 579 580 static inline unsigned int atmci_get_version(struct atmel_mci *host) 581 { 582 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; 583 } 584 585 static void atmci_timeout_timer(unsigned long data) 586 { 587 struct atmel_mci *host; 588 589 host = (struct atmel_mci *)data; 590 591 dev_dbg(&host->pdev->dev, "software timeout\n"); 592 593 if (host->mrq->cmd->data) { 594 host->mrq->cmd->data->error = -ETIMEDOUT; 595 host->data = NULL; 596 /* 597 * With some SDIO modules, sometimes DMA transfer hangs. If 598 * stop_transfer() is not called then the DMA request is not 599 * removed, following ones are queued and never computed. 600 */ 601 if (host->state == STATE_DATA_XFER) 602 host->stop_transfer(host); 603 } else { 604 host->mrq->cmd->error = -ETIMEDOUT; 605 host->cmd = NULL; 606 } 607 host->need_reset = 1; 608 host->state = STATE_END_REQUEST; 609 smp_wmb(); 610 tasklet_schedule(&host->tasklet); 611 } 612 613 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, 614 unsigned int ns) 615 { 616 /* 617 * It is easier here to use us instead of ns for the timeout, 618 * it prevents from overflows during calculation. 619 */ 620 unsigned int us = DIV_ROUND_UP(ns, 1000); 621 622 /* Maximum clock frequency is host->bus_hz/2 */ 623 return us * (DIV_ROUND_UP(host->bus_hz, 2000000)); 624 } 625 626 static void atmci_set_timeout(struct atmel_mci *host, 627 struct atmel_mci_slot *slot, struct mmc_data *data) 628 { 629 static unsigned dtomul_to_shift[] = { 630 0, 4, 7, 8, 10, 12, 16, 20 631 }; 632 unsigned timeout; 633 unsigned dtocyc; 634 unsigned dtomul; 635 636 timeout = atmci_ns_to_clocks(host, data->timeout_ns) 637 + data->timeout_clks; 638 639 for (dtomul = 0; dtomul < 8; dtomul++) { 640 unsigned shift = dtomul_to_shift[dtomul]; 641 dtocyc = (timeout + (1 << shift) - 1) >> shift; 642 if (dtocyc < 15) 643 break; 644 } 645 646 if (dtomul >= 8) { 647 dtomul = 7; 648 dtocyc = 15; 649 } 650 651 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 652 dtocyc << dtomul_to_shift[dtomul]); 653 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); 654 } 655 656 /* 657 * Return mask with command flags to be enabled for this command. 658 */ 659 static u32 atmci_prepare_command(struct mmc_host *mmc, 660 struct mmc_command *cmd) 661 { 662 struct mmc_data *data; 663 u32 cmdr; 664 665 cmd->error = -EINPROGRESS; 666 667 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); 668 669 if (cmd->flags & MMC_RSP_PRESENT) { 670 if (cmd->flags & MMC_RSP_136) 671 cmdr |= ATMCI_CMDR_RSPTYP_136BIT; 672 else 673 cmdr |= ATMCI_CMDR_RSPTYP_48BIT; 674 } 675 676 /* 677 * This should really be MAXLAT_5 for CMD2 and ACMD41, but 678 * it's too difficult to determine whether this is an ACMD or 679 * not. Better make it 64. 680 */ 681 cmdr |= ATMCI_CMDR_MAXLAT_64CYC; 682 683 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) 684 cmdr |= ATMCI_CMDR_OPDCMD; 685 686 data = cmd->data; 687 if (data) { 688 cmdr |= ATMCI_CMDR_START_XFER; 689 690 if (cmd->opcode == SD_IO_RW_EXTENDED) { 691 cmdr |= ATMCI_CMDR_SDIO_BLOCK; 692 } else { 693 if (data->flags & MMC_DATA_STREAM) 694 cmdr |= ATMCI_CMDR_STREAM; 695 else if (data->blocks > 1) 696 cmdr |= ATMCI_CMDR_MULTI_BLOCK; 697 else 698 cmdr |= ATMCI_CMDR_BLOCK; 699 } 700 701 if (data->flags & MMC_DATA_READ) 702 cmdr |= ATMCI_CMDR_TRDIR_READ; 703 } 704 705 return cmdr; 706 } 707 708 static void atmci_send_command(struct atmel_mci *host, 709 struct mmc_command *cmd, u32 cmd_flags) 710 { 711 WARN_ON(host->cmd); 712 host->cmd = cmd; 713 714 dev_vdbg(&host->pdev->dev, 715 "start command: ARGR=0x%08x CMDR=0x%08x\n", 716 cmd->arg, cmd_flags); 717 718 atmci_writel(host, ATMCI_ARGR, cmd->arg); 719 atmci_writel(host, ATMCI_CMDR, cmd_flags); 720 } 721 722 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 723 { 724 dev_dbg(&host->pdev->dev, "send stop command\n"); 725 atmci_send_command(host, data->stop, host->stop_cmdr); 726 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 727 } 728 729 /* 730 * Configure given PDC buffer taking care of alignement issues. 731 * Update host->data_size and host->sg. 732 */ 733 static void atmci_pdc_set_single_buf(struct atmel_mci *host, 734 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) 735 { 736 u32 pointer_reg, counter_reg; 737 unsigned int buf_size; 738 739 if (dir == XFER_RECEIVE) { 740 pointer_reg = ATMEL_PDC_RPR; 741 counter_reg = ATMEL_PDC_RCR; 742 } else { 743 pointer_reg = ATMEL_PDC_TPR; 744 counter_reg = ATMEL_PDC_TCR; 745 } 746 747 if (buf_nb == PDC_SECOND_BUF) { 748 pointer_reg += ATMEL_PDC_SCND_BUF_OFF; 749 counter_reg += ATMEL_PDC_SCND_BUF_OFF; 750 } 751 752 if (!host->caps.has_rwproof) { 753 buf_size = host->buf_size; 754 atmci_writel(host, pointer_reg, host->buf_phys_addr); 755 } else { 756 buf_size = sg_dma_len(host->sg); 757 atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); 758 } 759 760 if (host->data_size <= buf_size) { 761 if (host->data_size & 0x3) { 762 /* If size is different from modulo 4, transfer bytes */ 763 atmci_writel(host, counter_reg, host->data_size); 764 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); 765 } else { 766 /* Else transfer 32-bits words */ 767 atmci_writel(host, counter_reg, host->data_size / 4); 768 } 769 host->data_size = 0; 770 } else { 771 /* We assume the size of a page is 32-bits aligned */ 772 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); 773 host->data_size -= sg_dma_len(host->sg); 774 if (host->data_size) 775 host->sg = sg_next(host->sg); 776 } 777 } 778 779 /* 780 * Configure PDC buffer according to the data size ie configuring one or two 781 * buffers. Don't use this function if you want to configure only the second 782 * buffer. In this case, use atmci_pdc_set_single_buf. 783 */ 784 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) 785 { 786 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); 787 if (host->data_size) 788 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); 789 } 790 791 /* 792 * Unmap sg lists, called when transfer is finished. 793 */ 794 static void atmci_pdc_cleanup(struct atmel_mci *host) 795 { 796 struct mmc_data *data = host->data; 797 798 if (data) 799 dma_unmap_sg(&host->pdev->dev, 800 data->sg, data->sg_len, 801 ((data->flags & MMC_DATA_WRITE) 802 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 803 } 804 805 /* 806 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after 807 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY 808 * interrupt needed for both transfer directions. 809 */ 810 static void atmci_pdc_complete(struct atmel_mci *host) 811 { 812 int transfer_size = host->data->blocks * host->data->blksz; 813 int i; 814 815 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 816 817 if ((!host->caps.has_rwproof) 818 && (host->data->flags & MMC_DATA_READ)) { 819 if (host->caps.has_bad_data_ordering) 820 for (i = 0; i < transfer_size; i++) 821 host->buffer[i] = swab32(host->buffer[i]); 822 sg_copy_from_buffer(host->data->sg, host->data->sg_len, 823 host->buffer, transfer_size); 824 } 825 826 atmci_pdc_cleanup(host); 827 828 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__); 829 atmci_set_pending(host, EVENT_XFER_COMPLETE); 830 tasklet_schedule(&host->tasklet); 831 } 832 833 static void atmci_dma_cleanup(struct atmel_mci *host) 834 { 835 struct mmc_data *data = host->data; 836 837 if (data) 838 dma_unmap_sg(host->dma.chan->device->dev, 839 data->sg, data->sg_len, 840 ((data->flags & MMC_DATA_WRITE) 841 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 842 } 843 844 /* 845 * This function is called by the DMA driver from tasklet context. 846 */ 847 static void atmci_dma_complete(void *arg) 848 { 849 struct atmel_mci *host = arg; 850 struct mmc_data *data = host->data; 851 852 dev_vdbg(&host->pdev->dev, "DMA complete\n"); 853 854 if (host->caps.has_dma_conf_reg) 855 /* Disable DMA hardware handshaking on MCI */ 856 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); 857 858 atmci_dma_cleanup(host); 859 860 /* 861 * If the card was removed, data will be NULL. No point trying 862 * to send the stop command or waiting for NBUSY in this case. 863 */ 864 if (data) { 865 dev_dbg(&host->pdev->dev, 866 "(%s) set pending xfer complete\n", __func__); 867 atmci_set_pending(host, EVENT_XFER_COMPLETE); 868 tasklet_schedule(&host->tasklet); 869 870 /* 871 * Regardless of what the documentation says, we have 872 * to wait for NOTBUSY even after block read 873 * operations. 874 * 875 * When the DMA transfer is complete, the controller 876 * may still be reading the CRC from the card, i.e. 877 * the data transfer is still in progress and we 878 * haven't seen all the potential error bits yet. 879 * 880 * The interrupt handler will schedule a different 881 * tasklet to finish things up when the data transfer 882 * is completely done. 883 * 884 * We may not complete the mmc request here anyway 885 * because the mmc layer may call back and cause us to 886 * violate the "don't submit new operations from the 887 * completion callback" rule of the dma engine 888 * framework. 889 */ 890 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 891 } 892 } 893 894 /* 895 * Returns a mask of interrupt flags to be enabled after the whole 896 * request has been prepared. 897 */ 898 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) 899 { 900 u32 iflags; 901 902 data->error = -EINPROGRESS; 903 904 host->sg = data->sg; 905 host->sg_len = data->sg_len; 906 host->data = data; 907 host->data_chan = NULL; 908 909 iflags = ATMCI_DATA_ERROR_FLAGS; 910 911 /* 912 * Errata: MMC data write operation with less than 12 913 * bytes is impossible. 914 * 915 * Errata: MCI Transmit Data Register (TDR) FIFO 916 * corruption when length is not multiple of 4. 917 */ 918 if (data->blocks * data->blksz < 12 919 || (data->blocks * data->blksz) & 3) 920 host->need_reset = true; 921 922 host->pio_offset = 0; 923 if (data->flags & MMC_DATA_READ) 924 iflags |= ATMCI_RXRDY; 925 else 926 iflags |= ATMCI_TXRDY; 927 928 return iflags; 929 } 930 931 /* 932 * Set interrupt flags and set block length into the MCI mode register even 933 * if this value is also accessible in the MCI block register. It seems to be 934 * necessary before the High Speed MCI version. It also map sg and configure 935 * PDC registers. 936 */ 937 static u32 938 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) 939 { 940 u32 iflags, tmp; 941 unsigned int sg_len; 942 enum dma_data_direction dir; 943 int i; 944 945 data->error = -EINPROGRESS; 946 947 host->data = data; 948 host->sg = data->sg; 949 iflags = ATMCI_DATA_ERROR_FLAGS; 950 951 /* Enable pdc mode */ 952 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); 953 954 if (data->flags & MMC_DATA_READ) { 955 dir = DMA_FROM_DEVICE; 956 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; 957 } else { 958 dir = DMA_TO_DEVICE; 959 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE; 960 } 961 962 /* Set BLKLEN */ 963 tmp = atmci_readl(host, ATMCI_MR); 964 tmp &= 0x0000ffff; 965 tmp |= ATMCI_BLKLEN(data->blksz); 966 atmci_writel(host, ATMCI_MR, tmp); 967 968 /* Configure PDC */ 969 host->data_size = data->blocks * data->blksz; 970 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir); 971 972 if ((!host->caps.has_rwproof) 973 && (host->data->flags & MMC_DATA_WRITE)) { 974 sg_copy_to_buffer(host->data->sg, host->data->sg_len, 975 host->buffer, host->data_size); 976 if (host->caps.has_bad_data_ordering) 977 for (i = 0; i < host->data_size; i++) 978 host->buffer[i] = swab32(host->buffer[i]); 979 } 980 981 if (host->data_size) 982 atmci_pdc_set_both_buf(host, 983 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT)); 984 985 return iflags; 986 } 987 988 static u32 989 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) 990 { 991 struct dma_chan *chan; 992 struct dma_async_tx_descriptor *desc; 993 struct scatterlist *sg; 994 unsigned int i; 995 enum dma_data_direction direction; 996 enum dma_transfer_direction slave_dirn; 997 unsigned int sglen; 998 u32 maxburst; 999 u32 iflags; 1000 1001 data->error = -EINPROGRESS; 1002 1003 WARN_ON(host->data); 1004 host->sg = NULL; 1005 host->data = data; 1006 1007 iflags = ATMCI_DATA_ERROR_FLAGS; 1008 1009 /* 1010 * We don't do DMA on "complex" transfers, i.e. with 1011 * non-word-aligned buffers or lengths. Also, we don't bother 1012 * with all the DMA setup overhead for short transfers. 1013 */ 1014 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 1015 return atmci_prepare_data(host, data); 1016 if (data->blksz & 3) 1017 return atmci_prepare_data(host, data); 1018 1019 for_each_sg(data->sg, sg, data->sg_len, i) { 1020 if (sg->offset & 3 || sg->length & 3) 1021 return atmci_prepare_data(host, data); 1022 } 1023 1024 /* If we don't have a channel, we can't do DMA */ 1025 chan = host->dma.chan; 1026 if (chan) 1027 host->data_chan = chan; 1028 1029 if (!chan) 1030 return -ENODEV; 1031 1032 if (data->flags & MMC_DATA_READ) { 1033 direction = DMA_FROM_DEVICE; 1034 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM; 1035 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst); 1036 } else { 1037 direction = DMA_TO_DEVICE; 1038 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV; 1039 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst); 1040 } 1041 1042 if (host->caps.has_dma_conf_reg) 1043 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | 1044 ATMCI_DMAEN); 1045 1046 sglen = dma_map_sg(chan->device->dev, data->sg, 1047 data->sg_len, direction); 1048 1049 dmaengine_slave_config(chan, &host->dma_conf); 1050 desc = dmaengine_prep_slave_sg(chan, 1051 data->sg, sglen, slave_dirn, 1052 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1053 if (!desc) 1054 goto unmap_exit; 1055 1056 host->dma.data_desc = desc; 1057 desc->callback = atmci_dma_complete; 1058 desc->callback_param = host; 1059 1060 return iflags; 1061 unmap_exit: 1062 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction); 1063 return -ENOMEM; 1064 } 1065 1066 static void 1067 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) 1068 { 1069 return; 1070 } 1071 1072 /* 1073 * Start PDC according to transfer direction. 1074 */ 1075 static void 1076 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) 1077 { 1078 if (data->flags & MMC_DATA_READ) 1079 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1080 else 1081 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1082 } 1083 1084 static void 1085 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) 1086 { 1087 struct dma_chan *chan = host->data_chan; 1088 struct dma_async_tx_descriptor *desc = host->dma.data_desc; 1089 1090 if (chan) { 1091 dmaengine_submit(desc); 1092 dma_async_issue_pending(chan); 1093 } 1094 } 1095 1096 static void atmci_stop_transfer(struct atmel_mci *host) 1097 { 1098 dev_dbg(&host->pdev->dev, 1099 "(%s) set pending xfer complete\n", __func__); 1100 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1101 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1102 } 1103 1104 /* 1105 * Stop data transfer because error(s) occurred. 1106 */ 1107 static void atmci_stop_transfer_pdc(struct atmel_mci *host) 1108 { 1109 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 1110 } 1111 1112 static void atmci_stop_transfer_dma(struct atmel_mci *host) 1113 { 1114 struct dma_chan *chan = host->data_chan; 1115 1116 if (chan) { 1117 dmaengine_terminate_all(chan); 1118 atmci_dma_cleanup(host); 1119 } else { 1120 /* Data transfer was stopped by the interrupt handler */ 1121 dev_dbg(&host->pdev->dev, 1122 "(%s) set pending xfer complete\n", __func__); 1123 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1124 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1125 } 1126 } 1127 1128 /* 1129 * Start a request: prepare data if needed, prepare the command and activate 1130 * interrupts. 1131 */ 1132 static void atmci_start_request(struct atmel_mci *host, 1133 struct atmel_mci_slot *slot) 1134 { 1135 struct mmc_request *mrq; 1136 struct mmc_command *cmd; 1137 struct mmc_data *data; 1138 u32 iflags; 1139 u32 cmdflags; 1140 1141 mrq = slot->mrq; 1142 host->cur_slot = slot; 1143 host->mrq = mrq; 1144 1145 host->pending_events = 0; 1146 host->completed_events = 0; 1147 host->cmd_status = 0; 1148 host->data_status = 0; 1149 1150 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode); 1151 1152 if (host->need_reset || host->caps.need_reset_after_xfer) { 1153 iflags = atmci_readl(host, ATMCI_IMR); 1154 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB); 1155 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1156 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1157 atmci_writel(host, ATMCI_MR, host->mode_reg); 1158 if (host->caps.has_cfg_reg) 1159 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1160 atmci_writel(host, ATMCI_IER, iflags); 1161 host->need_reset = false; 1162 } 1163 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); 1164 1165 iflags = atmci_readl(host, ATMCI_IMR); 1166 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 1167 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 1168 iflags); 1169 1170 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 1171 /* Send init sequence (74 clock cycles) */ 1172 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); 1173 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) 1174 cpu_relax(); 1175 } 1176 iflags = 0; 1177 data = mrq->data; 1178 if (data) { 1179 atmci_set_timeout(host, slot, data); 1180 1181 /* Must set block count/size before sending command */ 1182 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) 1183 | ATMCI_BLKLEN(data->blksz)); 1184 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 1185 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); 1186 1187 iflags |= host->prepare_data(host, data); 1188 } 1189 1190 iflags |= ATMCI_CMDRDY; 1191 cmd = mrq->cmd; 1192 cmdflags = atmci_prepare_command(slot->mmc, cmd); 1193 1194 /* 1195 * DMA transfer should be started before sending the command to avoid 1196 * unexpected errors especially for read operations in SDIO mode. 1197 * Unfortunately, in PDC mode, command has to be sent before starting 1198 * the transfer. 1199 */ 1200 if (host->submit_data != &atmci_submit_data_dma) 1201 atmci_send_command(host, cmd, cmdflags); 1202 1203 if (data) 1204 host->submit_data(host, data); 1205 1206 if (host->submit_data == &atmci_submit_data_dma) 1207 atmci_send_command(host, cmd, cmdflags); 1208 1209 if (mrq->stop) { 1210 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 1211 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; 1212 if (!(data->flags & MMC_DATA_WRITE)) 1213 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; 1214 if (data->flags & MMC_DATA_STREAM) 1215 host->stop_cmdr |= ATMCI_CMDR_STREAM; 1216 else 1217 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; 1218 } 1219 1220 /* 1221 * We could have enabled interrupts earlier, but I suspect 1222 * that would open up a nice can of interesting race 1223 * conditions (e.g. command and data complete, but stop not 1224 * prepared yet.) 1225 */ 1226 atmci_writel(host, ATMCI_IER, iflags); 1227 1228 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); 1229 } 1230 1231 static void atmci_queue_request(struct atmel_mci *host, 1232 struct atmel_mci_slot *slot, struct mmc_request *mrq) 1233 { 1234 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1235 host->state); 1236 1237 spin_lock_bh(&host->lock); 1238 slot->mrq = mrq; 1239 if (host->state == STATE_IDLE) { 1240 host->state = STATE_SENDING_CMD; 1241 atmci_start_request(host, slot); 1242 } else { 1243 dev_dbg(&host->pdev->dev, "queue request\n"); 1244 list_add_tail(&slot->queue_node, &host->queue); 1245 } 1246 spin_unlock_bh(&host->lock); 1247 } 1248 1249 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1250 { 1251 struct atmel_mci_slot *slot = mmc_priv(mmc); 1252 struct atmel_mci *host = slot->host; 1253 struct mmc_data *data; 1254 1255 WARN_ON(slot->mrq); 1256 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode); 1257 1258 /* 1259 * We may "know" the card is gone even though there's still an 1260 * electrical connection. If so, we really need to communicate 1261 * this to the MMC core since there won't be any more 1262 * interrupts as the card is completely removed. Otherwise, 1263 * the MMC core might believe the card is still there even 1264 * though the card was just removed very slowly. 1265 */ 1266 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { 1267 mrq->cmd->error = -ENOMEDIUM; 1268 mmc_request_done(mmc, mrq); 1269 return; 1270 } 1271 1272 /* We don't support multiple blocks of weird lengths. */ 1273 data = mrq->data; 1274 if (data && data->blocks > 1 && data->blksz & 3) { 1275 mrq->cmd->error = -EINVAL; 1276 mmc_request_done(mmc, mrq); 1277 } 1278 1279 atmci_queue_request(host, slot, mrq); 1280 } 1281 1282 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1283 { 1284 struct atmel_mci_slot *slot = mmc_priv(mmc); 1285 struct atmel_mci *host = slot->host; 1286 unsigned int i; 1287 bool unprepare_clk; 1288 1289 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; 1290 switch (ios->bus_width) { 1291 case MMC_BUS_WIDTH_1: 1292 slot->sdc_reg |= ATMCI_SDCBUS_1BIT; 1293 break; 1294 case MMC_BUS_WIDTH_4: 1295 slot->sdc_reg |= ATMCI_SDCBUS_4BIT; 1296 break; 1297 } 1298 1299 if (ios->clock) { 1300 unsigned int clock_min = ~0U; 1301 u32 clkdiv; 1302 1303 clk_prepare(host->mck); 1304 unprepare_clk = true; 1305 1306 spin_lock_bh(&host->lock); 1307 if (!host->mode_reg) { 1308 clk_enable(host->mck); 1309 unprepare_clk = false; 1310 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1311 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1312 if (host->caps.has_cfg_reg) 1313 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1314 } 1315 1316 /* 1317 * Use mirror of ios->clock to prevent race with mmc 1318 * core ios update when finding the minimum. 1319 */ 1320 slot->clock = ios->clock; 1321 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1322 if (host->slot[i] && host->slot[i]->clock 1323 && host->slot[i]->clock < clock_min) 1324 clock_min = host->slot[i]->clock; 1325 } 1326 1327 /* Calculate clock divider */ 1328 if (host->caps.has_odd_clk_div) { 1329 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; 1330 if (clkdiv > 511) { 1331 dev_warn(&mmc->class_dev, 1332 "clock %u too slow; using %lu\n", 1333 clock_min, host->bus_hz / (511 + 2)); 1334 clkdiv = 511; 1335 } 1336 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) 1337 | ATMCI_MR_CLKODD(clkdiv & 1); 1338 } else { 1339 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; 1340 if (clkdiv > 255) { 1341 dev_warn(&mmc->class_dev, 1342 "clock %u too slow; using %lu\n", 1343 clock_min, host->bus_hz / (2 * 256)); 1344 clkdiv = 255; 1345 } 1346 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); 1347 } 1348 1349 /* 1350 * WRPROOF and RDPROOF prevent overruns/underruns by 1351 * stopping the clock when the FIFO is full/empty. 1352 * This state is not expected to last for long. 1353 */ 1354 if (host->caps.has_rwproof) 1355 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); 1356 1357 if (host->caps.has_cfg_reg) { 1358 /* setup High Speed mode in relation with card capacity */ 1359 if (ios->timing == MMC_TIMING_SD_HS) 1360 host->cfg_reg |= ATMCI_CFG_HSMODE; 1361 else 1362 host->cfg_reg &= ~ATMCI_CFG_HSMODE; 1363 } 1364 1365 if (list_empty(&host->queue)) { 1366 atmci_writel(host, ATMCI_MR, host->mode_reg); 1367 if (host->caps.has_cfg_reg) 1368 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1369 } else { 1370 host->need_clock_update = true; 1371 } 1372 1373 spin_unlock_bh(&host->lock); 1374 } else { 1375 bool any_slot_active = false; 1376 1377 unprepare_clk = false; 1378 1379 spin_lock_bh(&host->lock); 1380 slot->clock = 0; 1381 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1382 if (host->slot[i] && host->slot[i]->clock) { 1383 any_slot_active = true; 1384 break; 1385 } 1386 } 1387 if (!any_slot_active) { 1388 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 1389 if (host->mode_reg) { 1390 atmci_readl(host, ATMCI_MR); 1391 clk_disable(host->mck); 1392 unprepare_clk = true; 1393 } 1394 host->mode_reg = 0; 1395 } 1396 spin_unlock_bh(&host->lock); 1397 } 1398 1399 if (unprepare_clk) 1400 clk_unprepare(host->mck); 1401 1402 switch (ios->power_mode) { 1403 case MMC_POWER_OFF: 1404 if (!IS_ERR(mmc->supply.vmmc)) 1405 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1406 break; 1407 case MMC_POWER_UP: 1408 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); 1409 if (!IS_ERR(mmc->supply.vmmc)) 1410 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1411 break; 1412 default: 1413 /* 1414 * TODO: None of the currently available AVR32-based 1415 * boards allow MMC power to be turned off. Implement 1416 * power control when this can be tested properly. 1417 * 1418 * We also need to hook this into the clock management 1419 * somehow so that newly inserted cards aren't 1420 * subjected to a fast clock before we have a chance 1421 * to figure out what the maximum rate is. Currently, 1422 * there's no way to avoid this, and there never will 1423 * be for boards that don't support power control. 1424 */ 1425 break; 1426 } 1427 } 1428 1429 static int atmci_get_ro(struct mmc_host *mmc) 1430 { 1431 int read_only = -ENOSYS; 1432 struct atmel_mci_slot *slot = mmc_priv(mmc); 1433 1434 if (gpio_is_valid(slot->wp_pin)) { 1435 read_only = gpio_get_value(slot->wp_pin); 1436 dev_dbg(&mmc->class_dev, "card is %s\n", 1437 read_only ? "read-only" : "read-write"); 1438 } 1439 1440 return read_only; 1441 } 1442 1443 static int atmci_get_cd(struct mmc_host *mmc) 1444 { 1445 int present = -ENOSYS; 1446 struct atmel_mci_slot *slot = mmc_priv(mmc); 1447 1448 if (gpio_is_valid(slot->detect_pin)) { 1449 present = !(gpio_get_value(slot->detect_pin) ^ 1450 slot->detect_is_active_high); 1451 dev_dbg(&mmc->class_dev, "card is %spresent\n", 1452 present ? "" : "not "); 1453 } 1454 1455 return present; 1456 } 1457 1458 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1459 { 1460 struct atmel_mci_slot *slot = mmc_priv(mmc); 1461 struct atmel_mci *host = slot->host; 1462 1463 if (enable) 1464 atmci_writel(host, ATMCI_IER, slot->sdio_irq); 1465 else 1466 atmci_writel(host, ATMCI_IDR, slot->sdio_irq); 1467 } 1468 1469 static const struct mmc_host_ops atmci_ops = { 1470 .request = atmci_request, 1471 .set_ios = atmci_set_ios, 1472 .get_ro = atmci_get_ro, 1473 .get_cd = atmci_get_cd, 1474 .enable_sdio_irq = atmci_enable_sdio_irq, 1475 }; 1476 1477 /* Called with host->lock held */ 1478 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) 1479 __releases(&host->lock) 1480 __acquires(&host->lock) 1481 { 1482 struct atmel_mci_slot *slot = NULL; 1483 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1484 1485 WARN_ON(host->cmd || host->data); 1486 1487 /* 1488 * Update the MMC clock rate if necessary. This may be 1489 * necessary if set_ios() is called when a different slot is 1490 * busy transferring data. 1491 */ 1492 if (host->need_clock_update) { 1493 atmci_writel(host, ATMCI_MR, host->mode_reg); 1494 if (host->caps.has_cfg_reg) 1495 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1496 } 1497 1498 host->cur_slot->mrq = NULL; 1499 host->mrq = NULL; 1500 if (!list_empty(&host->queue)) { 1501 slot = list_entry(host->queue.next, 1502 struct atmel_mci_slot, queue_node); 1503 list_del(&slot->queue_node); 1504 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 1505 mmc_hostname(slot->mmc)); 1506 host->state = STATE_SENDING_CMD; 1507 atmci_start_request(host, slot); 1508 } else { 1509 dev_vdbg(&host->pdev->dev, "list empty\n"); 1510 host->state = STATE_IDLE; 1511 } 1512 1513 del_timer(&host->timer); 1514 1515 spin_unlock(&host->lock); 1516 mmc_request_done(prev_mmc, mrq); 1517 spin_lock(&host->lock); 1518 } 1519 1520 static void atmci_command_complete(struct atmel_mci *host, 1521 struct mmc_command *cmd) 1522 { 1523 u32 status = host->cmd_status; 1524 1525 /* Read the response from the card (up to 16 bytes) */ 1526 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); 1527 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); 1528 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); 1529 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); 1530 1531 if (status & ATMCI_RTOE) 1532 cmd->error = -ETIMEDOUT; 1533 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) 1534 cmd->error = -EILSEQ; 1535 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) 1536 cmd->error = -EIO; 1537 else if (host->mrq->data && (host->mrq->data->blksz & 3)) { 1538 if (host->caps.need_blksz_mul_4) { 1539 cmd->error = -EINVAL; 1540 host->need_reset = 1; 1541 } 1542 } else 1543 cmd->error = 0; 1544 } 1545 1546 static void atmci_detect_change(unsigned long data) 1547 { 1548 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; 1549 bool present; 1550 bool present_old; 1551 1552 /* 1553 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before 1554 * freeing the interrupt. We must not re-enable the interrupt 1555 * if it has been freed, and if we're shutting down, it 1556 * doesn't really matter whether the card is present or not. 1557 */ 1558 smp_rmb(); 1559 if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) 1560 return; 1561 1562 enable_irq(gpio_to_irq(slot->detect_pin)); 1563 present = !(gpio_get_value(slot->detect_pin) ^ 1564 slot->detect_is_active_high); 1565 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1566 1567 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 1568 present, present_old); 1569 1570 if (present != present_old) { 1571 struct atmel_mci *host = slot->host; 1572 struct mmc_request *mrq; 1573 1574 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1575 present ? "inserted" : "removed"); 1576 1577 spin_lock(&host->lock); 1578 1579 if (!present) 1580 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1581 else 1582 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1583 1584 /* Clean up queue if present */ 1585 mrq = slot->mrq; 1586 if (mrq) { 1587 if (mrq == host->mrq) { 1588 /* 1589 * Reset controller to terminate any ongoing 1590 * commands or data transfers. 1591 */ 1592 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1593 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1594 atmci_writel(host, ATMCI_MR, host->mode_reg); 1595 if (host->caps.has_cfg_reg) 1596 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1597 1598 host->data = NULL; 1599 host->cmd = NULL; 1600 1601 switch (host->state) { 1602 case STATE_IDLE: 1603 break; 1604 case STATE_SENDING_CMD: 1605 mrq->cmd->error = -ENOMEDIUM; 1606 if (mrq->data) 1607 host->stop_transfer(host); 1608 break; 1609 case STATE_DATA_XFER: 1610 mrq->data->error = -ENOMEDIUM; 1611 host->stop_transfer(host); 1612 break; 1613 case STATE_WAITING_NOTBUSY: 1614 mrq->data->error = -ENOMEDIUM; 1615 break; 1616 case STATE_SENDING_STOP: 1617 mrq->stop->error = -ENOMEDIUM; 1618 break; 1619 case STATE_END_REQUEST: 1620 break; 1621 } 1622 1623 atmci_request_end(host, mrq); 1624 } else { 1625 list_del(&slot->queue_node); 1626 mrq->cmd->error = -ENOMEDIUM; 1627 if (mrq->data) 1628 mrq->data->error = -ENOMEDIUM; 1629 if (mrq->stop) 1630 mrq->stop->error = -ENOMEDIUM; 1631 1632 spin_unlock(&host->lock); 1633 mmc_request_done(slot->mmc, mrq); 1634 spin_lock(&host->lock); 1635 } 1636 } 1637 spin_unlock(&host->lock); 1638 1639 mmc_detect_change(slot->mmc, 0); 1640 } 1641 } 1642 1643 static void atmci_tasklet_func(unsigned long priv) 1644 { 1645 struct atmel_mci *host = (struct atmel_mci *)priv; 1646 struct mmc_request *mrq = host->mrq; 1647 struct mmc_data *data = host->data; 1648 enum atmel_mci_state state = host->state; 1649 enum atmel_mci_state prev_state; 1650 u32 status; 1651 1652 spin_lock(&host->lock); 1653 1654 state = host->state; 1655 1656 dev_vdbg(&host->pdev->dev, 1657 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1658 state, host->pending_events, host->completed_events, 1659 atmci_readl(host, ATMCI_IMR)); 1660 1661 do { 1662 prev_state = state; 1663 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state); 1664 1665 switch (state) { 1666 case STATE_IDLE: 1667 break; 1668 1669 case STATE_SENDING_CMD: 1670 /* 1671 * Command has been sent, we are waiting for command 1672 * ready. Then we have three next states possible: 1673 * END_REQUEST by default, WAITING_NOTBUSY if it's a 1674 * command needing it or DATA_XFER if there is data. 1675 */ 1676 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1677 if (!atmci_test_and_clear_pending(host, 1678 EVENT_CMD_RDY)) 1679 break; 1680 1681 dev_dbg(&host->pdev->dev, "set completed cmd ready\n"); 1682 host->cmd = NULL; 1683 atmci_set_completed(host, EVENT_CMD_RDY); 1684 atmci_command_complete(host, mrq->cmd); 1685 if (mrq->data) { 1686 dev_dbg(&host->pdev->dev, 1687 "command with data transfer"); 1688 /* 1689 * If there is a command error don't start 1690 * data transfer. 1691 */ 1692 if (mrq->cmd->error) { 1693 host->stop_transfer(host); 1694 host->data = NULL; 1695 atmci_writel(host, ATMCI_IDR, 1696 ATMCI_TXRDY | ATMCI_RXRDY 1697 | ATMCI_DATA_ERROR_FLAGS); 1698 state = STATE_END_REQUEST; 1699 } else 1700 state = STATE_DATA_XFER; 1701 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) { 1702 dev_dbg(&host->pdev->dev, 1703 "command response need waiting notbusy"); 1704 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1705 state = STATE_WAITING_NOTBUSY; 1706 } else 1707 state = STATE_END_REQUEST; 1708 1709 break; 1710 1711 case STATE_DATA_XFER: 1712 if (atmci_test_and_clear_pending(host, 1713 EVENT_DATA_ERROR)) { 1714 dev_dbg(&host->pdev->dev, "set completed data error\n"); 1715 atmci_set_completed(host, EVENT_DATA_ERROR); 1716 state = STATE_END_REQUEST; 1717 break; 1718 } 1719 1720 /* 1721 * A data transfer is in progress. The event expected 1722 * to move to the next state depends of data transfer 1723 * type (PDC or DMA). Once transfer done we can move 1724 * to the next step which is WAITING_NOTBUSY in write 1725 * case and directly SENDING_STOP in read case. 1726 */ 1727 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n"); 1728 if (!atmci_test_and_clear_pending(host, 1729 EVENT_XFER_COMPLETE)) 1730 break; 1731 1732 dev_dbg(&host->pdev->dev, 1733 "(%s) set completed xfer complete\n", 1734 __func__); 1735 atmci_set_completed(host, EVENT_XFER_COMPLETE); 1736 1737 if (host->caps.need_notbusy_for_read_ops || 1738 (host->data->flags & MMC_DATA_WRITE)) { 1739 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1740 state = STATE_WAITING_NOTBUSY; 1741 } else if (host->mrq->stop) { 1742 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 1743 atmci_send_stop_cmd(host, data); 1744 state = STATE_SENDING_STOP; 1745 } else { 1746 host->data = NULL; 1747 data->bytes_xfered = data->blocks * data->blksz; 1748 data->error = 0; 1749 state = STATE_END_REQUEST; 1750 } 1751 break; 1752 1753 case STATE_WAITING_NOTBUSY: 1754 /* 1755 * We can be in the state for two reasons: a command 1756 * requiring waiting not busy signal (stop command 1757 * included) or a write operation. In the latest case, 1758 * we need to send a stop command. 1759 */ 1760 dev_dbg(&host->pdev->dev, "FSM: not busy?\n"); 1761 if (!atmci_test_and_clear_pending(host, 1762 EVENT_NOTBUSY)) 1763 break; 1764 1765 dev_dbg(&host->pdev->dev, "set completed not busy\n"); 1766 atmci_set_completed(host, EVENT_NOTBUSY); 1767 1768 if (host->data) { 1769 /* 1770 * For some commands such as CMD53, even if 1771 * there is data transfer, there is no stop 1772 * command to send. 1773 */ 1774 if (host->mrq->stop) { 1775 atmci_writel(host, ATMCI_IER, 1776 ATMCI_CMDRDY); 1777 atmci_send_stop_cmd(host, data); 1778 state = STATE_SENDING_STOP; 1779 } else { 1780 host->data = NULL; 1781 data->bytes_xfered = data->blocks 1782 * data->blksz; 1783 data->error = 0; 1784 state = STATE_END_REQUEST; 1785 } 1786 } else 1787 state = STATE_END_REQUEST; 1788 break; 1789 1790 case STATE_SENDING_STOP: 1791 /* 1792 * In this state, it is important to set host->data to 1793 * NULL (which is tested in the waiting notbusy state) 1794 * in order to go to the end request state instead of 1795 * sending stop again. 1796 */ 1797 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1798 if (!atmci_test_and_clear_pending(host, 1799 EVENT_CMD_RDY)) 1800 break; 1801 1802 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n"); 1803 host->cmd = NULL; 1804 data->bytes_xfered = data->blocks * data->blksz; 1805 data->error = 0; 1806 atmci_command_complete(host, mrq->stop); 1807 if (mrq->stop->error) { 1808 host->stop_transfer(host); 1809 atmci_writel(host, ATMCI_IDR, 1810 ATMCI_TXRDY | ATMCI_RXRDY 1811 | ATMCI_DATA_ERROR_FLAGS); 1812 state = STATE_END_REQUEST; 1813 } else { 1814 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1815 state = STATE_WAITING_NOTBUSY; 1816 } 1817 host->data = NULL; 1818 break; 1819 1820 case STATE_END_REQUEST: 1821 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY 1822 | ATMCI_DATA_ERROR_FLAGS); 1823 status = host->data_status; 1824 if (unlikely(status)) { 1825 host->stop_transfer(host); 1826 host->data = NULL; 1827 if (data) { 1828 if (status & ATMCI_DTOE) { 1829 data->error = -ETIMEDOUT; 1830 } else if (status & ATMCI_DCRCE) { 1831 data->error = -EILSEQ; 1832 } else { 1833 data->error = -EIO; 1834 } 1835 } 1836 } 1837 1838 atmci_request_end(host, host->mrq); 1839 state = STATE_IDLE; 1840 break; 1841 } 1842 } while (state != prev_state); 1843 1844 host->state = state; 1845 1846 spin_unlock(&host->lock); 1847 } 1848 1849 static void atmci_read_data_pio(struct atmel_mci *host) 1850 { 1851 struct scatterlist *sg = host->sg; 1852 void *buf = sg_virt(sg); 1853 unsigned int offset = host->pio_offset; 1854 struct mmc_data *data = host->data; 1855 u32 value; 1856 u32 status; 1857 unsigned int nbytes = 0; 1858 1859 do { 1860 value = atmci_readl(host, ATMCI_RDR); 1861 if (likely(offset + 4 <= sg->length)) { 1862 put_unaligned(value, (u32 *)(buf + offset)); 1863 1864 offset += 4; 1865 nbytes += 4; 1866 1867 if (offset == sg->length) { 1868 flush_dcache_page(sg_page(sg)); 1869 host->sg = sg = sg_next(sg); 1870 host->sg_len--; 1871 if (!sg || !host->sg_len) 1872 goto done; 1873 1874 offset = 0; 1875 buf = sg_virt(sg); 1876 } 1877 } else { 1878 unsigned int remaining = sg->length - offset; 1879 memcpy(buf + offset, &value, remaining); 1880 nbytes += remaining; 1881 1882 flush_dcache_page(sg_page(sg)); 1883 host->sg = sg = sg_next(sg); 1884 host->sg_len--; 1885 if (!sg || !host->sg_len) 1886 goto done; 1887 1888 offset = 4 - remaining; 1889 buf = sg_virt(sg); 1890 memcpy(buf, (u8 *)&value + remaining, offset); 1891 nbytes += offset; 1892 } 1893 1894 status = atmci_readl(host, ATMCI_SR); 1895 if (status & ATMCI_DATA_ERROR_FLAGS) { 1896 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY 1897 | ATMCI_DATA_ERROR_FLAGS)); 1898 host->data_status = status; 1899 data->bytes_xfered += nbytes; 1900 return; 1901 } 1902 } while (status & ATMCI_RXRDY); 1903 1904 host->pio_offset = offset; 1905 data->bytes_xfered += nbytes; 1906 1907 return; 1908 1909 done: 1910 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); 1911 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1912 data->bytes_xfered += nbytes; 1913 smp_wmb(); 1914 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1915 } 1916 1917 static void atmci_write_data_pio(struct atmel_mci *host) 1918 { 1919 struct scatterlist *sg = host->sg; 1920 void *buf = sg_virt(sg); 1921 unsigned int offset = host->pio_offset; 1922 struct mmc_data *data = host->data; 1923 u32 value; 1924 u32 status; 1925 unsigned int nbytes = 0; 1926 1927 do { 1928 if (likely(offset + 4 <= sg->length)) { 1929 value = get_unaligned((u32 *)(buf + offset)); 1930 atmci_writel(host, ATMCI_TDR, value); 1931 1932 offset += 4; 1933 nbytes += 4; 1934 if (offset == sg->length) { 1935 host->sg = sg = sg_next(sg); 1936 host->sg_len--; 1937 if (!sg || !host->sg_len) 1938 goto done; 1939 1940 offset = 0; 1941 buf = sg_virt(sg); 1942 } 1943 } else { 1944 unsigned int remaining = sg->length - offset; 1945 1946 value = 0; 1947 memcpy(&value, buf + offset, remaining); 1948 nbytes += remaining; 1949 1950 host->sg = sg = sg_next(sg); 1951 host->sg_len--; 1952 if (!sg || !host->sg_len) { 1953 atmci_writel(host, ATMCI_TDR, value); 1954 goto done; 1955 } 1956 1957 offset = 4 - remaining; 1958 buf = sg_virt(sg); 1959 memcpy((u8 *)&value + remaining, buf, offset); 1960 atmci_writel(host, ATMCI_TDR, value); 1961 nbytes += offset; 1962 } 1963 1964 status = atmci_readl(host, ATMCI_SR); 1965 if (status & ATMCI_DATA_ERROR_FLAGS) { 1966 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY 1967 | ATMCI_DATA_ERROR_FLAGS)); 1968 host->data_status = status; 1969 data->bytes_xfered += nbytes; 1970 return; 1971 } 1972 } while (status & ATMCI_TXRDY); 1973 1974 host->pio_offset = offset; 1975 data->bytes_xfered += nbytes; 1976 1977 return; 1978 1979 done: 1980 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); 1981 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1982 data->bytes_xfered += nbytes; 1983 smp_wmb(); 1984 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1985 } 1986 1987 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) 1988 { 1989 int i; 1990 1991 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1992 struct atmel_mci_slot *slot = host->slot[i]; 1993 if (slot && (status & slot->sdio_irq)) { 1994 mmc_signal_sdio_irq(slot->mmc); 1995 } 1996 } 1997 } 1998 1999 2000 static irqreturn_t atmci_interrupt(int irq, void *dev_id) 2001 { 2002 struct atmel_mci *host = dev_id; 2003 u32 status, mask, pending; 2004 unsigned int pass_count = 0; 2005 2006 do { 2007 status = atmci_readl(host, ATMCI_SR); 2008 mask = atmci_readl(host, ATMCI_IMR); 2009 pending = status & mask; 2010 if (!pending) 2011 break; 2012 2013 if (pending & ATMCI_DATA_ERROR_FLAGS) { 2014 dev_dbg(&host->pdev->dev, "IRQ: data error\n"); 2015 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS 2016 | ATMCI_RXRDY | ATMCI_TXRDY 2017 | ATMCI_ENDRX | ATMCI_ENDTX 2018 | ATMCI_RXBUFF | ATMCI_TXBUFE); 2019 2020 host->data_status = status; 2021 dev_dbg(&host->pdev->dev, "set pending data error\n"); 2022 smp_wmb(); 2023 atmci_set_pending(host, EVENT_DATA_ERROR); 2024 tasklet_schedule(&host->tasklet); 2025 } 2026 2027 if (pending & ATMCI_TXBUFE) { 2028 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n"); 2029 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); 2030 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2031 /* 2032 * We can receive this interruption before having configured 2033 * the second pdc buffer, so we need to reconfigure first and 2034 * second buffers again 2035 */ 2036 if (host->data_size) { 2037 atmci_pdc_set_both_buf(host, XFER_TRANSMIT); 2038 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2039 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); 2040 } else { 2041 atmci_pdc_complete(host); 2042 } 2043 } else if (pending & ATMCI_ENDTX) { 2044 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n"); 2045 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2046 2047 if (host->data_size) { 2048 atmci_pdc_set_single_buf(host, 2049 XFER_TRANSMIT, PDC_SECOND_BUF); 2050 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2051 } 2052 } 2053 2054 if (pending & ATMCI_RXBUFF) { 2055 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n"); 2056 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); 2057 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2058 /* 2059 * We can receive this interruption before having configured 2060 * the second pdc buffer, so we need to reconfigure first and 2061 * second buffers again 2062 */ 2063 if (host->data_size) { 2064 atmci_pdc_set_both_buf(host, XFER_RECEIVE); 2065 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2066 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); 2067 } else { 2068 atmci_pdc_complete(host); 2069 } 2070 } else if (pending & ATMCI_ENDRX) { 2071 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n"); 2072 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2073 2074 if (host->data_size) { 2075 atmci_pdc_set_single_buf(host, 2076 XFER_RECEIVE, PDC_SECOND_BUF); 2077 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2078 } 2079 } 2080 2081 /* 2082 * First mci IPs, so mainly the ones having pdc, have some 2083 * issues with the notbusy signal. You can't get it after 2084 * data transmission if you have not sent a stop command. 2085 * The appropriate workaround is to use the BLKE signal. 2086 */ 2087 if (pending & ATMCI_BLKE) { 2088 dev_dbg(&host->pdev->dev, "IRQ: blke\n"); 2089 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE); 2090 smp_wmb(); 2091 dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2092 atmci_set_pending(host, EVENT_NOTBUSY); 2093 tasklet_schedule(&host->tasklet); 2094 } 2095 2096 if (pending & ATMCI_NOTBUSY) { 2097 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n"); 2098 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY); 2099 smp_wmb(); 2100 dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2101 atmci_set_pending(host, EVENT_NOTBUSY); 2102 tasklet_schedule(&host->tasklet); 2103 } 2104 2105 if (pending & ATMCI_RXRDY) 2106 atmci_read_data_pio(host); 2107 if (pending & ATMCI_TXRDY) 2108 atmci_write_data_pio(host); 2109 2110 if (pending & ATMCI_CMDRDY) { 2111 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n"); 2112 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); 2113 host->cmd_status = status; 2114 smp_wmb(); 2115 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n"); 2116 atmci_set_pending(host, EVENT_CMD_RDY); 2117 tasklet_schedule(&host->tasklet); 2118 } 2119 2120 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 2121 atmci_sdio_interrupt(host, status); 2122 2123 } while (pass_count++ < 5); 2124 2125 return pass_count ? IRQ_HANDLED : IRQ_NONE; 2126 } 2127 2128 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) 2129 { 2130 struct atmel_mci_slot *slot = dev_id; 2131 2132 /* 2133 * Disable interrupts until the pin has stabilized and check 2134 * the state then. Use mod_timer() since we may be in the 2135 * middle of the timer routine when this interrupt triggers. 2136 */ 2137 disable_irq_nosync(irq); 2138 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); 2139 2140 return IRQ_HANDLED; 2141 } 2142 2143 static int __init atmci_init_slot(struct atmel_mci *host, 2144 struct mci_slot_pdata *slot_data, unsigned int id, 2145 u32 sdc_reg, u32 sdio_irq) 2146 { 2147 struct mmc_host *mmc; 2148 struct atmel_mci_slot *slot; 2149 2150 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 2151 if (!mmc) 2152 return -ENOMEM; 2153 2154 slot = mmc_priv(mmc); 2155 slot->mmc = mmc; 2156 slot->host = host; 2157 slot->detect_pin = slot_data->detect_pin; 2158 slot->wp_pin = slot_data->wp_pin; 2159 slot->detect_is_active_high = slot_data->detect_is_active_high; 2160 slot->sdc_reg = sdc_reg; 2161 slot->sdio_irq = sdio_irq; 2162 2163 dev_dbg(&mmc->class_dev, 2164 "slot[%u]: bus_width=%u, detect_pin=%d, " 2165 "detect_is_active_high=%s, wp_pin=%d\n", 2166 id, slot_data->bus_width, slot_data->detect_pin, 2167 slot_data->detect_is_active_high ? "true" : "false", 2168 slot_data->wp_pin); 2169 2170 mmc->ops = &atmci_ops; 2171 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); 2172 mmc->f_max = host->bus_hz / 2; 2173 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2174 if (sdio_irq) 2175 mmc->caps |= MMC_CAP_SDIO_IRQ; 2176 if (host->caps.has_highspeed) 2177 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2178 /* 2179 * Without the read/write proof capability, it is strongly suggested to 2180 * use only one bit for data to prevent fifo underruns and overruns 2181 * which will corrupt data. 2182 */ 2183 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) 2184 mmc->caps |= MMC_CAP_4_BIT_DATA; 2185 2186 if (atmci_get_version(host) < 0x200) { 2187 mmc->max_segs = 256; 2188 mmc->max_blk_size = 4095; 2189 mmc->max_blk_count = 256; 2190 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2191 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs; 2192 } else { 2193 mmc->max_segs = 64; 2194 mmc->max_req_size = 32768 * 512; 2195 mmc->max_blk_size = 32768; 2196 mmc->max_blk_count = 512; 2197 } 2198 2199 /* Assume card is present initially */ 2200 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 2201 if (gpio_is_valid(slot->detect_pin)) { 2202 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin, 2203 "mmc_detect")) { 2204 dev_dbg(&mmc->class_dev, "no detect pin available\n"); 2205 slot->detect_pin = -EBUSY; 2206 } else if (gpio_get_value(slot->detect_pin) ^ 2207 slot->detect_is_active_high) { 2208 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 2209 } 2210 } 2211 2212 if (!gpio_is_valid(slot->detect_pin)) { 2213 if (slot_data->non_removable) 2214 mmc->caps |= MMC_CAP_NONREMOVABLE; 2215 else 2216 mmc->caps |= MMC_CAP_NEEDS_POLL; 2217 } 2218 2219 if (gpio_is_valid(slot->wp_pin)) { 2220 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin, 2221 "mmc_wp")) { 2222 dev_dbg(&mmc->class_dev, "no WP pin available\n"); 2223 slot->wp_pin = -EBUSY; 2224 } 2225 } 2226 2227 host->slot[id] = slot; 2228 mmc_regulator_get_supply(mmc); 2229 mmc_add_host(mmc); 2230 2231 if (gpio_is_valid(slot->detect_pin)) { 2232 int ret; 2233 2234 setup_timer(&slot->detect_timer, atmci_detect_change, 2235 (unsigned long)slot); 2236 2237 ret = request_irq(gpio_to_irq(slot->detect_pin), 2238 atmci_detect_interrupt, 2239 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 2240 "mmc-detect", slot); 2241 if (ret) { 2242 dev_dbg(&mmc->class_dev, 2243 "could not request IRQ %d for detect pin\n", 2244 gpio_to_irq(slot->detect_pin)); 2245 slot->detect_pin = -EBUSY; 2246 } 2247 } 2248 2249 atmci_init_debugfs(slot); 2250 2251 return 0; 2252 } 2253 2254 static void atmci_cleanup_slot(struct atmel_mci_slot *slot, 2255 unsigned int id) 2256 { 2257 /* Debugfs stuff is cleaned up by mmc core */ 2258 2259 set_bit(ATMCI_SHUTDOWN, &slot->flags); 2260 smp_wmb(); 2261 2262 mmc_remove_host(slot->mmc); 2263 2264 if (gpio_is_valid(slot->detect_pin)) { 2265 int pin = slot->detect_pin; 2266 2267 free_irq(gpio_to_irq(pin), slot); 2268 del_timer_sync(&slot->detect_timer); 2269 } 2270 2271 slot->host->slot[id] = NULL; 2272 mmc_free_host(slot->mmc); 2273 } 2274 2275 static bool atmci_filter(struct dma_chan *chan, void *pdata) 2276 { 2277 struct mci_platform_data *sl_pdata = pdata; 2278 struct mci_dma_data *sl; 2279 2280 if (!sl_pdata) 2281 return false; 2282 2283 sl = sl_pdata->dma_slave; 2284 if (sl && find_slave_dev(sl) == chan->device->dev) { 2285 chan->private = slave_data_ptr(sl); 2286 return true; 2287 } else { 2288 return false; 2289 } 2290 } 2291 2292 static bool atmci_configure_dma(struct atmel_mci *host) 2293 { 2294 struct mci_platform_data *pdata; 2295 dma_cap_mask_t mask; 2296 2297 if (host == NULL) 2298 return false; 2299 2300 pdata = host->pdev->dev.platform_data; 2301 2302 dma_cap_zero(mask); 2303 dma_cap_set(DMA_SLAVE, mask); 2304 2305 host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata, 2306 &host->pdev->dev, "rxtx"); 2307 if (!host->dma.chan) { 2308 dev_warn(&host->pdev->dev, "no DMA channel available\n"); 2309 return false; 2310 } else { 2311 dev_info(&host->pdev->dev, 2312 "using %s for DMA transfers\n", 2313 dma_chan_name(host->dma.chan)); 2314 2315 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR; 2316 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2317 host->dma_conf.src_maxburst = 1; 2318 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR; 2319 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2320 host->dma_conf.dst_maxburst = 1; 2321 host->dma_conf.device_fc = false; 2322 return true; 2323 } 2324 } 2325 2326 /* 2327 * HSMCI (High Speed MCI) module is not fully compatible with MCI module. 2328 * HSMCI provides DMA support and a new config register but no more supports 2329 * PDC. 2330 */ 2331 static void __init atmci_get_cap(struct atmel_mci *host) 2332 { 2333 unsigned int version; 2334 2335 version = atmci_get_version(host); 2336 dev_info(&host->pdev->dev, 2337 "version: 0x%x\n", version); 2338 2339 host->caps.has_dma_conf_reg = 0; 2340 host->caps.has_pdc = ATMCI_PDC_CONNECTED; 2341 host->caps.has_cfg_reg = 0; 2342 host->caps.has_cstor_reg = 0; 2343 host->caps.has_highspeed = 0; 2344 host->caps.has_rwproof = 0; 2345 host->caps.has_odd_clk_div = 0; 2346 host->caps.has_bad_data_ordering = 1; 2347 host->caps.need_reset_after_xfer = 1; 2348 host->caps.need_blksz_mul_4 = 1; 2349 host->caps.need_notbusy_for_read_ops = 0; 2350 2351 /* keep only major version number */ 2352 switch (version & 0xf00) { 2353 case 0x600: 2354 case 0x500: 2355 host->caps.has_odd_clk_div = 1; 2356 case 0x400: 2357 case 0x300: 2358 host->caps.has_dma_conf_reg = 1; 2359 host->caps.has_pdc = 0; 2360 host->caps.has_cfg_reg = 1; 2361 host->caps.has_cstor_reg = 1; 2362 host->caps.has_highspeed = 1; 2363 case 0x200: 2364 host->caps.has_rwproof = 1; 2365 host->caps.need_blksz_mul_4 = 0; 2366 host->caps.need_notbusy_for_read_ops = 1; 2367 case 0x100: 2368 host->caps.has_bad_data_ordering = 0; 2369 host->caps.need_reset_after_xfer = 0; 2370 case 0x0: 2371 break; 2372 default: 2373 host->caps.has_pdc = 0; 2374 dev_warn(&host->pdev->dev, 2375 "Unmanaged mci version, set minimum capabilities\n"); 2376 break; 2377 } 2378 } 2379 2380 static int __init atmci_probe(struct platform_device *pdev) 2381 { 2382 struct mci_platform_data *pdata; 2383 struct atmel_mci *host; 2384 struct resource *regs; 2385 unsigned int nr_slots; 2386 int irq; 2387 int ret, i; 2388 2389 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2390 if (!regs) 2391 return -ENXIO; 2392 pdata = pdev->dev.platform_data; 2393 if (!pdata) { 2394 pdata = atmci_of_init(pdev); 2395 if (IS_ERR(pdata)) { 2396 dev_err(&pdev->dev, "platform data not available\n"); 2397 return PTR_ERR(pdata); 2398 } 2399 } 2400 2401 irq = platform_get_irq(pdev, 0); 2402 if (irq < 0) 2403 return irq; 2404 2405 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 2406 if (!host) 2407 return -ENOMEM; 2408 2409 host->pdev = pdev; 2410 spin_lock_init(&host->lock); 2411 INIT_LIST_HEAD(&host->queue); 2412 2413 host->mck = devm_clk_get(&pdev->dev, "mci_clk"); 2414 if (IS_ERR(host->mck)) 2415 return PTR_ERR(host->mck); 2416 2417 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); 2418 if (!host->regs) 2419 return -ENOMEM; 2420 2421 ret = clk_prepare_enable(host->mck); 2422 if (ret) 2423 return ret; 2424 2425 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 2426 host->bus_hz = clk_get_rate(host->mck); 2427 clk_disable_unprepare(host->mck); 2428 2429 host->mapbase = regs->start; 2430 2431 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); 2432 2433 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); 2434 if (ret) 2435 return ret; 2436 2437 /* Get MCI capabilities and set operations according to it */ 2438 atmci_get_cap(host); 2439 if (atmci_configure_dma(host)) { 2440 host->prepare_data = &atmci_prepare_data_dma; 2441 host->submit_data = &atmci_submit_data_dma; 2442 host->stop_transfer = &atmci_stop_transfer_dma; 2443 } else if (host->caps.has_pdc) { 2444 dev_info(&pdev->dev, "using PDC\n"); 2445 host->prepare_data = &atmci_prepare_data_pdc; 2446 host->submit_data = &atmci_submit_data_pdc; 2447 host->stop_transfer = &atmci_stop_transfer_pdc; 2448 } else { 2449 dev_info(&pdev->dev, "using PIO\n"); 2450 host->prepare_data = &atmci_prepare_data; 2451 host->submit_data = &atmci_submit_data; 2452 host->stop_transfer = &atmci_stop_transfer; 2453 } 2454 2455 platform_set_drvdata(pdev, host); 2456 2457 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host); 2458 2459 /* We need at least one slot to succeed */ 2460 nr_slots = 0; 2461 ret = -ENODEV; 2462 if (pdata->slot[0].bus_width) { 2463 ret = atmci_init_slot(host, &pdata->slot[0], 2464 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); 2465 if (!ret) { 2466 nr_slots++; 2467 host->buf_size = host->slot[0]->mmc->max_req_size; 2468 } 2469 } 2470 if (pdata->slot[1].bus_width) { 2471 ret = atmci_init_slot(host, &pdata->slot[1], 2472 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); 2473 if (!ret) { 2474 nr_slots++; 2475 if (host->slot[1]->mmc->max_req_size > host->buf_size) 2476 host->buf_size = 2477 host->slot[1]->mmc->max_req_size; 2478 } 2479 } 2480 2481 if (!nr_slots) { 2482 dev_err(&pdev->dev, "init failed: no slot defined\n"); 2483 goto err_init_slot; 2484 } 2485 2486 if (!host->caps.has_rwproof) { 2487 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size, 2488 &host->buf_phys_addr, 2489 GFP_KERNEL); 2490 if (!host->buffer) { 2491 ret = -ENOMEM; 2492 dev_err(&pdev->dev, "buffer allocation failed\n"); 2493 goto err_dma_alloc; 2494 } 2495 } 2496 2497 dev_info(&pdev->dev, 2498 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2499 host->mapbase, irq, nr_slots); 2500 2501 return 0; 2502 2503 err_dma_alloc: 2504 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2505 if (host->slot[i]) 2506 atmci_cleanup_slot(host->slot[i], i); 2507 } 2508 err_init_slot: 2509 del_timer_sync(&host->timer); 2510 if (host->dma.chan) 2511 dma_release_channel(host->dma.chan); 2512 free_irq(irq, host); 2513 return ret; 2514 } 2515 2516 static int __exit atmci_remove(struct platform_device *pdev) 2517 { 2518 struct atmel_mci *host = platform_get_drvdata(pdev); 2519 unsigned int i; 2520 2521 if (host->buffer) 2522 dma_free_coherent(&pdev->dev, host->buf_size, 2523 host->buffer, host->buf_phys_addr); 2524 2525 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2526 if (host->slot[i]) 2527 atmci_cleanup_slot(host->slot[i], i); 2528 } 2529 2530 clk_prepare_enable(host->mck); 2531 atmci_writel(host, ATMCI_IDR, ~0UL); 2532 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 2533 atmci_readl(host, ATMCI_SR); 2534 clk_disable_unprepare(host->mck); 2535 2536 del_timer_sync(&host->timer); 2537 if (host->dma.chan) 2538 dma_release_channel(host->dma.chan); 2539 2540 free_irq(platform_get_irq(pdev, 0), host); 2541 2542 return 0; 2543 } 2544 2545 static struct platform_driver atmci_driver = { 2546 .remove = __exit_p(atmci_remove), 2547 .driver = { 2548 .name = "atmel_mci", 2549 .of_match_table = of_match_ptr(atmci_dt_ids), 2550 }, 2551 }; 2552 2553 static int __init atmci_init(void) 2554 { 2555 return platform_driver_probe(&atmci_driver, atmci_probe); 2556 } 2557 2558 static void __exit atmci_exit(void) 2559 { 2560 platform_driver_unregister(&atmci_driver); 2561 } 2562 2563 late_initcall(atmci_init); /* try to load after dma driver when built-in */ 2564 module_exit(atmci_exit); 2565 2566 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); 2567 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2568 MODULE_LICENSE("GPL v2"); 2569