1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de> 4 * 5 * Driver for Alcor Micro AU6601 and AU6621 controllers 6 */ 7 8 /* Note: this driver was created without any documentation. Based 9 * on sniffing, testing and in some cases mimic of original driver. 10 * As soon as some one with documentation or more experience in SD/MMC, or 11 * reverse engineering then me, please review this driver and question every 12 * thing what I did. 2018 Oleksij Rempel <linux@rempel-privat.de> 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/pci.h> 17 #include <linux/module.h> 18 #include <linux/io.h> 19 #include <linux/pm.h> 20 #include <linux/irq.h> 21 #include <linux/interrupt.h> 22 #include <linux/platform_device.h> 23 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/mmc.h> 26 27 #include <linux/alcor_pci.h> 28 29 enum alcor_cookie { 30 COOKIE_UNMAPPED, 31 COOKIE_PRE_MAPPED, 32 COOKIE_MAPPED, 33 }; 34 35 struct alcor_pll_conf { 36 unsigned int clk_src_freq; 37 unsigned int clk_src_reg; 38 unsigned int min_div; 39 unsigned int max_div; 40 }; 41 42 struct alcor_sdmmc_host { 43 struct device *dev; 44 struct alcor_pci_priv *alcor_pci; 45 46 struct mmc_host *mmc; 47 struct mmc_request *mrq; 48 struct mmc_command *cmd; 49 struct mmc_data *data; 50 unsigned int dma_on:1; 51 unsigned int early_data:1; 52 53 struct mutex cmd_mutex; 54 55 struct delayed_work timeout_work; 56 57 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 58 struct scatterlist *sg; 59 unsigned int blocks; /* remaining PIO blocks */ 60 int sg_count; 61 62 u32 irq_status_sd; 63 unsigned char cur_power_mode; 64 }; 65 66 static const struct alcor_pll_conf alcor_pll_cfg[] = { 67 /* MHZ, CLK src, max div, min div */ 68 { 31250000, AU6601_CLK_31_25_MHZ, 1, 511}, 69 { 48000000, AU6601_CLK_48_MHZ, 1, 511}, 70 {125000000, AU6601_CLK_125_MHZ, 1, 511}, 71 {384000000, AU6601_CLK_384_MHZ, 1, 511}, 72 }; 73 74 static inline void alcor_rmw8(struct alcor_sdmmc_host *host, unsigned int addr, 75 u8 clear, u8 set) 76 { 77 struct alcor_pci_priv *priv = host->alcor_pci; 78 u32 var; 79 80 var = alcor_read8(priv, addr); 81 var &= ~clear; 82 var |= set; 83 alcor_write8(priv, var, addr); 84 } 85 86 /* As soon as irqs are masked, some status updates may be missed. 87 * Use this with care. 88 */ 89 static inline void alcor_mask_sd_irqs(struct alcor_sdmmc_host *host) 90 { 91 struct alcor_pci_priv *priv = host->alcor_pci; 92 93 alcor_write32(priv, 0, AU6601_REG_INT_ENABLE); 94 } 95 96 static inline void alcor_unmask_sd_irqs(struct alcor_sdmmc_host *host) 97 { 98 struct alcor_pci_priv *priv = host->alcor_pci; 99 100 alcor_write32(priv, AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK | 101 AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE | 102 AU6601_INT_OVER_CURRENT_ERR, 103 AU6601_REG_INT_ENABLE); 104 } 105 106 static void alcor_reset(struct alcor_sdmmc_host *host, u8 val) 107 { 108 struct alcor_pci_priv *priv = host->alcor_pci; 109 int i; 110 111 alcor_write8(priv, val | AU6601_BUF_CTRL_RESET, 112 AU6601_REG_SW_RESET); 113 for (i = 0; i < 100; i++) { 114 if (!(alcor_read8(priv, AU6601_REG_SW_RESET) & val)) 115 return; 116 udelay(50); 117 } 118 dev_err(host->dev, "%s: timeout\n", __func__); 119 } 120 121 static void alcor_data_set_dma(struct alcor_sdmmc_host *host) 122 { 123 struct alcor_pci_priv *priv = host->alcor_pci; 124 u32 addr, len; 125 126 if (!host->sg_count) 127 return; 128 129 if (!host->sg) { 130 dev_err(host->dev, "have blocks, but no SG\n"); 131 return; 132 } 133 134 if (!sg_dma_len(host->sg)) { 135 dev_err(host->dev, "DMA SG len == 0\n"); 136 return; 137 } 138 139 140 addr = (u32)sg_dma_address(host->sg); 141 len = sg_dma_len(host->sg); 142 143 alcor_write32(priv, addr, AU6601_REG_SDMA_ADDR); 144 host->sg = sg_next(host->sg); 145 host->sg_count--; 146 } 147 148 static void alcor_trigger_data_transfer(struct alcor_sdmmc_host *host, 149 bool early) 150 { 151 struct alcor_pci_priv *priv = host->alcor_pci; 152 struct mmc_data *data = host->data; 153 u8 ctrl = 0; 154 155 if (data->flags & MMC_DATA_WRITE) 156 ctrl |= AU6601_DATA_WRITE; 157 158 if (data->host_cookie == COOKIE_MAPPED) { 159 if (host->early_data) { 160 host->early_data = false; 161 return; 162 } 163 164 host->early_data = early; 165 166 alcor_data_set_dma(host); 167 ctrl |= AU6601_DATA_DMA_MODE; 168 host->dma_on = 1; 169 alcor_write32(priv, data->sg_count * 0x1000, 170 AU6601_REG_BLOCK_SIZE); 171 } else { 172 alcor_write32(priv, data->blksz, AU6601_REG_BLOCK_SIZE); 173 } 174 175 alcor_write8(priv, ctrl | AU6601_DATA_START_XFER, 176 AU6601_DATA_XFER_CTRL); 177 } 178 179 static void alcor_trf_block_pio(struct alcor_sdmmc_host *host, bool read) 180 { 181 struct alcor_pci_priv *priv = host->alcor_pci; 182 size_t blksize, len; 183 u8 *buf; 184 185 if (!host->blocks) 186 return; 187 188 if (host->dma_on) { 189 dev_err(host->dev, "configured DMA but got PIO request.\n"); 190 return; 191 } 192 193 if (!!(host->data->flags & MMC_DATA_READ) != read) { 194 dev_err(host->dev, "got unexpected direction %i != %i\n", 195 !!(host->data->flags & MMC_DATA_READ), read); 196 } 197 198 if (!sg_miter_next(&host->sg_miter)) 199 return; 200 201 blksize = host->data->blksz; 202 len = min(host->sg_miter.length, blksize); 203 204 dev_dbg(host->dev, "PIO, %s block size: 0x%zx\n", 205 read ? "read" : "write", blksize); 206 207 host->sg_miter.consumed = len; 208 host->blocks--; 209 210 buf = host->sg_miter.addr; 211 212 if (read) 213 ioread32_rep(priv->iobase + AU6601_REG_BUFFER, buf, len >> 2); 214 else 215 iowrite32_rep(priv->iobase + AU6601_REG_BUFFER, buf, len >> 2); 216 217 sg_miter_stop(&host->sg_miter); 218 } 219 220 static void alcor_prepare_sg_miter(struct alcor_sdmmc_host *host) 221 { 222 unsigned int flags = SG_MITER_ATOMIC; 223 struct mmc_data *data = host->data; 224 225 if (data->flags & MMC_DATA_READ) 226 flags |= SG_MITER_TO_SG; 227 else 228 flags |= SG_MITER_FROM_SG; 229 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 230 } 231 232 static void alcor_prepare_data(struct alcor_sdmmc_host *host, 233 struct mmc_command *cmd) 234 { 235 struct mmc_data *data = cmd->data; 236 237 if (!data) 238 return; 239 240 241 host->data = data; 242 host->data->bytes_xfered = 0; 243 host->blocks = data->blocks; 244 host->sg = data->sg; 245 host->sg_count = data->sg_count; 246 dev_dbg(host->dev, "prepare DATA: sg %i, blocks: %i\n", 247 host->sg_count, host->blocks); 248 249 if (data->host_cookie != COOKIE_MAPPED) 250 alcor_prepare_sg_miter(host); 251 252 alcor_trigger_data_transfer(host, true); 253 } 254 255 static void alcor_send_cmd(struct alcor_sdmmc_host *host, 256 struct mmc_command *cmd, bool set_timeout) 257 { 258 struct alcor_pci_priv *priv = host->alcor_pci; 259 unsigned long timeout = 0; 260 u8 ctrl = 0; 261 262 host->cmd = cmd; 263 alcor_prepare_data(host, cmd); 264 265 dev_dbg(host->dev, "send CMD. opcode: 0x%02x, arg; 0x%08x\n", 266 cmd->opcode, cmd->arg); 267 alcor_write8(priv, cmd->opcode | 0x40, AU6601_REG_CMD_OPCODE); 268 alcor_write32be(priv, cmd->arg, AU6601_REG_CMD_ARG); 269 270 switch (mmc_resp_type(cmd)) { 271 case MMC_RSP_NONE: 272 ctrl = AU6601_CMD_NO_RESP; 273 break; 274 case MMC_RSP_R1: 275 ctrl = AU6601_CMD_6_BYTE_CRC; 276 break; 277 case MMC_RSP_R1B: 278 ctrl = AU6601_CMD_6_BYTE_CRC | AU6601_CMD_STOP_WAIT_RDY; 279 break; 280 case MMC_RSP_R2: 281 ctrl = AU6601_CMD_17_BYTE_CRC; 282 break; 283 case MMC_RSP_R3: 284 ctrl = AU6601_CMD_6_BYTE_WO_CRC; 285 break; 286 default: 287 dev_err(host->dev, "%s: cmd->flag (0x%02x) is not valid\n", 288 mmc_hostname(host->mmc), mmc_resp_type(cmd)); 289 break; 290 } 291 292 if (set_timeout) { 293 if (!cmd->data && cmd->busy_timeout) 294 timeout = cmd->busy_timeout; 295 else 296 timeout = 10000; 297 298 schedule_delayed_work(&host->timeout_work, 299 msecs_to_jiffies(timeout)); 300 } 301 302 dev_dbg(host->dev, "xfer ctrl: 0x%02x; timeout: %lu\n", ctrl, timeout); 303 alcor_write8(priv, ctrl | AU6601_CMD_START_XFER, 304 AU6601_CMD_XFER_CTRL); 305 } 306 307 static void alcor_request_complete(struct alcor_sdmmc_host *host, 308 bool cancel_timeout) 309 { 310 struct mmc_request *mrq; 311 312 /* 313 * If this work gets rescheduled while running, it will 314 * be run again afterwards but without any active request. 315 */ 316 if (!host->mrq) 317 return; 318 319 if (cancel_timeout) 320 cancel_delayed_work(&host->timeout_work); 321 322 mrq = host->mrq; 323 324 host->mrq = NULL; 325 host->cmd = NULL; 326 host->data = NULL; 327 host->dma_on = 0; 328 329 mmc_request_done(host->mmc, mrq); 330 } 331 332 static void alcor_finish_data(struct alcor_sdmmc_host *host) 333 { 334 struct mmc_data *data; 335 336 data = host->data; 337 host->data = NULL; 338 host->dma_on = 0; 339 340 /* 341 * The specification states that the block count register must 342 * be updated, but it does not specify at what point in the 343 * data flow. That makes the register entirely useless to read 344 * back so we have to assume that nothing made it to the card 345 * in the event of an error. 346 */ 347 if (data->error) 348 data->bytes_xfered = 0; 349 else 350 data->bytes_xfered = data->blksz * data->blocks; 351 352 /* 353 * Need to send CMD12 if - 354 * a) open-ended multiblock transfer (no CMD23) 355 * b) error in multiblock transfer 356 */ 357 if (data->stop && 358 (data->error || 359 !host->mrq->sbc)) { 360 361 /* 362 * The controller needs a reset of internal state machines 363 * upon error conditions. 364 */ 365 if (data->error) 366 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA); 367 368 alcor_unmask_sd_irqs(host); 369 alcor_send_cmd(host, data->stop, false); 370 return; 371 } 372 373 alcor_request_complete(host, 1); 374 } 375 376 static void alcor_err_irq(struct alcor_sdmmc_host *host, u32 intmask) 377 { 378 dev_dbg(host->dev, "ERR IRQ %x\n", intmask); 379 380 if (host->cmd) { 381 if (intmask & AU6601_INT_CMD_TIMEOUT_ERR) 382 host->cmd->error = -ETIMEDOUT; 383 else 384 host->cmd->error = -EILSEQ; 385 } 386 387 if (host->data) { 388 if (intmask & AU6601_INT_DATA_TIMEOUT_ERR) 389 host->data->error = -ETIMEDOUT; 390 else 391 host->data->error = -EILSEQ; 392 393 host->data->bytes_xfered = 0; 394 } 395 396 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA); 397 alcor_request_complete(host, 1); 398 } 399 400 static int alcor_cmd_irq_done(struct alcor_sdmmc_host *host, u32 intmask) 401 { 402 struct alcor_pci_priv *priv = host->alcor_pci; 403 404 intmask &= AU6601_INT_CMD_END; 405 406 if (!intmask) 407 return true; 408 409 /* got CMD_END but no CMD is in progress, wake thread an process the 410 * error 411 */ 412 if (!host->cmd) 413 return false; 414 415 if (host->cmd->flags & MMC_RSP_PRESENT) { 416 struct mmc_command *cmd = host->cmd; 417 418 cmd->resp[0] = alcor_read32be(priv, AU6601_REG_CMD_RSP0); 419 dev_dbg(host->dev, "RSP0: 0x%04x\n", cmd->resp[0]); 420 if (host->cmd->flags & MMC_RSP_136) { 421 cmd->resp[1] = 422 alcor_read32be(priv, AU6601_REG_CMD_RSP1); 423 cmd->resp[2] = 424 alcor_read32be(priv, AU6601_REG_CMD_RSP2); 425 cmd->resp[3] = 426 alcor_read32be(priv, AU6601_REG_CMD_RSP3); 427 dev_dbg(host->dev, "RSP1,2,3: 0x%04x 0x%04x 0x%04x\n", 428 cmd->resp[1], cmd->resp[2], cmd->resp[3]); 429 } 430 431 } 432 433 host->cmd->error = 0; 434 435 /* Processed actual command. */ 436 if (!host->data) 437 return false; 438 439 alcor_trigger_data_transfer(host, false); 440 host->cmd = NULL; 441 return true; 442 } 443 444 static void alcor_cmd_irq_thread(struct alcor_sdmmc_host *host, u32 intmask) 445 { 446 intmask &= AU6601_INT_CMD_END; 447 448 if (!intmask) 449 return; 450 451 if (!host->cmd && intmask & AU6601_INT_CMD_END) { 452 dev_dbg(host->dev, "Got command interrupt 0x%08x even though no command operation was in progress.\n", 453 intmask); 454 } 455 456 /* Processed actual command. */ 457 if (!host->data) 458 alcor_request_complete(host, 1); 459 else 460 alcor_trigger_data_transfer(host, false); 461 host->cmd = NULL; 462 } 463 464 static int alcor_data_irq_done(struct alcor_sdmmc_host *host, u32 intmask) 465 { 466 u32 tmp; 467 468 intmask &= AU6601_INT_DATA_MASK; 469 470 /* nothing here to do */ 471 if (!intmask) 472 return 1; 473 474 /* we was too fast and got DATA_END after it was processed? 475 * lets ignore it for now. 476 */ 477 if (!host->data && intmask == AU6601_INT_DATA_END) 478 return 1; 479 480 /* looks like an error, so lets handle it. */ 481 if (!host->data) 482 return 0; 483 484 tmp = intmask & (AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY 485 | AU6601_INT_DMA_END); 486 switch (tmp) { 487 case 0: 488 break; 489 case AU6601_INT_READ_BUF_RDY: 490 alcor_trf_block_pio(host, true); 491 if (!host->blocks) 492 break; 493 alcor_trigger_data_transfer(host, false); 494 return 1; 495 case AU6601_INT_WRITE_BUF_RDY: 496 alcor_trf_block_pio(host, false); 497 if (!host->blocks) 498 break; 499 alcor_trigger_data_transfer(host, false); 500 return 1; 501 case AU6601_INT_DMA_END: 502 if (!host->sg_count) 503 break; 504 505 alcor_data_set_dma(host); 506 break; 507 default: 508 dev_err(host->dev, "Got READ_BUF_RDY and WRITE_BUF_RDY at same time\n"); 509 break; 510 } 511 512 if (intmask & AU6601_INT_DATA_END) 513 return 0; 514 515 return 1; 516 } 517 518 static void alcor_data_irq_thread(struct alcor_sdmmc_host *host, u32 intmask) 519 { 520 intmask &= AU6601_INT_DATA_MASK; 521 522 if (!intmask) 523 return; 524 525 if (!host->data) { 526 dev_dbg(host->dev, "Got data interrupt 0x%08x even though no data operation was in progress.\n", 527 intmask); 528 alcor_reset(host, AU6601_RESET_DATA); 529 return; 530 } 531 532 if (alcor_data_irq_done(host, intmask)) 533 return; 534 535 if ((intmask & AU6601_INT_DATA_END) || !host->blocks || 536 (host->dma_on && !host->sg_count)) 537 alcor_finish_data(host); 538 } 539 540 static void alcor_cd_irq(struct alcor_sdmmc_host *host, u32 intmask) 541 { 542 dev_dbg(host->dev, "card %s\n", 543 intmask & AU6601_INT_CARD_REMOVE ? "removed" : "inserted"); 544 545 if (host->mrq) { 546 dev_dbg(host->dev, "cancel all pending tasks.\n"); 547 548 if (host->data) 549 host->data->error = -ENOMEDIUM; 550 551 if (host->cmd) 552 host->cmd->error = -ENOMEDIUM; 553 else 554 host->mrq->cmd->error = -ENOMEDIUM; 555 556 alcor_request_complete(host, 1); 557 } 558 559 mmc_detect_change(host->mmc, msecs_to_jiffies(1)); 560 } 561 562 static irqreturn_t alcor_irq_thread(int irq, void *d) 563 { 564 struct alcor_sdmmc_host *host = d; 565 irqreturn_t ret = IRQ_HANDLED; 566 u32 intmask, tmp; 567 568 mutex_lock(&host->cmd_mutex); 569 570 intmask = host->irq_status_sd; 571 572 /* some thing bad */ 573 if (unlikely(!intmask || AU6601_INT_ALL_MASK == intmask)) { 574 dev_dbg(host->dev, "unexpected IRQ: 0x%04x\n", intmask); 575 ret = IRQ_NONE; 576 goto exit; 577 } 578 579 tmp = intmask & (AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK); 580 if (tmp) { 581 if (tmp & AU6601_INT_ERROR_MASK) 582 alcor_err_irq(host, tmp); 583 else { 584 alcor_cmd_irq_thread(host, tmp); 585 alcor_data_irq_thread(host, tmp); 586 } 587 intmask &= ~(AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK); 588 } 589 590 if (intmask & (AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE)) { 591 alcor_cd_irq(host, intmask); 592 intmask &= ~(AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE); 593 } 594 595 if (intmask & AU6601_INT_OVER_CURRENT_ERR) { 596 dev_warn(host->dev, 597 "warning: over current detected!\n"); 598 intmask &= ~AU6601_INT_OVER_CURRENT_ERR; 599 } 600 601 if (intmask) 602 dev_dbg(host->dev, "got not handled IRQ: 0x%04x\n", intmask); 603 604 exit: 605 mutex_unlock(&host->cmd_mutex); 606 alcor_unmask_sd_irqs(host); 607 return ret; 608 } 609 610 611 static irqreturn_t alcor_irq(int irq, void *d) 612 { 613 struct alcor_sdmmc_host *host = d; 614 struct alcor_pci_priv *priv = host->alcor_pci; 615 u32 status, tmp; 616 irqreturn_t ret; 617 int cmd_done, data_done; 618 619 status = alcor_read32(priv, AU6601_REG_INT_STATUS); 620 if (!status) 621 return IRQ_NONE; 622 623 alcor_write32(priv, status, AU6601_REG_INT_STATUS); 624 625 tmp = status & (AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY 626 | AU6601_INT_DATA_END | AU6601_INT_DMA_END 627 | AU6601_INT_CMD_END); 628 if (tmp == status) { 629 cmd_done = alcor_cmd_irq_done(host, tmp); 630 data_done = alcor_data_irq_done(host, tmp); 631 /* use fast path for simple tasks */ 632 if (cmd_done && data_done) { 633 ret = IRQ_HANDLED; 634 goto alcor_irq_done; 635 } 636 } 637 638 host->irq_status_sd = status; 639 ret = IRQ_WAKE_THREAD; 640 alcor_mask_sd_irqs(host); 641 alcor_irq_done: 642 return ret; 643 } 644 645 static void alcor_set_clock(struct alcor_sdmmc_host *host, unsigned int clock) 646 { 647 struct alcor_pci_priv *priv = host->alcor_pci; 648 unsigned int clock_out = 0; 649 int i, diff = 0x7fffffff, tmp_clock = 0; 650 u16 clk_src = 0; 651 u8 clk_div = 0; 652 653 if (clock == 0) { 654 alcor_write16(priv, 0, AU6601_CLK_SELECT); 655 return; 656 } 657 658 for (i = 0; i < ARRAY_SIZE(alcor_pll_cfg); i++) { 659 unsigned int tmp_div, tmp_diff; 660 const struct alcor_pll_conf *cfg = &alcor_pll_cfg[i]; 661 662 tmp_div = DIV_ROUND_UP(cfg->clk_src_freq, clock); 663 if (cfg->min_div > tmp_div || tmp_div > cfg->max_div) 664 continue; 665 666 tmp_clock = DIV_ROUND_UP(cfg->clk_src_freq, tmp_div); 667 tmp_diff = abs(clock - tmp_clock); 668 669 if (tmp_diff >= 0 && tmp_diff < diff) { 670 diff = tmp_diff; 671 clk_src = cfg->clk_src_reg; 672 clk_div = tmp_div; 673 clock_out = tmp_clock; 674 } 675 } 676 677 clk_src |= ((clk_div - 1) << 8); 678 clk_src |= AU6601_CLK_ENABLE; 679 680 dev_dbg(host->dev, "set freq %d cal freq %d, use div %d, mod %x\n", 681 clock, tmp_clock, clk_div, clk_src); 682 683 alcor_write16(priv, clk_src, AU6601_CLK_SELECT); 684 685 } 686 687 static void alcor_set_timing(struct mmc_host *mmc, struct mmc_ios *ios) 688 { 689 struct alcor_sdmmc_host *host = mmc_priv(mmc); 690 691 if (ios->timing == MMC_TIMING_LEGACY) { 692 alcor_rmw8(host, AU6601_CLK_DELAY, 693 AU6601_CLK_POSITIVE_EDGE_ALL, 0); 694 } else { 695 alcor_rmw8(host, AU6601_CLK_DELAY, 696 0, AU6601_CLK_POSITIVE_EDGE_ALL); 697 } 698 } 699 700 static void alcor_set_bus_width(struct mmc_host *mmc, struct mmc_ios *ios) 701 { 702 struct alcor_sdmmc_host *host = mmc_priv(mmc); 703 struct alcor_pci_priv *priv = host->alcor_pci; 704 705 if (ios->bus_width == MMC_BUS_WIDTH_1) { 706 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL); 707 } else if (ios->bus_width == MMC_BUS_WIDTH_4) { 708 alcor_write8(priv, AU6601_BUS_WIDTH_4BIT, 709 AU6601_REG_BUS_CTRL); 710 } else 711 dev_err(host->dev, "Unknown BUS mode\n"); 712 713 } 714 715 static int alcor_card_busy(struct mmc_host *mmc) 716 { 717 struct alcor_sdmmc_host *host = mmc_priv(mmc); 718 struct alcor_pci_priv *priv = host->alcor_pci; 719 u8 status; 720 721 /* Check whether dat[0:3] low */ 722 status = alcor_read8(priv, AU6601_DATA_PIN_STATE); 723 724 return !(status & AU6601_BUS_STAT_DAT_MASK); 725 } 726 727 static int alcor_get_cd(struct mmc_host *mmc) 728 { 729 struct alcor_sdmmc_host *host = mmc_priv(mmc); 730 struct alcor_pci_priv *priv = host->alcor_pci; 731 u8 detect; 732 733 detect = alcor_read8(priv, AU6601_DETECT_STATUS) 734 & AU6601_DETECT_STATUS_M; 735 /* check if card is present then send command and data */ 736 return (detect == AU6601_SD_DETECTED); 737 } 738 739 static int alcor_get_ro(struct mmc_host *mmc) 740 { 741 struct alcor_sdmmc_host *host = mmc_priv(mmc); 742 struct alcor_pci_priv *priv = host->alcor_pci; 743 u8 status; 744 745 /* get write protect pin status */ 746 status = alcor_read8(priv, AU6601_INTERFACE_MODE_CTRL); 747 748 return !!(status & AU6601_SD_CARD_WP); 749 } 750 751 static void alcor_request(struct mmc_host *mmc, struct mmc_request *mrq) 752 { 753 struct alcor_sdmmc_host *host = mmc_priv(mmc); 754 755 mutex_lock(&host->cmd_mutex); 756 757 host->mrq = mrq; 758 759 /* check if card is present then send command and data */ 760 if (alcor_get_cd(mmc)) 761 alcor_send_cmd(host, mrq->cmd, true); 762 else { 763 mrq->cmd->error = -ENOMEDIUM; 764 alcor_request_complete(host, 1); 765 } 766 767 mutex_unlock(&host->cmd_mutex); 768 } 769 770 static void alcor_pre_req(struct mmc_host *mmc, 771 struct mmc_request *mrq) 772 { 773 struct alcor_sdmmc_host *host = mmc_priv(mmc); 774 struct mmc_data *data = mrq->data; 775 struct mmc_command *cmd = mrq->cmd; 776 struct scatterlist *sg; 777 unsigned int i, sg_len; 778 779 if (!data || !cmd) 780 return; 781 782 data->host_cookie = COOKIE_UNMAPPED; 783 784 /* FIXME: looks like the DMA engine works only with CMD18 */ 785 if (cmd->opcode != 18) 786 return; 787 /* 788 * We don't do DMA on "complex" transfers, i.e. with 789 * non-word-aligned buffers or lengths. Also, we don't bother 790 * with all the DMA setup overhead for short transfers. 791 */ 792 if (data->blocks * data->blksz < AU6601_MAX_DMA_BLOCK_SIZE) 793 return; 794 795 if (data->blksz & 3) 796 return; 797 798 for_each_sg(data->sg, sg, data->sg_len, i) { 799 if (sg->length != AU6601_MAX_DMA_BLOCK_SIZE) 800 return; 801 } 802 803 /* This data might be unmapped at this time */ 804 805 sg_len = dma_map_sg(host->dev, data->sg, data->sg_len, 806 mmc_get_dma_dir(data)); 807 if (sg_len) 808 data->host_cookie = COOKIE_MAPPED; 809 810 data->sg_count = sg_len; 811 } 812 813 static void alcor_post_req(struct mmc_host *mmc, 814 struct mmc_request *mrq, 815 int err) 816 { 817 struct alcor_sdmmc_host *host = mmc_priv(mmc); 818 struct mmc_data *data = mrq->data; 819 820 if (!data) 821 return; 822 823 if (data->host_cookie == COOKIE_MAPPED) { 824 dma_unmap_sg(host->dev, 825 data->sg, 826 data->sg_len, 827 mmc_get_dma_dir(data)); 828 } 829 830 data->host_cookie = COOKIE_UNMAPPED; 831 } 832 833 static void alcor_set_power_mode(struct mmc_host *mmc, struct mmc_ios *ios) 834 { 835 struct alcor_sdmmc_host *host = mmc_priv(mmc); 836 struct alcor_pci_priv *priv = host->alcor_pci; 837 838 switch (ios->power_mode) { 839 case MMC_POWER_OFF: 840 alcor_set_clock(host, ios->clock); 841 /* set all pins to input */ 842 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE); 843 /* turn of VDD */ 844 alcor_write8(priv, 0, AU6601_POWER_CONTROL); 845 break; 846 case MMC_POWER_UP: 847 break; 848 case MMC_POWER_ON: 849 /* This is most trickiest part. The order and timings of 850 * instructions seems to play important role. Any changes may 851 * confuse internal state engine if this HW. 852 * FIXME: If we will ever get access to documentation, then this 853 * part should be reviewed again. 854 */ 855 856 /* enable SD card mode */ 857 alcor_write8(priv, AU6601_SD_CARD, 858 AU6601_ACTIVE_CTRL); 859 /* set signal voltage to 3.3V */ 860 alcor_write8(priv, 0, AU6601_OPT); 861 /* no documentation about clk delay, for now just try to mimic 862 * original driver. 863 */ 864 alcor_write8(priv, 0x20, AU6601_CLK_DELAY); 865 /* set BUS width to 1 bit */ 866 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL); 867 /* set CLK first time */ 868 alcor_set_clock(host, ios->clock); 869 /* power on VDD */ 870 alcor_write8(priv, AU6601_SD_CARD, 871 AU6601_POWER_CONTROL); 872 /* wait until the CLK will get stable */ 873 mdelay(20); 874 /* set CLK again, mimic original driver. */ 875 alcor_set_clock(host, ios->clock); 876 877 /* enable output */ 878 alcor_write8(priv, AU6601_SD_CARD, 879 AU6601_OUTPUT_ENABLE); 880 /* The clk will not work on au6621. We need to trigger data 881 * transfer. 882 */ 883 alcor_write8(priv, AU6601_DATA_WRITE, 884 AU6601_DATA_XFER_CTRL); 885 /* configure timeout. Not clear what exactly it means. */ 886 alcor_write8(priv, 0x7d, AU6601_TIME_OUT_CTRL); 887 mdelay(100); 888 break; 889 default: 890 dev_err(host->dev, "Unknown power parameter\n"); 891 } 892 } 893 894 static void alcor_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 895 { 896 struct alcor_sdmmc_host *host = mmc_priv(mmc); 897 898 mutex_lock(&host->cmd_mutex); 899 900 dev_dbg(host->dev, "set ios. bus width: %x, power mode: %x\n", 901 ios->bus_width, ios->power_mode); 902 903 if (ios->power_mode != host->cur_power_mode) { 904 alcor_set_power_mode(mmc, ios); 905 host->cur_power_mode = ios->power_mode; 906 } else { 907 alcor_set_timing(mmc, ios); 908 alcor_set_bus_width(mmc, ios); 909 alcor_set_clock(host, ios->clock); 910 } 911 912 mutex_unlock(&host->cmd_mutex); 913 } 914 915 static int alcor_signal_voltage_switch(struct mmc_host *mmc, 916 struct mmc_ios *ios) 917 { 918 struct alcor_sdmmc_host *host = mmc_priv(mmc); 919 920 mutex_lock(&host->cmd_mutex); 921 922 switch (ios->signal_voltage) { 923 case MMC_SIGNAL_VOLTAGE_330: 924 alcor_rmw8(host, AU6601_OPT, AU6601_OPT_SD_18V, 0); 925 break; 926 case MMC_SIGNAL_VOLTAGE_180: 927 alcor_rmw8(host, AU6601_OPT, 0, AU6601_OPT_SD_18V); 928 break; 929 default: 930 /* No signal voltage switch required */ 931 break; 932 } 933 934 mutex_unlock(&host->cmd_mutex); 935 return 0; 936 } 937 938 static const struct mmc_host_ops alcor_sdc_ops = { 939 .card_busy = alcor_card_busy, 940 .get_cd = alcor_get_cd, 941 .get_ro = alcor_get_ro, 942 .post_req = alcor_post_req, 943 .pre_req = alcor_pre_req, 944 .request = alcor_request, 945 .set_ios = alcor_set_ios, 946 .start_signal_voltage_switch = alcor_signal_voltage_switch, 947 }; 948 949 static void alcor_timeout_timer(struct work_struct *work) 950 { 951 struct delayed_work *d = to_delayed_work(work); 952 struct alcor_sdmmc_host *host = container_of(d, struct alcor_sdmmc_host, 953 timeout_work); 954 mutex_lock(&host->cmd_mutex); 955 956 dev_dbg(host->dev, "triggered timeout\n"); 957 if (host->mrq) { 958 dev_err(host->dev, "Timeout waiting for hardware interrupt.\n"); 959 960 if (host->data) { 961 host->data->error = -ETIMEDOUT; 962 } else { 963 if (host->cmd) 964 host->cmd->error = -ETIMEDOUT; 965 else 966 host->mrq->cmd->error = -ETIMEDOUT; 967 } 968 969 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA); 970 alcor_request_complete(host, 0); 971 } 972 973 mmiowb(); 974 mutex_unlock(&host->cmd_mutex); 975 } 976 977 static void alcor_hw_init(struct alcor_sdmmc_host *host) 978 { 979 struct alcor_pci_priv *priv = host->alcor_pci; 980 struct alcor_dev_cfg *cfg = priv->cfg; 981 982 /* FIXME: This part is a mimics HW init of original driver. 983 * If we will ever get access to documentation, then this part 984 * should be reviewed again. 985 */ 986 987 /* reset command state engine */ 988 alcor_reset(host, AU6601_RESET_CMD); 989 990 alcor_write8(priv, 0, AU6601_DMA_BOUNDARY); 991 /* enable sd card mode */ 992 alcor_write8(priv, AU6601_SD_CARD, AU6601_ACTIVE_CTRL); 993 994 /* set BUS width to 1 bit */ 995 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL); 996 997 /* reset data state engine */ 998 alcor_reset(host, AU6601_RESET_DATA); 999 /* Not sure if a voodoo with AU6601_DMA_BOUNDARY is really needed */ 1000 alcor_write8(priv, 0, AU6601_DMA_BOUNDARY); 1001 1002 alcor_write8(priv, 0, AU6601_INTERFACE_MODE_CTRL); 1003 /* not clear what we are doing here. */ 1004 alcor_write8(priv, 0x44, AU6601_PAD_DRIVE0); 1005 alcor_write8(priv, 0x44, AU6601_PAD_DRIVE1); 1006 alcor_write8(priv, 0x00, AU6601_PAD_DRIVE2); 1007 1008 /* for 6601 - dma_boundary; for 6621 - dma_page_cnt 1009 * exact meaning of this register is not clear. 1010 */ 1011 alcor_write8(priv, cfg->dma, AU6601_DMA_BOUNDARY); 1012 1013 /* make sure all pins are set to input and VDD is off */ 1014 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE); 1015 alcor_write8(priv, 0, AU6601_POWER_CONTROL); 1016 1017 alcor_write8(priv, AU6601_DETECT_EN, AU6601_DETECT_STATUS); 1018 /* now we should be safe to enable IRQs */ 1019 alcor_unmask_sd_irqs(host); 1020 } 1021 1022 static void alcor_hw_uninit(struct alcor_sdmmc_host *host) 1023 { 1024 struct alcor_pci_priv *priv = host->alcor_pci; 1025 1026 alcor_mask_sd_irqs(host); 1027 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA); 1028 1029 alcor_write8(priv, 0, AU6601_DETECT_STATUS); 1030 1031 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE); 1032 alcor_write8(priv, 0, AU6601_POWER_CONTROL); 1033 1034 alcor_write8(priv, 0, AU6601_OPT); 1035 } 1036 1037 static void alcor_init_mmc(struct alcor_sdmmc_host *host) 1038 { 1039 struct mmc_host *mmc = host->mmc; 1040 1041 mmc->f_min = AU6601_MIN_CLOCK; 1042 mmc->f_max = AU6601_MAX_CLOCK; 1043 mmc->ocr_avail = MMC_VDD_33_34; 1044 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED 1045 | MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 1046 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50; 1047 mmc->caps2 = MMC_CAP2_NO_SDIO; 1048 mmc->ops = &alcor_sdc_ops; 1049 1050 /* Hardware cannot do scatter lists */ 1051 mmc->max_segs = AU6601_MAX_DMA_SEGMENTS; 1052 mmc->max_seg_size = AU6601_MAX_DMA_BLOCK_SIZE; 1053 1054 mmc->max_blk_size = mmc->max_seg_size; 1055 mmc->max_blk_count = mmc->max_segs; 1056 1057 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 1058 } 1059 1060 static int alcor_pci_sdmmc_drv_probe(struct platform_device *pdev) 1061 { 1062 struct alcor_pci_priv *priv = pdev->dev.platform_data; 1063 struct mmc_host *mmc; 1064 struct alcor_sdmmc_host *host; 1065 int ret; 1066 1067 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1068 if (!mmc) { 1069 dev_err(&pdev->dev, "Can't allocate MMC\n"); 1070 return -ENOMEM; 1071 } 1072 1073 host = mmc_priv(mmc); 1074 host->mmc = mmc; 1075 host->dev = &pdev->dev; 1076 host->cur_power_mode = MMC_POWER_UNDEFINED; 1077 host->alcor_pci = priv; 1078 1079 /* make sure irqs are disabled */ 1080 alcor_write32(priv, 0, AU6601_REG_INT_ENABLE); 1081 alcor_write32(priv, 0, AU6601_MS_INT_ENABLE); 1082 1083 ret = devm_request_threaded_irq(&pdev->dev, priv->irq, 1084 alcor_irq, alcor_irq_thread, IRQF_SHARED, 1085 DRV_NAME_ALCOR_PCI_SDMMC, host); 1086 1087 if (ret) { 1088 dev_err(&pdev->dev, "Failed to get irq for data line\n"); 1089 return ret; 1090 } 1091 1092 mutex_init(&host->cmd_mutex); 1093 INIT_DELAYED_WORK(&host->timeout_work, alcor_timeout_timer); 1094 1095 alcor_init_mmc(host); 1096 alcor_hw_init(host); 1097 1098 dev_set_drvdata(&pdev->dev, host); 1099 mmc_add_host(mmc); 1100 return 0; 1101 } 1102 1103 static int alcor_pci_sdmmc_drv_remove(struct platform_device *pdev) 1104 { 1105 struct alcor_sdmmc_host *host = dev_get_drvdata(&pdev->dev); 1106 1107 if (cancel_delayed_work_sync(&host->timeout_work)) 1108 alcor_request_complete(host, 0); 1109 1110 alcor_hw_uninit(host); 1111 mmc_remove_host(host->mmc); 1112 mmc_free_host(host->mmc); 1113 1114 return 0; 1115 } 1116 1117 #ifdef CONFIG_PM_SLEEP 1118 static int alcor_pci_sdmmc_suspend(struct device *dev) 1119 { 1120 struct alcor_sdmmc_host *host = dev_get_drvdata(dev); 1121 1122 if (cancel_delayed_work_sync(&host->timeout_work)) 1123 alcor_request_complete(host, 0); 1124 1125 alcor_hw_uninit(host); 1126 1127 return 0; 1128 } 1129 1130 static int alcor_pci_sdmmc_resume(struct device *dev) 1131 { 1132 struct alcor_sdmmc_host *host = dev_get_drvdata(dev); 1133 1134 alcor_hw_init(host); 1135 1136 return 0; 1137 } 1138 #endif /* CONFIG_PM_SLEEP */ 1139 1140 static SIMPLE_DEV_PM_OPS(alcor_mmc_pm_ops, alcor_pci_sdmmc_suspend, 1141 alcor_pci_sdmmc_resume); 1142 1143 static const struct platform_device_id alcor_pci_sdmmc_ids[] = { 1144 { 1145 .name = DRV_NAME_ALCOR_PCI_SDMMC, 1146 }, { 1147 /* sentinel */ 1148 } 1149 }; 1150 MODULE_DEVICE_TABLE(platform, alcor_pci_sdmmc_ids); 1151 1152 static struct platform_driver alcor_pci_sdmmc_driver = { 1153 .probe = alcor_pci_sdmmc_drv_probe, 1154 .remove = alcor_pci_sdmmc_drv_remove, 1155 .id_table = alcor_pci_sdmmc_ids, 1156 .driver = { 1157 .name = DRV_NAME_ALCOR_PCI_SDMMC, 1158 .pm = &alcor_mmc_pm_ops 1159 }, 1160 }; 1161 module_platform_driver(alcor_pci_sdmmc_driver); 1162 1163 MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>"); 1164 MODULE_DESCRIPTION("PCI driver for Alcor Micro AU6601 Secure Digital Host Controller Interface"); 1165 MODULE_LICENSE("GPL"); 1166