1 /* 2 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU Lesser General Public License as published by 6 * the Free Software Foundation; either version 2.1 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19 #ifndef __GRU_INSTRUCTIONS_H__ 20 #define __GRU_INSTRUCTIONS_H__ 21 22 #define gru_flush_cache_hook(p) 23 #define gru_emulator_wait_hook(p, w) 24 25 /* 26 * Architecture dependent functions 27 */ 28 29 #if defined(CONFIG_IA64) 30 #include <linux/compiler.h> 31 #include <asm/intrinsics.h> 32 #define __flush_cache(p) ia64_fc(p) 33 /* Use volatile on IA64 to ensure ordering via st4.rel */ 34 #define gru_ordered_store_int(p,v) \ 35 do { \ 36 barrier(); \ 37 *((volatile int *)(p)) = v; /* force st.rel */ \ 38 } while (0) 39 #elif defined(CONFIG_X86_64) 40 #define __flush_cache(p) clflush(p) 41 #define gru_ordered_store_int(p,v) \ 42 do { \ 43 barrier(); \ 44 *(int *)p = v; \ 45 } while (0) 46 #else 47 #error "Unsupported architecture" 48 #endif 49 50 /* 51 * Control block status and exception codes 52 */ 53 #define CBS_IDLE 0 54 #define CBS_EXCEPTION 1 55 #define CBS_ACTIVE 2 56 #define CBS_CALL_OS 3 57 58 /* CB substatus bitmasks */ 59 #define CBSS_MSG_QUEUE_MASK 7 60 #define CBSS_IMPLICIT_ABORT_ACTIVE_MASK 8 61 62 /* CB substatus message queue values (low 3 bits of substatus) */ 63 #define CBSS_NO_ERROR 0 64 #define CBSS_LB_OVERFLOWED 1 65 #define CBSS_QLIMIT_REACHED 2 66 #define CBSS_PAGE_OVERFLOW 3 67 #define CBSS_AMO_NACKED 4 68 #define CBSS_PUT_NACKED 5 69 70 /* 71 * Structure used to fetch exception detail for CBs that terminate with 72 * CBS_EXCEPTION 73 */ 74 struct control_block_extended_exc_detail { 75 unsigned long cb; 76 int opc; 77 int ecause; 78 int exopc; 79 long exceptdet0; 80 int exceptdet1; 81 }; 82 83 /* 84 * Instruction formats 85 */ 86 87 /* 88 * Generic instruction format. 89 * This definition has precise bit field definitions. 90 */ 91 struct gru_instruction_bits { 92 /* DW 0 - low */ 93 unsigned int icmd: 1; 94 unsigned char ima: 3; /* CB_DelRep, unmapped mode */ 95 unsigned char reserved0: 4; 96 unsigned int xtype: 3; 97 unsigned int iaa0: 2; 98 unsigned int iaa1: 2; 99 unsigned char reserved1: 1; 100 unsigned char opc: 8; /* opcode */ 101 unsigned char exopc: 8; /* extended opcode */ 102 /* DW 0 - high */ 103 unsigned int idef2: 22; /* TRi0 */ 104 unsigned char reserved2: 2; 105 unsigned char istatus: 2; 106 unsigned char isubstatus:4; 107 unsigned char reserved3: 2; 108 /* DW 1 */ 109 unsigned long idef4; /* 42 bits: TRi1, BufSize */ 110 /* DW 2-6 */ 111 unsigned long idef1; /* BAddr0 */ 112 unsigned long idef5; /* Nelem */ 113 unsigned long idef6; /* Stride, Operand1 */ 114 unsigned long idef3; /* BAddr1, Value, Operand2 */ 115 unsigned long reserved4; 116 /* DW 7 */ 117 unsigned long avalue; /* AValue */ 118 }; 119 120 /* 121 * Generic instruction with friendlier names. This format is used 122 * for inline instructions. 123 */ 124 struct gru_instruction { 125 /* DW 0 */ 126 unsigned int op32; /* icmd,xtype,iaa0,ima,opc */ 127 unsigned int tri0; 128 unsigned long tri1_bufsize; /* DW 1 */ 129 unsigned long baddr0; /* DW 2 */ 130 unsigned long nelem; /* DW 3 */ 131 unsigned long op1_stride; /* DW 4 */ 132 unsigned long op2_value_baddr1; /* DW 5 */ 133 unsigned long reserved0; /* DW 6 */ 134 unsigned long avalue; /* DW 7 */ 135 }; 136 137 /* Some shifts and masks for the low 32 bits of a GRU command */ 138 #define GRU_CB_ICMD_SHFT 0 139 #define GRU_CB_ICMD_MASK 0x1 140 #define GRU_CB_XTYPE_SHFT 8 141 #define GRU_CB_XTYPE_MASK 0x7 142 #define GRU_CB_IAA0_SHFT 11 143 #define GRU_CB_IAA0_MASK 0x3 144 #define GRU_CB_IAA1_SHFT 13 145 #define GRU_CB_IAA1_MASK 0x3 146 #define GRU_CB_IMA_SHFT 1 147 #define GRU_CB_IMA_MASK 0x3 148 #define GRU_CB_OPC_SHFT 16 149 #define GRU_CB_OPC_MASK 0xff 150 #define GRU_CB_EXOPC_SHFT 24 151 #define GRU_CB_EXOPC_MASK 0xff 152 153 /* GRU instruction opcodes (opc field) */ 154 #define OP_NOP 0x00 155 #define OP_BCOPY 0x01 156 #define OP_VLOAD 0x02 157 #define OP_IVLOAD 0x03 158 #define OP_VSTORE 0x04 159 #define OP_IVSTORE 0x05 160 #define OP_VSET 0x06 161 #define OP_IVSET 0x07 162 #define OP_MESQ 0x08 163 #define OP_GAMXR 0x09 164 #define OP_GAMIR 0x0a 165 #define OP_GAMIRR 0x0b 166 #define OP_GAMER 0x0c 167 #define OP_GAMERR 0x0d 168 #define OP_BSTORE 0x0e 169 #define OP_VFLUSH 0x0f 170 171 172 /* Extended opcodes values (exopc field) */ 173 174 /* GAMIR - AMOs with implicit operands */ 175 #define EOP_IR_FETCH 0x01 /* Plain fetch of memory */ 176 #define EOP_IR_CLR 0x02 /* Fetch and clear */ 177 #define EOP_IR_INC 0x05 /* Fetch and increment */ 178 #define EOP_IR_DEC 0x07 /* Fetch and decrement */ 179 #define EOP_IR_QCHK1 0x0d /* Queue check, 64 byte msg */ 180 #define EOP_IR_QCHK2 0x0e /* Queue check, 128 byte msg */ 181 182 /* GAMIRR - Registered AMOs with implicit operands */ 183 #define EOP_IRR_FETCH 0x01 /* Registered fetch of memory */ 184 #define EOP_IRR_CLR 0x02 /* Registered fetch and clear */ 185 #define EOP_IRR_INC 0x05 /* Registered fetch and increment */ 186 #define EOP_IRR_DEC 0x07 /* Registered fetch and decrement */ 187 #define EOP_IRR_DECZ 0x0f /* Registered fetch and decrement, update on zero*/ 188 189 /* GAMER - AMOs with explicit operands */ 190 #define EOP_ER_SWAP 0x00 /* Exchange argument and memory */ 191 #define EOP_ER_OR 0x01 /* Logical OR with memory */ 192 #define EOP_ER_AND 0x02 /* Logical AND with memory */ 193 #define EOP_ER_XOR 0x03 /* Logical XOR with memory */ 194 #define EOP_ER_ADD 0x04 /* Add value to memory */ 195 #define EOP_ER_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/ 196 #define EOP_ER_CADD 0x0c /* Queue check, operand1*64 byte msg */ 197 198 /* GAMERR - Registered AMOs with explicit operands */ 199 #define EOP_ERR_SWAP 0x00 /* Exchange argument and memory */ 200 #define EOP_ERR_OR 0x01 /* Logical OR with memory */ 201 #define EOP_ERR_AND 0x02 /* Logical AND with memory */ 202 #define EOP_ERR_XOR 0x03 /* Logical XOR with memory */ 203 #define EOP_ERR_ADD 0x04 /* Add value to memory */ 204 #define EOP_ERR_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/ 205 #define EOP_ERR_EPOLL 0x09 /* Poll for equality */ 206 #define EOP_ERR_NPOLL 0x0a /* Poll for inequality */ 207 208 /* GAMXR - SGI Arithmetic unit */ 209 #define EOP_XR_CSWAP 0x0b /* Masked compare exchange */ 210 211 212 /* Transfer types (xtype field) */ 213 #define XTYPE_B 0x0 /* byte */ 214 #define XTYPE_S 0x1 /* short (2-byte) */ 215 #define XTYPE_W 0x2 /* word (4-byte) */ 216 #define XTYPE_DW 0x3 /* doubleword (8-byte) */ 217 #define XTYPE_CL 0x6 /* cacheline (64-byte) */ 218 219 220 /* Instruction access attributes (iaa0, iaa1 fields) */ 221 #define IAA_RAM 0x0 /* normal cached RAM access */ 222 #define IAA_NCRAM 0x2 /* noncoherent RAM access */ 223 #define IAA_MMIO 0x1 /* noncoherent memory-mapped I/O space */ 224 #define IAA_REGISTER 0x3 /* memory-mapped registers, etc. */ 225 226 227 /* Instruction mode attributes (ima field) */ 228 #define IMA_MAPPED 0x0 /* Virtual mode */ 229 #define IMA_CB_DELAY 0x1 /* hold read responses until status changes */ 230 #define IMA_UNMAPPED 0x2 /* bypass the TLBs (OS only) */ 231 #define IMA_INTERRUPT 0x4 /* Interrupt when instruction completes */ 232 233 /* CBE ecause bits */ 234 #define CBE_CAUSE_RI (1 << 0) 235 #define CBE_CAUSE_INVALID_INSTRUCTION (1 << 1) 236 #define CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN (1 << 2) 237 #define CBE_CAUSE_PE_CHECK_DATA_ERROR (1 << 3) 238 #define CBE_CAUSE_IAA_GAA_MISMATCH (1 << 4) 239 #define CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION (1 << 5) 240 #define CBE_CAUSE_OS_FATAL_TLB_FAULT (1 << 6) 241 #define CBE_CAUSE_EXECUTION_HW_ERROR (1 << 7) 242 #define CBE_CAUSE_TLBHW_ERROR (1 << 8) 243 #define CBE_CAUSE_RA_REQUEST_TIMEOUT (1 << 9) 244 #define CBE_CAUSE_HA_REQUEST_TIMEOUT (1 << 10) 245 #define CBE_CAUSE_RA_RESPONSE_FATAL (1 << 11) 246 #define CBE_CAUSE_RA_RESPONSE_NON_FATAL (1 << 12) 247 #define CBE_CAUSE_HA_RESPONSE_FATAL (1 << 13) 248 #define CBE_CAUSE_HA_RESPONSE_NON_FATAL (1 << 14) 249 #define CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR (1 << 15) 250 #define CBE_CAUSE_RESPONSE_DATA_ERROR (1 << 16) 251 #define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR (1 << 17) 252 253 /* 254 * Exceptions are retried for the following cases. If any OTHER bits are set 255 * in ecause, the exception is not retryable. 256 */ 257 #define EXCEPTION_RETRY_BITS (CBE_CAUSE_RESPONSE_DATA_ERROR | \ 258 CBE_CAUSE_RA_REQUEST_TIMEOUT | \ 259 CBE_CAUSE_TLBHW_ERROR | \ 260 CBE_CAUSE_HA_REQUEST_TIMEOUT) 261 262 /* Message queue head structure */ 263 union gru_mesqhead { 264 unsigned long val; 265 struct { 266 unsigned int head; 267 unsigned int limit; 268 }; 269 }; 270 271 272 /* Generate the low word of a GRU instruction */ 273 static inline unsigned int 274 __opword(unsigned char opcode, unsigned char exopc, unsigned char xtype, 275 unsigned char iaa0, unsigned char iaa1, 276 unsigned char ima) 277 { 278 return (1 << GRU_CB_ICMD_SHFT) | 279 (iaa0 << GRU_CB_IAA0_SHFT) | 280 (iaa1 << GRU_CB_IAA1_SHFT) | 281 (ima << GRU_CB_IMA_SHFT) | 282 (xtype << GRU_CB_XTYPE_SHFT) | 283 (opcode << GRU_CB_OPC_SHFT) | 284 (exopc << GRU_CB_EXOPC_SHFT); 285 } 286 287 /* 288 * Architecture specific intrinsics 289 */ 290 static inline void gru_flush_cache(void *p) 291 { 292 __flush_cache(p); 293 } 294 295 /* 296 * Store the lower 32 bits of the command including the "start" bit. Then 297 * start the instruction executing. 298 */ 299 static inline void gru_start_instruction(struct gru_instruction *ins, int op32) 300 { 301 gru_ordered_store_int(ins, op32); 302 gru_flush_cache(ins); 303 } 304 305 306 /* Convert "hints" to IMA */ 307 #define CB_IMA(h) ((h) | IMA_UNMAPPED) 308 309 /* Convert data segment cache line index into TRI0 / TRI1 value */ 310 #define GRU_DINDEX(i) ((i) * GRU_CACHE_LINE_BYTES) 311 312 /* Inline functions for GRU instructions. 313 * Note: 314 * - nelem and stride are in elements 315 * - tri0/tri1 is in bytes for the beginning of the data segment. 316 */ 317 static inline void gru_vload(void *cb, unsigned long mem_addr, 318 unsigned int tri0, unsigned char xtype, unsigned long nelem, 319 unsigned long stride, unsigned long hints) 320 { 321 struct gru_instruction *ins = (struct gru_instruction *)cb; 322 323 ins->baddr0 = (long)mem_addr; 324 ins->nelem = nelem; 325 ins->tri0 = tri0; 326 ins->op1_stride = stride; 327 gru_start_instruction(ins, __opword(OP_VLOAD, 0, xtype, IAA_RAM, 0, 328 CB_IMA(hints))); 329 } 330 331 static inline void gru_vstore(void *cb, unsigned long mem_addr, 332 unsigned int tri0, unsigned char xtype, unsigned long nelem, 333 unsigned long stride, unsigned long hints) 334 { 335 struct gru_instruction *ins = (void *)cb; 336 337 ins->baddr0 = (long)mem_addr; 338 ins->nelem = nelem; 339 ins->tri0 = tri0; 340 ins->op1_stride = stride; 341 gru_start_instruction(ins, __opword(OP_VSTORE, 0, xtype, IAA_RAM, 0, 342 CB_IMA(hints))); 343 } 344 345 static inline void gru_ivload(void *cb, unsigned long mem_addr, 346 unsigned int tri0, unsigned int tri1, unsigned char xtype, 347 unsigned long nelem, unsigned long hints) 348 { 349 struct gru_instruction *ins = (void *)cb; 350 351 ins->baddr0 = (long)mem_addr; 352 ins->nelem = nelem; 353 ins->tri0 = tri0; 354 ins->tri1_bufsize = tri1; 355 gru_start_instruction(ins, __opword(OP_IVLOAD, 0, xtype, IAA_RAM, 0, 356 CB_IMA(hints))); 357 } 358 359 static inline void gru_ivstore(void *cb, unsigned long mem_addr, 360 unsigned int tri0, unsigned int tri1, 361 unsigned char xtype, unsigned long nelem, unsigned long hints) 362 { 363 struct gru_instruction *ins = (void *)cb; 364 365 ins->baddr0 = (long)mem_addr; 366 ins->nelem = nelem; 367 ins->tri0 = tri0; 368 ins->tri1_bufsize = tri1; 369 gru_start_instruction(ins, __opword(OP_IVSTORE, 0, xtype, IAA_RAM, 0, 370 CB_IMA(hints))); 371 } 372 373 static inline void gru_vset(void *cb, unsigned long mem_addr, 374 unsigned long value, unsigned char xtype, unsigned long nelem, 375 unsigned long stride, unsigned long hints) 376 { 377 struct gru_instruction *ins = (void *)cb; 378 379 ins->baddr0 = (long)mem_addr; 380 ins->op2_value_baddr1 = value; 381 ins->nelem = nelem; 382 ins->op1_stride = stride; 383 gru_start_instruction(ins, __opword(OP_VSET, 0, xtype, IAA_RAM, 0, 384 CB_IMA(hints))); 385 } 386 387 static inline void gru_ivset(void *cb, unsigned long mem_addr, 388 unsigned int tri1, unsigned long value, unsigned char xtype, 389 unsigned long nelem, unsigned long hints) 390 { 391 struct gru_instruction *ins = (void *)cb; 392 393 ins->baddr0 = (long)mem_addr; 394 ins->op2_value_baddr1 = value; 395 ins->nelem = nelem; 396 ins->tri1_bufsize = tri1; 397 gru_start_instruction(ins, __opword(OP_IVSET, 0, xtype, IAA_RAM, 0, 398 CB_IMA(hints))); 399 } 400 401 static inline void gru_vflush(void *cb, unsigned long mem_addr, 402 unsigned long nelem, unsigned char xtype, unsigned long stride, 403 unsigned long hints) 404 { 405 struct gru_instruction *ins = (void *)cb; 406 407 ins->baddr0 = (long)mem_addr; 408 ins->op1_stride = stride; 409 ins->nelem = nelem; 410 gru_start_instruction(ins, __opword(OP_VFLUSH, 0, xtype, IAA_RAM, 0, 411 CB_IMA(hints))); 412 } 413 414 static inline void gru_nop(void *cb, int hints) 415 { 416 struct gru_instruction *ins = (void *)cb; 417 418 gru_start_instruction(ins, __opword(OP_NOP, 0, 0, 0, 0, CB_IMA(hints))); 419 } 420 421 422 static inline void gru_bcopy(void *cb, const unsigned long src, 423 unsigned long dest, 424 unsigned int tri0, unsigned int xtype, unsigned long nelem, 425 unsigned int bufsize, unsigned long hints) 426 { 427 struct gru_instruction *ins = (void *)cb; 428 429 ins->baddr0 = (long)src; 430 ins->op2_value_baddr1 = (long)dest; 431 ins->nelem = nelem; 432 ins->tri0 = tri0; 433 ins->tri1_bufsize = bufsize; 434 gru_start_instruction(ins, __opword(OP_BCOPY, 0, xtype, IAA_RAM, 435 IAA_RAM, CB_IMA(hints))); 436 } 437 438 static inline void gru_bstore(void *cb, const unsigned long src, 439 unsigned long dest, unsigned int tri0, unsigned int xtype, 440 unsigned long nelem, unsigned long hints) 441 { 442 struct gru_instruction *ins = (void *)cb; 443 444 ins->baddr0 = (long)src; 445 ins->op2_value_baddr1 = (long)dest; 446 ins->nelem = nelem; 447 ins->tri0 = tri0; 448 gru_start_instruction(ins, __opword(OP_BSTORE, 0, xtype, 0, IAA_RAM, 449 CB_IMA(hints))); 450 } 451 452 static inline void gru_gamir(void *cb, int exopc, unsigned long src, 453 unsigned int xtype, unsigned long hints) 454 { 455 struct gru_instruction *ins = (void *)cb; 456 457 ins->baddr0 = (long)src; 458 gru_start_instruction(ins, __opword(OP_GAMIR, exopc, xtype, IAA_RAM, 0, 459 CB_IMA(hints))); 460 } 461 462 static inline void gru_gamirr(void *cb, int exopc, unsigned long src, 463 unsigned int xtype, unsigned long hints) 464 { 465 struct gru_instruction *ins = (void *)cb; 466 467 ins->baddr0 = (long)src; 468 gru_start_instruction(ins, __opword(OP_GAMIRR, exopc, xtype, IAA_RAM, 0, 469 CB_IMA(hints))); 470 } 471 472 static inline void gru_gamer(void *cb, int exopc, unsigned long src, 473 unsigned int xtype, 474 unsigned long operand1, unsigned long operand2, 475 unsigned long hints) 476 { 477 struct gru_instruction *ins = (void *)cb; 478 479 ins->baddr0 = (long)src; 480 ins->op1_stride = operand1; 481 ins->op2_value_baddr1 = operand2; 482 gru_start_instruction(ins, __opword(OP_GAMER, exopc, xtype, IAA_RAM, 0, 483 CB_IMA(hints))); 484 } 485 486 static inline void gru_gamerr(void *cb, int exopc, unsigned long src, 487 unsigned int xtype, unsigned long operand1, 488 unsigned long operand2, unsigned long hints) 489 { 490 struct gru_instruction *ins = (void *)cb; 491 492 ins->baddr0 = (long)src; 493 ins->op1_stride = operand1; 494 ins->op2_value_baddr1 = operand2; 495 gru_start_instruction(ins, __opword(OP_GAMERR, exopc, xtype, IAA_RAM, 0, 496 CB_IMA(hints))); 497 } 498 499 static inline void gru_gamxr(void *cb, unsigned long src, 500 unsigned int tri0, unsigned long hints) 501 { 502 struct gru_instruction *ins = (void *)cb; 503 504 ins->baddr0 = (long)src; 505 ins->nelem = 4; 506 gru_start_instruction(ins, __opword(OP_GAMXR, EOP_XR_CSWAP, XTYPE_DW, 507 IAA_RAM, 0, CB_IMA(hints))); 508 } 509 510 static inline void gru_mesq(void *cb, unsigned long queue, 511 unsigned long tri0, unsigned long nelem, 512 unsigned long hints) 513 { 514 struct gru_instruction *ins = (void *)cb; 515 516 ins->baddr0 = (long)queue; 517 ins->nelem = nelem; 518 ins->tri0 = tri0; 519 gru_start_instruction(ins, __opword(OP_MESQ, 0, XTYPE_CL, IAA_RAM, 0, 520 CB_IMA(hints))); 521 } 522 523 static inline unsigned long gru_get_amo_value(void *cb) 524 { 525 struct gru_instruction *ins = (void *)cb; 526 527 return ins->avalue; 528 } 529 530 static inline int gru_get_amo_value_head(void *cb) 531 { 532 struct gru_instruction *ins = (void *)cb; 533 534 return ins->avalue & 0xffffffff; 535 } 536 537 static inline int gru_get_amo_value_limit(void *cb) 538 { 539 struct gru_instruction *ins = (void *)cb; 540 541 return ins->avalue >> 32; 542 } 543 544 static inline union gru_mesqhead gru_mesq_head(int head, int limit) 545 { 546 union gru_mesqhead mqh; 547 548 mqh.head = head; 549 mqh.limit = limit; 550 return mqh; 551 } 552 553 /* 554 * Get struct control_block_extended_exc_detail for CB. 555 */ 556 extern int gru_get_cb_exception_detail(void *cb, 557 struct control_block_extended_exc_detail *excdet); 558 559 #define GRU_EXC_STR_SIZE 256 560 561 extern int gru_check_status_proc(void *cb); 562 extern int gru_wait_proc(void *cb); 563 extern void gru_wait_abort_proc(void *cb); 564 565 /* 566 * Control block definition for checking status 567 */ 568 struct gru_control_block_status { 569 unsigned int icmd :1; 570 unsigned int unused1 :31; 571 unsigned int unused2 :24; 572 unsigned int istatus :2; 573 unsigned int isubstatus :4; 574 unsigned int inused3 :2; 575 }; 576 577 /* Get CB status */ 578 static inline int gru_get_cb_status(void *cb) 579 { 580 struct gru_control_block_status *cbs = (void *)cb; 581 582 return cbs->istatus; 583 } 584 585 /* Get CB message queue substatus */ 586 static inline int gru_get_cb_message_queue_substatus(void *cb) 587 { 588 struct gru_control_block_status *cbs = (void *)cb; 589 590 return cbs->isubstatus & CBSS_MSG_QUEUE_MASK; 591 } 592 593 /* Get CB substatus */ 594 static inline int gru_get_cb_substatus(void *cb) 595 { 596 struct gru_control_block_status *cbs = (void *)cb; 597 598 return cbs->isubstatus; 599 } 600 601 /* Check the status of a CB. If the CB is in UPM mode, call the 602 * OS to handle the UPM status. 603 * Returns the CB status field value (0 for normal completion) 604 */ 605 static inline int gru_check_status(void *cb) 606 { 607 struct gru_control_block_status *cbs = (void *)cb; 608 int ret; 609 610 ret = cbs->istatus; 611 if (ret == CBS_CALL_OS) 612 ret = gru_check_status_proc(cb); 613 return ret; 614 } 615 616 /* Wait for CB to complete. 617 * Returns the CB status field value (0 for normal completion) 618 */ 619 static inline int gru_wait(void *cb) 620 { 621 struct gru_control_block_status *cbs = (void *)cb; 622 int ret = cbs->istatus; 623 624 if (ret != CBS_IDLE) 625 ret = gru_wait_proc(cb); 626 return ret; 627 } 628 629 /* Wait for CB to complete. Aborts program if error. (Note: error does NOT 630 * mean TLB mis - only fatal errors such as memory parity error or user 631 * bugs will cause termination. 632 */ 633 static inline void gru_wait_abort(void *cb) 634 { 635 struct gru_control_block_status *cbs = (void *)cb; 636 637 if (cbs->istatus != CBS_IDLE) 638 gru_wait_abort_proc(cb); 639 } 640 641 642 /* 643 * Get a pointer to a control block 644 * gseg - GSeg address returned from gru_get_thread_gru_segment() 645 * index - index of desired CB 646 */ 647 static inline void *gru_get_cb_pointer(void *gseg, 648 int index) 649 { 650 return gseg + GRU_CB_BASE + index * GRU_HANDLE_STRIDE; 651 } 652 653 /* 654 * Get a pointer to a cacheline in the data segment portion of a GSeg 655 * gseg - GSeg address returned from gru_get_thread_gru_segment() 656 * index - index of desired cache line 657 */ 658 static inline void *gru_get_data_pointer(void *gseg, int index) 659 { 660 return gseg + GRU_DS_BASE + index * GRU_CACHE_LINE_BYTES; 661 } 662 663 /* 664 * Convert a vaddr into the tri index within the GSEG 665 * vaddr - virtual address of within gseg 666 */ 667 static inline int gru_get_tri(void *vaddr) 668 { 669 return ((unsigned long)vaddr & (GRU_GSEG_PAGESIZE - 1)) - GRU_DS_BASE; 670 } 671 #endif /* __GRU_INSTRUCTIONS_H__ */ 672