1 /* 2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/types.h> 21 #include <linux/fs.h> 22 #include <linux/uaccess.h> 23 #include <linux/string.h> 24 #include <linux/pci.h> 25 #include <linux/io.h> 26 #include <linux/delay.h> 27 #include <linux/mutex.h> 28 #include <linux/if_ether.h> 29 #include <linux/ctype.h> 30 #include <linux/dmi.h> 31 #include <linux/of.h> 32 33 #define PHUB_STATUS 0x00 /* Status Register offset */ 34 #define PHUB_CONTROL 0x04 /* Control Register offset */ 35 #define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */ 36 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */ 37 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */ 38 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address 39 offset */ 40 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address 41 offset */ 42 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset 43 (Intel EG20T PCH)*/ 44 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address 45 offset(LAPIS Semicon ML7213) 46 */ 47 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address 48 offset(LAPIS Semicon ML7223) 49 */ 50 51 /* MAX number of INT_REDUCE_CONTROL registers */ 52 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128 53 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801 54 #define PCH_MINOR_NOS 1 55 #define CLKCFG_CAN_50MHZ 0x12000000 56 #define CLKCFG_CANCLK_MASK 0xFF000000 57 #define CLKCFG_UART_MASK 0xFFFFFF 58 59 /* CM-iTC */ 60 #define CLKCFG_UART_48MHZ (1 << 16) 61 #define CLKCFG_UART_25MHZ (2 << 16) 62 #define CLKCFG_BAUDDIV (2 << 20) 63 #define CLKCFG_PLL2VCO (8 << 9) 64 #define CLKCFG_UARTCLKSEL (1 << 18) 65 66 /* Macros for ML7213 */ 67 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A 68 69 /* Macros for ML7223 */ 70 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */ 71 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */ 72 73 /* Macros for ML7831 */ 74 #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801 75 76 /* SROM ACCESS Macro */ 77 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1)) 78 79 /* Registers address offset */ 80 #define PCH_PHUB_ID_REG 0x0000 81 #define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004 82 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008 83 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C 84 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010 85 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014 86 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018 87 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020 88 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024 89 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028 90 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C 91 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040 92 #define CLKCFG_REG_OFFSET 0x500 93 #define FUNCSEL_REG_OFFSET 0x508 94 95 #define PCH_PHUB_OROM_SIZE 15360 96 97 /** 98 * struct pch_phub_reg - PHUB register structure 99 * @phub_id_reg: PHUB_ID register val 100 * @q_pri_val_reg: QUEUE_PRI_VAL register val 101 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val 102 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val 103 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val 104 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val 105 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val 106 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val 107 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val 108 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val 109 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val 110 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val 111 * @clkcfg_reg: CLK CFG register val 112 * @funcsel_reg: Function select register value 113 * @pch_phub_base_address: Register base address 114 * @pch_phub_extrom_base_address: external rom base address 115 * @pch_mac_start_address: MAC address area start address 116 * @pch_opt_rom_start_address: Option ROM start address 117 * @ioh_type: Save IOH type 118 * @pdev: pointer to pci device struct 119 */ 120 struct pch_phub_reg { 121 u32 phub_id_reg; 122 u32 q_pri_val_reg; 123 u32 rc_q_maxsize_reg; 124 u32 bri_q_maxsize_reg; 125 u32 comp_resp_timeout_reg; 126 u32 bus_slave_control_reg; 127 u32 deadlock_avoid_type_reg; 128 u32 intpin_reg_wpermit_reg0; 129 u32 intpin_reg_wpermit_reg1; 130 u32 intpin_reg_wpermit_reg2; 131 u32 intpin_reg_wpermit_reg3; 132 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG]; 133 u32 clkcfg_reg; 134 u32 funcsel_reg; 135 void __iomem *pch_phub_base_address; 136 void __iomem *pch_phub_extrom_base_address; 137 u32 pch_mac_start_address; 138 u32 pch_opt_rom_start_address; 139 int ioh_type; 140 struct pci_dev *pdev; 141 }; 142 143 /* SROM SPEC for MAC address assignment offset */ 144 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa}; 145 146 static DEFINE_MUTEX(pch_phub_mutex); 147 148 /** 149 * pch_phub_read_modify_write_reg() - Reading modifying and writing register 150 * @reg_addr_offset: Register offset address value. 151 * @data: Writing value. 152 * @mask: Mask value. 153 */ 154 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip, 155 unsigned int reg_addr_offset, 156 unsigned int data, unsigned int mask) 157 { 158 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; 159 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); 160 } 161 162 #ifdef CONFIG_PM 163 /* pch_phub_save_reg_conf - saves register configuration */ 164 static void pch_phub_save_reg_conf(struct pci_dev *pdev) 165 { 166 unsigned int i; 167 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 168 169 void __iomem *p = chip->pch_phub_base_address; 170 171 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG); 172 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG); 173 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 174 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 175 chip->comp_resp_timeout_reg = 176 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 177 chip->bus_slave_control_reg = 178 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 179 chip->deadlock_avoid_type_reg = 180 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 181 chip->intpin_reg_wpermit_reg0 = 182 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 183 chip->intpin_reg_wpermit_reg1 = 184 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 185 chip->intpin_reg_wpermit_reg2 = 186 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 187 chip->intpin_reg_wpermit_reg3 = 188 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 189 dev_dbg(&pdev->dev, "%s : " 190 "chip->phub_id_reg=%x, " 191 "chip->q_pri_val_reg=%x, " 192 "chip->rc_q_maxsize_reg=%x, " 193 "chip->bri_q_maxsize_reg=%x, " 194 "chip->comp_resp_timeout_reg=%x, " 195 "chip->bus_slave_control_reg=%x, " 196 "chip->deadlock_avoid_type_reg=%x, " 197 "chip->intpin_reg_wpermit_reg0=%x, " 198 "chip->intpin_reg_wpermit_reg1=%x, " 199 "chip->intpin_reg_wpermit_reg2=%x, " 200 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 201 chip->phub_id_reg, 202 chip->q_pri_val_reg, 203 chip->rc_q_maxsize_reg, 204 chip->bri_q_maxsize_reg, 205 chip->comp_resp_timeout_reg, 206 chip->bus_slave_control_reg, 207 chip->deadlock_avoid_type_reg, 208 chip->intpin_reg_wpermit_reg0, 209 chip->intpin_reg_wpermit_reg1, 210 chip->intpin_reg_wpermit_reg2, 211 chip->intpin_reg_wpermit_reg3); 212 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 213 chip->int_reduce_control_reg[i] = 214 ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 215 dev_dbg(&pdev->dev, "%s : " 216 "chip->int_reduce_control_reg[%d]=%x\n", 217 __func__, i, chip->int_reduce_control_reg[i]); 218 } 219 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET); 220 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 221 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET); 222 } 223 224 /* pch_phub_restore_reg_conf - restore register configuration */ 225 static void pch_phub_restore_reg_conf(struct pci_dev *pdev) 226 { 227 unsigned int i; 228 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 229 void __iomem *p; 230 p = chip->pch_phub_base_address; 231 232 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG); 233 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG); 234 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 235 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 236 iowrite32(chip->comp_resp_timeout_reg, 237 p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 238 iowrite32(chip->bus_slave_control_reg, 239 p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 240 iowrite32(chip->deadlock_avoid_type_reg, 241 p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 242 iowrite32(chip->intpin_reg_wpermit_reg0, 243 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 244 iowrite32(chip->intpin_reg_wpermit_reg1, 245 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 246 iowrite32(chip->intpin_reg_wpermit_reg2, 247 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 248 iowrite32(chip->intpin_reg_wpermit_reg3, 249 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 250 dev_dbg(&pdev->dev, "%s : " 251 "chip->phub_id_reg=%x, " 252 "chip->q_pri_val_reg=%x, " 253 "chip->rc_q_maxsize_reg=%x, " 254 "chip->bri_q_maxsize_reg=%x, " 255 "chip->comp_resp_timeout_reg=%x, " 256 "chip->bus_slave_control_reg=%x, " 257 "chip->deadlock_avoid_type_reg=%x, " 258 "chip->intpin_reg_wpermit_reg0=%x, " 259 "chip->intpin_reg_wpermit_reg1=%x, " 260 "chip->intpin_reg_wpermit_reg2=%x, " 261 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 262 chip->phub_id_reg, 263 chip->q_pri_val_reg, 264 chip->rc_q_maxsize_reg, 265 chip->bri_q_maxsize_reg, 266 chip->comp_resp_timeout_reg, 267 chip->bus_slave_control_reg, 268 chip->deadlock_avoid_type_reg, 269 chip->intpin_reg_wpermit_reg0, 270 chip->intpin_reg_wpermit_reg1, 271 chip->intpin_reg_wpermit_reg2, 272 chip->intpin_reg_wpermit_reg3); 273 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 274 iowrite32(chip->int_reduce_control_reg[i], 275 p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 276 dev_dbg(&pdev->dev, "%s : " 277 "chip->int_reduce_control_reg[%d]=%x\n", 278 __func__, i, chip->int_reduce_control_reg[i]); 279 } 280 281 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET); 282 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 283 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET); 284 } 285 #endif 286 287 /** 288 * pch_phub_read_serial_rom() - Reading Serial ROM 289 * @offset_address: Serial ROM offset address to read. 290 * @data: Read buffer for specified Serial ROM value. 291 */ 292 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip, 293 unsigned int offset_address, u8 *data) 294 { 295 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 296 offset_address; 297 298 *data = ioread8(mem_addr); 299 } 300 301 /** 302 * pch_phub_write_serial_rom() - Writing Serial ROM 303 * @offset_address: Serial ROM offset address. 304 * @data: Serial ROM value to write. 305 */ 306 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip, 307 unsigned int offset_address, u8 data) 308 { 309 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 310 (offset_address & PCH_WORD_ADDR_MASK); 311 int i; 312 unsigned int word_data; 313 unsigned int pos; 314 unsigned int mask; 315 pos = (offset_address % 4) * 8; 316 mask = ~(0xFF << pos); 317 318 iowrite32(PCH_PHUB_ROM_WRITE_ENABLE, 319 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 320 321 word_data = ioread32(mem_addr); 322 iowrite32((word_data & mask) | (u32)data << pos, mem_addr); 323 324 i = 0; 325 while (ioread8(chip->pch_phub_extrom_base_address + 326 PHUB_STATUS) != 0x00) { 327 msleep(1); 328 if (i == PHUB_TIMEOUT) 329 return -ETIMEDOUT; 330 i++; 331 } 332 333 iowrite32(PCH_PHUB_ROM_WRITE_DISABLE, 334 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 335 336 return 0; 337 } 338 339 /** 340 * pch_phub_read_serial_rom_val() - Read Serial ROM value 341 * @offset_address: Serial ROM address offset value. 342 * @data: Serial ROM value to read. 343 */ 344 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip, 345 unsigned int offset_address, u8 *data) 346 { 347 unsigned int mem_addr; 348 349 mem_addr = chip->pch_mac_start_address + 350 pch_phub_mac_offset[offset_address]; 351 352 pch_phub_read_serial_rom(chip, mem_addr, data); 353 } 354 355 /** 356 * pch_phub_write_serial_rom_val() - writing Serial ROM value 357 * @offset_address: Serial ROM address offset value. 358 * @data: Serial ROM value. 359 */ 360 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip, 361 unsigned int offset_address, u8 data) 362 { 363 int retval; 364 unsigned int mem_addr; 365 366 mem_addr = chip->pch_mac_start_address + 367 pch_phub_mac_offset[offset_address]; 368 369 retval = pch_phub_write_serial_rom(chip, mem_addr, data); 370 371 return retval; 372 } 373 374 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration 375 * for Gigabit Ethernet MAC address 376 */ 377 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip) 378 { 379 int retval; 380 381 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc); 382 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10); 383 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01); 384 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02); 385 386 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00); 387 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00); 388 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00); 389 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80); 390 391 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc); 392 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10); 393 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01); 394 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18); 395 396 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc); 397 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10); 398 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01); 399 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19); 400 401 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc); 402 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10); 403 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01); 404 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a); 405 406 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01); 407 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00); 408 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00); 409 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00); 410 411 return retval; 412 } 413 414 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration 415 * for Gigabit Ethernet MAC address 416 */ 417 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip) 418 { 419 int retval; 420 u32 offset_addr; 421 422 offset_addr = 0x200; 423 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc); 424 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00); 425 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40); 426 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02); 427 428 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00); 429 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00); 430 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00); 431 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80); 432 433 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc); 434 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00); 435 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40); 436 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18); 437 438 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc); 439 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00); 440 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40); 441 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19); 442 443 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc); 444 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00); 445 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40); 446 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a); 447 448 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01); 449 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00); 450 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00); 451 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00); 452 453 return retval; 454 } 455 456 /** 457 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address 458 * @offset_address: Gigabit Ethernet MAC address offset value. 459 * @data: Buffer of the Gigabit Ethernet MAC address value. 460 */ 461 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 462 { 463 int i; 464 for (i = 0; i < ETH_ALEN; i++) 465 pch_phub_read_serial_rom_val(chip, i, &data[i]); 466 } 467 468 /** 469 * pch_phub_write_gbe_mac_addr() - Write MAC address 470 * @offset_address: Gigabit Ethernet MAC address offset value. 471 * @data: Gigabit Ethernet MAC address value. 472 */ 473 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 474 { 475 int retval; 476 int i; 477 478 if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/ 479 retval = pch_phub_gbe_serial_rom_conf(chip); 480 else /* ML7223 */ 481 retval = pch_phub_gbe_serial_rom_conf_mp(chip); 482 if (retval) 483 return retval; 484 485 for (i = 0; i < ETH_ALEN; i++) { 486 retval = pch_phub_write_serial_rom_val(chip, i, data[i]); 487 if (retval) 488 return retval; 489 } 490 491 return retval; 492 } 493 494 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj, 495 struct bin_attribute *attr, char *buf, 496 loff_t off, size_t count) 497 { 498 unsigned int rom_signature; 499 unsigned char rom_length; 500 unsigned int tmp; 501 unsigned int addr_offset; 502 unsigned int orom_size; 503 int ret; 504 int err; 505 ssize_t rom_size; 506 507 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj)); 508 509 ret = mutex_lock_interruptible(&pch_phub_mutex); 510 if (ret) { 511 err = -ERESTARTSYS; 512 goto return_err_nomutex; 513 } 514 515 /* Get Rom signature */ 516 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 517 if (!chip->pch_phub_extrom_base_address) { 518 err = -ENODATA; 519 goto exrom_map_err; 520 } 521 522 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address, 523 (unsigned char *)&rom_signature); 524 rom_signature &= 0xff; 525 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1, 526 (unsigned char *)&tmp); 527 rom_signature |= (tmp & 0xff) << 8; 528 if (rom_signature == 0xAA55) { 529 pch_phub_read_serial_rom(chip, 530 chip->pch_opt_rom_start_address + 2, 531 &rom_length); 532 orom_size = rom_length * 512; 533 if (orom_size < off) { 534 addr_offset = 0; 535 goto return_ok; 536 } 537 if (orom_size < count) { 538 addr_offset = 0; 539 goto return_ok; 540 } 541 542 for (addr_offset = 0; addr_offset < count; addr_offset++) { 543 pch_phub_read_serial_rom(chip, 544 chip->pch_opt_rom_start_address + addr_offset + off, 545 &buf[addr_offset]); 546 } 547 } else { 548 err = -ENODATA; 549 goto return_err; 550 } 551 return_ok: 552 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 553 mutex_unlock(&pch_phub_mutex); 554 return addr_offset; 555 556 return_err: 557 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 558 exrom_map_err: 559 mutex_unlock(&pch_phub_mutex); 560 return_err_nomutex: 561 return err; 562 } 563 564 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj, 565 struct bin_attribute *attr, 566 char *buf, loff_t off, size_t count) 567 { 568 int err; 569 unsigned int addr_offset; 570 int ret; 571 ssize_t rom_size; 572 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj)); 573 574 ret = mutex_lock_interruptible(&pch_phub_mutex); 575 if (ret) 576 return -ERESTARTSYS; 577 578 if (off > PCH_PHUB_OROM_SIZE) { 579 addr_offset = 0; 580 goto return_ok; 581 } 582 if (count > PCH_PHUB_OROM_SIZE) { 583 addr_offset = 0; 584 goto return_ok; 585 } 586 587 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 588 if (!chip->pch_phub_extrom_base_address) { 589 err = -ENOMEM; 590 goto exrom_map_err; 591 } 592 593 for (addr_offset = 0; addr_offset < count; addr_offset++) { 594 if (PCH_PHUB_OROM_SIZE < off + addr_offset) 595 goto return_ok; 596 597 ret = pch_phub_write_serial_rom(chip, 598 chip->pch_opt_rom_start_address + addr_offset + off, 599 buf[addr_offset]); 600 if (ret) { 601 err = ret; 602 goto return_err; 603 } 604 } 605 606 return_ok: 607 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 608 mutex_unlock(&pch_phub_mutex); 609 return addr_offset; 610 611 return_err: 612 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 613 614 exrom_map_err: 615 mutex_unlock(&pch_phub_mutex); 616 return err; 617 } 618 619 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr, 620 char *buf) 621 { 622 u8 mac[8]; 623 struct pch_phub_reg *chip = dev_get_drvdata(dev); 624 ssize_t rom_size; 625 626 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 627 if (!chip->pch_phub_extrom_base_address) 628 return -ENOMEM; 629 630 pch_phub_read_gbe_mac_addr(chip, mac); 631 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 632 633 return sprintf(buf, "%pM\n", mac); 634 } 635 636 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr, 637 const char *buf, size_t count) 638 { 639 u8 mac[ETH_ALEN]; 640 ssize_t rom_size; 641 struct pch_phub_reg *chip = dev_get_drvdata(dev); 642 int ret; 643 644 if (!mac_pton(buf, mac)) 645 return -EINVAL; 646 647 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 648 if (!chip->pch_phub_extrom_base_address) 649 return -ENOMEM; 650 651 ret = pch_phub_write_gbe_mac_addr(chip, mac); 652 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 653 if (ret) 654 return ret; 655 656 return count; 657 } 658 659 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac); 660 661 static const struct bin_attribute pch_bin_attr = { 662 .attr = { 663 .name = "pch_firmware", 664 .mode = S_IRUGO | S_IWUSR, 665 }, 666 .size = PCH_PHUB_OROM_SIZE + 1, 667 .read = pch_phub_bin_read, 668 .write = pch_phub_bin_write, 669 }; 670 671 static int pch_phub_probe(struct pci_dev *pdev, 672 const struct pci_device_id *id) 673 { 674 int ret; 675 struct pch_phub_reg *chip; 676 677 chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL); 678 if (chip == NULL) 679 return -ENOMEM; 680 681 ret = pci_enable_device(pdev); 682 if (ret) { 683 dev_err(&pdev->dev, 684 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret); 685 goto err_pci_enable_dev; 686 } 687 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__, 688 ret); 689 690 ret = pci_request_regions(pdev, KBUILD_MODNAME); 691 if (ret) { 692 dev_err(&pdev->dev, 693 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret); 694 goto err_req_regions; 695 } 696 dev_dbg(&pdev->dev, "%s : " 697 "pci_request_regions returns %d\n", __func__, ret); 698 699 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0); 700 701 702 if (chip->pch_phub_base_address == NULL) { 703 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); 704 ret = -ENOMEM; 705 goto err_pci_iomap; 706 } 707 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value " 708 "in pch_phub_base_address variable is %p\n", __func__, 709 chip->pch_phub_base_address); 710 711 chip->pdev = pdev; /* Save pci device struct */ 712 713 if (id->driver_data == 1) { /* EG20T PCH */ 714 const char *board_name; 715 unsigned int prefetch = 0x000affaa; 716 717 if (pdev->dev.of_node) 718 of_property_read_u32(pdev->dev.of_node, 719 "intel,eg20t-prefetch", 720 &prefetch); 721 722 ret = sysfs_create_file(&pdev->dev.kobj, 723 &dev_attr_pch_mac.attr); 724 if (ret) 725 goto err_sysfs_create; 726 727 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 728 if (ret) 729 goto exit_bin_attr; 730 731 pch_phub_read_modify_write_reg(chip, 732 (unsigned int)CLKCFG_REG_OFFSET, 733 CLKCFG_CAN_50MHZ, 734 CLKCFG_CANCLK_MASK); 735 736 /* quirk for CM-iTC board */ 737 board_name = dmi_get_system_info(DMI_BOARD_NAME); 738 if (board_name && strstr(board_name, "CM-iTC")) 739 pch_phub_read_modify_write_reg(chip, 740 (unsigned int)CLKCFG_REG_OFFSET, 741 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV | 742 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL, 743 CLKCFG_UART_MASK); 744 745 /* set the prefech value */ 746 iowrite32(prefetch, chip->pch_phub_base_address + 0x14); 747 /* set the interrupt delay value */ 748 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 749 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 750 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 751 752 /* quirk for MIPS Boston platform */ 753 if (pdev->dev.of_node) { 754 if (of_machine_is_compatible("img,boston")) { 755 pch_phub_read_modify_write_reg(chip, 756 (unsigned int)CLKCFG_REG_OFFSET, 757 CLKCFG_UART_25MHZ, 758 CLKCFG_UART_MASK); 759 } 760 } 761 } else if (id->driver_data == 2) { /* ML7213 IOH */ 762 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 763 if (ret) 764 goto err_sysfs_create; 765 /* set the prefech value 766 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a 767 * Device4(SDIO #0,1,2):f 768 * Device6(SATA 2):f 769 * Device8(USB OHCI #0/ USB EHCI #0):a 770 */ 771 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14); 772 chip->pch_opt_rom_start_address =\ 773 PCH_PHUB_ROM_START_ADDR_ML7213; 774 } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/ 775 /* set the prefech value 776 * Device8(GbE) 777 */ 778 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14); 779 /* set the interrupt delay value */ 780 iowrite32(0x25, chip->pch_phub_base_address + 0x140); 781 chip->pch_opt_rom_start_address =\ 782 PCH_PHUB_ROM_START_ADDR_ML7223; 783 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 784 } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/ 785 ret = sysfs_create_file(&pdev->dev.kobj, 786 &dev_attr_pch_mac.attr); 787 if (ret) 788 goto err_sysfs_create; 789 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 790 if (ret) 791 goto exit_bin_attr; 792 /* set the prefech value 793 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a 794 * Device4(SDIO #0,1):f 795 * Device6(SATA 2):f 796 */ 797 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14); 798 chip->pch_opt_rom_start_address =\ 799 PCH_PHUB_ROM_START_ADDR_ML7223; 800 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 801 } else if (id->driver_data == 5) { /* ML7831 */ 802 ret = sysfs_create_file(&pdev->dev.kobj, 803 &dev_attr_pch_mac.attr); 804 if (ret) 805 goto err_sysfs_create; 806 807 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 808 if (ret) 809 goto exit_bin_attr; 810 811 /* set the prefech value */ 812 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 813 /* set the interrupt delay value */ 814 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 815 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 816 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 817 } 818 819 chip->ioh_type = id->driver_data; 820 pci_set_drvdata(pdev, chip); 821 822 return 0; 823 exit_bin_attr: 824 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 825 826 err_sysfs_create: 827 pci_iounmap(pdev, chip->pch_phub_base_address); 828 err_pci_iomap: 829 pci_release_regions(pdev); 830 err_req_regions: 831 pci_disable_device(pdev); 832 err_pci_enable_dev: 833 kfree(chip); 834 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret); 835 return ret; 836 } 837 838 static void pch_phub_remove(struct pci_dev *pdev) 839 { 840 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 841 842 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 843 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr); 844 pci_iounmap(pdev, chip->pch_phub_base_address); 845 pci_release_regions(pdev); 846 pci_disable_device(pdev); 847 kfree(chip); 848 } 849 850 #ifdef CONFIG_PM 851 852 static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state) 853 { 854 int ret; 855 856 pch_phub_save_reg_conf(pdev); 857 ret = pci_save_state(pdev); 858 if (ret) { 859 dev_err(&pdev->dev, 860 " %s -pci_save_state returns %d\n", __func__, ret); 861 return ret; 862 } 863 pci_enable_wake(pdev, PCI_D3hot, 0); 864 pci_disable_device(pdev); 865 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 866 867 return 0; 868 } 869 870 static int pch_phub_resume(struct pci_dev *pdev) 871 { 872 int ret; 873 874 pci_set_power_state(pdev, PCI_D0); 875 pci_restore_state(pdev); 876 ret = pci_enable_device(pdev); 877 if (ret) { 878 dev_err(&pdev->dev, 879 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 880 return ret; 881 } 882 883 pci_enable_wake(pdev, PCI_D3hot, 0); 884 pch_phub_restore_reg_conf(pdev); 885 886 return 0; 887 } 888 #else 889 #define pch_phub_suspend NULL 890 #define pch_phub_resume NULL 891 #endif /* CONFIG_PM */ 892 893 static const struct pci_device_id pch_phub_pcidev_id[] = { 894 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, }, 895 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, }, 896 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, }, 897 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, }, 898 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5, }, 899 { } 900 }; 901 MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id); 902 903 static struct pci_driver pch_phub_driver = { 904 .name = "pch_phub", 905 .id_table = pch_phub_pcidev_id, 906 .probe = pch_phub_probe, 907 .remove = pch_phub_remove, 908 .suspend = pch_phub_suspend, 909 .resume = pch_phub_resume 910 }; 911 912 module_pci_driver(pch_phub_driver); 913 914 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB"); 915 MODULE_LICENSE("GPL"); 916