1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright 2017 IBM Corp. 3 #include <linux/pci.h> 4 #include <asm/pnv-ocxl.h> 5 #include <misc/ocxl.h> 6 #include <misc/ocxl-config.h> 7 8 #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit))) 9 #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s) 10 11 #define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0) 12 #define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0) 13 #define OCXL_DVSEC_PASID_MASK GENMASK(19, 0) 14 #define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0) 15 16 #define OCXL_DVSEC_TEMPL_VERSION 0x0 17 #define OCXL_DVSEC_TEMPL_NAME 0x4 18 #define OCXL_DVSEC_TEMPL_AFU_VERSION 0x1C 19 #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL 0x20 20 #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ 0x28 21 #define OCXL_DVSEC_TEMPL_MMIO_PP 0x30 22 #define OCXL_DVSEC_TEMPL_MMIO_PP_SZ 0x38 23 #define OCXL_DVSEC_TEMPL_MEM_SZ 0x3C 24 #define OCXL_DVSEC_TEMPL_WWID 0x40 25 26 #define OCXL_MAX_AFU_PER_FUNCTION 64 27 #define OCXL_TEMPL_LEN 0x58 28 #define OCXL_TEMPL_NAME_LEN 24 29 #define OCXL_CFG_TIMEOUT 3 30 31 static int find_dvsec(struct pci_dev *dev, int dvsec_id) 32 { 33 int vsec = 0; 34 u16 vendor, id; 35 36 while ((vsec = pci_find_next_ext_capability(dev, vsec, 37 OCXL_EXT_CAP_ID_DVSEC))) { 38 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET, 39 &vendor); 40 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id); 41 if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id) 42 return vsec; 43 } 44 return 0; 45 } 46 47 static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx) 48 { 49 int vsec = 0; 50 u16 vendor, id; 51 u8 idx; 52 53 while ((vsec = pci_find_next_ext_capability(dev, vsec, 54 OCXL_EXT_CAP_ID_DVSEC))) { 55 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET, 56 &vendor); 57 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id); 58 59 if (vendor == PCI_VENDOR_ID_IBM && 60 id == OCXL_DVSEC_AFU_CTRL_ID) { 61 pci_read_config_byte(dev, 62 vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX, 63 &idx); 64 if (idx == afu_idx) 65 return vsec; 66 } 67 } 68 return 0; 69 } 70 71 static int read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn) 72 { 73 u16 val; 74 int pos; 75 76 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID); 77 if (!pos) { 78 /* 79 * PASID capability is not mandatory, but there 80 * shouldn't be any AFU 81 */ 82 dev_dbg(&dev->dev, "Function doesn't require any PASID\n"); 83 fn->max_pasid_log = -1; 84 goto out; 85 } 86 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val); 87 fn->max_pasid_log = EXTRACT_BITS(val, 8, 12); 88 89 out: 90 dev_dbg(&dev->dev, "PASID capability:\n"); 91 dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log); 92 return 0; 93 } 94 95 static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn) 96 { 97 int pos; 98 99 pos = find_dvsec(dev, OCXL_DVSEC_TL_ID); 100 if (!pos && PCI_FUNC(dev->devfn) == 0) { 101 dev_err(&dev->dev, "Can't find TL DVSEC\n"); 102 return -ENODEV; 103 } 104 if (pos && PCI_FUNC(dev->devfn) != 0) { 105 dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n"); 106 return -ENODEV; 107 } 108 fn->dvsec_tl_pos = pos; 109 return 0; 110 } 111 112 static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn) 113 { 114 int pos, afu_present; 115 u32 val; 116 117 pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID); 118 if (!pos) { 119 dev_err(&dev->dev, "Can't find function DVSEC\n"); 120 return -ENODEV; 121 } 122 fn->dvsec_function_pos = pos; 123 124 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val); 125 afu_present = EXTRACT_BIT(val, 31); 126 if (!afu_present) { 127 fn->max_afu_index = -1; 128 dev_dbg(&dev->dev, "Function doesn't define any AFU\n"); 129 goto out; 130 } 131 fn->max_afu_index = EXTRACT_BITS(val, 24, 29); 132 133 out: 134 dev_dbg(&dev->dev, "Function DVSEC:\n"); 135 dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index); 136 return 0; 137 } 138 139 static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn) 140 { 141 int pos; 142 143 if (fn->max_afu_index < 0) { 144 fn->dvsec_afu_info_pos = -1; 145 return 0; 146 } 147 148 pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID); 149 if (!pos) { 150 dev_err(&dev->dev, "Can't find AFU information DVSEC\n"); 151 return -ENODEV; 152 } 153 fn->dvsec_afu_info_pos = pos; 154 return 0; 155 } 156 157 static int read_dvsec_vendor(struct pci_dev *dev) 158 { 159 int pos; 160 u32 cfg, tlx, dlx; 161 162 /* 163 * vendor specific DVSEC is optional 164 * 165 * It's currently only used on function 0 to specify the 166 * version of some logic blocks. Some older images may not 167 * even have it so we ignore any errors 168 */ 169 if (PCI_FUNC(dev->devfn) != 0) 170 return 0; 171 172 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID); 173 if (!pos) 174 return 0; 175 176 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg); 177 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx); 178 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx); 179 180 dev_dbg(&dev->dev, "Vendor specific DVSEC:\n"); 181 dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg); 182 dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx); 183 dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx); 184 return 0; 185 } 186 187 static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn) 188 { 189 if (fn->max_pasid_log == -1 && fn->max_afu_index >= 0) { 190 dev_err(&dev->dev, 191 "AFUs are defined but no PASIDs are requested\n"); 192 return -EINVAL; 193 } 194 195 if (fn->max_afu_index > OCXL_MAX_AFU_PER_FUNCTION) { 196 dev_err(&dev->dev, 197 "Max AFU index out of architectural limit (%d vs %d)\n", 198 fn->max_afu_index, OCXL_MAX_AFU_PER_FUNCTION); 199 return -EINVAL; 200 } 201 return 0; 202 } 203 204 int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn) 205 { 206 int rc; 207 208 rc = read_pasid(dev, fn); 209 if (rc) { 210 dev_err(&dev->dev, "Invalid PASID configuration: %d\n", rc); 211 return -ENODEV; 212 } 213 214 rc = read_dvsec_tl(dev, fn); 215 if (rc) { 216 dev_err(&dev->dev, 217 "Invalid Transaction Layer DVSEC configuration: %d\n", 218 rc); 219 return -ENODEV; 220 } 221 222 rc = read_dvsec_function(dev, fn); 223 if (rc) { 224 dev_err(&dev->dev, 225 "Invalid Function DVSEC configuration: %d\n", rc); 226 return -ENODEV; 227 } 228 229 rc = read_dvsec_afu_info(dev, fn); 230 if (rc) { 231 dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc); 232 return -ENODEV; 233 } 234 235 rc = read_dvsec_vendor(dev); 236 if (rc) { 237 dev_err(&dev->dev, 238 "Invalid vendor specific DVSEC configuration: %d\n", 239 rc); 240 return -ENODEV; 241 } 242 243 rc = validate_function(dev, fn); 244 return rc; 245 } 246 EXPORT_SYMBOL_GPL(ocxl_config_read_function); 247 248 static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn, 249 int offset, u32 *data) 250 { 251 u32 val; 252 unsigned long timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT); 253 int pos = fn->dvsec_afu_info_pos; 254 255 /* Protect 'data valid' bit */ 256 if (EXTRACT_BIT(offset, 31)) { 257 dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n"); 258 return -EINVAL; 259 } 260 261 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset); 262 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val); 263 while (!EXTRACT_BIT(val, 31)) { 264 if (time_after_eq(jiffies, timeout)) { 265 dev_err(&dev->dev, 266 "Timeout while reading AFU info DVSEC (offset=%d)\n", 267 offset); 268 return -EBUSY; 269 } 270 cpu_relax(); 271 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val); 272 } 273 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data); 274 return 0; 275 } 276 277 int ocxl_config_check_afu_index(struct pci_dev *dev, 278 struct ocxl_fn_config *fn, int afu_idx) 279 { 280 u32 val; 281 int rc, templ_major, templ_minor, len; 282 283 pci_write_config_byte(dev, 284 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX, 285 afu_idx); 286 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val); 287 if (rc) 288 return rc; 289 290 /* AFU index map can have holes */ 291 if (!val) 292 return 0; 293 294 templ_major = EXTRACT_BITS(val, 8, 15); 295 templ_minor = EXTRACT_BITS(val, 0, 7); 296 dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n", 297 templ_major, templ_minor); 298 299 len = EXTRACT_BITS(val, 16, 31); 300 if (len != OCXL_TEMPL_LEN) { 301 dev_warn(&dev->dev, 302 "Unexpected template length in AFU information (%#x)\n", 303 len); 304 } 305 return 1; 306 } 307 EXPORT_SYMBOL_GPL(ocxl_config_check_afu_index); 308 309 static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn, 310 struct ocxl_afu_config *afu) 311 { 312 int i, rc; 313 u32 val, *ptr; 314 315 BUILD_BUG_ON(OCXL_AFU_NAME_SZ < OCXL_TEMPL_NAME_LEN); 316 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i += 4) { 317 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val); 318 if (rc) 319 return rc; 320 ptr = (u32 *) &afu->name[i]; 321 *ptr = le32_to_cpu((__force __le32) val); 322 } 323 afu->name[OCXL_AFU_NAME_SZ - 1] = '\0'; /* play safe */ 324 return 0; 325 } 326 327 static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn, 328 struct ocxl_afu_config *afu) 329 { 330 int rc; 331 u32 val; 332 333 /* 334 * Global MMIO 335 */ 336 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val); 337 if (rc) 338 return rc; 339 afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2); 340 afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16; 341 342 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val); 343 if (rc) 344 return rc; 345 afu->global_mmio_offset += (u64) val << 32; 346 347 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val); 348 if (rc) 349 return rc; 350 afu->global_mmio_size = val; 351 352 /* 353 * Per-process MMIO 354 */ 355 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val); 356 if (rc) 357 return rc; 358 afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2); 359 afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16; 360 361 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val); 362 if (rc) 363 return rc; 364 afu->pp_mmio_offset += (u64) val << 32; 365 366 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val); 367 if (rc) 368 return rc; 369 afu->pp_mmio_stride = val; 370 371 return 0; 372 } 373 374 static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu) 375 { 376 int pos; 377 u8 val8; 378 u16 val16; 379 380 pos = find_dvsec_afu_ctrl(dev, afu->idx); 381 if (!pos) { 382 dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n", 383 afu->idx); 384 return -ENODEV; 385 } 386 afu->dvsec_afu_control_pos = pos; 387 388 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8); 389 afu->pasid_supported_log = EXTRACT_BITS(val8, 0, 4); 390 391 pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16); 392 afu->actag_supported = EXTRACT_BITS(val16, 0, 11); 393 return 0; 394 } 395 396 static bool char_allowed(int c) 397 { 398 /* 399 * Permitted Characters : Alphanumeric, hyphen, underscore, comma 400 */ 401 if ((c >= 0x30 && c <= 0x39) /* digits */ || 402 (c >= 0x41 && c <= 0x5A) /* upper case */ || 403 (c >= 0x61 && c <= 0x7A) /* lower case */ || 404 c == 0 /* NULL */ || 405 c == 0x2D /* - */ || 406 c == 0x5F /* _ */ || 407 c == 0x2C /* , */) 408 return true; 409 return false; 410 } 411 412 static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu) 413 { 414 int i; 415 416 if (!afu->name[0]) { 417 dev_err(&dev->dev, "Empty AFU name\n"); 418 return -EINVAL; 419 } 420 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i++) { 421 if (!char_allowed(afu->name[i])) { 422 dev_err(&dev->dev, 423 "Invalid character in AFU name\n"); 424 return -EINVAL; 425 } 426 } 427 428 if (afu->global_mmio_bar != 0 && 429 afu->global_mmio_bar != 2 && 430 afu->global_mmio_bar != 4) { 431 dev_err(&dev->dev, "Invalid global MMIO bar number\n"); 432 return -EINVAL; 433 } 434 if (afu->pp_mmio_bar != 0 && 435 afu->pp_mmio_bar != 2 && 436 afu->pp_mmio_bar != 4) { 437 dev_err(&dev->dev, "Invalid per-process MMIO bar number\n"); 438 return -EINVAL; 439 } 440 return 0; 441 } 442 443 int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn, 444 struct ocxl_afu_config *afu, u8 afu_idx) 445 { 446 int rc; 447 u32 val32; 448 449 /* 450 * First, we need to write the AFU idx for the AFU we want to 451 * access. 452 */ 453 WARN_ON((afu_idx & OCXL_DVSEC_AFU_IDX_MASK) != afu_idx); 454 afu->idx = afu_idx; 455 pci_write_config_byte(dev, 456 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX, 457 afu->idx); 458 459 rc = read_afu_name(dev, fn, afu); 460 if (rc) 461 return rc; 462 463 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32); 464 if (rc) 465 return rc; 466 afu->version_major = EXTRACT_BITS(val32, 24, 31); 467 afu->version_minor = EXTRACT_BITS(val32, 16, 23); 468 afu->afuc_type = EXTRACT_BITS(val32, 14, 15); 469 afu->afum_type = EXTRACT_BITS(val32, 12, 13); 470 afu->profile = EXTRACT_BITS(val32, 0, 7); 471 472 rc = read_afu_mmio(dev, fn, afu); 473 if (rc) 474 return rc; 475 476 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MEM_SZ, &val32); 477 if (rc) 478 return rc; 479 afu->log_mem_size = EXTRACT_BITS(val32, 0, 7); 480 481 rc = read_afu_control(dev, afu); 482 if (rc) 483 return rc; 484 485 dev_dbg(&dev->dev, "AFU configuration:\n"); 486 dev_dbg(&dev->dev, " name = %s\n", afu->name); 487 dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major, 488 afu->version_minor); 489 dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar); 490 dev_dbg(&dev->dev, " global mmio offset = %#llx\n", 491 afu->global_mmio_offset); 492 dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size); 493 dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar); 494 dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset); 495 dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride); 496 dev_dbg(&dev->dev, " mem size (log) = %hhu\n", afu->log_mem_size); 497 dev_dbg(&dev->dev, " pasid supported (log) = %u\n", 498 afu->pasid_supported_log); 499 dev_dbg(&dev->dev, " actag supported = %u\n", 500 afu->actag_supported); 501 502 rc = validate_afu(dev, afu); 503 return rc; 504 } 505 EXPORT_SYMBOL_GPL(ocxl_config_read_afu); 506 507 int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled, 508 u16 *supported) 509 { 510 int rc; 511 512 /* 513 * This is really a simple wrapper for the kernel API, to 514 * avoid an external driver using ocxl as a library to call 515 * platform-dependent code 516 */ 517 rc = pnv_ocxl_get_actag(dev, base, enabled, supported); 518 if (rc) { 519 dev_err(&dev->dev, "Can't get actag for device: %d\n", rc); 520 return rc; 521 } 522 return 0; 523 } 524 EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info); 525 526 void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base, 527 int actag_count) 528 { 529 u16 val; 530 531 val = actag_count & OCXL_DVSEC_ACTAG_MASK; 532 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val); 533 534 val = actag_base & OCXL_DVSEC_ACTAG_MASK; 535 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val); 536 } 537 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag); 538 539 int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count) 540 { 541 return pnv_ocxl_get_pasid_count(dev, count); 542 } 543 EXPORT_SYMBOL_GPL(ocxl_config_get_pasid_info); 544 545 void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base, 546 u32 pasid_count_log) 547 { 548 u8 val8; 549 u32 val32; 550 551 val8 = pasid_count_log & OCXL_DVSEC_PASID_LOG_MASK; 552 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8); 553 554 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE, 555 &val32); 556 val32 &= ~OCXL_DVSEC_PASID_MASK; 557 val32 |= pasid_base & OCXL_DVSEC_PASID_MASK; 558 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE, 559 val32); 560 } 561 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid); 562 563 void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable) 564 { 565 u8 val; 566 567 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val); 568 if (enable) 569 val |= 1; 570 else 571 val &= 0xFE; 572 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val); 573 } 574 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state); 575 576 int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec) 577 { 578 u32 val; 579 __be32 *be32ptr; 580 u8 timers; 581 int i, rc; 582 long recv_cap; 583 char *recv_rate; 584 585 /* 586 * Skip on function != 0, as the TL can only be defined on 0 587 */ 588 if (PCI_FUNC(dev->devfn) != 0) 589 return 0; 590 591 recv_rate = kzalloc(PNV_OCXL_TL_RATE_BUF_SIZE, GFP_KERNEL); 592 if (!recv_rate) 593 return -ENOMEM; 594 /* 595 * The spec defines 64 templates for messages in the 596 * Transaction Layer (TL). 597 * 598 * The host and device each support a subset, so we need to 599 * configure the transmitters on each side to send only 600 * templates the receiver understands, at a rate the receiver 601 * can process. Per the spec, template 0 must be supported by 602 * everybody. That's the template which has been used by the 603 * host and device so far. 604 * 605 * The sending rate limit must be set before the template is 606 * enabled. 607 */ 608 609 /* 610 * Device -> host 611 */ 612 rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate, 613 PNV_OCXL_TL_RATE_BUF_SIZE); 614 if (rc) 615 goto out; 616 617 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) { 618 be32ptr = (__be32 *) &recv_rate[i]; 619 pci_write_config_dword(dev, 620 tl_dvsec + OCXL_DVSEC_TL_SEND_RATE + i, 621 be32_to_cpu(*be32ptr)); 622 } 623 val = recv_cap >> 32; 624 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val); 625 val = recv_cap & GENMASK(31, 0); 626 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val); 627 628 /* 629 * Host -> device 630 */ 631 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) { 632 pci_read_config_dword(dev, 633 tl_dvsec + OCXL_DVSEC_TL_RECV_RATE + i, 634 &val); 635 be32ptr = (__be32 *) &recv_rate[i]; 636 *be32ptr = cpu_to_be32(val); 637 } 638 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val); 639 recv_cap = (long) val << 32; 640 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val); 641 recv_cap |= val; 642 643 rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate), 644 PNV_OCXL_TL_RATE_BUF_SIZE); 645 if (rc) 646 goto out; 647 648 /* 649 * Opencapi commands needing to be retried are classified per 650 * the TL in 2 groups: short and long commands. 651 * 652 * The short back off timer it not used for now. It will be 653 * for opencapi 4.0. 654 * 655 * The long back off timer is typically used when an AFU hits 656 * a page fault but the NPU is already processing one. So the 657 * AFU needs to wait before it can resubmit. Having a value 658 * too low doesn't break anything, but can generate extra 659 * traffic on the link. 660 * We set it to 1.6 us for now. It's shorter than, but in the 661 * same order of magnitude as the time spent to process a page 662 * fault. 663 */ 664 timers = 0x2 << 4; /* long timer = 1.6 us */ 665 pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS, 666 timers); 667 668 rc = 0; 669 out: 670 kfree(recv_rate); 671 return rc; 672 } 673 EXPORT_SYMBOL_GPL(ocxl_config_set_TL); 674 675 int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid) 676 { 677 u32 val; 678 unsigned long timeout; 679 680 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID, 681 &val); 682 if (EXTRACT_BIT(val, 20)) { 683 dev_err(&dev->dev, 684 "Can't terminate PASID %#x, previous termination didn't complete\n", 685 pasid); 686 return -EBUSY; 687 } 688 689 val &= ~OCXL_DVSEC_PASID_MASK; 690 val |= pasid & OCXL_DVSEC_PASID_MASK; 691 val |= BIT(20); 692 pci_write_config_dword(dev, 693 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID, 694 val); 695 696 timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT); 697 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID, 698 &val); 699 while (EXTRACT_BIT(val, 20)) { 700 if (time_after_eq(jiffies, timeout)) { 701 dev_err(&dev->dev, 702 "Timeout while waiting for AFU to terminate PASID %#x\n", 703 pasid); 704 return -EBUSY; 705 } 706 cpu_relax(); 707 pci_read_config_dword(dev, 708 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID, 709 &val); 710 } 711 return 0; 712 } 713 EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid); 714 715 void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first, 716 u32 tag_count) 717 { 718 u32 val; 719 720 val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16; 721 val |= tag_count & OCXL_DVSEC_ACTAG_MASK; 722 pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG, 723 val); 724 } 725 EXPORT_SYMBOL_GPL(ocxl_config_set_actag); 726