1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/sched.h> 14 #include <linux/interrupt.h> 15 16 #include <linux/pm_domain.h> 17 #include <linux/pm_runtime.h> 18 19 #include <linux/mei.h> 20 21 #include "mei_dev.h" 22 #include "client.h" 23 #include "hw-me-regs.h" 24 #include "hw-me.h" 25 26 /* mei_pci_tbl - PCI Device ID Table */ 27 static const struct pci_device_id mei_me_pci_tbl[] = { 28 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 29 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 30 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 31 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 32 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 34 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 39 40 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 49 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 54 55 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 58 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 68 69 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, 74 75 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 77 78 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 79 80 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 81 82 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 83 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 84 85 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 86 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_CFG)}, 87 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, 88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_NODMA_CFG)}, 89 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 91 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, 92 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)}, 95 96 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 97 98 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 99 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, 100 101 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 102 103 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 104 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 105 106 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, 107 108 /* required last entry */ 109 {0, } 110 }; 111 112 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 113 114 #ifdef CONFIG_PM 115 static inline void mei_me_set_pm_domain(struct mei_device *dev); 116 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 117 #else 118 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 119 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 120 #endif /* CONFIG_PM */ 121 122 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 123 { 124 struct pci_dev *pdev = to_pci_dev(dev->dev); 125 126 return pci_read_config_dword(pdev, where, val); 127 } 128 129 /** 130 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 131 * 132 * @pdev: PCI device structure 133 * @cfg: per generation config 134 * 135 * Return: true if ME Interface is valid, false otherwise 136 */ 137 static bool mei_me_quirk_probe(struct pci_dev *pdev, 138 const struct mei_cfg *cfg) 139 { 140 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 141 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 142 return false; 143 } 144 145 return true; 146 } 147 148 /** 149 * mei_me_probe - Device Initialization Routine 150 * 151 * @pdev: PCI device structure 152 * @ent: entry in kcs_pci_tbl 153 * 154 * Return: 0 on success, <0 on failure. 155 */ 156 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 157 { 158 const struct mei_cfg *cfg; 159 struct mei_device *dev; 160 struct mei_me_hw *hw; 161 unsigned int irqflags; 162 int err; 163 164 cfg = mei_me_get_cfg(ent->driver_data); 165 if (!cfg) 166 return -ENODEV; 167 168 if (!mei_me_quirk_probe(pdev, cfg)) 169 return -ENODEV; 170 171 /* enable pci dev */ 172 err = pcim_enable_device(pdev); 173 if (err) { 174 dev_err(&pdev->dev, "failed to enable pci device.\n"); 175 goto end; 176 } 177 /* set PCI host mastering */ 178 pci_set_master(pdev); 179 /* pci request regions and mapping IO device memory for mei driver */ 180 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 181 if (err) { 182 dev_err(&pdev->dev, "failed to get pci regions.\n"); 183 goto end; 184 } 185 186 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 187 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 188 189 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 190 if (err) 191 err = dma_set_coherent_mask(&pdev->dev, 192 DMA_BIT_MASK(32)); 193 } 194 if (err) { 195 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 196 goto end; 197 } 198 199 /* allocates and initializes the mei dev structure */ 200 dev = mei_me_dev_init(&pdev->dev, cfg); 201 if (!dev) { 202 err = -ENOMEM; 203 goto end; 204 } 205 hw = to_me_hw(dev); 206 hw->mem_addr = pcim_iomap_table(pdev)[0]; 207 hw->read_fws = mei_me_read_fws; 208 209 pci_enable_msi(pdev); 210 211 hw->irq = pdev->irq; 212 213 /* request and enable interrupt */ 214 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 215 216 err = request_threaded_irq(pdev->irq, 217 mei_me_irq_quick_handler, 218 mei_me_irq_thread_handler, 219 irqflags, KBUILD_MODNAME, dev); 220 if (err) { 221 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 222 pdev->irq); 223 goto end; 224 } 225 226 if (mei_start(dev)) { 227 dev_err(&pdev->dev, "init hw failure.\n"); 228 err = -ENODEV; 229 goto release_irq; 230 } 231 232 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 233 pm_runtime_use_autosuspend(&pdev->dev); 234 235 err = mei_register(dev, &pdev->dev); 236 if (err) 237 goto stop; 238 239 pci_set_drvdata(pdev, dev); 240 241 /* 242 * MEI requires to resume from runtime suspend mode 243 * in order to perform link reset flow upon system suspend. 244 */ 245 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 246 247 /* 248 * ME maps runtime suspend/resume to D0i states, 249 * hence we need to go around native PCI runtime service which 250 * eventually brings the device into D3cold/hot state, 251 * but the mei device cannot wake up from D3 unlike from D0i3. 252 * To get around the PCI device native runtime pm, 253 * ME uses runtime pm domain handlers which take precedence 254 * over the driver's pm handlers. 255 */ 256 mei_me_set_pm_domain(dev); 257 258 if (mei_pg_is_enabled(dev)) { 259 pm_runtime_put_noidle(&pdev->dev); 260 if (hw->d0i3_supported) 261 pm_runtime_allow(&pdev->dev); 262 } 263 264 dev_dbg(&pdev->dev, "initialization successful.\n"); 265 266 return 0; 267 268 stop: 269 mei_stop(dev); 270 release_irq: 271 mei_cancel_work(dev); 272 mei_disable_interrupts(dev); 273 free_irq(pdev->irq, dev); 274 end: 275 dev_err(&pdev->dev, "initialization failed.\n"); 276 return err; 277 } 278 279 /** 280 * mei_me_shutdown - Device Removal Routine 281 * 282 * @pdev: PCI device structure 283 * 284 * mei_me_shutdown is called from the reboot notifier 285 * it's a simplified version of remove so we go down 286 * faster. 287 */ 288 static void mei_me_shutdown(struct pci_dev *pdev) 289 { 290 struct mei_device *dev; 291 292 dev = pci_get_drvdata(pdev); 293 if (!dev) 294 return; 295 296 dev_dbg(&pdev->dev, "shutdown\n"); 297 mei_stop(dev); 298 299 mei_me_unset_pm_domain(dev); 300 301 mei_disable_interrupts(dev); 302 free_irq(pdev->irq, dev); 303 } 304 305 /** 306 * mei_me_remove - Device Removal Routine 307 * 308 * @pdev: PCI device structure 309 * 310 * mei_me_remove is called by the PCI subsystem to alert the driver 311 * that it should release a PCI device. 312 */ 313 static void mei_me_remove(struct pci_dev *pdev) 314 { 315 struct mei_device *dev; 316 317 dev = pci_get_drvdata(pdev); 318 if (!dev) 319 return; 320 321 if (mei_pg_is_enabled(dev)) 322 pm_runtime_get_noresume(&pdev->dev); 323 324 dev_dbg(&pdev->dev, "stop\n"); 325 mei_stop(dev); 326 327 mei_me_unset_pm_domain(dev); 328 329 mei_disable_interrupts(dev); 330 331 free_irq(pdev->irq, dev); 332 333 mei_deregister(dev); 334 } 335 336 #ifdef CONFIG_PM_SLEEP 337 static int mei_me_pci_suspend(struct device *device) 338 { 339 struct pci_dev *pdev = to_pci_dev(device); 340 struct mei_device *dev = pci_get_drvdata(pdev); 341 342 if (!dev) 343 return -ENODEV; 344 345 dev_dbg(&pdev->dev, "suspend\n"); 346 347 mei_stop(dev); 348 349 mei_disable_interrupts(dev); 350 351 free_irq(pdev->irq, dev); 352 pci_disable_msi(pdev); 353 354 return 0; 355 } 356 357 static int mei_me_pci_resume(struct device *device) 358 { 359 struct pci_dev *pdev = to_pci_dev(device); 360 struct mei_device *dev; 361 unsigned int irqflags; 362 int err; 363 364 dev = pci_get_drvdata(pdev); 365 if (!dev) 366 return -ENODEV; 367 368 pci_enable_msi(pdev); 369 370 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 371 372 /* request and enable interrupt */ 373 err = request_threaded_irq(pdev->irq, 374 mei_me_irq_quick_handler, 375 mei_me_irq_thread_handler, 376 irqflags, KBUILD_MODNAME, dev); 377 378 if (err) { 379 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 380 pdev->irq); 381 return err; 382 } 383 384 err = mei_restart(dev); 385 if (err) 386 return err; 387 388 /* Start timer if stopped in suspend */ 389 schedule_delayed_work(&dev->timer_work, HZ); 390 391 return 0; 392 } 393 #endif /* CONFIG_PM_SLEEP */ 394 395 #ifdef CONFIG_PM 396 static int mei_me_pm_runtime_idle(struct device *device) 397 { 398 struct mei_device *dev; 399 400 dev_dbg(device, "rpm: me: runtime_idle\n"); 401 402 dev = dev_get_drvdata(device); 403 if (!dev) 404 return -ENODEV; 405 if (mei_write_is_idle(dev)) 406 pm_runtime_autosuspend(device); 407 408 return -EBUSY; 409 } 410 411 static int mei_me_pm_runtime_suspend(struct device *device) 412 { 413 struct mei_device *dev; 414 int ret; 415 416 dev_dbg(device, "rpm: me: runtime suspend\n"); 417 418 dev = dev_get_drvdata(device); 419 if (!dev) 420 return -ENODEV; 421 422 mutex_lock(&dev->device_lock); 423 424 if (mei_write_is_idle(dev)) 425 ret = mei_me_pg_enter_sync(dev); 426 else 427 ret = -EAGAIN; 428 429 mutex_unlock(&dev->device_lock); 430 431 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 432 433 if (ret && ret != -EAGAIN) 434 schedule_work(&dev->reset_work); 435 436 return ret; 437 } 438 439 static int mei_me_pm_runtime_resume(struct device *device) 440 { 441 struct mei_device *dev; 442 int ret; 443 444 dev_dbg(device, "rpm: me: runtime resume\n"); 445 446 dev = dev_get_drvdata(device); 447 if (!dev) 448 return -ENODEV; 449 450 mutex_lock(&dev->device_lock); 451 452 ret = mei_me_pg_exit_sync(dev); 453 454 mutex_unlock(&dev->device_lock); 455 456 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 457 458 if (ret) 459 schedule_work(&dev->reset_work); 460 461 return ret; 462 } 463 464 /** 465 * mei_me_set_pm_domain - fill and set pm domain structure for device 466 * 467 * @dev: mei_device 468 */ 469 static inline void mei_me_set_pm_domain(struct mei_device *dev) 470 { 471 struct pci_dev *pdev = to_pci_dev(dev->dev); 472 473 if (pdev->dev.bus && pdev->dev.bus->pm) { 474 dev->pg_domain.ops = *pdev->dev.bus->pm; 475 476 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 477 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 478 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 479 480 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 481 } 482 } 483 484 /** 485 * mei_me_unset_pm_domain - clean pm domain structure for device 486 * 487 * @dev: mei_device 488 */ 489 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 490 { 491 /* stop using pm callbacks if any */ 492 dev_pm_domain_set(dev->dev, NULL); 493 } 494 495 static const struct dev_pm_ops mei_me_pm_ops = { 496 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 497 mei_me_pci_resume) 498 SET_RUNTIME_PM_OPS( 499 mei_me_pm_runtime_suspend, 500 mei_me_pm_runtime_resume, 501 mei_me_pm_runtime_idle) 502 }; 503 504 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 505 #else 506 #define MEI_ME_PM_OPS NULL 507 #endif /* CONFIG_PM */ 508 /* 509 * PCI driver structure 510 */ 511 static struct pci_driver mei_me_driver = { 512 .name = KBUILD_MODNAME, 513 .id_table = mei_me_pci_tbl, 514 .probe = mei_me_probe, 515 .remove = mei_me_remove, 516 .shutdown = mei_me_shutdown, 517 .driver.pm = MEI_ME_PM_OPS, 518 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 519 }; 520 521 module_pci_driver(mei_me_driver); 522 523 MODULE_AUTHOR("Intel Corporation"); 524 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 525 MODULE_LICENSE("GPL v2"); 526