1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/sched.h> 14 #include <linux/interrupt.h> 15 16 #include <linux/pm_domain.h> 17 #include <linux/pm_runtime.h> 18 19 #include <linux/mei.h> 20 21 #include "mei_dev.h" 22 #include "client.h" 23 #include "hw-me-regs.h" 24 #include "hw-me.h" 25 26 /* mei_pci_tbl - PCI Device ID Table */ 27 static const struct pci_device_id mei_me_pci_tbl[] = { 28 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 29 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 30 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 31 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 32 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 34 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 39 40 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 49 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 54 55 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 58 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 68 69 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, 75 76 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 77 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 78 79 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 80 81 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 82 83 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)}, 86 87 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, 91 92 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, 97 98 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)}, 100 101 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, 103 104 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 105 106 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 108 109 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, 110 111 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, 112 113 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)}, 114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)}, 115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)}, 116 117 /* required last entry */ 118 {0, } 119 }; 120 121 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 122 123 #ifdef CONFIG_PM 124 static inline void mei_me_set_pm_domain(struct mei_device *dev); 125 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 126 #else 127 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 128 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 129 #endif /* CONFIG_PM */ 130 131 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 132 { 133 struct pci_dev *pdev = to_pci_dev(dev->dev); 134 135 return pci_read_config_dword(pdev, where, val); 136 } 137 138 /** 139 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 140 * 141 * @pdev: PCI device structure 142 * @cfg: per generation config 143 * 144 * Return: true if ME Interface is valid, false otherwise 145 */ 146 static bool mei_me_quirk_probe(struct pci_dev *pdev, 147 const struct mei_cfg *cfg) 148 { 149 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 150 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 151 return false; 152 } 153 154 return true; 155 } 156 157 /** 158 * mei_me_probe - Device Initialization Routine 159 * 160 * @pdev: PCI device structure 161 * @ent: entry in kcs_pci_tbl 162 * 163 * Return: 0 on success, <0 on failure. 164 */ 165 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 166 { 167 const struct mei_cfg *cfg; 168 struct mei_device *dev; 169 struct mei_me_hw *hw; 170 unsigned int irqflags; 171 int err; 172 173 cfg = mei_me_get_cfg(ent->driver_data); 174 if (!cfg) 175 return -ENODEV; 176 177 if (!mei_me_quirk_probe(pdev, cfg)) 178 return -ENODEV; 179 180 /* enable pci dev */ 181 err = pcim_enable_device(pdev); 182 if (err) { 183 dev_err(&pdev->dev, "failed to enable pci device.\n"); 184 goto end; 185 } 186 /* set PCI host mastering */ 187 pci_set_master(pdev); 188 /* pci request regions and mapping IO device memory for mei driver */ 189 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 190 if (err) { 191 dev_err(&pdev->dev, "failed to get pci regions.\n"); 192 goto end; 193 } 194 195 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 196 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 197 198 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 199 if (err) 200 err = dma_set_coherent_mask(&pdev->dev, 201 DMA_BIT_MASK(32)); 202 } 203 if (err) { 204 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 205 goto end; 206 } 207 208 /* allocates and initializes the mei dev structure */ 209 dev = mei_me_dev_init(&pdev->dev, cfg); 210 if (!dev) { 211 err = -ENOMEM; 212 goto end; 213 } 214 hw = to_me_hw(dev); 215 hw->mem_addr = pcim_iomap_table(pdev)[0]; 216 hw->read_fws = mei_me_read_fws; 217 218 pci_enable_msi(pdev); 219 220 hw->irq = pdev->irq; 221 222 /* request and enable interrupt */ 223 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 224 225 err = request_threaded_irq(pdev->irq, 226 mei_me_irq_quick_handler, 227 mei_me_irq_thread_handler, 228 irqflags, KBUILD_MODNAME, dev); 229 if (err) { 230 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 231 pdev->irq); 232 goto end; 233 } 234 235 if (mei_start(dev)) { 236 dev_err(&pdev->dev, "init hw failure.\n"); 237 err = -ENODEV; 238 goto release_irq; 239 } 240 241 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 242 pm_runtime_use_autosuspend(&pdev->dev); 243 244 err = mei_register(dev, &pdev->dev); 245 if (err) 246 goto stop; 247 248 pci_set_drvdata(pdev, dev); 249 250 /* 251 * MEI requires to resume from runtime suspend mode 252 * in order to perform link reset flow upon system suspend. 253 */ 254 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 255 256 /* 257 * ME maps runtime suspend/resume to D0i states, 258 * hence we need to go around native PCI runtime service which 259 * eventually brings the device into D3cold/hot state, 260 * but the mei device cannot wake up from D3 unlike from D0i3. 261 * To get around the PCI device native runtime pm, 262 * ME uses runtime pm domain handlers which take precedence 263 * over the driver's pm handlers. 264 */ 265 mei_me_set_pm_domain(dev); 266 267 if (mei_pg_is_enabled(dev)) { 268 pm_runtime_put_noidle(&pdev->dev); 269 if (hw->d0i3_supported) 270 pm_runtime_allow(&pdev->dev); 271 } 272 273 dev_dbg(&pdev->dev, "initialization successful.\n"); 274 275 return 0; 276 277 stop: 278 mei_stop(dev); 279 release_irq: 280 mei_cancel_work(dev); 281 mei_disable_interrupts(dev); 282 free_irq(pdev->irq, dev); 283 end: 284 dev_err(&pdev->dev, "initialization failed.\n"); 285 return err; 286 } 287 288 /** 289 * mei_me_shutdown - Device Removal Routine 290 * 291 * @pdev: PCI device structure 292 * 293 * mei_me_shutdown is called from the reboot notifier 294 * it's a simplified version of remove so we go down 295 * faster. 296 */ 297 static void mei_me_shutdown(struct pci_dev *pdev) 298 { 299 struct mei_device *dev; 300 301 dev = pci_get_drvdata(pdev); 302 if (!dev) 303 return; 304 305 dev_dbg(&pdev->dev, "shutdown\n"); 306 mei_stop(dev); 307 308 mei_me_unset_pm_domain(dev); 309 310 mei_disable_interrupts(dev); 311 free_irq(pdev->irq, dev); 312 } 313 314 /** 315 * mei_me_remove - Device Removal Routine 316 * 317 * @pdev: PCI device structure 318 * 319 * mei_me_remove is called by the PCI subsystem to alert the driver 320 * that it should release a PCI device. 321 */ 322 static void mei_me_remove(struct pci_dev *pdev) 323 { 324 struct mei_device *dev; 325 326 dev = pci_get_drvdata(pdev); 327 if (!dev) 328 return; 329 330 if (mei_pg_is_enabled(dev)) 331 pm_runtime_get_noresume(&pdev->dev); 332 333 dev_dbg(&pdev->dev, "stop\n"); 334 mei_stop(dev); 335 336 mei_me_unset_pm_domain(dev); 337 338 mei_disable_interrupts(dev); 339 340 free_irq(pdev->irq, dev); 341 342 mei_deregister(dev); 343 } 344 345 #ifdef CONFIG_PM_SLEEP 346 static int mei_me_pci_suspend(struct device *device) 347 { 348 struct pci_dev *pdev = to_pci_dev(device); 349 struct mei_device *dev = pci_get_drvdata(pdev); 350 351 if (!dev) 352 return -ENODEV; 353 354 dev_dbg(&pdev->dev, "suspend\n"); 355 356 mei_stop(dev); 357 358 mei_disable_interrupts(dev); 359 360 free_irq(pdev->irq, dev); 361 pci_disable_msi(pdev); 362 363 return 0; 364 } 365 366 static int mei_me_pci_resume(struct device *device) 367 { 368 struct pci_dev *pdev = to_pci_dev(device); 369 struct mei_device *dev; 370 unsigned int irqflags; 371 int err; 372 373 dev = pci_get_drvdata(pdev); 374 if (!dev) 375 return -ENODEV; 376 377 pci_enable_msi(pdev); 378 379 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 380 381 /* request and enable interrupt */ 382 err = request_threaded_irq(pdev->irq, 383 mei_me_irq_quick_handler, 384 mei_me_irq_thread_handler, 385 irqflags, KBUILD_MODNAME, dev); 386 387 if (err) { 388 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 389 pdev->irq); 390 return err; 391 } 392 393 err = mei_restart(dev); 394 if (err) 395 return err; 396 397 /* Start timer if stopped in suspend */ 398 schedule_delayed_work(&dev->timer_work, HZ); 399 400 return 0; 401 } 402 #endif /* CONFIG_PM_SLEEP */ 403 404 #ifdef CONFIG_PM 405 static int mei_me_pm_runtime_idle(struct device *device) 406 { 407 struct mei_device *dev; 408 409 dev_dbg(device, "rpm: me: runtime_idle\n"); 410 411 dev = dev_get_drvdata(device); 412 if (!dev) 413 return -ENODEV; 414 if (mei_write_is_idle(dev)) 415 pm_runtime_autosuspend(device); 416 417 return -EBUSY; 418 } 419 420 static int mei_me_pm_runtime_suspend(struct device *device) 421 { 422 struct mei_device *dev; 423 int ret; 424 425 dev_dbg(device, "rpm: me: runtime suspend\n"); 426 427 dev = dev_get_drvdata(device); 428 if (!dev) 429 return -ENODEV; 430 431 mutex_lock(&dev->device_lock); 432 433 if (mei_write_is_idle(dev)) 434 ret = mei_me_pg_enter_sync(dev); 435 else 436 ret = -EAGAIN; 437 438 mutex_unlock(&dev->device_lock); 439 440 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 441 442 if (ret && ret != -EAGAIN) 443 schedule_work(&dev->reset_work); 444 445 return ret; 446 } 447 448 static int mei_me_pm_runtime_resume(struct device *device) 449 { 450 struct mei_device *dev; 451 int ret; 452 453 dev_dbg(device, "rpm: me: runtime resume\n"); 454 455 dev = dev_get_drvdata(device); 456 if (!dev) 457 return -ENODEV; 458 459 mutex_lock(&dev->device_lock); 460 461 ret = mei_me_pg_exit_sync(dev); 462 463 mutex_unlock(&dev->device_lock); 464 465 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 466 467 if (ret) 468 schedule_work(&dev->reset_work); 469 470 return ret; 471 } 472 473 /** 474 * mei_me_set_pm_domain - fill and set pm domain structure for device 475 * 476 * @dev: mei_device 477 */ 478 static inline void mei_me_set_pm_domain(struct mei_device *dev) 479 { 480 struct pci_dev *pdev = to_pci_dev(dev->dev); 481 482 if (pdev->dev.bus && pdev->dev.bus->pm) { 483 dev->pg_domain.ops = *pdev->dev.bus->pm; 484 485 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 486 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 487 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 488 489 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 490 } 491 } 492 493 /** 494 * mei_me_unset_pm_domain - clean pm domain structure for device 495 * 496 * @dev: mei_device 497 */ 498 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 499 { 500 /* stop using pm callbacks if any */ 501 dev_pm_domain_set(dev->dev, NULL); 502 } 503 504 static const struct dev_pm_ops mei_me_pm_ops = { 505 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 506 mei_me_pci_resume) 507 SET_RUNTIME_PM_OPS( 508 mei_me_pm_runtime_suspend, 509 mei_me_pm_runtime_resume, 510 mei_me_pm_runtime_idle) 511 }; 512 513 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 514 #else 515 #define MEI_ME_PM_OPS NULL 516 #endif /* CONFIG_PM */ 517 /* 518 * PCI driver structure 519 */ 520 static struct pci_driver mei_me_driver = { 521 .name = KBUILD_MODNAME, 522 .id_table = mei_me_pci_tbl, 523 .probe = mei_me_probe, 524 .remove = mei_me_remove, 525 .shutdown = mei_me_shutdown, 526 .driver.pm = MEI_ME_PM_OPS, 527 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 528 }; 529 530 module_pci_driver(mei_me_driver); 531 532 MODULE_AUTHOR("Intel Corporation"); 533 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 534 MODULE_LICENSE("GPL v2"); 535