1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/sched.h> 15 #include <linux/interrupt.h> 16 17 #include <linux/pm_domain.h> 18 #include <linux/pm_runtime.h> 19 20 #include <linux/mei.h> 21 22 #include "mei_dev.h" 23 #include "client.h" 24 #include "hw-me-regs.h" 25 #include "hw-me.h" 26 27 /* mei_pci_tbl - PCI Device ID Table */ 28 static const struct pci_device_id mei_me_pci_tbl[] = { 29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 40 41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 50 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 55 56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 69 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, 76 77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 79 80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 81 82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 83 84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)}, 87 88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, 91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, 92 93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, 98 99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)}, 101 102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, 104 105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 106 107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 109 110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, 111 112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, 113 114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)}, 115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)}, 116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)}, 117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)}, 118 119 {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)}, 120 121 {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)}, 122 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)}, 123 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)}, 124 125 {MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)}, 126 127 /* required last entry */ 128 {0, } 129 }; 130 131 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 132 133 #ifdef CONFIG_PM 134 static inline void mei_me_set_pm_domain(struct mei_device *dev); 135 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 136 #else 137 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 138 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 139 #endif /* CONFIG_PM */ 140 141 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 142 { 143 struct pci_dev *pdev = to_pci_dev(dev->dev); 144 145 return pci_read_config_dword(pdev, where, val); 146 } 147 148 /** 149 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 150 * 151 * @pdev: PCI device structure 152 * @cfg: per generation config 153 * 154 * Return: true if ME Interface is valid, false otherwise 155 */ 156 static bool mei_me_quirk_probe(struct pci_dev *pdev, 157 const struct mei_cfg *cfg) 158 { 159 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 160 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 161 return false; 162 } 163 164 return true; 165 } 166 167 /** 168 * mei_me_probe - Device Initialization Routine 169 * 170 * @pdev: PCI device structure 171 * @ent: entry in kcs_pci_tbl 172 * 173 * Return: 0 on success, <0 on failure. 174 */ 175 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 176 { 177 const struct mei_cfg *cfg; 178 struct mei_device *dev; 179 struct mei_me_hw *hw; 180 unsigned int irqflags; 181 int err; 182 183 cfg = mei_me_get_cfg(ent->driver_data); 184 if (!cfg) 185 return -ENODEV; 186 187 if (!mei_me_quirk_probe(pdev, cfg)) 188 return -ENODEV; 189 190 /* enable pci dev */ 191 err = pcim_enable_device(pdev); 192 if (err) { 193 dev_err(&pdev->dev, "failed to enable pci device.\n"); 194 goto end; 195 } 196 /* set PCI host mastering */ 197 pci_set_master(pdev); 198 /* pci request regions and mapping IO device memory for mei driver */ 199 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 200 if (err) { 201 dev_err(&pdev->dev, "failed to get pci regions.\n"); 202 goto end; 203 } 204 205 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 206 if (err) { 207 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 208 goto end; 209 } 210 211 /* allocates and initializes the mei dev structure */ 212 dev = mei_me_dev_init(&pdev->dev, cfg, false); 213 if (!dev) { 214 err = -ENOMEM; 215 goto end; 216 } 217 hw = to_me_hw(dev); 218 hw->mem_addr = pcim_iomap_table(pdev)[0]; 219 hw->read_fws = mei_me_read_fws; 220 221 pci_enable_msi(pdev); 222 223 hw->irq = pdev->irq; 224 225 /* request and enable interrupt */ 226 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 227 228 err = request_threaded_irq(pdev->irq, 229 mei_me_irq_quick_handler, 230 mei_me_irq_thread_handler, 231 irqflags, KBUILD_MODNAME, dev); 232 if (err) { 233 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 234 pdev->irq); 235 goto end; 236 } 237 238 if (mei_start(dev)) { 239 dev_err(&pdev->dev, "init hw failure.\n"); 240 err = -ENODEV; 241 goto release_irq; 242 } 243 244 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 245 pm_runtime_use_autosuspend(&pdev->dev); 246 247 err = mei_register(dev, &pdev->dev); 248 if (err) 249 goto stop; 250 251 pci_set_drvdata(pdev, dev); 252 253 /* 254 * MEI requires to resume from runtime suspend mode 255 * in order to perform link reset flow upon system suspend. 256 */ 257 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 258 259 /* 260 * ME maps runtime suspend/resume to D0i states, 261 * hence we need to go around native PCI runtime service which 262 * eventually brings the device into D3cold/hot state, 263 * but the mei device cannot wake up from D3 unlike from D0i3. 264 * To get around the PCI device native runtime pm, 265 * ME uses runtime pm domain handlers which take precedence 266 * over the driver's pm handlers. 267 */ 268 mei_me_set_pm_domain(dev); 269 270 if (mei_pg_is_enabled(dev)) { 271 pm_runtime_put_noidle(&pdev->dev); 272 if (hw->d0i3_supported) 273 pm_runtime_allow(&pdev->dev); 274 } 275 276 dev_dbg(&pdev->dev, "initialization successful.\n"); 277 278 return 0; 279 280 stop: 281 mei_stop(dev); 282 release_irq: 283 mei_cancel_work(dev); 284 mei_disable_interrupts(dev); 285 free_irq(pdev->irq, dev); 286 end: 287 dev_err(&pdev->dev, "initialization failed.\n"); 288 return err; 289 } 290 291 /** 292 * mei_me_shutdown - Device Removal Routine 293 * 294 * @pdev: PCI device structure 295 * 296 * mei_me_shutdown is called from the reboot notifier 297 * it's a simplified version of remove so we go down 298 * faster. 299 */ 300 static void mei_me_shutdown(struct pci_dev *pdev) 301 { 302 struct mei_device *dev; 303 304 dev = pci_get_drvdata(pdev); 305 if (!dev) 306 return; 307 308 dev_dbg(&pdev->dev, "shutdown\n"); 309 mei_stop(dev); 310 311 mei_me_unset_pm_domain(dev); 312 313 mei_disable_interrupts(dev); 314 free_irq(pdev->irq, dev); 315 } 316 317 /** 318 * mei_me_remove - Device Removal Routine 319 * 320 * @pdev: PCI device structure 321 * 322 * mei_me_remove is called by the PCI subsystem to alert the driver 323 * that it should release a PCI device. 324 */ 325 static void mei_me_remove(struct pci_dev *pdev) 326 { 327 struct mei_device *dev; 328 329 dev = pci_get_drvdata(pdev); 330 if (!dev) 331 return; 332 333 if (mei_pg_is_enabled(dev)) 334 pm_runtime_get_noresume(&pdev->dev); 335 336 dev_dbg(&pdev->dev, "stop\n"); 337 mei_stop(dev); 338 339 mei_me_unset_pm_domain(dev); 340 341 mei_disable_interrupts(dev); 342 343 free_irq(pdev->irq, dev); 344 345 mei_deregister(dev); 346 } 347 348 #ifdef CONFIG_PM_SLEEP 349 static int mei_me_pci_prepare(struct device *device) 350 { 351 pm_runtime_resume(device); 352 return 0; 353 } 354 355 static int mei_me_pci_suspend(struct device *device) 356 { 357 struct pci_dev *pdev = to_pci_dev(device); 358 struct mei_device *dev = pci_get_drvdata(pdev); 359 360 if (!dev) 361 return -ENODEV; 362 363 dev_dbg(&pdev->dev, "suspend\n"); 364 365 mei_stop(dev); 366 367 mei_disable_interrupts(dev); 368 369 free_irq(pdev->irq, dev); 370 pci_disable_msi(pdev); 371 372 return 0; 373 } 374 375 static int mei_me_pci_resume(struct device *device) 376 { 377 struct pci_dev *pdev = to_pci_dev(device); 378 struct mei_device *dev; 379 unsigned int irqflags; 380 int err; 381 382 dev = pci_get_drvdata(pdev); 383 if (!dev) 384 return -ENODEV; 385 386 pci_enable_msi(pdev); 387 388 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 389 390 /* request and enable interrupt */ 391 err = request_threaded_irq(pdev->irq, 392 mei_me_irq_quick_handler, 393 mei_me_irq_thread_handler, 394 irqflags, KBUILD_MODNAME, dev); 395 396 if (err) { 397 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 398 pdev->irq); 399 return err; 400 } 401 402 err = mei_restart(dev); 403 if (err) { 404 free_irq(pdev->irq, dev); 405 return err; 406 } 407 408 /* Start timer if stopped in suspend */ 409 schedule_delayed_work(&dev->timer_work, HZ); 410 411 return 0; 412 } 413 414 static void mei_me_pci_complete(struct device *device) 415 { 416 pm_runtime_suspend(device); 417 } 418 #else /* CONFIG_PM_SLEEP */ 419 420 #define mei_me_pci_prepare NULL 421 #define mei_me_pci_complete NULL 422 423 #endif /* !CONFIG_PM_SLEEP */ 424 425 #ifdef CONFIG_PM 426 static int mei_me_pm_runtime_idle(struct device *device) 427 { 428 struct mei_device *dev; 429 430 dev_dbg(device, "rpm: me: runtime_idle\n"); 431 432 dev = dev_get_drvdata(device); 433 if (!dev) 434 return -ENODEV; 435 if (mei_write_is_idle(dev)) 436 pm_runtime_autosuspend(device); 437 438 return -EBUSY; 439 } 440 441 static int mei_me_pm_runtime_suspend(struct device *device) 442 { 443 struct mei_device *dev; 444 int ret; 445 446 dev_dbg(device, "rpm: me: runtime suspend\n"); 447 448 dev = dev_get_drvdata(device); 449 if (!dev) 450 return -ENODEV; 451 452 mutex_lock(&dev->device_lock); 453 454 if (mei_write_is_idle(dev)) 455 ret = mei_me_pg_enter_sync(dev); 456 else 457 ret = -EAGAIN; 458 459 mutex_unlock(&dev->device_lock); 460 461 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 462 463 if (ret && ret != -EAGAIN) 464 schedule_work(&dev->reset_work); 465 466 return ret; 467 } 468 469 static int mei_me_pm_runtime_resume(struct device *device) 470 { 471 struct mei_device *dev; 472 int ret; 473 474 dev_dbg(device, "rpm: me: runtime resume\n"); 475 476 dev = dev_get_drvdata(device); 477 if (!dev) 478 return -ENODEV; 479 480 mutex_lock(&dev->device_lock); 481 482 ret = mei_me_pg_exit_sync(dev); 483 484 mutex_unlock(&dev->device_lock); 485 486 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 487 488 if (ret) 489 schedule_work(&dev->reset_work); 490 491 return ret; 492 } 493 494 /** 495 * mei_me_set_pm_domain - fill and set pm domain structure for device 496 * 497 * @dev: mei_device 498 */ 499 static inline void mei_me_set_pm_domain(struct mei_device *dev) 500 { 501 struct pci_dev *pdev = to_pci_dev(dev->dev); 502 503 if (pdev->dev.bus && pdev->dev.bus->pm) { 504 dev->pg_domain.ops = *pdev->dev.bus->pm; 505 506 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 507 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 508 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 509 510 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 511 } 512 } 513 514 /** 515 * mei_me_unset_pm_domain - clean pm domain structure for device 516 * 517 * @dev: mei_device 518 */ 519 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 520 { 521 /* stop using pm callbacks if any */ 522 dev_pm_domain_set(dev->dev, NULL); 523 } 524 525 static const struct dev_pm_ops mei_me_pm_ops = { 526 .prepare = mei_me_pci_prepare, 527 .complete = mei_me_pci_complete, 528 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 529 mei_me_pci_resume) 530 SET_RUNTIME_PM_OPS( 531 mei_me_pm_runtime_suspend, 532 mei_me_pm_runtime_resume, 533 mei_me_pm_runtime_idle) 534 }; 535 536 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 537 #else 538 #define MEI_ME_PM_OPS NULL 539 #endif /* CONFIG_PM */ 540 /* 541 * PCI driver structure 542 */ 543 static struct pci_driver mei_me_driver = { 544 .name = KBUILD_MODNAME, 545 .id_table = mei_me_pci_tbl, 546 .probe = mei_me_probe, 547 .remove = mei_me_remove, 548 .shutdown = mei_me_shutdown, 549 .driver.pm = MEI_ME_PM_OPS, 550 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 551 }; 552 553 module_pci_driver(mei_me_driver); 554 555 MODULE_AUTHOR("Intel Corporation"); 556 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 557 MODULE_LICENSE("GPL v2"); 558