1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2019, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/moduleparam.h> 9 #include <linux/kernel.h> 10 #include <linux/device.h> 11 #include <linux/fs.h> 12 #include <linux/errno.h> 13 #include <linux/types.h> 14 #include <linux/fcntl.h> 15 #include <linux/pci.h> 16 #include <linux/poll.h> 17 #include <linux/ioctl.h> 18 #include <linux/cdev.h> 19 #include <linux/sched.h> 20 #include <linux/uuid.h> 21 #include <linux/compat.h> 22 #include <linux/jiffies.h> 23 #include <linux/interrupt.h> 24 25 #include <linux/pm_domain.h> 26 #include <linux/pm_runtime.h> 27 28 #include <linux/mei.h> 29 30 #include "mei_dev.h" 31 #include "client.h" 32 #include "hw-me-regs.h" 33 #include "hw-me.h" 34 35 /* mei_pci_tbl - PCI Device ID Table */ 36 static const struct pci_device_id mei_me_pci_tbl[] = { 37 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 39 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 40 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 48 49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 58 59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 63 64 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 68 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 69 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 77 78 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 79 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 80 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, 81 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, 82 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)}, 83 84 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 86 87 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 88 89 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 90 91 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 92 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 93 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)}, 97 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)}, 98 99 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 100 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, 101 102 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 103 104 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH12_CFG)}, 105 106 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)}, 107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 108 109 /* required last entry */ 110 {0, } 111 }; 112 113 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 114 115 #ifdef CONFIG_PM 116 static inline void mei_me_set_pm_domain(struct mei_device *dev); 117 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 118 #else 119 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 120 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 121 #endif /* CONFIG_PM */ 122 123 /** 124 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 125 * 126 * @pdev: PCI device structure 127 * @cfg: per generation config 128 * 129 * Return: true if ME Interface is valid, false otherwise 130 */ 131 static bool mei_me_quirk_probe(struct pci_dev *pdev, 132 const struct mei_cfg *cfg) 133 { 134 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 135 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 136 return false; 137 } 138 139 return true; 140 } 141 142 /** 143 * mei_me_probe - Device Initialization Routine 144 * 145 * @pdev: PCI device structure 146 * @ent: entry in kcs_pci_tbl 147 * 148 * Return: 0 on success, <0 on failure. 149 */ 150 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 151 { 152 const struct mei_cfg *cfg; 153 struct mei_device *dev; 154 struct mei_me_hw *hw; 155 unsigned int irqflags; 156 int err; 157 158 cfg = mei_me_get_cfg(ent->driver_data); 159 if (!cfg) 160 return -ENODEV; 161 162 if (!mei_me_quirk_probe(pdev, cfg)) 163 return -ENODEV; 164 165 /* enable pci dev */ 166 err = pcim_enable_device(pdev); 167 if (err) { 168 dev_err(&pdev->dev, "failed to enable pci device.\n"); 169 goto end; 170 } 171 /* set PCI host mastering */ 172 pci_set_master(pdev); 173 /* pci request regions and mapping IO device memory for mei driver */ 174 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 175 if (err) { 176 dev_err(&pdev->dev, "failed to get pci regions.\n"); 177 goto end; 178 } 179 180 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 181 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 182 183 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 184 if (err) 185 err = dma_set_coherent_mask(&pdev->dev, 186 DMA_BIT_MASK(32)); 187 } 188 if (err) { 189 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 190 goto end; 191 } 192 193 /* allocates and initializes the mei dev structure */ 194 dev = mei_me_dev_init(pdev, cfg); 195 if (!dev) { 196 err = -ENOMEM; 197 goto end; 198 } 199 hw = to_me_hw(dev); 200 hw->mem_addr = pcim_iomap_table(pdev)[0]; 201 202 pci_enable_msi(pdev); 203 204 /* request and enable interrupt */ 205 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 206 207 err = request_threaded_irq(pdev->irq, 208 mei_me_irq_quick_handler, 209 mei_me_irq_thread_handler, 210 irqflags, KBUILD_MODNAME, dev); 211 if (err) { 212 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 213 pdev->irq); 214 goto end; 215 } 216 217 if (mei_start(dev)) { 218 dev_err(&pdev->dev, "init hw failure.\n"); 219 err = -ENODEV; 220 goto release_irq; 221 } 222 223 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 224 pm_runtime_use_autosuspend(&pdev->dev); 225 226 err = mei_register(dev, &pdev->dev); 227 if (err) 228 goto stop; 229 230 pci_set_drvdata(pdev, dev); 231 232 /* 233 * MEI requires to resume from runtime suspend mode 234 * in order to perform link reset flow upon system suspend. 235 */ 236 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 237 238 /* 239 * ME maps runtime suspend/resume to D0i states, 240 * hence we need to go around native PCI runtime service which 241 * eventually brings the device into D3cold/hot state, 242 * but the mei device cannot wake up from D3 unlike from D0i3. 243 * To get around the PCI device native runtime pm, 244 * ME uses runtime pm domain handlers which take precedence 245 * over the driver's pm handlers. 246 */ 247 mei_me_set_pm_domain(dev); 248 249 if (mei_pg_is_enabled(dev)) { 250 pm_runtime_put_noidle(&pdev->dev); 251 if (hw->d0i3_supported) 252 pm_runtime_allow(&pdev->dev); 253 } 254 255 dev_dbg(&pdev->dev, "initialization successful.\n"); 256 257 return 0; 258 259 stop: 260 mei_stop(dev); 261 release_irq: 262 mei_cancel_work(dev); 263 mei_disable_interrupts(dev); 264 free_irq(pdev->irq, dev); 265 end: 266 dev_err(&pdev->dev, "initialization failed.\n"); 267 return err; 268 } 269 270 /** 271 * mei_me_shutdown - Device Removal Routine 272 * 273 * @pdev: PCI device structure 274 * 275 * mei_me_shutdown is called from the reboot notifier 276 * it's a simplified version of remove so we go down 277 * faster. 278 */ 279 static void mei_me_shutdown(struct pci_dev *pdev) 280 { 281 struct mei_device *dev; 282 283 dev = pci_get_drvdata(pdev); 284 if (!dev) 285 return; 286 287 dev_dbg(&pdev->dev, "shutdown\n"); 288 mei_stop(dev); 289 290 mei_me_unset_pm_domain(dev); 291 292 mei_disable_interrupts(dev); 293 free_irq(pdev->irq, dev); 294 } 295 296 /** 297 * mei_me_remove - Device Removal Routine 298 * 299 * @pdev: PCI device structure 300 * 301 * mei_me_remove is called by the PCI subsystem to alert the driver 302 * that it should release a PCI device. 303 */ 304 static void mei_me_remove(struct pci_dev *pdev) 305 { 306 struct mei_device *dev; 307 308 dev = pci_get_drvdata(pdev); 309 if (!dev) 310 return; 311 312 if (mei_pg_is_enabled(dev)) 313 pm_runtime_get_noresume(&pdev->dev); 314 315 dev_dbg(&pdev->dev, "stop\n"); 316 mei_stop(dev); 317 318 mei_me_unset_pm_domain(dev); 319 320 mei_disable_interrupts(dev); 321 322 free_irq(pdev->irq, dev); 323 324 mei_deregister(dev); 325 } 326 327 #ifdef CONFIG_PM_SLEEP 328 static int mei_me_pci_suspend(struct device *device) 329 { 330 struct pci_dev *pdev = to_pci_dev(device); 331 struct mei_device *dev = pci_get_drvdata(pdev); 332 333 if (!dev) 334 return -ENODEV; 335 336 dev_dbg(&pdev->dev, "suspend\n"); 337 338 mei_stop(dev); 339 340 mei_disable_interrupts(dev); 341 342 free_irq(pdev->irq, dev); 343 pci_disable_msi(pdev); 344 345 return 0; 346 } 347 348 static int mei_me_pci_resume(struct device *device) 349 { 350 struct pci_dev *pdev = to_pci_dev(device); 351 struct mei_device *dev; 352 unsigned int irqflags; 353 int err; 354 355 dev = pci_get_drvdata(pdev); 356 if (!dev) 357 return -ENODEV; 358 359 pci_enable_msi(pdev); 360 361 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 362 363 /* request and enable interrupt */ 364 err = request_threaded_irq(pdev->irq, 365 mei_me_irq_quick_handler, 366 mei_me_irq_thread_handler, 367 irqflags, KBUILD_MODNAME, dev); 368 369 if (err) { 370 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 371 pdev->irq); 372 return err; 373 } 374 375 err = mei_restart(dev); 376 if (err) 377 return err; 378 379 /* Start timer if stopped in suspend */ 380 schedule_delayed_work(&dev->timer_work, HZ); 381 382 return 0; 383 } 384 #endif /* CONFIG_PM_SLEEP */ 385 386 #ifdef CONFIG_PM 387 static int mei_me_pm_runtime_idle(struct device *device) 388 { 389 struct mei_device *dev; 390 391 dev_dbg(device, "rpm: me: runtime_idle\n"); 392 393 dev = dev_get_drvdata(device); 394 if (!dev) 395 return -ENODEV; 396 if (mei_write_is_idle(dev)) 397 pm_runtime_autosuspend(device); 398 399 return -EBUSY; 400 } 401 402 static int mei_me_pm_runtime_suspend(struct device *device) 403 { 404 struct mei_device *dev; 405 int ret; 406 407 dev_dbg(device, "rpm: me: runtime suspend\n"); 408 409 dev = dev_get_drvdata(device); 410 if (!dev) 411 return -ENODEV; 412 413 mutex_lock(&dev->device_lock); 414 415 if (mei_write_is_idle(dev)) 416 ret = mei_me_pg_enter_sync(dev); 417 else 418 ret = -EAGAIN; 419 420 mutex_unlock(&dev->device_lock); 421 422 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 423 424 if (ret && ret != -EAGAIN) 425 schedule_work(&dev->reset_work); 426 427 return ret; 428 } 429 430 static int mei_me_pm_runtime_resume(struct device *device) 431 { 432 struct mei_device *dev; 433 int ret; 434 435 dev_dbg(device, "rpm: me: runtime resume\n"); 436 437 dev = dev_get_drvdata(device); 438 if (!dev) 439 return -ENODEV; 440 441 mutex_lock(&dev->device_lock); 442 443 ret = mei_me_pg_exit_sync(dev); 444 445 mutex_unlock(&dev->device_lock); 446 447 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 448 449 if (ret) 450 schedule_work(&dev->reset_work); 451 452 return ret; 453 } 454 455 /** 456 * mei_me_set_pm_domain - fill and set pm domain structure for device 457 * 458 * @dev: mei_device 459 */ 460 static inline void mei_me_set_pm_domain(struct mei_device *dev) 461 { 462 struct pci_dev *pdev = to_pci_dev(dev->dev); 463 464 if (pdev->dev.bus && pdev->dev.bus->pm) { 465 dev->pg_domain.ops = *pdev->dev.bus->pm; 466 467 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 468 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 469 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 470 471 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 472 } 473 } 474 475 /** 476 * mei_me_unset_pm_domain - clean pm domain structure for device 477 * 478 * @dev: mei_device 479 */ 480 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 481 { 482 /* stop using pm callbacks if any */ 483 dev_pm_domain_set(dev->dev, NULL); 484 } 485 486 static const struct dev_pm_ops mei_me_pm_ops = { 487 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 488 mei_me_pci_resume) 489 SET_RUNTIME_PM_OPS( 490 mei_me_pm_runtime_suspend, 491 mei_me_pm_runtime_resume, 492 mei_me_pm_runtime_idle) 493 }; 494 495 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 496 #else 497 #define MEI_ME_PM_OPS NULL 498 #endif /* CONFIG_PM */ 499 /* 500 * PCI driver structure 501 */ 502 static struct pci_driver mei_me_driver = { 503 .name = KBUILD_MODNAME, 504 .id_table = mei_me_pci_tbl, 505 .probe = mei_me_probe, 506 .remove = mei_me_remove, 507 .shutdown = mei_me_shutdown, 508 .driver.pm = MEI_ME_PM_OPS, 509 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 510 }; 511 512 module_pci_driver(mei_me_driver); 513 514 MODULE_AUTHOR("Intel Corporation"); 515 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 516 MODULE_LICENSE("GPL v2"); 517