1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/sched.h> 14 #include <linux/interrupt.h> 15 16 #include <linux/pm_domain.h> 17 #include <linux/pm_runtime.h> 18 19 #include <linux/mei.h> 20 21 #include "mei_dev.h" 22 #include "client.h" 23 #include "hw-me-regs.h" 24 #include "hw-me.h" 25 26 /* mei_pci_tbl - PCI Device ID Table */ 27 static const struct pci_device_id mei_me_pci_tbl[] = { 28 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 29 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 30 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 31 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 32 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 34 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 39 40 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 49 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 54 55 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 58 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 68 69 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)}, 74 75 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 77 78 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 79 80 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 81 82 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 83 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 84 85 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 86 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_CFG)}, 87 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)}, 88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH8_CFG)}, 89 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 91 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, 92 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)}, 95 96 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 97 98 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 99 100 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 101 102 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 103 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 104 105 /* required last entry */ 106 {0, } 107 }; 108 109 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 110 111 #ifdef CONFIG_PM 112 static inline void mei_me_set_pm_domain(struct mei_device *dev); 113 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 114 #else 115 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 116 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 117 #endif /* CONFIG_PM */ 118 119 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 120 { 121 struct pci_dev *pdev = to_pci_dev(dev->dev); 122 123 return pci_read_config_dword(pdev, where, val); 124 } 125 126 /** 127 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 128 * 129 * @pdev: PCI device structure 130 * @cfg: per generation config 131 * 132 * Return: true if ME Interface is valid, false otherwise 133 */ 134 static bool mei_me_quirk_probe(struct pci_dev *pdev, 135 const struct mei_cfg *cfg) 136 { 137 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 138 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 139 return false; 140 } 141 142 return true; 143 } 144 145 /** 146 * mei_me_probe - Device Initialization Routine 147 * 148 * @pdev: PCI device structure 149 * @ent: entry in kcs_pci_tbl 150 * 151 * Return: 0 on success, <0 on failure. 152 */ 153 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 154 { 155 const struct mei_cfg *cfg; 156 struct mei_device *dev; 157 struct mei_me_hw *hw; 158 unsigned int irqflags; 159 int err; 160 161 cfg = mei_me_get_cfg(ent->driver_data); 162 if (!cfg) 163 return -ENODEV; 164 165 if (!mei_me_quirk_probe(pdev, cfg)) 166 return -ENODEV; 167 168 /* enable pci dev */ 169 err = pcim_enable_device(pdev); 170 if (err) { 171 dev_err(&pdev->dev, "failed to enable pci device.\n"); 172 goto end; 173 } 174 /* set PCI host mastering */ 175 pci_set_master(pdev); 176 /* pci request regions and mapping IO device memory for mei driver */ 177 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 178 if (err) { 179 dev_err(&pdev->dev, "failed to get pci regions.\n"); 180 goto end; 181 } 182 183 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 184 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 185 186 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 187 if (err) 188 err = dma_set_coherent_mask(&pdev->dev, 189 DMA_BIT_MASK(32)); 190 } 191 if (err) { 192 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 193 goto end; 194 } 195 196 /* allocates and initializes the mei dev structure */ 197 dev = mei_me_dev_init(&pdev->dev, cfg); 198 if (!dev) { 199 err = -ENOMEM; 200 goto end; 201 } 202 hw = to_me_hw(dev); 203 hw->mem_addr = pcim_iomap_table(pdev)[0]; 204 hw->irq = pdev->irq; 205 hw->read_fws = mei_me_read_fws; 206 207 pci_enable_msi(pdev); 208 209 /* request and enable interrupt */ 210 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 211 212 err = request_threaded_irq(pdev->irq, 213 mei_me_irq_quick_handler, 214 mei_me_irq_thread_handler, 215 irqflags, KBUILD_MODNAME, dev); 216 if (err) { 217 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 218 pdev->irq); 219 goto end; 220 } 221 222 if (mei_start(dev)) { 223 dev_err(&pdev->dev, "init hw failure.\n"); 224 err = -ENODEV; 225 goto release_irq; 226 } 227 228 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 229 pm_runtime_use_autosuspend(&pdev->dev); 230 231 err = mei_register(dev, &pdev->dev); 232 if (err) 233 goto stop; 234 235 pci_set_drvdata(pdev, dev); 236 237 /* 238 * MEI requires to resume from runtime suspend mode 239 * in order to perform link reset flow upon system suspend. 240 */ 241 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 242 243 /* 244 * ME maps runtime suspend/resume to D0i states, 245 * hence we need to go around native PCI runtime service which 246 * eventually brings the device into D3cold/hot state, 247 * but the mei device cannot wake up from D3 unlike from D0i3. 248 * To get around the PCI device native runtime pm, 249 * ME uses runtime pm domain handlers which take precedence 250 * over the driver's pm handlers. 251 */ 252 mei_me_set_pm_domain(dev); 253 254 if (mei_pg_is_enabled(dev)) { 255 pm_runtime_put_noidle(&pdev->dev); 256 if (hw->d0i3_supported) 257 pm_runtime_allow(&pdev->dev); 258 } 259 260 dev_dbg(&pdev->dev, "initialization successful.\n"); 261 262 return 0; 263 264 stop: 265 mei_stop(dev); 266 release_irq: 267 mei_cancel_work(dev); 268 mei_disable_interrupts(dev); 269 free_irq(pdev->irq, dev); 270 end: 271 dev_err(&pdev->dev, "initialization failed.\n"); 272 return err; 273 } 274 275 /** 276 * mei_me_shutdown - Device Removal Routine 277 * 278 * @pdev: PCI device structure 279 * 280 * mei_me_shutdown is called from the reboot notifier 281 * it's a simplified version of remove so we go down 282 * faster. 283 */ 284 static void mei_me_shutdown(struct pci_dev *pdev) 285 { 286 struct mei_device *dev; 287 288 dev = pci_get_drvdata(pdev); 289 if (!dev) 290 return; 291 292 dev_dbg(&pdev->dev, "shutdown\n"); 293 mei_stop(dev); 294 295 mei_me_unset_pm_domain(dev); 296 297 mei_disable_interrupts(dev); 298 free_irq(pdev->irq, dev); 299 } 300 301 /** 302 * mei_me_remove - Device Removal Routine 303 * 304 * @pdev: PCI device structure 305 * 306 * mei_me_remove is called by the PCI subsystem to alert the driver 307 * that it should release a PCI device. 308 */ 309 static void mei_me_remove(struct pci_dev *pdev) 310 { 311 struct mei_device *dev; 312 313 dev = pci_get_drvdata(pdev); 314 if (!dev) 315 return; 316 317 if (mei_pg_is_enabled(dev)) 318 pm_runtime_get_noresume(&pdev->dev); 319 320 dev_dbg(&pdev->dev, "stop\n"); 321 mei_stop(dev); 322 323 mei_me_unset_pm_domain(dev); 324 325 mei_disable_interrupts(dev); 326 327 free_irq(pdev->irq, dev); 328 329 mei_deregister(dev); 330 } 331 332 #ifdef CONFIG_PM_SLEEP 333 static int mei_me_pci_suspend(struct device *device) 334 { 335 struct pci_dev *pdev = to_pci_dev(device); 336 struct mei_device *dev = pci_get_drvdata(pdev); 337 338 if (!dev) 339 return -ENODEV; 340 341 dev_dbg(&pdev->dev, "suspend\n"); 342 343 mei_stop(dev); 344 345 mei_disable_interrupts(dev); 346 347 free_irq(pdev->irq, dev); 348 pci_disable_msi(pdev); 349 350 return 0; 351 } 352 353 static int mei_me_pci_resume(struct device *device) 354 { 355 struct pci_dev *pdev = to_pci_dev(device); 356 struct mei_device *dev; 357 unsigned int irqflags; 358 int err; 359 360 dev = pci_get_drvdata(pdev); 361 if (!dev) 362 return -ENODEV; 363 364 pci_enable_msi(pdev); 365 366 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 367 368 /* request and enable interrupt */ 369 err = request_threaded_irq(pdev->irq, 370 mei_me_irq_quick_handler, 371 mei_me_irq_thread_handler, 372 irqflags, KBUILD_MODNAME, dev); 373 374 if (err) { 375 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 376 pdev->irq); 377 return err; 378 } 379 380 err = mei_restart(dev); 381 if (err) 382 return err; 383 384 /* Start timer if stopped in suspend */ 385 schedule_delayed_work(&dev->timer_work, HZ); 386 387 return 0; 388 } 389 #endif /* CONFIG_PM_SLEEP */ 390 391 #ifdef CONFIG_PM 392 static int mei_me_pm_runtime_idle(struct device *device) 393 { 394 struct mei_device *dev; 395 396 dev_dbg(device, "rpm: me: runtime_idle\n"); 397 398 dev = dev_get_drvdata(device); 399 if (!dev) 400 return -ENODEV; 401 if (mei_write_is_idle(dev)) 402 pm_runtime_autosuspend(device); 403 404 return -EBUSY; 405 } 406 407 static int mei_me_pm_runtime_suspend(struct device *device) 408 { 409 struct mei_device *dev; 410 int ret; 411 412 dev_dbg(device, "rpm: me: runtime suspend\n"); 413 414 dev = dev_get_drvdata(device); 415 if (!dev) 416 return -ENODEV; 417 418 mutex_lock(&dev->device_lock); 419 420 if (mei_write_is_idle(dev)) 421 ret = mei_me_pg_enter_sync(dev); 422 else 423 ret = -EAGAIN; 424 425 mutex_unlock(&dev->device_lock); 426 427 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 428 429 if (ret && ret != -EAGAIN) 430 schedule_work(&dev->reset_work); 431 432 return ret; 433 } 434 435 static int mei_me_pm_runtime_resume(struct device *device) 436 { 437 struct mei_device *dev; 438 int ret; 439 440 dev_dbg(device, "rpm: me: runtime resume\n"); 441 442 dev = dev_get_drvdata(device); 443 if (!dev) 444 return -ENODEV; 445 446 mutex_lock(&dev->device_lock); 447 448 ret = mei_me_pg_exit_sync(dev); 449 450 mutex_unlock(&dev->device_lock); 451 452 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 453 454 if (ret) 455 schedule_work(&dev->reset_work); 456 457 return ret; 458 } 459 460 /** 461 * mei_me_set_pm_domain - fill and set pm domain structure for device 462 * 463 * @dev: mei_device 464 */ 465 static inline void mei_me_set_pm_domain(struct mei_device *dev) 466 { 467 struct pci_dev *pdev = to_pci_dev(dev->dev); 468 469 if (pdev->dev.bus && pdev->dev.bus->pm) { 470 dev->pg_domain.ops = *pdev->dev.bus->pm; 471 472 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 473 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 474 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 475 476 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 477 } 478 } 479 480 /** 481 * mei_me_unset_pm_domain - clean pm domain structure for device 482 * 483 * @dev: mei_device 484 */ 485 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 486 { 487 /* stop using pm callbacks if any */ 488 dev_pm_domain_set(dev->dev, NULL); 489 } 490 491 static const struct dev_pm_ops mei_me_pm_ops = { 492 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 493 mei_me_pci_resume) 494 SET_RUNTIME_PM_OPS( 495 mei_me_pm_runtime_suspend, 496 mei_me_pm_runtime_resume, 497 mei_me_pm_runtime_idle) 498 }; 499 500 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 501 #else 502 #define MEI_ME_PM_OPS NULL 503 #endif /* CONFIG_PM */ 504 /* 505 * PCI driver structure 506 */ 507 static struct pci_driver mei_me_driver = { 508 .name = KBUILD_MODNAME, 509 .id_table = mei_me_pci_tbl, 510 .probe = mei_me_probe, 511 .remove = mei_me_remove, 512 .shutdown = mei_me_shutdown, 513 .driver.pm = MEI_ME_PM_OPS, 514 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 515 }; 516 517 module_pci_driver(mei_me_driver); 518 519 MODULE_AUTHOR("Intel Corporation"); 520 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 521 MODULE_LICENSE("GPL v2"); 522