1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2019, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/moduleparam.h> 9 #include <linux/kernel.h> 10 #include <linux/device.h> 11 #include <linux/fs.h> 12 #include <linux/errno.h> 13 #include <linux/types.h> 14 #include <linux/fcntl.h> 15 #include <linux/pci.h> 16 #include <linux/poll.h> 17 #include <linux/ioctl.h> 18 #include <linux/cdev.h> 19 #include <linux/sched.h> 20 #include <linux/uuid.h> 21 #include <linux/compat.h> 22 #include <linux/jiffies.h> 23 #include <linux/interrupt.h> 24 25 #include <linux/pm_domain.h> 26 #include <linux/pm_runtime.h> 27 28 #include <linux/mei.h> 29 30 #include "mei_dev.h" 31 #include "client.h" 32 #include "hw-me-regs.h" 33 #include "hw-me.h" 34 35 /* mei_pci_tbl - PCI Device ID Table */ 36 static const struct pci_device_id mei_me_pci_tbl[] = { 37 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 39 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 40 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 48 49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 58 59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 63 64 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 68 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 69 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 77 78 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 79 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 80 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, 81 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, 82 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)}, 83 84 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 86 87 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 88 89 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 90 91 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 92 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 93 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)}, 97 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)}, 98 99 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 100 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, 101 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 102 103 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 104 105 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 106 107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 109 110 /* required last entry */ 111 {0, } 112 }; 113 114 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 115 116 #ifdef CONFIG_PM 117 static inline void mei_me_set_pm_domain(struct mei_device *dev); 118 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 119 #else 120 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 121 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 122 #endif /* CONFIG_PM */ 123 124 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 125 { 126 struct pci_dev *pdev = to_pci_dev(dev->dev); 127 128 return pci_read_config_dword(pdev, where, val); 129 } 130 131 /** 132 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 133 * 134 * @pdev: PCI device structure 135 * @cfg: per generation config 136 * 137 * Return: true if ME Interface is valid, false otherwise 138 */ 139 static bool mei_me_quirk_probe(struct pci_dev *pdev, 140 const struct mei_cfg *cfg) 141 { 142 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 143 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 144 return false; 145 } 146 147 return true; 148 } 149 150 /** 151 * mei_me_probe - Device Initialization Routine 152 * 153 * @pdev: PCI device structure 154 * @ent: entry in kcs_pci_tbl 155 * 156 * Return: 0 on success, <0 on failure. 157 */ 158 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 159 { 160 const struct mei_cfg *cfg; 161 struct mei_device *dev; 162 struct mei_me_hw *hw; 163 unsigned int irqflags; 164 int err; 165 166 cfg = mei_me_get_cfg(ent->driver_data); 167 if (!cfg) 168 return -ENODEV; 169 170 if (!mei_me_quirk_probe(pdev, cfg)) 171 return -ENODEV; 172 173 /* enable pci dev */ 174 err = pcim_enable_device(pdev); 175 if (err) { 176 dev_err(&pdev->dev, "failed to enable pci device.\n"); 177 goto end; 178 } 179 /* set PCI host mastering */ 180 pci_set_master(pdev); 181 /* pci request regions and mapping IO device memory for mei driver */ 182 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 183 if (err) { 184 dev_err(&pdev->dev, "failed to get pci regions.\n"); 185 goto end; 186 } 187 188 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 189 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 190 191 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 192 if (err) 193 err = dma_set_coherent_mask(&pdev->dev, 194 DMA_BIT_MASK(32)); 195 } 196 if (err) { 197 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 198 goto end; 199 } 200 201 /* allocates and initializes the mei dev structure */ 202 dev = mei_me_dev_init(&pdev->dev, cfg); 203 if (!dev) { 204 err = -ENOMEM; 205 goto end; 206 } 207 hw = to_me_hw(dev); 208 hw->mem_addr = pcim_iomap_table(pdev)[0]; 209 hw->irq = pdev->irq; 210 hw->read_fws = mei_me_read_fws; 211 212 pci_enable_msi(pdev); 213 214 /* request and enable interrupt */ 215 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 216 217 err = request_threaded_irq(pdev->irq, 218 mei_me_irq_quick_handler, 219 mei_me_irq_thread_handler, 220 irqflags, KBUILD_MODNAME, dev); 221 if (err) { 222 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 223 pdev->irq); 224 goto end; 225 } 226 227 if (mei_start(dev)) { 228 dev_err(&pdev->dev, "init hw failure.\n"); 229 err = -ENODEV; 230 goto release_irq; 231 } 232 233 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 234 pm_runtime_use_autosuspend(&pdev->dev); 235 236 err = mei_register(dev, &pdev->dev); 237 if (err) 238 goto stop; 239 240 pci_set_drvdata(pdev, dev); 241 242 /* 243 * MEI requires to resume from runtime suspend mode 244 * in order to perform link reset flow upon system suspend. 245 */ 246 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 247 248 /* 249 * ME maps runtime suspend/resume to D0i states, 250 * hence we need to go around native PCI runtime service which 251 * eventually brings the device into D3cold/hot state, 252 * but the mei device cannot wake up from D3 unlike from D0i3. 253 * To get around the PCI device native runtime pm, 254 * ME uses runtime pm domain handlers which take precedence 255 * over the driver's pm handlers. 256 */ 257 mei_me_set_pm_domain(dev); 258 259 if (mei_pg_is_enabled(dev)) { 260 pm_runtime_put_noidle(&pdev->dev); 261 if (hw->d0i3_supported) 262 pm_runtime_allow(&pdev->dev); 263 } 264 265 dev_dbg(&pdev->dev, "initialization successful.\n"); 266 267 return 0; 268 269 stop: 270 mei_stop(dev); 271 release_irq: 272 mei_cancel_work(dev); 273 mei_disable_interrupts(dev); 274 free_irq(pdev->irq, dev); 275 end: 276 dev_err(&pdev->dev, "initialization failed.\n"); 277 return err; 278 } 279 280 /** 281 * mei_me_shutdown - Device Removal Routine 282 * 283 * @pdev: PCI device structure 284 * 285 * mei_me_shutdown is called from the reboot notifier 286 * it's a simplified version of remove so we go down 287 * faster. 288 */ 289 static void mei_me_shutdown(struct pci_dev *pdev) 290 { 291 struct mei_device *dev; 292 293 dev = pci_get_drvdata(pdev); 294 if (!dev) 295 return; 296 297 dev_dbg(&pdev->dev, "shutdown\n"); 298 mei_stop(dev); 299 300 mei_me_unset_pm_domain(dev); 301 302 mei_disable_interrupts(dev); 303 free_irq(pdev->irq, dev); 304 } 305 306 /** 307 * mei_me_remove - Device Removal Routine 308 * 309 * @pdev: PCI device structure 310 * 311 * mei_me_remove is called by the PCI subsystem to alert the driver 312 * that it should release a PCI device. 313 */ 314 static void mei_me_remove(struct pci_dev *pdev) 315 { 316 struct mei_device *dev; 317 318 dev = pci_get_drvdata(pdev); 319 if (!dev) 320 return; 321 322 if (mei_pg_is_enabled(dev)) 323 pm_runtime_get_noresume(&pdev->dev); 324 325 dev_dbg(&pdev->dev, "stop\n"); 326 mei_stop(dev); 327 328 mei_me_unset_pm_domain(dev); 329 330 mei_disable_interrupts(dev); 331 332 free_irq(pdev->irq, dev); 333 334 mei_deregister(dev); 335 } 336 337 #ifdef CONFIG_PM_SLEEP 338 static int mei_me_pci_suspend(struct device *device) 339 { 340 struct pci_dev *pdev = to_pci_dev(device); 341 struct mei_device *dev = pci_get_drvdata(pdev); 342 343 if (!dev) 344 return -ENODEV; 345 346 dev_dbg(&pdev->dev, "suspend\n"); 347 348 mei_stop(dev); 349 350 mei_disable_interrupts(dev); 351 352 free_irq(pdev->irq, dev); 353 pci_disable_msi(pdev); 354 355 return 0; 356 } 357 358 static int mei_me_pci_resume(struct device *device) 359 { 360 struct pci_dev *pdev = to_pci_dev(device); 361 struct mei_device *dev; 362 unsigned int irqflags; 363 int err; 364 365 dev = pci_get_drvdata(pdev); 366 if (!dev) 367 return -ENODEV; 368 369 pci_enable_msi(pdev); 370 371 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 372 373 /* request and enable interrupt */ 374 err = request_threaded_irq(pdev->irq, 375 mei_me_irq_quick_handler, 376 mei_me_irq_thread_handler, 377 irqflags, KBUILD_MODNAME, dev); 378 379 if (err) { 380 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 381 pdev->irq); 382 return err; 383 } 384 385 err = mei_restart(dev); 386 if (err) 387 return err; 388 389 /* Start timer if stopped in suspend */ 390 schedule_delayed_work(&dev->timer_work, HZ); 391 392 return 0; 393 } 394 #endif /* CONFIG_PM_SLEEP */ 395 396 #ifdef CONFIG_PM 397 static int mei_me_pm_runtime_idle(struct device *device) 398 { 399 struct mei_device *dev; 400 401 dev_dbg(device, "rpm: me: runtime_idle\n"); 402 403 dev = dev_get_drvdata(device); 404 if (!dev) 405 return -ENODEV; 406 if (mei_write_is_idle(dev)) 407 pm_runtime_autosuspend(device); 408 409 return -EBUSY; 410 } 411 412 static int mei_me_pm_runtime_suspend(struct device *device) 413 { 414 struct mei_device *dev; 415 int ret; 416 417 dev_dbg(device, "rpm: me: runtime suspend\n"); 418 419 dev = dev_get_drvdata(device); 420 if (!dev) 421 return -ENODEV; 422 423 mutex_lock(&dev->device_lock); 424 425 if (mei_write_is_idle(dev)) 426 ret = mei_me_pg_enter_sync(dev); 427 else 428 ret = -EAGAIN; 429 430 mutex_unlock(&dev->device_lock); 431 432 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 433 434 if (ret && ret != -EAGAIN) 435 schedule_work(&dev->reset_work); 436 437 return ret; 438 } 439 440 static int mei_me_pm_runtime_resume(struct device *device) 441 { 442 struct mei_device *dev; 443 int ret; 444 445 dev_dbg(device, "rpm: me: runtime resume\n"); 446 447 dev = dev_get_drvdata(device); 448 if (!dev) 449 return -ENODEV; 450 451 mutex_lock(&dev->device_lock); 452 453 ret = mei_me_pg_exit_sync(dev); 454 455 mutex_unlock(&dev->device_lock); 456 457 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 458 459 if (ret) 460 schedule_work(&dev->reset_work); 461 462 return ret; 463 } 464 465 /** 466 * mei_me_set_pm_domain - fill and set pm domain structure for device 467 * 468 * @dev: mei_device 469 */ 470 static inline void mei_me_set_pm_domain(struct mei_device *dev) 471 { 472 struct pci_dev *pdev = to_pci_dev(dev->dev); 473 474 if (pdev->dev.bus && pdev->dev.bus->pm) { 475 dev->pg_domain.ops = *pdev->dev.bus->pm; 476 477 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 478 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 479 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 480 481 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 482 } 483 } 484 485 /** 486 * mei_me_unset_pm_domain - clean pm domain structure for device 487 * 488 * @dev: mei_device 489 */ 490 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 491 { 492 /* stop using pm callbacks if any */ 493 dev_pm_domain_set(dev->dev, NULL); 494 } 495 496 static const struct dev_pm_ops mei_me_pm_ops = { 497 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 498 mei_me_pci_resume) 499 SET_RUNTIME_PM_OPS( 500 mei_me_pm_runtime_suspend, 501 mei_me_pm_runtime_resume, 502 mei_me_pm_runtime_idle) 503 }; 504 505 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 506 #else 507 #define MEI_ME_PM_OPS NULL 508 #endif /* CONFIG_PM */ 509 /* 510 * PCI driver structure 511 */ 512 static struct pci_driver mei_me_driver = { 513 .name = KBUILD_MODNAME, 514 .id_table = mei_me_pci_tbl, 515 .probe = mei_me_probe, 516 .remove = mei_me_remove, 517 .shutdown = mei_me_shutdown, 518 .driver.pm = MEI_ME_PM_OPS, 519 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 520 }; 521 522 module_pci_driver(mei_me_driver); 523 524 MODULE_AUTHOR("Intel Corporation"); 525 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 526 MODULE_LICENSE("GPL v2"); 527