xref: /openbmc/linux/drivers/misc/mei/pci-me.c (revision 7a010c3c)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
4  * Intel Management Engine Interface (Intel MEI) Linux driver
5  */
6 
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 
16 #include <linux/pm_domain.h>
17 #include <linux/pm_runtime.h>
18 
19 #include <linux/mei.h>
20 
21 #include "mei_dev.h"
22 #include "client.h"
23 #include "hw-me-regs.h"
24 #include "hw-me.h"
25 
26 /* mei_pci_tbl - PCI Device ID Table */
27 static const struct pci_device_id mei_me_pci_tbl[] = {
28 	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
29 	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
30 	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
31 	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
32 	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
33 	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
34 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
35 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
36 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
37 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
38 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
39 
40 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
41 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
42 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
43 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
44 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
45 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
46 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
47 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
48 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
49 
50 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
51 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
52 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
53 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
54 
55 	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
56 	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
57 	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
58 	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
59 	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
60 	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
61 	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
62 	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
63 	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
64 	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
65 	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
66 	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
67 	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
68 
69 	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
70 	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
71 	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
72 	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
73 	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
74 	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
75 
76 	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
77 	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
78 
79 	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
80 
81 	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
82 
83 	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
84 	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
85 	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
86 
87 	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
88 	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
89 	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
90 	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
91 
92 	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
93 	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
94 	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
95 	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
96 	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
97 
98 	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
99 
100 	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
101 	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
102 
103 	{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
104 
105 	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
106 	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
107 
108 	{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
109 
110 	{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
111 
112 	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
113 	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
114 	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
115 
116 	/* required last entry */
117 	{0, }
118 };
119 
120 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
121 
122 #ifdef CONFIG_PM
123 static inline void mei_me_set_pm_domain(struct mei_device *dev);
124 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
125 #else
126 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
127 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
128 #endif /* CONFIG_PM */
129 
130 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
131 {
132 	struct pci_dev *pdev = to_pci_dev(dev->dev);
133 
134 	return pci_read_config_dword(pdev, where, val);
135 }
136 
137 /**
138  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
139  *
140  * @pdev: PCI device structure
141  * @cfg: per generation config
142  *
143  * Return: true if ME Interface is valid, false otherwise
144  */
145 static bool mei_me_quirk_probe(struct pci_dev *pdev,
146 				const struct mei_cfg *cfg)
147 {
148 	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
149 		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
150 		return false;
151 	}
152 
153 	return true;
154 }
155 
156 /**
157  * mei_me_probe - Device Initialization Routine
158  *
159  * @pdev: PCI device structure
160  * @ent: entry in kcs_pci_tbl
161  *
162  * Return: 0 on success, <0 on failure.
163  */
164 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
165 {
166 	const struct mei_cfg *cfg;
167 	struct mei_device *dev;
168 	struct mei_me_hw *hw;
169 	unsigned int irqflags;
170 	int err;
171 
172 	cfg = mei_me_get_cfg(ent->driver_data);
173 	if (!cfg)
174 		return -ENODEV;
175 
176 	if (!mei_me_quirk_probe(pdev, cfg))
177 		return -ENODEV;
178 
179 	/* enable pci dev */
180 	err = pcim_enable_device(pdev);
181 	if (err) {
182 		dev_err(&pdev->dev, "failed to enable pci device.\n");
183 		goto end;
184 	}
185 	/* set PCI host mastering  */
186 	pci_set_master(pdev);
187 	/* pci request regions and mapping IO device memory for mei driver */
188 	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
189 	if (err) {
190 		dev_err(&pdev->dev, "failed to get pci regions.\n");
191 		goto end;
192 	}
193 
194 	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
195 	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
196 
197 		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
198 		if (err)
199 			err = dma_set_coherent_mask(&pdev->dev,
200 						    DMA_BIT_MASK(32));
201 	}
202 	if (err) {
203 		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
204 		goto end;
205 	}
206 
207 	/* allocates and initializes the mei dev structure */
208 	dev = mei_me_dev_init(&pdev->dev, cfg);
209 	if (!dev) {
210 		err = -ENOMEM;
211 		goto end;
212 	}
213 	hw = to_me_hw(dev);
214 	hw->mem_addr = pcim_iomap_table(pdev)[0];
215 	hw->read_fws = mei_me_read_fws;
216 
217 	pci_enable_msi(pdev);
218 
219 	hw->irq = pdev->irq;
220 
221 	 /* request and enable interrupt */
222 	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
223 
224 	err = request_threaded_irq(pdev->irq,
225 			mei_me_irq_quick_handler,
226 			mei_me_irq_thread_handler,
227 			irqflags, KBUILD_MODNAME, dev);
228 	if (err) {
229 		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
230 		       pdev->irq);
231 		goto end;
232 	}
233 
234 	if (mei_start(dev)) {
235 		dev_err(&pdev->dev, "init hw failure.\n");
236 		err = -ENODEV;
237 		goto release_irq;
238 	}
239 
240 	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
241 	pm_runtime_use_autosuspend(&pdev->dev);
242 
243 	err = mei_register(dev, &pdev->dev);
244 	if (err)
245 		goto stop;
246 
247 	pci_set_drvdata(pdev, dev);
248 
249 	/*
250 	 * MEI requires to resume from runtime suspend mode
251 	 * in order to perform link reset flow upon system suspend.
252 	 */
253 	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
254 
255 	/*
256 	 * ME maps runtime suspend/resume to D0i states,
257 	 * hence we need to go around native PCI runtime service which
258 	 * eventually brings the device into D3cold/hot state,
259 	 * but the mei device cannot wake up from D3 unlike from D0i3.
260 	 * To get around the PCI device native runtime pm,
261 	 * ME uses runtime pm domain handlers which take precedence
262 	 * over the driver's pm handlers.
263 	 */
264 	mei_me_set_pm_domain(dev);
265 
266 	if (mei_pg_is_enabled(dev)) {
267 		pm_runtime_put_noidle(&pdev->dev);
268 		if (hw->d0i3_supported)
269 			pm_runtime_allow(&pdev->dev);
270 	}
271 
272 	dev_dbg(&pdev->dev, "initialization successful.\n");
273 
274 	return 0;
275 
276 stop:
277 	mei_stop(dev);
278 release_irq:
279 	mei_cancel_work(dev);
280 	mei_disable_interrupts(dev);
281 	free_irq(pdev->irq, dev);
282 end:
283 	dev_err(&pdev->dev, "initialization failed.\n");
284 	return err;
285 }
286 
287 /**
288  * mei_me_shutdown - Device Removal Routine
289  *
290  * @pdev: PCI device structure
291  *
292  * mei_me_shutdown is called from the reboot notifier
293  * it's a simplified version of remove so we go down
294  * faster.
295  */
296 static void mei_me_shutdown(struct pci_dev *pdev)
297 {
298 	struct mei_device *dev;
299 
300 	dev = pci_get_drvdata(pdev);
301 	if (!dev)
302 		return;
303 
304 	dev_dbg(&pdev->dev, "shutdown\n");
305 	mei_stop(dev);
306 
307 	mei_me_unset_pm_domain(dev);
308 
309 	mei_disable_interrupts(dev);
310 	free_irq(pdev->irq, dev);
311 }
312 
313 /**
314  * mei_me_remove - Device Removal Routine
315  *
316  * @pdev: PCI device structure
317  *
318  * mei_me_remove is called by the PCI subsystem to alert the driver
319  * that it should release a PCI device.
320  */
321 static void mei_me_remove(struct pci_dev *pdev)
322 {
323 	struct mei_device *dev;
324 
325 	dev = pci_get_drvdata(pdev);
326 	if (!dev)
327 		return;
328 
329 	if (mei_pg_is_enabled(dev))
330 		pm_runtime_get_noresume(&pdev->dev);
331 
332 	dev_dbg(&pdev->dev, "stop\n");
333 	mei_stop(dev);
334 
335 	mei_me_unset_pm_domain(dev);
336 
337 	mei_disable_interrupts(dev);
338 
339 	free_irq(pdev->irq, dev);
340 
341 	mei_deregister(dev);
342 }
343 
344 #ifdef CONFIG_PM_SLEEP
345 static int mei_me_pci_suspend(struct device *device)
346 {
347 	struct pci_dev *pdev = to_pci_dev(device);
348 	struct mei_device *dev = pci_get_drvdata(pdev);
349 
350 	if (!dev)
351 		return -ENODEV;
352 
353 	dev_dbg(&pdev->dev, "suspend\n");
354 
355 	mei_stop(dev);
356 
357 	mei_disable_interrupts(dev);
358 
359 	free_irq(pdev->irq, dev);
360 	pci_disable_msi(pdev);
361 
362 	return 0;
363 }
364 
365 static int mei_me_pci_resume(struct device *device)
366 {
367 	struct pci_dev *pdev = to_pci_dev(device);
368 	struct mei_device *dev;
369 	unsigned int irqflags;
370 	int err;
371 
372 	dev = pci_get_drvdata(pdev);
373 	if (!dev)
374 		return -ENODEV;
375 
376 	pci_enable_msi(pdev);
377 
378 	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
379 
380 	/* request and enable interrupt */
381 	err = request_threaded_irq(pdev->irq,
382 			mei_me_irq_quick_handler,
383 			mei_me_irq_thread_handler,
384 			irqflags, KBUILD_MODNAME, dev);
385 
386 	if (err) {
387 		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
388 				pdev->irq);
389 		return err;
390 	}
391 
392 	err = mei_restart(dev);
393 	if (err)
394 		return err;
395 
396 	/* Start timer if stopped in suspend */
397 	schedule_delayed_work(&dev->timer_work, HZ);
398 
399 	return 0;
400 }
401 #endif /* CONFIG_PM_SLEEP */
402 
403 #ifdef CONFIG_PM
404 static int mei_me_pm_runtime_idle(struct device *device)
405 {
406 	struct mei_device *dev;
407 
408 	dev_dbg(device, "rpm: me: runtime_idle\n");
409 
410 	dev = dev_get_drvdata(device);
411 	if (!dev)
412 		return -ENODEV;
413 	if (mei_write_is_idle(dev))
414 		pm_runtime_autosuspend(device);
415 
416 	return -EBUSY;
417 }
418 
419 static int mei_me_pm_runtime_suspend(struct device *device)
420 {
421 	struct mei_device *dev;
422 	int ret;
423 
424 	dev_dbg(device, "rpm: me: runtime suspend\n");
425 
426 	dev = dev_get_drvdata(device);
427 	if (!dev)
428 		return -ENODEV;
429 
430 	mutex_lock(&dev->device_lock);
431 
432 	if (mei_write_is_idle(dev))
433 		ret = mei_me_pg_enter_sync(dev);
434 	else
435 		ret = -EAGAIN;
436 
437 	mutex_unlock(&dev->device_lock);
438 
439 	dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
440 
441 	if (ret && ret != -EAGAIN)
442 		schedule_work(&dev->reset_work);
443 
444 	return ret;
445 }
446 
447 static int mei_me_pm_runtime_resume(struct device *device)
448 {
449 	struct mei_device *dev;
450 	int ret;
451 
452 	dev_dbg(device, "rpm: me: runtime resume\n");
453 
454 	dev = dev_get_drvdata(device);
455 	if (!dev)
456 		return -ENODEV;
457 
458 	mutex_lock(&dev->device_lock);
459 
460 	ret = mei_me_pg_exit_sync(dev);
461 
462 	mutex_unlock(&dev->device_lock);
463 
464 	dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
465 
466 	if (ret)
467 		schedule_work(&dev->reset_work);
468 
469 	return ret;
470 }
471 
472 /**
473  * mei_me_set_pm_domain - fill and set pm domain structure for device
474  *
475  * @dev: mei_device
476  */
477 static inline void mei_me_set_pm_domain(struct mei_device *dev)
478 {
479 	struct pci_dev *pdev  = to_pci_dev(dev->dev);
480 
481 	if (pdev->dev.bus && pdev->dev.bus->pm) {
482 		dev->pg_domain.ops = *pdev->dev.bus->pm;
483 
484 		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
485 		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
486 		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
487 
488 		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
489 	}
490 }
491 
492 /**
493  * mei_me_unset_pm_domain - clean pm domain structure for device
494  *
495  * @dev: mei_device
496  */
497 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
498 {
499 	/* stop using pm callbacks if any */
500 	dev_pm_domain_set(dev->dev, NULL);
501 }
502 
503 static const struct dev_pm_ops mei_me_pm_ops = {
504 	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
505 				mei_me_pci_resume)
506 	SET_RUNTIME_PM_OPS(
507 		mei_me_pm_runtime_suspend,
508 		mei_me_pm_runtime_resume,
509 		mei_me_pm_runtime_idle)
510 };
511 
512 #define MEI_ME_PM_OPS	(&mei_me_pm_ops)
513 #else
514 #define MEI_ME_PM_OPS	NULL
515 #endif /* CONFIG_PM */
516 /*
517  *  PCI driver structure
518  */
519 static struct pci_driver mei_me_driver = {
520 	.name = KBUILD_MODNAME,
521 	.id_table = mei_me_pci_tbl,
522 	.probe = mei_me_probe,
523 	.remove = mei_me_remove,
524 	.shutdown = mei_me_shutdown,
525 	.driver.pm = MEI_ME_PM_OPS,
526 	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
527 };
528 
529 module_pci_driver(mei_me_driver);
530 
531 MODULE_AUTHOR("Intel Corporation");
532 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
533 MODULE_LICENSE("GPL v2");
534