1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2003-2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/fs.h> 21 #include <linux/errno.h> 22 #include <linux/types.h> 23 #include <linux/fcntl.h> 24 #include <linux/pci.h> 25 #include <linux/poll.h> 26 #include <linux/ioctl.h> 27 #include <linux/cdev.h> 28 #include <linux/sched.h> 29 #include <linux/uuid.h> 30 #include <linux/compat.h> 31 #include <linux/jiffies.h> 32 #include <linux/interrupt.h> 33 34 #include <linux/pm_domain.h> 35 #include <linux/pm_runtime.h> 36 37 #include <linux/mei.h> 38 39 #include "mei_dev.h" 40 #include "client.h" 41 #include "hw-me-regs.h" 42 #include "hw-me.h" 43 44 /* mei_pci_tbl - PCI Device ID Table */ 45 static const struct pci_device_id mei_me_pci_tbl[] = { 46 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 49 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 50 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 57 58 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 67 68 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 69 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 72 73 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 77 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)}, 78 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)}, 79 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)}, 80 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, 81 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, 82 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 83 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, 84 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 86 87 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 88 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 89 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, 90 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, 91 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH8_CFG)}, 92 93 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 95 96 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 97 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 98 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 104 105 #ifdef CONFIG_PM 106 static inline void mei_me_set_pm_domain(struct mei_device *dev); 107 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 108 #else 109 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 110 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 111 #endif /* CONFIG_PM */ 112 113 /** 114 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 115 * 116 * @pdev: PCI device structure 117 * @cfg: per generation config 118 * 119 * Return: true if ME Interface is valid, false otherwise 120 */ 121 static bool mei_me_quirk_probe(struct pci_dev *pdev, 122 const struct mei_cfg *cfg) 123 { 124 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 125 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 126 return false; 127 } 128 129 return true; 130 } 131 132 /** 133 * mei_me_probe - Device Initialization Routine 134 * 135 * @pdev: PCI device structure 136 * @ent: entry in kcs_pci_tbl 137 * 138 * Return: 0 on success, <0 on failure. 139 */ 140 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 141 { 142 const struct mei_cfg *cfg; 143 struct mei_device *dev; 144 struct mei_me_hw *hw; 145 unsigned int irqflags; 146 int err; 147 148 cfg = mei_me_get_cfg(ent->driver_data); 149 if (!cfg) 150 return -ENODEV; 151 152 if (!mei_me_quirk_probe(pdev, cfg)) 153 return -ENODEV; 154 155 /* enable pci dev */ 156 err = pcim_enable_device(pdev); 157 if (err) { 158 dev_err(&pdev->dev, "failed to enable pci device.\n"); 159 goto end; 160 } 161 /* set PCI host mastering */ 162 pci_set_master(pdev); 163 /* pci request regions and mapping IO device memory for mei driver */ 164 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 165 if (err) { 166 dev_err(&pdev->dev, "failed to get pci regions.\n"); 167 goto end; 168 } 169 170 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 171 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 172 173 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 174 if (err) 175 err = dma_set_coherent_mask(&pdev->dev, 176 DMA_BIT_MASK(32)); 177 } 178 if (err) { 179 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 180 goto end; 181 } 182 183 /* allocates and initializes the mei dev structure */ 184 dev = mei_me_dev_init(pdev, cfg); 185 if (!dev) { 186 err = -ENOMEM; 187 goto end; 188 } 189 hw = to_me_hw(dev); 190 hw->mem_addr = pcim_iomap_table(pdev)[0]; 191 192 pci_enable_msi(pdev); 193 194 /* request and enable interrupt */ 195 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 196 197 err = request_threaded_irq(pdev->irq, 198 mei_me_irq_quick_handler, 199 mei_me_irq_thread_handler, 200 irqflags, KBUILD_MODNAME, dev); 201 if (err) { 202 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 203 pdev->irq); 204 goto end; 205 } 206 207 if (mei_start(dev)) { 208 dev_err(&pdev->dev, "init hw failure.\n"); 209 err = -ENODEV; 210 goto release_irq; 211 } 212 213 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 214 pm_runtime_use_autosuspend(&pdev->dev); 215 216 err = mei_register(dev, &pdev->dev); 217 if (err) 218 goto stop; 219 220 pci_set_drvdata(pdev, dev); 221 222 /* 223 * MEI requires to resume from runtime suspend mode 224 * in order to perform link reset flow upon system suspend. 225 */ 226 pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME; 227 228 /* 229 * For not wake-able HW runtime pm framework 230 * can't be used on pci device level. 231 * Use domain runtime pm callbacks instead. 232 */ 233 if (!pci_dev_run_wake(pdev)) 234 mei_me_set_pm_domain(dev); 235 236 if (mei_pg_is_enabled(dev)) 237 pm_runtime_put_noidle(&pdev->dev); 238 239 dev_dbg(&pdev->dev, "initialization successful.\n"); 240 241 return 0; 242 243 stop: 244 mei_stop(dev); 245 release_irq: 246 mei_cancel_work(dev); 247 mei_disable_interrupts(dev); 248 free_irq(pdev->irq, dev); 249 end: 250 dev_err(&pdev->dev, "initialization failed.\n"); 251 return err; 252 } 253 254 /** 255 * mei_me_shutdown - Device Removal Routine 256 * 257 * @pdev: PCI device structure 258 * 259 * mei_me_shutdown is called from the reboot notifier 260 * it's a simplified version of remove so we go down 261 * faster. 262 */ 263 static void mei_me_shutdown(struct pci_dev *pdev) 264 { 265 struct mei_device *dev; 266 267 dev = pci_get_drvdata(pdev); 268 if (!dev) 269 return; 270 271 dev_dbg(&pdev->dev, "shutdown\n"); 272 mei_stop(dev); 273 274 if (!pci_dev_run_wake(pdev)) 275 mei_me_unset_pm_domain(dev); 276 277 mei_disable_interrupts(dev); 278 free_irq(pdev->irq, dev); 279 } 280 281 /** 282 * mei_me_remove - Device Removal Routine 283 * 284 * @pdev: PCI device structure 285 * 286 * mei_me_remove is called by the PCI subsystem to alert the driver 287 * that it should release a PCI device. 288 */ 289 static void mei_me_remove(struct pci_dev *pdev) 290 { 291 struct mei_device *dev; 292 293 dev = pci_get_drvdata(pdev); 294 if (!dev) 295 return; 296 297 if (mei_pg_is_enabled(dev)) 298 pm_runtime_get_noresume(&pdev->dev); 299 300 dev_dbg(&pdev->dev, "stop\n"); 301 mei_stop(dev); 302 303 if (!pci_dev_run_wake(pdev)) 304 mei_me_unset_pm_domain(dev); 305 306 mei_disable_interrupts(dev); 307 308 free_irq(pdev->irq, dev); 309 310 mei_deregister(dev); 311 } 312 313 #ifdef CONFIG_PM_SLEEP 314 static int mei_me_pci_suspend(struct device *device) 315 { 316 struct pci_dev *pdev = to_pci_dev(device); 317 struct mei_device *dev = pci_get_drvdata(pdev); 318 319 if (!dev) 320 return -ENODEV; 321 322 dev_dbg(&pdev->dev, "suspend\n"); 323 324 mei_stop(dev); 325 326 mei_disable_interrupts(dev); 327 328 free_irq(pdev->irq, dev); 329 pci_disable_msi(pdev); 330 331 return 0; 332 } 333 334 static int mei_me_pci_resume(struct device *device) 335 { 336 struct pci_dev *pdev = to_pci_dev(device); 337 struct mei_device *dev; 338 unsigned int irqflags; 339 int err; 340 341 dev = pci_get_drvdata(pdev); 342 if (!dev) 343 return -ENODEV; 344 345 pci_enable_msi(pdev); 346 347 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 348 349 /* request and enable interrupt */ 350 err = request_threaded_irq(pdev->irq, 351 mei_me_irq_quick_handler, 352 mei_me_irq_thread_handler, 353 irqflags, KBUILD_MODNAME, dev); 354 355 if (err) { 356 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 357 pdev->irq); 358 return err; 359 } 360 361 err = mei_restart(dev); 362 if (err) 363 return err; 364 365 /* Start timer if stopped in suspend */ 366 schedule_delayed_work(&dev->timer_work, HZ); 367 368 return 0; 369 } 370 #endif /* CONFIG_PM_SLEEP */ 371 372 #ifdef CONFIG_PM 373 static int mei_me_pm_runtime_idle(struct device *device) 374 { 375 struct pci_dev *pdev = to_pci_dev(device); 376 struct mei_device *dev; 377 378 dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n"); 379 380 dev = pci_get_drvdata(pdev); 381 if (!dev) 382 return -ENODEV; 383 if (mei_write_is_idle(dev)) 384 pm_runtime_autosuspend(device); 385 386 return -EBUSY; 387 } 388 389 static int mei_me_pm_runtime_suspend(struct device *device) 390 { 391 struct pci_dev *pdev = to_pci_dev(device); 392 struct mei_device *dev; 393 int ret; 394 395 dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n"); 396 397 dev = pci_get_drvdata(pdev); 398 if (!dev) 399 return -ENODEV; 400 401 mutex_lock(&dev->device_lock); 402 403 if (mei_write_is_idle(dev)) 404 ret = mei_me_pg_enter_sync(dev); 405 else 406 ret = -EAGAIN; 407 408 mutex_unlock(&dev->device_lock); 409 410 dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret); 411 412 if (ret && ret != -EAGAIN) 413 schedule_work(&dev->reset_work); 414 415 return ret; 416 } 417 418 static int mei_me_pm_runtime_resume(struct device *device) 419 { 420 struct pci_dev *pdev = to_pci_dev(device); 421 struct mei_device *dev; 422 int ret; 423 424 dev_dbg(&pdev->dev, "rpm: me: runtime resume\n"); 425 426 dev = pci_get_drvdata(pdev); 427 if (!dev) 428 return -ENODEV; 429 430 mutex_lock(&dev->device_lock); 431 432 ret = mei_me_pg_exit_sync(dev); 433 434 mutex_unlock(&dev->device_lock); 435 436 dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret); 437 438 if (ret) 439 schedule_work(&dev->reset_work); 440 441 return ret; 442 } 443 444 /** 445 * mei_me_set_pm_domain - fill and set pm domain structure for device 446 * 447 * @dev: mei_device 448 */ 449 static inline void mei_me_set_pm_domain(struct mei_device *dev) 450 { 451 struct pci_dev *pdev = to_pci_dev(dev->dev); 452 453 if (pdev->dev.bus && pdev->dev.bus->pm) { 454 dev->pg_domain.ops = *pdev->dev.bus->pm; 455 456 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 457 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 458 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 459 460 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 461 } 462 } 463 464 /** 465 * mei_me_unset_pm_domain - clean pm domain structure for device 466 * 467 * @dev: mei_device 468 */ 469 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 470 { 471 /* stop using pm callbacks if any */ 472 dev_pm_domain_set(dev->dev, NULL); 473 } 474 475 static const struct dev_pm_ops mei_me_pm_ops = { 476 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 477 mei_me_pci_resume) 478 SET_RUNTIME_PM_OPS( 479 mei_me_pm_runtime_suspend, 480 mei_me_pm_runtime_resume, 481 mei_me_pm_runtime_idle) 482 }; 483 484 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 485 #else 486 #define MEI_ME_PM_OPS NULL 487 #endif /* CONFIG_PM */ 488 /* 489 * PCI driver structure 490 */ 491 static struct pci_driver mei_me_driver = { 492 .name = KBUILD_MODNAME, 493 .id_table = mei_me_pci_tbl, 494 .probe = mei_me_probe, 495 .remove = mei_me_remove, 496 .shutdown = mei_me_shutdown, 497 .driver.pm = MEI_ME_PM_OPS, 498 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 499 }; 500 501 module_pci_driver(mei_me_driver); 502 503 MODULE_AUTHOR("Intel Corporation"); 504 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 505 MODULE_LICENSE("GPL v2"); 506