1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2003-2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/kernel.h> 22 #include <linux/device.h> 23 #include <linux/fs.h> 24 #include <linux/errno.h> 25 #include <linux/types.h> 26 #include <linux/fcntl.h> 27 #include <linux/aio.h> 28 #include <linux/pci.h> 29 #include <linux/poll.h> 30 #include <linux/init.h> 31 #include <linux/ioctl.h> 32 #include <linux/cdev.h> 33 #include <linux/sched.h> 34 #include <linux/uuid.h> 35 #include <linux/compat.h> 36 #include <linux/jiffies.h> 37 #include <linux/interrupt.h> 38 #include <linux/miscdevice.h> 39 40 #include <linux/mei.h> 41 42 #include "mei_dev.h" 43 #include "hw-me.h" 44 #include "client.h" 45 46 /* mei_pci_tbl - PCI Device ID Table */ 47 static DEFINE_PCI_DEVICE_TABLE(mei_me_pci_tbl) = { 48 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)}, 49 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)}, 50 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)}, 51 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)}, 52 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)}, 53 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)}, 54 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)}, 55 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)}, 56 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)}, 57 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)}, 58 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)}, 59 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)}, 60 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)}, 61 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)}, 62 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)}, 63 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)}, 64 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)}, 65 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)}, 66 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)}, 67 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)}, 68 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)}, 69 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)}, 70 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)}, 71 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)}, 72 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)}, 73 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)}, 74 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)}, 75 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)}, 76 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)}, 77 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)}, 78 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)}, 79 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_H)}, 80 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_W)}, 81 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)}, 82 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_HR)}, 83 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_WPT_LP)}, 84 85 /* required last entry */ 86 {0, } 87 }; 88 89 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 90 91 /** 92 * mei_quirk_probe - probe for devices that doesn't valid ME interface 93 * 94 * @pdev: PCI device structure 95 * @ent: entry into pci_device_table 96 * 97 * returns true if ME Interface is valid, false otherwise 98 */ 99 static bool mei_me_quirk_probe(struct pci_dev *pdev, 100 const struct pci_device_id *ent) 101 { 102 u32 reg; 103 if (ent->device == MEI_DEV_ID_PBG_1) { 104 pci_read_config_dword(pdev, 0x48, ®); 105 /* make sure that bit 9 is up and bit 10 is down */ 106 if ((reg & 0x600) == 0x200) { 107 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 108 return false; 109 } 110 } 111 return true; 112 } 113 /** 114 * mei_probe - Device Initialization Routine 115 * 116 * @pdev: PCI device structure 117 * @ent: entry in kcs_pci_tbl 118 * 119 * returns 0 on success, <0 on failure. 120 */ 121 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 122 { 123 struct mei_device *dev; 124 struct mei_me_hw *hw; 125 int err; 126 127 128 if (!mei_me_quirk_probe(pdev, ent)) { 129 err = -ENODEV; 130 goto end; 131 } 132 133 /* enable pci dev */ 134 err = pci_enable_device(pdev); 135 if (err) { 136 dev_err(&pdev->dev, "failed to enable pci device.\n"); 137 goto end; 138 } 139 /* set PCI host mastering */ 140 pci_set_master(pdev); 141 /* pci request regions for mei driver */ 142 err = pci_request_regions(pdev, KBUILD_MODNAME); 143 if (err) { 144 dev_err(&pdev->dev, "failed to get pci regions.\n"); 145 goto disable_device; 146 } 147 148 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 149 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 150 151 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 152 if (err) 153 err = dma_set_coherent_mask(&pdev->dev, 154 DMA_BIT_MASK(32)); 155 } 156 if (err) { 157 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 158 goto release_regions; 159 } 160 161 162 /* allocates and initializes the mei dev structure */ 163 dev = mei_me_dev_init(pdev); 164 if (!dev) { 165 err = -ENOMEM; 166 goto release_regions; 167 } 168 hw = to_me_hw(dev); 169 /* mapping IO device memory */ 170 hw->mem_addr = pci_iomap(pdev, 0, 0); 171 if (!hw->mem_addr) { 172 dev_err(&pdev->dev, "mapping I/O device memory failure.\n"); 173 err = -ENOMEM; 174 goto free_device; 175 } 176 pci_enable_msi(pdev); 177 178 /* request and enable interrupt */ 179 if (pci_dev_msi_enabled(pdev)) 180 err = request_threaded_irq(pdev->irq, 181 NULL, 182 mei_me_irq_thread_handler, 183 IRQF_ONESHOT, KBUILD_MODNAME, dev); 184 else 185 err = request_threaded_irq(pdev->irq, 186 mei_me_irq_quick_handler, 187 mei_me_irq_thread_handler, 188 IRQF_SHARED, KBUILD_MODNAME, dev); 189 190 if (err) { 191 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 192 pdev->irq); 193 goto disable_msi; 194 } 195 196 if (mei_start(dev)) { 197 dev_err(&pdev->dev, "init hw failure.\n"); 198 err = -ENODEV; 199 goto release_irq; 200 } 201 202 err = mei_register(dev); 203 if (err) 204 goto release_irq; 205 206 pci_set_drvdata(pdev, dev); 207 208 schedule_delayed_work(&dev->timer_work, HZ); 209 210 dev_dbg(&pdev->dev, "initialization successful.\n"); 211 212 return 0; 213 214 release_irq: 215 mei_cancel_work(dev); 216 mei_disable_interrupts(dev); 217 free_irq(pdev->irq, dev); 218 disable_msi: 219 pci_disable_msi(pdev); 220 pci_iounmap(pdev, hw->mem_addr); 221 free_device: 222 kfree(dev); 223 release_regions: 224 pci_release_regions(pdev); 225 disable_device: 226 pci_disable_device(pdev); 227 end: 228 dev_err(&pdev->dev, "initialization failed.\n"); 229 return err; 230 } 231 232 /** 233 * mei_remove - Device Removal Routine 234 * 235 * @pdev: PCI device structure 236 * 237 * mei_remove is called by the PCI subsystem to alert the driver 238 * that it should release a PCI device. 239 */ 240 static void mei_me_remove(struct pci_dev *pdev) 241 { 242 struct mei_device *dev; 243 struct mei_me_hw *hw; 244 245 dev = pci_get_drvdata(pdev); 246 if (!dev) 247 return; 248 249 hw = to_me_hw(dev); 250 251 252 dev_dbg(&pdev->dev, "stop\n"); 253 mei_stop(dev); 254 255 /* disable interrupts */ 256 mei_disable_interrupts(dev); 257 258 free_irq(pdev->irq, dev); 259 pci_disable_msi(pdev); 260 261 if (hw->mem_addr) 262 pci_iounmap(pdev, hw->mem_addr); 263 264 mei_deregister(dev); 265 266 kfree(dev); 267 268 pci_release_regions(pdev); 269 pci_disable_device(pdev); 270 271 272 } 273 #ifdef CONFIG_PM 274 static int mei_me_pci_suspend(struct device *device) 275 { 276 struct pci_dev *pdev = to_pci_dev(device); 277 struct mei_device *dev = pci_get_drvdata(pdev); 278 279 if (!dev) 280 return -ENODEV; 281 282 dev_dbg(&pdev->dev, "suspend\n"); 283 284 mei_stop(dev); 285 286 mei_disable_interrupts(dev); 287 288 free_irq(pdev->irq, dev); 289 pci_disable_msi(pdev); 290 291 return 0; 292 } 293 294 static int mei_me_pci_resume(struct device *device) 295 { 296 struct pci_dev *pdev = to_pci_dev(device); 297 struct mei_device *dev; 298 int err; 299 300 dev = pci_get_drvdata(pdev); 301 if (!dev) 302 return -ENODEV; 303 304 pci_enable_msi(pdev); 305 306 /* request and enable interrupt */ 307 if (pci_dev_msi_enabled(pdev)) 308 err = request_threaded_irq(pdev->irq, 309 NULL, 310 mei_me_irq_thread_handler, 311 IRQF_ONESHOT, KBUILD_MODNAME, dev); 312 else 313 err = request_threaded_irq(pdev->irq, 314 mei_me_irq_quick_handler, 315 mei_me_irq_thread_handler, 316 IRQF_SHARED, KBUILD_MODNAME, dev); 317 318 if (err) { 319 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 320 pdev->irq); 321 return err; 322 } 323 324 err = mei_restart(dev); 325 if (err) 326 return err; 327 328 /* Start timer if stopped in suspend */ 329 schedule_delayed_work(&dev->timer_work, HZ); 330 331 return 0; 332 } 333 static SIMPLE_DEV_PM_OPS(mei_me_pm_ops, mei_me_pci_suspend, mei_me_pci_resume); 334 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 335 #else 336 #define MEI_ME_PM_OPS NULL 337 #endif /* CONFIG_PM */ 338 /* 339 * PCI driver structure 340 */ 341 static struct pci_driver mei_me_driver = { 342 .name = KBUILD_MODNAME, 343 .id_table = mei_me_pci_tbl, 344 .probe = mei_me_probe, 345 .remove = mei_me_remove, 346 .shutdown = mei_me_remove, 347 .driver.pm = MEI_ME_PM_OPS, 348 }; 349 350 module_pci_driver(mei_me_driver); 351 352 MODULE_AUTHOR("Intel Corporation"); 353 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 354 MODULE_LICENSE("GPL v2"); 355