1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2013-2014, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/jiffies.h> 19 #include <linux/delay.h> 20 #include <linux/kthread.h> 21 #include <linux/irqreturn.h> 22 23 #include <linux/mei.h> 24 25 #include "mei_dev.h" 26 #include "hw-txe.h" 27 #include "client.h" 28 #include "hbm.h" 29 30 /** 31 * mei_txe_reg_read - Reads 32bit data from the device 32 * 33 * @base_addr: registers base address 34 * @offset: register offset 35 * 36 */ 37 static inline u32 mei_txe_reg_read(void __iomem *base_addr, 38 unsigned long offset) 39 { 40 return ioread32(base_addr + offset); 41 } 42 43 /** 44 * mei_txe_reg_write - Writes 32bit data to the device 45 * 46 * @base_addr: registers base address 47 * @offset: register offset 48 * @value: the value to write 49 */ 50 static inline void mei_txe_reg_write(void __iomem *base_addr, 51 unsigned long offset, u32 value) 52 { 53 iowrite32(value, base_addr + offset); 54 } 55 56 /** 57 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR 58 * 59 * @dev: the device structure 60 * @offset: register offset 61 * 62 * Doesn't check for aliveness while Reads 32bit data from the SeC BAR 63 */ 64 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, 65 unsigned long offset) 66 { 67 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); 68 } 69 70 /** 71 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR 72 * 73 * @dev: the device structure 74 * @offset: register offset 75 * 76 * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set 77 */ 78 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, 79 unsigned long offset) 80 { 81 WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); 82 return mei_txe_sec_reg_read_silent(hw, offset); 83 } 84 /** 85 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR 86 * doesn't check for aliveness 87 * 88 * @dev: the device structure 89 * @offset: register offset 90 * @value: value to write 91 * 92 * Doesn't check for aliveness while writes 32bit data from to the SeC BAR 93 */ 94 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, 95 unsigned long offset, u32 value) 96 { 97 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); 98 } 99 100 /** 101 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR 102 * 103 * @dev: the device structure 104 * @offset: register offset 105 * @value: value to write 106 * 107 * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set 108 */ 109 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, 110 unsigned long offset, u32 value) 111 { 112 WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); 113 mei_txe_sec_reg_write_silent(hw, offset, value); 114 } 115 /** 116 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR 117 * 118 * @hw: the device structure 119 * @offset: offset from which to read the data 120 * 121 */ 122 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, 123 unsigned long offset) 124 { 125 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); 126 } 127 128 /** 129 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR 130 * 131 * @hw: the device structure 132 * @offset: offset from which to write the data 133 * @value: the byte to write 134 */ 135 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, 136 unsigned long offset, u32 value) 137 { 138 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); 139 } 140 141 /** 142 * mei_txe_aliveness_set - request for aliveness change 143 * 144 * @dev: the device structure 145 * @req: requested aliveness value 146 * 147 * Request for aliveness change and returns true if the change is 148 * really needed and false if aliveness is already 149 * in the requested state 150 * Requires device lock to be held 151 */ 152 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req) 153 { 154 155 struct mei_txe_hw *hw = to_txe_hw(dev); 156 bool do_req = hw->aliveness != req; 157 158 dev_dbg(&dev->pdev->dev, "Aliveness current=%d request=%d\n", 159 hw->aliveness, req); 160 if (do_req) { 161 dev->pg_event = MEI_PG_EVENT_WAIT; 162 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); 163 } 164 return do_req; 165 } 166 167 168 /** 169 * mei_txe_aliveness_req_get - get aliveness requested register value 170 * 171 * @dev: the device structure 172 * 173 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from 174 * from HICR_HOST_ALIVENESS_REQ register value 175 */ 176 static u32 mei_txe_aliveness_req_get(struct mei_device *dev) 177 { 178 struct mei_txe_hw *hw = to_txe_hw(dev); 179 u32 reg; 180 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); 181 return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED; 182 } 183 184 /** 185 * mei_txe_aliveness_get - get aliveness response register value 186 * @dev: the device structure 187 * 188 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit 189 * from HICR_HOST_ALIVENESS_RESP register value 190 */ 191 static u32 mei_txe_aliveness_get(struct mei_device *dev) 192 { 193 struct mei_txe_hw *hw = to_txe_hw(dev); 194 u32 reg; 195 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); 196 return reg & HICR_HOST_ALIVENESS_RESP_ACK; 197 } 198 199 /** 200 * mei_txe_aliveness_poll - waits for aliveness to settle 201 * 202 * @dev: the device structure 203 * @expected: expected aliveness value 204 * 205 * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set 206 * returns > 0 if the expected value was received, -ETIME otherwise 207 */ 208 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected) 209 { 210 struct mei_txe_hw *hw = to_txe_hw(dev); 211 int t = 0; 212 213 do { 214 hw->aliveness = mei_txe_aliveness_get(dev); 215 if (hw->aliveness == expected) { 216 dev->pg_event = MEI_PG_EVENT_IDLE; 217 dev_dbg(&dev->pdev->dev, 218 "aliveness settled after %d msecs\n", t); 219 return t; 220 } 221 mutex_unlock(&dev->device_lock); 222 msleep(MSEC_PER_SEC / 5); 223 mutex_lock(&dev->device_lock); 224 t += MSEC_PER_SEC / 5; 225 } while (t < SEC_ALIVENESS_WAIT_TIMEOUT); 226 227 dev->pg_event = MEI_PG_EVENT_IDLE; 228 dev_err(&dev->pdev->dev, "aliveness timed out\n"); 229 return -ETIME; 230 } 231 232 /** 233 * mei_txe_aliveness_wait - waits for aliveness to settle 234 * 235 * @dev: the device structure 236 * @expected: expected aliveness value 237 * 238 * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set 239 * returns returns 0 on success and < 0 otherwise 240 */ 241 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected) 242 { 243 struct mei_txe_hw *hw = to_txe_hw(dev); 244 const unsigned long timeout = 245 msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT); 246 long err; 247 int ret; 248 249 hw->aliveness = mei_txe_aliveness_get(dev); 250 if (hw->aliveness == expected) 251 return 0; 252 253 mutex_unlock(&dev->device_lock); 254 err = wait_event_timeout(hw->wait_aliveness_resp, 255 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 256 mutex_lock(&dev->device_lock); 257 258 hw->aliveness = mei_txe_aliveness_get(dev); 259 ret = hw->aliveness == expected ? 0 : -ETIME; 260 261 if (ret) 262 dev_warn(&dev->pdev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n", 263 err, hw->aliveness, dev->pg_event); 264 else 265 dev_dbg(&dev->pdev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n", 266 jiffies_to_msecs(timeout - err), 267 hw->aliveness, dev->pg_event); 268 269 dev->pg_event = MEI_PG_EVENT_IDLE; 270 return ret; 271 } 272 273 /** 274 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete 275 * 276 * @dev: the device structure 277 * 278 * returns returns 0 on success and < 0 otherwise 279 */ 280 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req) 281 { 282 if (mei_txe_aliveness_set(dev, req)) 283 return mei_txe_aliveness_wait(dev, req); 284 return 0; 285 } 286 287 /** 288 * mei_txe_pg_is_enabled - detect if PG is supported by HW 289 * 290 * @dev: the device structure 291 * 292 * returns: true is pg supported, false otherwise 293 */ 294 static bool mei_txe_pg_is_enabled(struct mei_device *dev) 295 { 296 return true; 297 } 298 299 /** 300 * mei_txe_pg_state - translate aliveness register value 301 * to the mei power gating state 302 * 303 * @dev: the device structure 304 * 305 * returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise 306 */ 307 static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev) 308 { 309 struct mei_txe_hw *hw = to_txe_hw(dev); 310 return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON; 311 } 312 313 /** 314 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt 315 * 316 * @dev: the device structure 317 */ 318 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev) 319 { 320 struct mei_txe_hw *hw = to_txe_hw(dev); 321 u32 hintmsk; 322 /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */ 323 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); 324 hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY; 325 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); 326 } 327 328 /** 329 * mei_txe_input_doorbell_set 330 * - Sets bit 0 in SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL. 331 * @dev: the device structure 332 */ 333 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) 334 { 335 /* Clear the interrupt cause */ 336 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); 337 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); 338 } 339 340 /** 341 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1 342 * 343 * @dev: the device structure 344 */ 345 static void mei_txe_output_ready_set(struct mei_txe_hw *hw) 346 { 347 mei_txe_br_reg_write(hw, 348 SICR_SEC_IPC_OUTPUT_STATUS_REG, 349 SEC_IPC_OUTPUT_STATUS_RDY); 350 } 351 352 /** 353 * mei_txe_is_input_ready - check if TXE is ready for receiving data 354 * 355 * @dev: the device structure 356 */ 357 static bool mei_txe_is_input_ready(struct mei_device *dev) 358 { 359 struct mei_txe_hw *hw = to_txe_hw(dev); 360 u32 status; 361 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); 362 return !!(SEC_IPC_INPUT_STATUS_RDY & status); 363 } 364 365 /** 366 * mei_txe_intr_clear - clear all interrupts 367 * 368 * @dev: the device structure 369 */ 370 static inline void mei_txe_intr_clear(struct mei_device *dev) 371 { 372 struct mei_txe_hw *hw = to_txe_hw(dev); 373 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, 374 SEC_IPC_HOST_INT_STATUS_PENDING); 375 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); 376 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); 377 } 378 379 /** 380 * mei_txe_intr_disable - disable all interrupts 381 * 382 * @dev: the device structure 383 */ 384 static void mei_txe_intr_disable(struct mei_device *dev) 385 { 386 struct mei_txe_hw *hw = to_txe_hw(dev); 387 mei_txe_br_reg_write(hw, HHIER_REG, 0); 388 mei_txe_br_reg_write(hw, HIER_REG, 0); 389 } 390 /** 391 * mei_txe_intr_disable - enable all interrupts 392 * 393 * @dev: the device structure 394 */ 395 static void mei_txe_intr_enable(struct mei_device *dev) 396 { 397 struct mei_txe_hw *hw = to_txe_hw(dev); 398 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); 399 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); 400 } 401 402 /** 403 * mei_txe_pending_interrupts - check if there are pending interrupts 404 * only Aliveness, Input ready, and output doorbell are of relevance 405 * 406 * @dev: the device structure 407 * 408 * Checks if there are pending interrupts 409 * only Aliveness, Readiness, Input ready, and Output doorbell are relevant 410 */ 411 static bool mei_txe_pending_interrupts(struct mei_device *dev) 412 { 413 414 struct mei_txe_hw *hw = to_txe_hw(dev); 415 bool ret = (hw->intr_cause & (TXE_INTR_READINESS | 416 TXE_INTR_ALIVENESS | 417 TXE_INTR_IN_READY | 418 TXE_INTR_OUT_DB)); 419 420 if (ret) { 421 dev_dbg(&dev->pdev->dev, 422 "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n", 423 !!(hw->intr_cause & TXE_INTR_IN_READY), 424 !!(hw->intr_cause & TXE_INTR_READINESS), 425 !!(hw->intr_cause & TXE_INTR_ALIVENESS), 426 !!(hw->intr_cause & TXE_INTR_OUT_DB)); 427 } 428 return ret; 429 } 430 431 /** 432 * mei_txe_input_payload_write - write a dword to the host buffer 433 * at offset idx 434 * 435 * @dev: the device structure 436 * @idx: index in the host buffer 437 * @value: value 438 */ 439 static void mei_txe_input_payload_write(struct mei_device *dev, 440 unsigned long idx, u32 value) 441 { 442 struct mei_txe_hw *hw = to_txe_hw(dev); 443 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + 444 (idx * sizeof(u32)), value); 445 } 446 447 /** 448 * mei_txe_out_data_read - read dword from the device buffer 449 * at offset idx 450 * 451 * @dev: the device structure 452 * @idx: index in the device buffer 453 * 454 * returns register value at index 455 */ 456 static u32 mei_txe_out_data_read(const struct mei_device *dev, 457 unsigned long idx) 458 { 459 struct mei_txe_hw *hw = to_txe_hw(dev); 460 return mei_txe_br_reg_read(hw, 461 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32))); 462 } 463 464 /* Readiness */ 465 466 /** 467 * mei_txe_readiness_set_host_rdy 468 * 469 * @dev: the device structure 470 */ 471 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev) 472 { 473 struct mei_txe_hw *hw = to_txe_hw(dev); 474 mei_txe_br_reg_write(hw, 475 SICR_HOST_IPC_READINESS_REQ_REG, 476 SICR_HOST_IPC_READINESS_HOST_RDY); 477 } 478 479 /** 480 * mei_txe_readiness_clear 481 * 482 * @dev: the device structure 483 */ 484 static void mei_txe_readiness_clear(struct mei_device *dev) 485 { 486 struct mei_txe_hw *hw = to_txe_hw(dev); 487 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, 488 SICR_HOST_IPC_READINESS_RDY_CLR); 489 } 490 /** 491 * mei_txe_readiness_get - Reads and returns 492 * the HICR_SEC_IPC_READINESS register value 493 * 494 * @dev: the device structure 495 */ 496 static u32 mei_txe_readiness_get(struct mei_device *dev) 497 { 498 struct mei_txe_hw *hw = to_txe_hw(dev); 499 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); 500 } 501 502 503 /** 504 * mei_txe_readiness_is_sec_rdy - check readiness 505 * for HICR_SEC_IPC_READINESS_SEC_RDY 506 * 507 * @readiness - cached readiness state 508 */ 509 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness) 510 { 511 return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY); 512 } 513 514 /** 515 * mei_txe_hw_is_ready - check if the hw is ready 516 * 517 * @dev: the device structure 518 */ 519 static bool mei_txe_hw_is_ready(struct mei_device *dev) 520 { 521 u32 readiness = mei_txe_readiness_get(dev); 522 return mei_txe_readiness_is_sec_rdy(readiness); 523 } 524 525 /** 526 * mei_txe_host_is_ready - check if the host is ready 527 * 528 * @dev: the device structure 529 */ 530 static inline bool mei_txe_host_is_ready(struct mei_device *dev) 531 { 532 struct mei_txe_hw *hw = to_txe_hw(dev); 533 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); 534 return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY); 535 } 536 537 /** 538 * mei_txe_readiness_wait - wait till readiness settles 539 * 540 * @dev: the device structure 541 * 542 * returns 0 on success and -ETIME on timeout 543 */ 544 static int mei_txe_readiness_wait(struct mei_device *dev) 545 { 546 if (mei_txe_hw_is_ready(dev)) 547 return 0; 548 549 mutex_unlock(&dev->device_lock); 550 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, 551 msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT)); 552 mutex_lock(&dev->device_lock); 553 if (!dev->recvd_hw_ready) { 554 dev_err(&dev->pdev->dev, "wait for readiness failed\n"); 555 return -ETIME; 556 } 557 558 dev->recvd_hw_ready = false; 559 return 0; 560 } 561 562 /** 563 * mei_txe_hw_config - configure hardware at the start of the devices 564 * 565 * @dev: the device structure 566 * 567 * Configure hardware at the start of the device should be done only 568 * once at the device probe time 569 */ 570 static void mei_txe_hw_config(struct mei_device *dev) 571 { 572 573 struct mei_txe_hw *hw = to_txe_hw(dev); 574 /* Doesn't change in runtime */ 575 dev->hbuf_depth = PAYLOAD_SIZE / 4; 576 577 hw->aliveness = mei_txe_aliveness_get(dev); 578 hw->readiness = mei_txe_readiness_get(dev); 579 580 dev_dbg(&dev->pdev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", 581 hw->aliveness, hw->readiness); 582 } 583 584 585 /** 586 * mei_txe_write - writes a message to device. 587 * 588 * @dev: the device structure 589 * @header: header of message 590 * @buf: message buffer will be written 591 * returns 1 if success, 0 - otherwise. 592 */ 593 594 static int mei_txe_write(struct mei_device *dev, 595 struct mei_msg_hdr *header, unsigned char *buf) 596 { 597 struct mei_txe_hw *hw = to_txe_hw(dev); 598 unsigned long rem; 599 unsigned long length; 600 int slots = dev->hbuf_depth; 601 u32 *reg_buf = (u32 *)buf; 602 u32 dw_cnt; 603 int i; 604 605 if (WARN_ON(!header || !buf)) 606 return -EINVAL; 607 608 length = header->length; 609 610 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); 611 612 dw_cnt = mei_data2slots(length); 613 if (dw_cnt > slots) 614 return -EMSGSIZE; 615 616 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) 617 return -EAGAIN; 618 619 /* Enable Input Ready Interrupt. */ 620 mei_txe_input_ready_interrupt_enable(dev); 621 622 if (!mei_txe_is_input_ready(dev)) { 623 struct mei_fw_status fw_status; 624 mei_fw_status(dev, &fw_status); 625 dev_err(&dev->pdev->dev, "Input is not ready " FW_STS_FMT "\n", 626 FW_STS_PRM(fw_status)); 627 return -EAGAIN; 628 } 629 630 mei_txe_input_payload_write(dev, 0, *((u32 *)header)); 631 632 for (i = 0; i < length / 4; i++) 633 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]); 634 635 rem = length & 0x3; 636 if (rem > 0) { 637 u32 reg = 0; 638 memcpy(®, &buf[length - rem], rem); 639 mei_txe_input_payload_write(dev, i + 1, reg); 640 } 641 642 /* after each write the whole buffer is consumed */ 643 hw->slots = 0; 644 645 /* Set Input-Doorbell */ 646 mei_txe_input_doorbell_set(hw); 647 648 return 0; 649 } 650 651 /** 652 * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer 653 * 654 * @dev: the device structure 655 * 656 * returns the PAYLOAD_SIZE - 4 657 */ 658 static size_t mei_txe_hbuf_max_len(const struct mei_device *dev) 659 { 660 return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr); 661 } 662 663 /** 664 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer 665 * 666 * @dev: the device structure 667 * 668 * returns always hbuf_depth 669 */ 670 static int mei_txe_hbuf_empty_slots(struct mei_device *dev) 671 { 672 struct mei_txe_hw *hw = to_txe_hw(dev); 673 return hw->slots; 674 } 675 676 /** 677 * mei_txe_count_full_read_slots - mimics the me device circular buffer 678 * 679 * @dev: the device structure 680 * 681 * returns always buffer size in dwords count 682 */ 683 static int mei_txe_count_full_read_slots(struct mei_device *dev) 684 { 685 /* read buffers has static size */ 686 return PAYLOAD_SIZE / 4; 687 } 688 689 /** 690 * mei_txe_read_hdr - read message header which is always in 4 first bytes 691 * 692 * @dev: the device structure 693 * 694 * returns mei message header 695 */ 696 697 static u32 mei_txe_read_hdr(const struct mei_device *dev) 698 { 699 return mei_txe_out_data_read(dev, 0); 700 } 701 /** 702 * mei_txe_read - reads a message from the txe device. 703 * 704 * @dev: the device structure 705 * @buf: message buffer will be written 706 * @len: message size will be read 707 * 708 * returns -EINVAL on error wrong argument and 0 on success 709 */ 710 static int mei_txe_read(struct mei_device *dev, 711 unsigned char *buf, unsigned long len) 712 { 713 714 struct mei_txe_hw *hw = to_txe_hw(dev); 715 u32 i; 716 u32 *reg_buf = (u32 *)buf; 717 u32 rem = len & 0x3; 718 719 if (WARN_ON(!buf || !len)) 720 return -EINVAL; 721 722 dev_dbg(&dev->pdev->dev, 723 "buffer-length = %lu buf[0]0x%08X\n", 724 len, mei_txe_out_data_read(dev, 0)); 725 726 for (i = 0; i < len / 4; i++) { 727 /* skip header: index starts from 1 */ 728 u32 reg = mei_txe_out_data_read(dev, i + 1); 729 dev_dbg(&dev->pdev->dev, "buf[%d] = 0x%08X\n", i, reg); 730 *reg_buf++ = reg; 731 } 732 733 if (rem) { 734 u32 reg = mei_txe_out_data_read(dev, i + 1); 735 memcpy(reg_buf, ®, rem); 736 } 737 738 mei_txe_output_ready_set(hw); 739 return 0; 740 } 741 742 /** 743 * mei_txe_hw_reset - resets host and fw. 744 * 745 * @dev: the device structure 746 * @intr_enable: if interrupt should be enabled after reset. 747 * 748 * returns 0 on success and < 0 in case of error 749 */ 750 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable) 751 { 752 struct mei_txe_hw *hw = to_txe_hw(dev); 753 754 u32 aliveness_req; 755 /* 756 * read input doorbell to ensure consistency between Bridge and SeC 757 * return value might be garbage return 758 */ 759 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); 760 761 aliveness_req = mei_txe_aliveness_req_get(dev); 762 hw->aliveness = mei_txe_aliveness_get(dev); 763 764 /* Disable interrupts in this stage we will poll */ 765 mei_txe_intr_disable(dev); 766 767 /* 768 * If Aliveness Request and Aliveness Response are not equal then 769 * wait for them to be equal 770 * Since we might have interrupts disabled - poll for it 771 */ 772 if (aliveness_req != hw->aliveness) 773 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) { 774 dev_err(&dev->pdev->dev, 775 "wait for aliveness settle failed ... bailing out\n"); 776 return -EIO; 777 } 778 779 /* 780 * If Aliveness Request and Aliveness Response are set then clear them 781 */ 782 if (aliveness_req) { 783 mei_txe_aliveness_set(dev, 0); 784 if (mei_txe_aliveness_poll(dev, 0) < 0) { 785 dev_err(&dev->pdev->dev, 786 "wait for aliveness failed ... bailing out\n"); 787 return -EIO; 788 } 789 } 790 791 /* 792 * Set rediness RDY_CLR bit 793 */ 794 mei_txe_readiness_clear(dev); 795 796 return 0; 797 } 798 799 /** 800 * mei_txe_hw_start - start the hardware after reset 801 * 802 * @dev: the device structure 803 * 804 * returns 0 on success and < 0 in case of error 805 */ 806 static int mei_txe_hw_start(struct mei_device *dev) 807 { 808 struct mei_txe_hw *hw = to_txe_hw(dev); 809 int ret; 810 811 u32 hisr; 812 813 /* bring back interrupts */ 814 mei_txe_intr_enable(dev); 815 816 ret = mei_txe_readiness_wait(dev); 817 if (ret < 0) { 818 dev_err(&dev->pdev->dev, "wating for readiness failed\n"); 819 return ret; 820 } 821 822 /* 823 * If HISR.INT2_STS interrupt status bit is set then clear it. 824 */ 825 hisr = mei_txe_br_reg_read(hw, HISR_REG); 826 if (hisr & HISR_INT_2_STS) 827 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); 828 829 /* Clear the interrupt cause of OutputDoorbell */ 830 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); 831 832 ret = mei_txe_aliveness_set_sync(dev, 1); 833 if (ret < 0) { 834 dev_err(&dev->pdev->dev, "wait for aliveness failed ... bailing out\n"); 835 return ret; 836 } 837 838 /* enable input ready interrupts: 839 * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK 840 */ 841 mei_txe_input_ready_interrupt_enable(dev); 842 843 844 /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */ 845 mei_txe_output_ready_set(hw); 846 847 /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY 848 */ 849 mei_txe_readiness_set_host_rdy(dev); 850 851 return 0; 852 } 853 854 /** 855 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into 856 * single bit mask and acknowledge the interrupts 857 * 858 * @dev: the device structure 859 * @do_ack: acknowledge interrupts 860 */ 861 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack) 862 { 863 struct mei_txe_hw *hw = to_txe_hw(dev); 864 u32 hisr; 865 u32 hhisr; 866 u32 ipc_isr; 867 u32 aliveness; 868 bool generated; 869 870 /* read interrupt registers */ 871 hhisr = mei_txe_br_reg_read(hw, HHISR_REG); 872 generated = (hhisr & IPC_HHIER_MSK); 873 if (!generated) 874 goto out; 875 876 hisr = mei_txe_br_reg_read(hw, HISR_REG); 877 878 aliveness = mei_txe_aliveness_get(dev); 879 if (hhisr & IPC_HHIER_SEC && aliveness) 880 ipc_isr = mei_txe_sec_reg_read_silent(hw, 881 SEC_IPC_HOST_INT_STATUS_REG); 882 else 883 ipc_isr = 0; 884 885 generated = generated || 886 (hisr & HISR_INT_STS_MSK) || 887 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING); 888 889 if (generated && do_ack) { 890 /* Save the interrupt causes */ 891 hw->intr_cause |= hisr & HISR_INT_STS_MSK; 892 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY) 893 hw->intr_cause |= TXE_INTR_IN_READY; 894 895 896 mei_txe_intr_disable(dev); 897 /* Clear the interrupts in hierarchy: 898 * IPC and Bridge, than the High Level */ 899 mei_txe_sec_reg_write_silent(hw, 900 SEC_IPC_HOST_INT_STATUS_REG, ipc_isr); 901 mei_txe_br_reg_write(hw, HISR_REG, hisr); 902 mei_txe_br_reg_write(hw, HHISR_REG, hhisr); 903 } 904 905 out: 906 return generated; 907 } 908 909 /** 910 * mei_txe_irq_quick_handler - The ISR of the MEI device 911 * 912 * @irq: The irq number 913 * @dev_id: pointer to the device structure 914 * 915 * returns irqreturn_t 916 */ 917 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id) 918 { 919 struct mei_device *dev = dev_id; 920 921 if (mei_txe_check_and_ack_intrs(dev, true)) 922 return IRQ_WAKE_THREAD; 923 return IRQ_NONE; 924 } 925 926 927 /** 928 * mei_txe_irq_thread_handler - txe interrupt thread 929 * 930 * @irq: The irq number 931 * @dev_id: pointer to the device structure 932 * 933 * returns irqreturn_t 934 * 935 */ 936 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id) 937 { 938 struct mei_device *dev = (struct mei_device *) dev_id; 939 struct mei_txe_hw *hw = to_txe_hw(dev); 940 struct mei_cl_cb complete_list; 941 s32 slots; 942 int rets = 0; 943 944 dev_dbg(&dev->pdev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", 945 mei_txe_br_reg_read(hw, HHISR_REG), 946 mei_txe_br_reg_read(hw, HISR_REG), 947 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); 948 949 950 /* initialize our complete list */ 951 mutex_lock(&dev->device_lock); 952 mei_io_list_init(&complete_list); 953 954 if (pci_dev_msi_enabled(dev->pdev)) 955 mei_txe_check_and_ack_intrs(dev, true); 956 957 /* show irq events */ 958 mei_txe_pending_interrupts(dev); 959 960 hw->aliveness = mei_txe_aliveness_get(dev); 961 hw->readiness = mei_txe_readiness_get(dev); 962 963 /* Readiness: 964 * Detection of TXE driver going through reset 965 * or TXE driver resetting the HECI interface. 966 */ 967 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { 968 dev_dbg(&dev->pdev->dev, "Readiness Interrupt was received...\n"); 969 970 /* Check if SeC is going through reset */ 971 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { 972 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n"); 973 dev->recvd_hw_ready = true; 974 } else { 975 dev->recvd_hw_ready = false; 976 if (dev->dev_state != MEI_DEV_RESETTING) { 977 978 dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n"); 979 schedule_work(&dev->reset_work); 980 goto end; 981 982 } 983 } 984 wake_up(&dev->wait_hw_ready); 985 } 986 987 /************************************************************/ 988 /* Check interrupt cause: 989 * Aliveness: Detection of SeC acknowledge of host request that 990 * it remain alive or host cancellation of that request. 991 */ 992 993 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { 994 /* Clear the interrupt cause */ 995 dev_dbg(&dev->pdev->dev, 996 "Aliveness Interrupt: Status: %d\n", hw->aliveness); 997 dev->pg_event = MEI_PG_EVENT_RECEIVED; 998 if (waitqueue_active(&hw->wait_aliveness_resp)) 999 wake_up(&hw->wait_aliveness_resp); 1000 } 1001 1002 1003 /* Output Doorbell: 1004 * Detection of SeC having sent output to host 1005 */ 1006 slots = mei_count_full_read_slots(dev); 1007 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { 1008 /* Read from TXE */ 1009 rets = mei_irq_read_handler(dev, &complete_list, &slots); 1010 if (rets && dev->dev_state != MEI_DEV_RESETTING) { 1011 dev_err(&dev->pdev->dev, 1012 "mei_irq_read_handler ret = %d.\n", rets); 1013 1014 schedule_work(&dev->reset_work); 1015 goto end; 1016 } 1017 } 1018 /* Input Ready: Detection if host can write to SeC */ 1019 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { 1020 dev->hbuf_is_ready = true; 1021 hw->slots = dev->hbuf_depth; 1022 } 1023 1024 if (hw->aliveness && dev->hbuf_is_ready) { 1025 /* get the real register value */ 1026 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1027 rets = mei_irq_write_handler(dev, &complete_list); 1028 if (rets && rets != -EMSGSIZE) 1029 dev_err(&dev->pdev->dev, "mei_irq_write_handler ret = %d.\n", 1030 rets); 1031 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1032 } 1033 1034 mei_irq_compl_handler(dev, &complete_list); 1035 1036 end: 1037 dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets); 1038 1039 mutex_unlock(&dev->device_lock); 1040 1041 mei_enable_interrupts(dev); 1042 return IRQ_HANDLED; 1043 } 1044 1045 1046 /** 1047 * mei_txe_fw_status - retrieve fw status from the pci config space 1048 * 1049 * @dev: the device structure 1050 * @fw_status: fw status registers storage 1051 * 1052 * returns: 0 on success an error code otherwise 1053 */ 1054 static int mei_txe_fw_status(struct mei_device *dev, 1055 struct mei_fw_status *fw_status) 1056 { 1057 const u32 pci_cfg_reg[] = {PCI_CFG_TXE_FW_STS0, PCI_CFG_TXE_FW_STS1}; 1058 int i; 1059 1060 if (!fw_status) 1061 return -EINVAL; 1062 1063 fw_status->count = 2; 1064 1065 for (i = 0; i < fw_status->count && i < MEI_FW_STATUS_MAX; i++) { 1066 int ret; 1067 ret = pci_read_config_dword(dev->pdev, 1068 pci_cfg_reg[i], &fw_status->status[i]); 1069 if (ret) 1070 return ret; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static const struct mei_hw_ops mei_txe_hw_ops = { 1077 1078 .fw_status = mei_txe_fw_status, 1079 .host_is_ready = mei_txe_host_is_ready, 1080 1081 .pg_state = mei_txe_pg_state, 1082 1083 .hw_is_ready = mei_txe_hw_is_ready, 1084 .hw_reset = mei_txe_hw_reset, 1085 .hw_config = mei_txe_hw_config, 1086 .hw_start = mei_txe_hw_start, 1087 1088 .pg_is_enabled = mei_txe_pg_is_enabled, 1089 1090 .intr_clear = mei_txe_intr_clear, 1091 .intr_enable = mei_txe_intr_enable, 1092 .intr_disable = mei_txe_intr_disable, 1093 1094 .hbuf_free_slots = mei_txe_hbuf_empty_slots, 1095 .hbuf_is_ready = mei_txe_is_input_ready, 1096 .hbuf_max_len = mei_txe_hbuf_max_len, 1097 1098 .write = mei_txe_write, 1099 1100 .rdbuf_full_slots = mei_txe_count_full_read_slots, 1101 .read_hdr = mei_txe_read_hdr, 1102 1103 .read = mei_txe_read, 1104 1105 }; 1106 1107 #define MEI_CFG_TXE_FW_STS \ 1108 .fw_status.count = 2, \ 1109 .fw_status.status[0] = PCI_CFG_TXE_FW_STS0, \ 1110 .fw_status.status[1] = PCI_CFG_TXE_FW_STS1 1111 1112 const struct mei_cfg mei_txe_cfg = { 1113 MEI_CFG_TXE_FW_STS, 1114 }; 1115 1116 1117 /** 1118 * mei_txe_dev_init - allocates and initializes txe hardware specific structure 1119 * 1120 * @pdev - pci device 1121 * @cfg - per device generation config 1122 * 1123 * returns struct mei_device * on success or NULL; 1124 * 1125 */ 1126 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev, 1127 const struct mei_cfg *cfg) 1128 { 1129 struct mei_device *dev; 1130 struct mei_txe_hw *hw; 1131 1132 dev = kzalloc(sizeof(struct mei_device) + 1133 sizeof(struct mei_txe_hw), GFP_KERNEL); 1134 if (!dev) 1135 return NULL; 1136 1137 mei_device_init(dev, cfg); 1138 1139 hw = to_txe_hw(dev); 1140 1141 init_waitqueue_head(&hw->wait_aliveness_resp); 1142 1143 dev->ops = &mei_txe_hw_ops; 1144 1145 dev->pdev = pdev; 1146 return dev; 1147 } 1148 1149 /** 1150 * mei_txe_setup_satt2 - SATT2 configuration for DMA support. 1151 * 1152 * @dev: the device structure 1153 * @addr: physical address start of the range 1154 * @range: physical range size 1155 */ 1156 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range) 1157 { 1158 struct mei_txe_hw *hw = to_txe_hw(dev); 1159 1160 u32 lo32 = lower_32_bits(addr); 1161 u32 hi32 = upper_32_bits(addr); 1162 u32 ctrl; 1163 1164 /* SATT is limited to 36 Bits */ 1165 if (hi32 & ~0xF) 1166 return -EINVAL; 1167 1168 /* SATT has to be 16Byte aligned */ 1169 if (lo32 & 0xF) 1170 return -EINVAL; 1171 1172 /* SATT range has to be 4Bytes aligned */ 1173 if (range & 0x4) 1174 return -EINVAL; 1175 1176 /* SATT is limited to 32 MB range*/ 1177 if (range > SATT_RANGE_MAX) 1178 return -EINVAL; 1179 1180 ctrl = SATT2_CTRL_VALID_MSK; 1181 ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT; 1182 1183 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); 1184 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); 1185 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); 1186 dev_dbg(&dev->pdev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", 1187 range, lo32, ctrl); 1188 1189 return 0; 1190 } 1191