1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2013-2014, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/jiffies.h> 19 #include <linux/delay.h> 20 #include <linux/kthread.h> 21 #include <linux/irqreturn.h> 22 23 #include <linux/mei.h> 24 25 #include "mei_dev.h" 26 #include "hw-txe.h" 27 #include "client.h" 28 #include "hbm.h" 29 30 /** 31 * mei_txe_reg_read - Reads 32bit data from the txe device 32 * 33 * @base_addr: registers base address 34 * @offset: register offset 35 * 36 * Return: register value 37 */ 38 static inline u32 mei_txe_reg_read(void __iomem *base_addr, 39 unsigned long offset) 40 { 41 return ioread32(base_addr + offset); 42 } 43 44 /** 45 * mei_txe_reg_write - Writes 32bit data to the txe device 46 * 47 * @base_addr: registers base address 48 * @offset: register offset 49 * @value: the value to write 50 */ 51 static inline void mei_txe_reg_write(void __iomem *base_addr, 52 unsigned long offset, u32 value) 53 { 54 iowrite32(value, base_addr + offset); 55 } 56 57 /** 58 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR 59 * 60 * @hw: the txe hardware structure 61 * @offset: register offset 62 * 63 * Doesn't check for aliveness while Reads 32bit data from the SeC BAR 64 * 65 * Return: register value 66 */ 67 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, 68 unsigned long offset) 69 { 70 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); 71 } 72 73 /** 74 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR 75 * 76 * @hw: the txe hardware structure 77 * @offset: register offset 78 * 79 * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set 80 * 81 * Return: register value 82 */ 83 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, 84 unsigned long offset) 85 { 86 WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); 87 return mei_txe_sec_reg_read_silent(hw, offset); 88 } 89 /** 90 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR 91 * doesn't check for aliveness 92 * 93 * @hw: the txe hardware structure 94 * @offset: register offset 95 * @value: value to write 96 * 97 * Doesn't check for aliveness while writes 32bit data from to the SeC BAR 98 */ 99 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, 100 unsigned long offset, u32 value) 101 { 102 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); 103 } 104 105 /** 106 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR 107 * 108 * @hw: the txe hardware structure 109 * @offset: register offset 110 * @value: value to write 111 * 112 * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set 113 */ 114 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, 115 unsigned long offset, u32 value) 116 { 117 WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); 118 mei_txe_sec_reg_write_silent(hw, offset, value); 119 } 120 /** 121 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR 122 * 123 * @hw: the txe hardware structure 124 * @offset: offset from which to read the data 125 * 126 * Return: the byte read. 127 */ 128 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, 129 unsigned long offset) 130 { 131 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); 132 } 133 134 /** 135 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR 136 * 137 * @hw: the txe hardware structure 138 * @offset: offset from which to write the data 139 * @value: the byte to write 140 */ 141 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, 142 unsigned long offset, u32 value) 143 { 144 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); 145 } 146 147 /** 148 * mei_txe_aliveness_set - request for aliveness change 149 * 150 * @dev: the device structure 151 * @req: requested aliveness value 152 * 153 * Request for aliveness change and returns true if the change is 154 * really needed and false if aliveness is already 155 * in the requested state 156 * 157 * Locking: called under "dev->device_lock" lock 158 * 159 * Return: true if request was send 160 */ 161 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req) 162 { 163 164 struct mei_txe_hw *hw = to_txe_hw(dev); 165 bool do_req = hw->aliveness != req; 166 167 dev_dbg(dev->dev, "Aliveness current=%d request=%d\n", 168 hw->aliveness, req); 169 if (do_req) { 170 dev->pg_event = MEI_PG_EVENT_WAIT; 171 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); 172 } 173 return do_req; 174 } 175 176 177 /** 178 * mei_txe_aliveness_req_get - get aliveness requested register value 179 * 180 * @dev: the device structure 181 * 182 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from 183 * from HICR_HOST_ALIVENESS_REQ register value 184 * 185 * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value 186 */ 187 static u32 mei_txe_aliveness_req_get(struct mei_device *dev) 188 { 189 struct mei_txe_hw *hw = to_txe_hw(dev); 190 u32 reg; 191 192 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); 193 return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED; 194 } 195 196 /** 197 * mei_txe_aliveness_get - get aliveness response register value 198 * 199 * @dev: the device structure 200 * 201 * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP 202 * register 203 */ 204 static u32 mei_txe_aliveness_get(struct mei_device *dev) 205 { 206 struct mei_txe_hw *hw = to_txe_hw(dev); 207 u32 reg; 208 209 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); 210 return reg & HICR_HOST_ALIVENESS_RESP_ACK; 211 } 212 213 /** 214 * mei_txe_aliveness_poll - waits for aliveness to settle 215 * 216 * @dev: the device structure 217 * @expected: expected aliveness value 218 * 219 * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set 220 * 221 * Return: > 0 if the expected value was received, -ETIME otherwise 222 */ 223 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected) 224 { 225 struct mei_txe_hw *hw = to_txe_hw(dev); 226 int t = 0; 227 228 do { 229 hw->aliveness = mei_txe_aliveness_get(dev); 230 if (hw->aliveness == expected) { 231 dev->pg_event = MEI_PG_EVENT_IDLE; 232 dev_dbg(dev->dev, 233 "aliveness settled after %d msecs\n", t); 234 return t; 235 } 236 mutex_unlock(&dev->device_lock); 237 msleep(MSEC_PER_SEC / 5); 238 mutex_lock(&dev->device_lock); 239 t += MSEC_PER_SEC / 5; 240 } while (t < SEC_ALIVENESS_WAIT_TIMEOUT); 241 242 dev->pg_event = MEI_PG_EVENT_IDLE; 243 dev_err(dev->dev, "aliveness timed out\n"); 244 return -ETIME; 245 } 246 247 /** 248 * mei_txe_aliveness_wait - waits for aliveness to settle 249 * 250 * @dev: the device structure 251 * @expected: expected aliveness value 252 * 253 * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set 254 * 255 * Return: 0 on success and < 0 otherwise 256 */ 257 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected) 258 { 259 struct mei_txe_hw *hw = to_txe_hw(dev); 260 const unsigned long timeout = 261 msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT); 262 long err; 263 int ret; 264 265 hw->aliveness = mei_txe_aliveness_get(dev); 266 if (hw->aliveness == expected) 267 return 0; 268 269 mutex_unlock(&dev->device_lock); 270 err = wait_event_timeout(hw->wait_aliveness_resp, 271 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 272 mutex_lock(&dev->device_lock); 273 274 hw->aliveness = mei_txe_aliveness_get(dev); 275 ret = hw->aliveness == expected ? 0 : -ETIME; 276 277 if (ret) 278 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n", 279 err, hw->aliveness, dev->pg_event); 280 else 281 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n", 282 jiffies_to_msecs(timeout - err), 283 hw->aliveness, dev->pg_event); 284 285 dev->pg_event = MEI_PG_EVENT_IDLE; 286 return ret; 287 } 288 289 /** 290 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete 291 * 292 * @dev: the device structure 293 * @req: requested aliveness value 294 * 295 * Return: 0 on success and < 0 otherwise 296 */ 297 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req) 298 { 299 if (mei_txe_aliveness_set(dev, req)) 300 return mei_txe_aliveness_wait(dev, req); 301 return 0; 302 } 303 304 /** 305 * mei_txe_pg_is_enabled - detect if PG is supported by HW 306 * 307 * @dev: the device structure 308 * 309 * Return: true is pg supported, false otherwise 310 */ 311 static bool mei_txe_pg_is_enabled(struct mei_device *dev) 312 { 313 return true; 314 } 315 316 /** 317 * mei_txe_pg_state - translate aliveness register value 318 * to the mei power gating state 319 * 320 * @dev: the device structure 321 * 322 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise 323 */ 324 static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev) 325 { 326 struct mei_txe_hw *hw = to_txe_hw(dev); 327 328 return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON; 329 } 330 331 /** 332 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt 333 * 334 * @dev: the device structure 335 */ 336 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev) 337 { 338 struct mei_txe_hw *hw = to_txe_hw(dev); 339 u32 hintmsk; 340 /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */ 341 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); 342 hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY; 343 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); 344 } 345 346 /** 347 * mei_txe_input_doorbell_set - sets bit 0 in 348 * SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL. 349 * 350 * @hw: the txe hardware structure 351 */ 352 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) 353 { 354 /* Clear the interrupt cause */ 355 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); 356 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); 357 } 358 359 /** 360 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1 361 * 362 * @hw: the txe hardware structure 363 */ 364 static void mei_txe_output_ready_set(struct mei_txe_hw *hw) 365 { 366 mei_txe_br_reg_write(hw, 367 SICR_SEC_IPC_OUTPUT_STATUS_REG, 368 SEC_IPC_OUTPUT_STATUS_RDY); 369 } 370 371 /** 372 * mei_txe_is_input_ready - check if TXE is ready for receiving data 373 * 374 * @dev: the device structure 375 * 376 * Return: true if INPUT STATUS READY bit is set 377 */ 378 static bool mei_txe_is_input_ready(struct mei_device *dev) 379 { 380 struct mei_txe_hw *hw = to_txe_hw(dev); 381 u32 status; 382 383 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); 384 return !!(SEC_IPC_INPUT_STATUS_RDY & status); 385 } 386 387 /** 388 * mei_txe_intr_clear - clear all interrupts 389 * 390 * @dev: the device structure 391 */ 392 static inline void mei_txe_intr_clear(struct mei_device *dev) 393 { 394 struct mei_txe_hw *hw = to_txe_hw(dev); 395 396 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, 397 SEC_IPC_HOST_INT_STATUS_PENDING); 398 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); 399 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); 400 } 401 402 /** 403 * mei_txe_intr_disable - disable all interrupts 404 * 405 * @dev: the device structure 406 */ 407 static void mei_txe_intr_disable(struct mei_device *dev) 408 { 409 struct mei_txe_hw *hw = to_txe_hw(dev); 410 411 mei_txe_br_reg_write(hw, HHIER_REG, 0); 412 mei_txe_br_reg_write(hw, HIER_REG, 0); 413 } 414 /** 415 * mei_txe_intr_disable - enable all interrupts 416 * 417 * @dev: the device structure 418 */ 419 static void mei_txe_intr_enable(struct mei_device *dev) 420 { 421 struct mei_txe_hw *hw = to_txe_hw(dev); 422 423 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); 424 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); 425 } 426 427 /** 428 * mei_txe_pending_interrupts - check if there are pending interrupts 429 * only Aliveness, Input ready, and output doorbell are of relevance 430 * 431 * @dev: the device structure 432 * 433 * Checks if there are pending interrupts 434 * only Aliveness, Readiness, Input ready, and Output doorbell are relevant 435 * 436 * Return: true if there are pending interrupts 437 */ 438 static bool mei_txe_pending_interrupts(struct mei_device *dev) 439 { 440 441 struct mei_txe_hw *hw = to_txe_hw(dev); 442 bool ret = (hw->intr_cause & (TXE_INTR_READINESS | 443 TXE_INTR_ALIVENESS | 444 TXE_INTR_IN_READY | 445 TXE_INTR_OUT_DB)); 446 447 if (ret) { 448 dev_dbg(dev->dev, 449 "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n", 450 !!(hw->intr_cause & TXE_INTR_IN_READY), 451 !!(hw->intr_cause & TXE_INTR_READINESS), 452 !!(hw->intr_cause & TXE_INTR_ALIVENESS), 453 !!(hw->intr_cause & TXE_INTR_OUT_DB)); 454 } 455 return ret; 456 } 457 458 /** 459 * mei_txe_input_payload_write - write a dword to the host buffer 460 * at offset idx 461 * 462 * @dev: the device structure 463 * @idx: index in the host buffer 464 * @value: value 465 */ 466 static void mei_txe_input_payload_write(struct mei_device *dev, 467 unsigned long idx, u32 value) 468 { 469 struct mei_txe_hw *hw = to_txe_hw(dev); 470 471 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + 472 (idx * sizeof(u32)), value); 473 } 474 475 /** 476 * mei_txe_out_data_read - read dword from the device buffer 477 * at offset idx 478 * 479 * @dev: the device structure 480 * @idx: index in the device buffer 481 * 482 * Return: register value at index 483 */ 484 static u32 mei_txe_out_data_read(const struct mei_device *dev, 485 unsigned long idx) 486 { 487 struct mei_txe_hw *hw = to_txe_hw(dev); 488 489 return mei_txe_br_reg_read(hw, 490 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32))); 491 } 492 493 /* Readiness */ 494 495 /** 496 * mei_txe_readiness_set_host_rdy - set host readiness bit 497 * 498 * @dev: the device structure 499 */ 500 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev) 501 { 502 struct mei_txe_hw *hw = to_txe_hw(dev); 503 504 mei_txe_br_reg_write(hw, 505 SICR_HOST_IPC_READINESS_REQ_REG, 506 SICR_HOST_IPC_READINESS_HOST_RDY); 507 } 508 509 /** 510 * mei_txe_readiness_clear - clear host readiness bit 511 * 512 * @dev: the device structure 513 */ 514 static void mei_txe_readiness_clear(struct mei_device *dev) 515 { 516 struct mei_txe_hw *hw = to_txe_hw(dev); 517 518 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, 519 SICR_HOST_IPC_READINESS_RDY_CLR); 520 } 521 /** 522 * mei_txe_readiness_get - Reads and returns 523 * the HICR_SEC_IPC_READINESS register value 524 * 525 * @dev: the device structure 526 * 527 * Return: the HICR_SEC_IPC_READINESS register value 528 */ 529 static u32 mei_txe_readiness_get(struct mei_device *dev) 530 { 531 struct mei_txe_hw *hw = to_txe_hw(dev); 532 533 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); 534 } 535 536 537 /** 538 * mei_txe_readiness_is_sec_rdy - check readiness 539 * for HICR_SEC_IPC_READINESS_SEC_RDY 540 * 541 * @readiness: cached readiness state 542 * 543 * Return: true if readiness bit is set 544 */ 545 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness) 546 { 547 return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY); 548 } 549 550 /** 551 * mei_txe_hw_is_ready - check if the hw is ready 552 * 553 * @dev: the device structure 554 * 555 * Return: true if sec is ready 556 */ 557 static bool mei_txe_hw_is_ready(struct mei_device *dev) 558 { 559 u32 readiness = mei_txe_readiness_get(dev); 560 561 return mei_txe_readiness_is_sec_rdy(readiness); 562 } 563 564 /** 565 * mei_txe_host_is_ready - check if the host is ready 566 * 567 * @dev: the device structure 568 * 569 * Return: true if host is ready 570 */ 571 static inline bool mei_txe_host_is_ready(struct mei_device *dev) 572 { 573 struct mei_txe_hw *hw = to_txe_hw(dev); 574 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); 575 576 return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY); 577 } 578 579 /** 580 * mei_txe_readiness_wait - wait till readiness settles 581 * 582 * @dev: the device structure 583 * 584 * Return: 0 on success and -ETIME on timeout 585 */ 586 static int mei_txe_readiness_wait(struct mei_device *dev) 587 { 588 if (mei_txe_hw_is_ready(dev)) 589 return 0; 590 591 mutex_unlock(&dev->device_lock); 592 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, 593 msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT)); 594 mutex_lock(&dev->device_lock); 595 if (!dev->recvd_hw_ready) { 596 dev_err(dev->dev, "wait for readiness failed\n"); 597 return -ETIME; 598 } 599 600 dev->recvd_hw_ready = false; 601 return 0; 602 } 603 604 static const struct mei_fw_status mei_txe_fw_sts = { 605 .count = 2, 606 .status[0] = PCI_CFG_TXE_FW_STS0, 607 .status[1] = PCI_CFG_TXE_FW_STS1 608 }; 609 610 /** 611 * mei_txe_fw_status - read fw status register from pci config space 612 * 613 * @dev: mei device 614 * @fw_status: fw status register values 615 * 616 * Return: 0 on success, error otherwise 617 */ 618 static int mei_txe_fw_status(struct mei_device *dev, 619 struct mei_fw_status *fw_status) 620 { 621 const struct mei_fw_status *fw_src = &mei_txe_fw_sts; 622 struct pci_dev *pdev = to_pci_dev(dev->dev); 623 int ret; 624 int i; 625 626 if (!fw_status) 627 return -EINVAL; 628 629 fw_status->count = fw_src->count; 630 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { 631 ret = pci_read_config_dword(pdev, 632 fw_src->status[i], &fw_status->status[i]); 633 if (ret) 634 return ret; 635 } 636 637 return 0; 638 } 639 640 /** 641 * mei_txe_hw_config - configure hardware at the start of the devices 642 * 643 * @dev: the device structure 644 * 645 * Configure hardware at the start of the device should be done only 646 * once at the device probe time 647 */ 648 static void mei_txe_hw_config(struct mei_device *dev) 649 { 650 651 struct mei_txe_hw *hw = to_txe_hw(dev); 652 653 /* Doesn't change in runtime */ 654 dev->hbuf_depth = PAYLOAD_SIZE / 4; 655 656 hw->aliveness = mei_txe_aliveness_get(dev); 657 hw->readiness = mei_txe_readiness_get(dev); 658 659 dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", 660 hw->aliveness, hw->readiness); 661 } 662 663 664 /** 665 * mei_txe_write - writes a message to device. 666 * 667 * @dev: the device structure 668 * @header: header of message 669 * @buf: message buffer will be written 670 * 671 * Return: 0 if success, <0 - otherwise. 672 */ 673 674 static int mei_txe_write(struct mei_device *dev, 675 struct mei_msg_hdr *header, unsigned char *buf) 676 { 677 struct mei_txe_hw *hw = to_txe_hw(dev); 678 unsigned long rem; 679 unsigned long length; 680 int slots = dev->hbuf_depth; 681 u32 *reg_buf = (u32 *)buf; 682 u32 dw_cnt; 683 int i; 684 685 if (WARN_ON(!header || !buf)) 686 return -EINVAL; 687 688 length = header->length; 689 690 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); 691 692 dw_cnt = mei_data2slots(length); 693 if (dw_cnt > slots) 694 return -EMSGSIZE; 695 696 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) 697 return -EAGAIN; 698 699 /* Enable Input Ready Interrupt. */ 700 mei_txe_input_ready_interrupt_enable(dev); 701 702 if (!mei_txe_is_input_ready(dev)) { 703 char fw_sts_str[MEI_FW_STATUS_STR_SZ]; 704 705 mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ); 706 dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str); 707 return -EAGAIN; 708 } 709 710 mei_txe_input_payload_write(dev, 0, *((u32 *)header)); 711 712 for (i = 0; i < length / 4; i++) 713 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]); 714 715 rem = length & 0x3; 716 if (rem > 0) { 717 u32 reg = 0; 718 719 memcpy(®, &buf[length - rem], rem); 720 mei_txe_input_payload_write(dev, i + 1, reg); 721 } 722 723 /* after each write the whole buffer is consumed */ 724 hw->slots = 0; 725 726 /* Set Input-Doorbell */ 727 mei_txe_input_doorbell_set(hw); 728 729 return 0; 730 } 731 732 /** 733 * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer 734 * 735 * @dev: the device structure 736 * 737 * Return: the PAYLOAD_SIZE - 4 738 */ 739 static size_t mei_txe_hbuf_max_len(const struct mei_device *dev) 740 { 741 return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr); 742 } 743 744 /** 745 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer 746 * 747 * @dev: the device structure 748 * 749 * Return: always hbuf_depth 750 */ 751 static int mei_txe_hbuf_empty_slots(struct mei_device *dev) 752 { 753 struct mei_txe_hw *hw = to_txe_hw(dev); 754 755 return hw->slots; 756 } 757 758 /** 759 * mei_txe_count_full_read_slots - mimics the me device circular buffer 760 * 761 * @dev: the device structure 762 * 763 * Return: always buffer size in dwords count 764 */ 765 static int mei_txe_count_full_read_slots(struct mei_device *dev) 766 { 767 /* read buffers has static size */ 768 return PAYLOAD_SIZE / 4; 769 } 770 771 /** 772 * mei_txe_read_hdr - read message header which is always in 4 first bytes 773 * 774 * @dev: the device structure 775 * 776 * Return: mei message header 777 */ 778 779 static u32 mei_txe_read_hdr(const struct mei_device *dev) 780 { 781 return mei_txe_out_data_read(dev, 0); 782 } 783 /** 784 * mei_txe_read - reads a message from the txe device. 785 * 786 * @dev: the device structure 787 * @buf: message buffer will be written 788 * @len: message size will be read 789 * 790 * Return: -EINVAL on error wrong argument and 0 on success 791 */ 792 static int mei_txe_read(struct mei_device *dev, 793 unsigned char *buf, unsigned long len) 794 { 795 796 struct mei_txe_hw *hw = to_txe_hw(dev); 797 u32 *reg_buf, reg; 798 u32 rem; 799 u32 i; 800 801 if (WARN_ON(!buf || !len)) 802 return -EINVAL; 803 804 reg_buf = (u32 *)buf; 805 rem = len & 0x3; 806 807 dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n", 808 len, mei_txe_out_data_read(dev, 0)); 809 810 for (i = 0; i < len / 4; i++) { 811 /* skip header: index starts from 1 */ 812 reg = mei_txe_out_data_read(dev, i + 1); 813 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg); 814 *reg_buf++ = reg; 815 } 816 817 if (rem) { 818 reg = mei_txe_out_data_read(dev, i + 1); 819 memcpy(reg_buf, ®, rem); 820 } 821 822 mei_txe_output_ready_set(hw); 823 return 0; 824 } 825 826 /** 827 * mei_txe_hw_reset - resets host and fw. 828 * 829 * @dev: the device structure 830 * @intr_enable: if interrupt should be enabled after reset. 831 * 832 * Return: 0 on success and < 0 in case of error 833 */ 834 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable) 835 { 836 struct mei_txe_hw *hw = to_txe_hw(dev); 837 838 u32 aliveness_req; 839 /* 840 * read input doorbell to ensure consistency between Bridge and SeC 841 * return value might be garbage return 842 */ 843 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); 844 845 aliveness_req = mei_txe_aliveness_req_get(dev); 846 hw->aliveness = mei_txe_aliveness_get(dev); 847 848 /* Disable interrupts in this stage we will poll */ 849 mei_txe_intr_disable(dev); 850 851 /* 852 * If Aliveness Request and Aliveness Response are not equal then 853 * wait for them to be equal 854 * Since we might have interrupts disabled - poll for it 855 */ 856 if (aliveness_req != hw->aliveness) 857 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) { 858 dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n"); 859 return -EIO; 860 } 861 862 /* 863 * If Aliveness Request and Aliveness Response are set then clear them 864 */ 865 if (aliveness_req) { 866 mei_txe_aliveness_set(dev, 0); 867 if (mei_txe_aliveness_poll(dev, 0) < 0) { 868 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); 869 return -EIO; 870 } 871 } 872 873 /* 874 * Set readiness RDY_CLR bit 875 */ 876 mei_txe_readiness_clear(dev); 877 878 return 0; 879 } 880 881 /** 882 * mei_txe_hw_start - start the hardware after reset 883 * 884 * @dev: the device structure 885 * 886 * Return: 0 on success an error code otherwise 887 */ 888 static int mei_txe_hw_start(struct mei_device *dev) 889 { 890 struct mei_txe_hw *hw = to_txe_hw(dev); 891 int ret; 892 893 u32 hisr; 894 895 /* bring back interrupts */ 896 mei_txe_intr_enable(dev); 897 898 ret = mei_txe_readiness_wait(dev); 899 if (ret < 0) { 900 dev_err(dev->dev, "waiting for readiness failed\n"); 901 return ret; 902 } 903 904 /* 905 * If HISR.INT2_STS interrupt status bit is set then clear it. 906 */ 907 hisr = mei_txe_br_reg_read(hw, HISR_REG); 908 if (hisr & HISR_INT_2_STS) 909 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); 910 911 /* Clear the interrupt cause of OutputDoorbell */ 912 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); 913 914 ret = mei_txe_aliveness_set_sync(dev, 1); 915 if (ret < 0) { 916 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); 917 return ret; 918 } 919 920 /* enable input ready interrupts: 921 * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK 922 */ 923 mei_txe_input_ready_interrupt_enable(dev); 924 925 926 /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */ 927 mei_txe_output_ready_set(hw); 928 929 /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY 930 */ 931 mei_txe_readiness_set_host_rdy(dev); 932 933 return 0; 934 } 935 936 /** 937 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into 938 * single bit mask and acknowledge the interrupts 939 * 940 * @dev: the device structure 941 * @do_ack: acknowledge interrupts 942 * 943 * Return: true if found interrupts to process. 944 */ 945 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack) 946 { 947 struct mei_txe_hw *hw = to_txe_hw(dev); 948 u32 hisr; 949 u32 hhisr; 950 u32 ipc_isr; 951 u32 aliveness; 952 bool generated; 953 954 /* read interrupt registers */ 955 hhisr = mei_txe_br_reg_read(hw, HHISR_REG); 956 generated = (hhisr & IPC_HHIER_MSK); 957 if (!generated) 958 goto out; 959 960 hisr = mei_txe_br_reg_read(hw, HISR_REG); 961 962 aliveness = mei_txe_aliveness_get(dev); 963 if (hhisr & IPC_HHIER_SEC && aliveness) 964 ipc_isr = mei_txe_sec_reg_read_silent(hw, 965 SEC_IPC_HOST_INT_STATUS_REG); 966 else 967 ipc_isr = 0; 968 969 generated = generated || 970 (hisr & HISR_INT_STS_MSK) || 971 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING); 972 973 if (generated && do_ack) { 974 /* Save the interrupt causes */ 975 hw->intr_cause |= hisr & HISR_INT_STS_MSK; 976 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY) 977 hw->intr_cause |= TXE_INTR_IN_READY; 978 979 980 mei_txe_intr_disable(dev); 981 /* Clear the interrupts in hierarchy: 982 * IPC and Bridge, than the High Level */ 983 mei_txe_sec_reg_write_silent(hw, 984 SEC_IPC_HOST_INT_STATUS_REG, ipc_isr); 985 mei_txe_br_reg_write(hw, HISR_REG, hisr); 986 mei_txe_br_reg_write(hw, HHISR_REG, hhisr); 987 } 988 989 out: 990 return generated; 991 } 992 993 /** 994 * mei_txe_irq_quick_handler - The ISR of the MEI device 995 * 996 * @irq: The irq number 997 * @dev_id: pointer to the device structure 998 * 999 * Return: IRQ_WAKE_THREAD if interrupt is designed for the device 1000 * IRQ_NONE otherwise 1001 */ 1002 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id) 1003 { 1004 struct mei_device *dev = dev_id; 1005 1006 if (mei_txe_check_and_ack_intrs(dev, true)) 1007 return IRQ_WAKE_THREAD; 1008 return IRQ_NONE; 1009 } 1010 1011 1012 /** 1013 * mei_txe_irq_thread_handler - txe interrupt thread 1014 * 1015 * @irq: The irq number 1016 * @dev_id: pointer to the device structure 1017 * 1018 * Return: IRQ_HANDLED 1019 */ 1020 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id) 1021 { 1022 struct mei_device *dev = (struct mei_device *) dev_id; 1023 struct mei_txe_hw *hw = to_txe_hw(dev); 1024 struct mei_cl_cb complete_list; 1025 s32 slots; 1026 int rets = 0; 1027 1028 dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", 1029 mei_txe_br_reg_read(hw, HHISR_REG), 1030 mei_txe_br_reg_read(hw, HISR_REG), 1031 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); 1032 1033 1034 /* initialize our complete list */ 1035 mutex_lock(&dev->device_lock); 1036 mei_io_list_init(&complete_list); 1037 1038 if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) 1039 mei_txe_check_and_ack_intrs(dev, true); 1040 1041 /* show irq events */ 1042 mei_txe_pending_interrupts(dev); 1043 1044 hw->aliveness = mei_txe_aliveness_get(dev); 1045 hw->readiness = mei_txe_readiness_get(dev); 1046 1047 /* Readiness: 1048 * Detection of TXE driver going through reset 1049 * or TXE driver resetting the HECI interface. 1050 */ 1051 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { 1052 dev_dbg(dev->dev, "Readiness Interrupt was received...\n"); 1053 1054 /* Check if SeC is going through reset */ 1055 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { 1056 dev_dbg(dev->dev, "we need to start the dev.\n"); 1057 dev->recvd_hw_ready = true; 1058 } else { 1059 dev->recvd_hw_ready = false; 1060 if (dev->dev_state != MEI_DEV_RESETTING) { 1061 1062 dev_warn(dev->dev, "FW not ready: resetting.\n"); 1063 schedule_work(&dev->reset_work); 1064 goto end; 1065 1066 } 1067 } 1068 wake_up(&dev->wait_hw_ready); 1069 } 1070 1071 /************************************************************/ 1072 /* Check interrupt cause: 1073 * Aliveness: Detection of SeC acknowledge of host request that 1074 * it remain alive or host cancellation of that request. 1075 */ 1076 1077 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { 1078 /* Clear the interrupt cause */ 1079 dev_dbg(dev->dev, 1080 "Aliveness Interrupt: Status: %d\n", hw->aliveness); 1081 dev->pg_event = MEI_PG_EVENT_RECEIVED; 1082 if (waitqueue_active(&hw->wait_aliveness_resp)) 1083 wake_up(&hw->wait_aliveness_resp); 1084 } 1085 1086 1087 /* Output Doorbell: 1088 * Detection of SeC having sent output to host 1089 */ 1090 slots = mei_count_full_read_slots(dev); 1091 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { 1092 /* Read from TXE */ 1093 rets = mei_irq_read_handler(dev, &complete_list, &slots); 1094 if (rets && dev->dev_state != MEI_DEV_RESETTING) { 1095 dev_err(dev->dev, 1096 "mei_irq_read_handler ret = %d.\n", rets); 1097 1098 schedule_work(&dev->reset_work); 1099 goto end; 1100 } 1101 } 1102 /* Input Ready: Detection if host can write to SeC */ 1103 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { 1104 dev->hbuf_is_ready = true; 1105 hw->slots = dev->hbuf_depth; 1106 } 1107 1108 if (hw->aliveness && dev->hbuf_is_ready) { 1109 /* get the real register value */ 1110 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1111 rets = mei_irq_write_handler(dev, &complete_list); 1112 if (rets && rets != -EMSGSIZE) 1113 dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n", 1114 rets); 1115 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1116 } 1117 1118 mei_irq_compl_handler(dev, &complete_list); 1119 1120 end: 1121 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); 1122 1123 mutex_unlock(&dev->device_lock); 1124 1125 mei_enable_interrupts(dev); 1126 return IRQ_HANDLED; 1127 } 1128 1129 static const struct mei_hw_ops mei_txe_hw_ops = { 1130 1131 .host_is_ready = mei_txe_host_is_ready, 1132 1133 .fw_status = mei_txe_fw_status, 1134 .pg_state = mei_txe_pg_state, 1135 1136 .hw_is_ready = mei_txe_hw_is_ready, 1137 .hw_reset = mei_txe_hw_reset, 1138 .hw_config = mei_txe_hw_config, 1139 .hw_start = mei_txe_hw_start, 1140 1141 .pg_is_enabled = mei_txe_pg_is_enabled, 1142 1143 .intr_clear = mei_txe_intr_clear, 1144 .intr_enable = mei_txe_intr_enable, 1145 .intr_disable = mei_txe_intr_disable, 1146 1147 .hbuf_free_slots = mei_txe_hbuf_empty_slots, 1148 .hbuf_is_ready = mei_txe_is_input_ready, 1149 .hbuf_max_len = mei_txe_hbuf_max_len, 1150 1151 .write = mei_txe_write, 1152 1153 .rdbuf_full_slots = mei_txe_count_full_read_slots, 1154 .read_hdr = mei_txe_read_hdr, 1155 1156 .read = mei_txe_read, 1157 1158 }; 1159 1160 /** 1161 * mei_txe_dev_init - allocates and initializes txe hardware specific structure 1162 * 1163 * @pdev: pci device 1164 * 1165 * Return: struct mei_device * on success or NULL 1166 */ 1167 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev) 1168 { 1169 struct mei_device *dev; 1170 struct mei_txe_hw *hw; 1171 1172 dev = kzalloc(sizeof(struct mei_device) + 1173 sizeof(struct mei_txe_hw), GFP_KERNEL); 1174 if (!dev) 1175 return NULL; 1176 1177 mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); 1178 1179 hw = to_txe_hw(dev); 1180 1181 init_waitqueue_head(&hw->wait_aliveness_resp); 1182 1183 return dev; 1184 } 1185 1186 /** 1187 * mei_txe_setup_satt2 - SATT2 configuration for DMA support. 1188 * 1189 * @dev: the device structure 1190 * @addr: physical address start of the range 1191 * @range: physical range size 1192 * 1193 * Return: 0 on success an error code otherwise 1194 */ 1195 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range) 1196 { 1197 struct mei_txe_hw *hw = to_txe_hw(dev); 1198 1199 u32 lo32 = lower_32_bits(addr); 1200 u32 hi32 = upper_32_bits(addr); 1201 u32 ctrl; 1202 1203 /* SATT is limited to 36 Bits */ 1204 if (hi32 & ~0xF) 1205 return -EINVAL; 1206 1207 /* SATT has to be 16Byte aligned */ 1208 if (lo32 & 0xF) 1209 return -EINVAL; 1210 1211 /* SATT range has to be 4Bytes aligned */ 1212 if (range & 0x4) 1213 return -EINVAL; 1214 1215 /* SATT is limited to 32 MB range*/ 1216 if (range > SATT_RANGE_MAX) 1217 return -EINVAL; 1218 1219 ctrl = SATT2_CTRL_VALID_MSK; 1220 ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT; 1221 1222 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); 1223 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); 1224 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); 1225 dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", 1226 range, lo32, ctrl); 1227 1228 return 0; 1229 } 1230